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[mirror_ubuntu-hirsute-kernel.git] / drivers / staging / comedi / drivers / rtd520.c
1 /*
2 comedi/drivers/rtd520.c
3 Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2001 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22 /*
23 Driver: rtd520
24 Description: Real Time Devices PCI4520/DM7520
25 Author: Dan Christian
26 Devices: [Real Time Devices] DM7520HR-1 (rtd520), DM7520HR-8,
27 PCI4520, PCI4520-8
28 Status: Works. Only tested on DM7520-8. Not SMP safe.
29
30 Configuration options:
31 [0] - PCI bus of device (optional)
32 If bus / slot is not specified, the first available PCI
33 device will be used.
34 [1] - PCI slot of device (optional)
35 */
36 /*
37 Created by Dan Christian, NASA Ames Research Center.
38
39 The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
40 Both have:
41 8/16 12 bit ADC with FIFO and channel gain table
42 8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
43 8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
44 2 12 bit DACs with FIFOs
45 2 bits output
46 2 bits input
47 bus mastering DMA
48 timers: ADC sample, pacer, burst, about, delay, DA1, DA2
49 sample counter
50 3 user timer/counters (8254)
51 external interrupt
52
53 The DM7520 has slightly fewer features (fewer gain steps).
54
55 These boards can support external multiplexors and multi-board
56 synchronization, but this driver doesn't support that.
57
58 Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
59 Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
60 Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
61 Call them and ask for the register level manual.
62 PCI chip: http://www.plxtech.com/products/io/pci9080
63
64 Notes:
65 This board is memory mapped. There is some IO stuff, but it isn't needed.
66
67 I use a pretty loose naming style within the driver (rtd_blah).
68 All externally visible names should be rtd520_blah.
69 I use camelCase for structures (and inside them).
70 I may also use upper CamelCase for function names (old habit).
71
72 This board is somewhat related to the RTD PCI4400 board.
73
74 I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
75 das1800, since they have the best documented code. Driver
76 cb_pcidas64.c uses the same DMA controller.
77
78 As far as I can tell, the About interrupt doesn't work if Sample is
79 also enabled. It turns out that About really isn't needed, since
80 we always count down samples read.
81
82 There was some timer/counter code, but it didn't follow the right API.
83
84 */
85
86 /*
87 driver status:
88
89 Analog-In supports instruction and command mode.
90
91 With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
92 (single channel, 64K read buffer). I get random system lockups when
93 using DMA with ALI-15xx based systems. I haven't been able to test
94 any other chipsets. The lockups happen soon after the start of an
95 acquistion, not in the middle of a long run.
96
97 Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
98 (with a 256K read buffer).
99
100 Digital-IO and Analog-Out only support instruction mode.
101
102 */
103
104 #include <linux/interrupt.h>
105 #include <linux/delay.h>
106
107 #include "../comedidev.h"
108
109 #define DRV_NAME "rtd520"
110
111 /*======================================================================
112 Driver specific stuff (tunable)
113 ======================================================================*/
114 /* Enable this to test the new DMA support. You may get hard lock ups */
115 /*#define USE_DMA*/
116
117 /* We really only need 2 buffers. More than that means being much
118 smarter about knowing which ones are full. */
119 #define DMA_CHAIN_COUNT 2 /* max DMA segments/buffers in a ring (min 2) */
120
121 /* Target period for periodic transfers. This sets the user read latency. */
122 /* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
123 /* If this is too low, efficiency is poor */
124 #define TRANS_TARGET_PERIOD 10000000 /* 10 ms (in nanoseconds) */
125
126 /* Set a practical limit on how long a list to support (affects memory use) */
127 /* The board support a channel list up to the FIFO length (1K or 8K) */
128 #define RTD_MAX_CHANLIST 128 /* max channel list that we allow */
129
130 /* tuning for ai/ao instruction done polling */
131 #ifdef FAST_SPIN
132 #define WAIT_QUIETLY /* as nothing, spin on done bit */
133 #define RTD_ADC_TIMEOUT 66000 /* 2 msec at 33mhz bus rate */
134 #define RTD_DAC_TIMEOUT 66000
135 #define RTD_DMA_TIMEOUT 33000 /* 1 msec */
136 #else
137 /* by delaying, power and electrical noise are reduced somewhat */
138 #define WAIT_QUIETLY udelay(1)
139 #define RTD_ADC_TIMEOUT 2000 /* in usec */
140 #define RTD_DAC_TIMEOUT 2000 /* in usec */
141 #define RTD_DMA_TIMEOUT 1000 /* in usec */
142 #endif
143
144 /*======================================================================
145 Board specific stuff
146 ======================================================================*/
147
148 /* registers */
149 #define PCI_VENDOR_ID_RTD 0x1435
150 /*
151 The board has three memory windows: las0, las1, and lcfg (the PCI chip)
152 Las1 has the data and can be burst DMAed 32bits at a time.
153 */
154 #define LCFG_PCIINDEX 0
155 /* PCI region 1 is a 256 byte IO space mapping. Use??? */
156 #define LAS0_PCIINDEX 2 /* PCI memory resources */
157 #define LAS1_PCIINDEX 3
158 #define LCFG_PCISIZE 0x100
159 #define LAS0_PCISIZE 0x200
160 #define LAS1_PCISIZE 0x10
161
162 #define RTD_CLOCK_RATE 8000000 /* 8Mhz onboard clock */
163 #define RTD_CLOCK_BASE 125 /* clock period in ns */
164
165 /* Note: these speed are slower than the spec, but fit the counter resolution*/
166 #define RTD_MAX_SPEED 1625 /* when sampling, in nanoseconds */
167 /* max speed if we don't have to wait for settling */
168 #define RTD_MAX_SPEED_1 875 /* if single channel, in nanoseconds */
169
170 #define RTD_MIN_SPEED 2097151875 /* (24bit counter) in nanoseconds */
171 /* min speed when only 1 channel (no burst counter) */
172 #define RTD_MIN_SPEED_1 5000000 /* 200Hz, in nanoseconds */
173
174 #include "rtd520.h"
175 #include "plx9080.h"
176
177 /* Setup continuous ring of 1/2 FIFO transfers. See RTD manual p91 */
178 #define DMA_MODE_BITS (\
179 PLX_LOCAL_BUS_16_WIDE_BITS \
180 | PLX_DMA_EN_READYIN_BIT \
181 | PLX_DMA_LOCAL_BURST_EN_BIT \
182 | PLX_EN_CHAIN_BIT \
183 | PLX_DMA_INTR_PCI_BIT \
184 | PLX_LOCAL_ADDR_CONST_BIT \
185 | PLX_DEMAND_MODE_BIT)
186
187 #define DMA_TRANSFER_BITS (\
188 /* descriptors in PCI memory*/ PLX_DESC_IN_PCI_BIT \
189 /* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
190 /* from board to PCI */ | PLX_XFER_LOCAL_TO_PCI)
191
192 /*======================================================================
193 Comedi specific stuff
194 ======================================================================*/
195
196 /*
197 The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
198 */
199 static const struct comedi_lrange rtd_ai_7520_range = { 18, {
200 /* +-5V input range gain steps */
201 BIP_RANGE(5.0),
202 BIP_RANGE(5.0 / 2),
203 BIP_RANGE(5.0 / 4),
204 BIP_RANGE(5.0 / 8),
205 BIP_RANGE(5.0 /
206 16),
207 BIP_RANGE(5.0 /
208 32),
209 /* +-10V input range gain steps */
210 BIP_RANGE(10.0),
211 BIP_RANGE(10.0 /
212 2),
213 BIP_RANGE(10.0 /
214 4),
215 BIP_RANGE(10.0 /
216 8),
217 BIP_RANGE(10.0 /
218 16),
219 BIP_RANGE(10.0 /
220 32),
221 /* +10V input range gain steps */
222 UNI_RANGE(10.0),
223 UNI_RANGE(10.0 /
224 2),
225 UNI_RANGE(10.0 /
226 4),
227 UNI_RANGE(10.0 /
228 8),
229 UNI_RANGE(10.0 /
230 16),
231 UNI_RANGE(10.0 /
232 32),
233
234 }
235 };
236
237 /* PCI4520 has two more gains (6 more entries) */
238 static const struct comedi_lrange rtd_ai_4520_range = { 24, {
239 /* +-5V input range gain steps */
240 BIP_RANGE(5.0),
241 BIP_RANGE(5.0 / 2),
242 BIP_RANGE(5.0 / 4),
243 BIP_RANGE(5.0 / 8),
244 BIP_RANGE(5.0 /
245 16),
246 BIP_RANGE(5.0 /
247 32),
248 BIP_RANGE(5.0 /
249 64),
250 BIP_RANGE(5.0 /
251 128),
252 /* +-10V input range gain steps */
253 BIP_RANGE(10.0),
254 BIP_RANGE(10.0 /
255 2),
256 BIP_RANGE(10.0 /
257 4),
258 BIP_RANGE(10.0 /
259 8),
260 BIP_RANGE(10.0 /
261 16),
262 BIP_RANGE(10.0 /
263 32),
264 BIP_RANGE(10.0 /
265 64),
266 BIP_RANGE(10.0 /
267 128),
268 /* +10V input range gain steps */
269 UNI_RANGE(10.0),
270 UNI_RANGE(10.0 /
271 2),
272 UNI_RANGE(10.0 /
273 4),
274 UNI_RANGE(10.0 /
275 8),
276 UNI_RANGE(10.0 /
277 16),
278 UNI_RANGE(10.0 /
279 32),
280 UNI_RANGE(10.0 /
281 64),
282 UNI_RANGE(10.0 /
283 128),
284 }
285 };
286
287 /* Table order matches range values */
288 static const struct comedi_lrange rtd_ao_range = { 4, {
289 RANGE(0, 5),
290 RANGE(0, 10),
291 RANGE(-5, 5),
292 RANGE(-10, 10),
293 }
294 };
295
296 /*
297 Board descriptions
298 */
299 struct rtdBoard {
300 const char *name; /* must be first */
301 int device_id;
302 int aiChans;
303 int aiBits;
304 int aiMaxGain;
305 int range10Start; /* start of +-10V range */
306 int rangeUniStart; /* start of +10V range */
307 };
308
309 static const struct rtdBoard rtd520Boards[] = {
310 {
311 .name = "DM7520",
312 .device_id = 0x7520,
313 .aiChans = 16,
314 .aiBits = 12,
315 .aiMaxGain = 32,
316 .range10Start = 6,
317 .rangeUniStart = 12,
318 },
319 {
320 .name = "PCI4520",
321 .device_id = 0x4520,
322 .aiChans = 16,
323 .aiBits = 12,
324 .aiMaxGain = 128,
325 .range10Start = 8,
326 .rangeUniStart = 16,
327 },
328 };
329
330 /*
331 * Useful for shorthand access to the particular board structure
332 */
333 #define thisboard ((const struct rtdBoard *)dev->board_ptr)
334
335 /*
336 This structure is for data unique to this hardware driver.
337 This is also unique for each board in the system.
338 */
339 struct rtdPrivate {
340 /* memory mapped board structures */
341 void __iomem *las0;
342 void __iomem *las1;
343 void __iomem *lcfg;
344
345 unsigned long intCount; /* interrupt count */
346 long aiCount; /* total transfer size (samples) */
347 int transCount; /* # to transfer data. 0->1/2FIFO */
348 int flags; /* flag event modes */
349
350 /* PCI device info */
351 struct pci_dev *pci_dev;
352 int got_regions; /* non-zero if PCI regions owned */
353
354 /* channel list info */
355 /* chanBipolar tracks whether a channel is bipolar (and needs +2048) */
356 unsigned char chanBipolar[RTD_MAX_CHANLIST / 8]; /* bit array */
357
358 /* read back data */
359 unsigned int aoValue[2]; /* Used for AO read back */
360
361 /* timer gate (when enabled) */
362 u8 utcGate[4]; /* 1 extra allows simple range check */
363
364 /* shadow registers affect other registers, but can't be read back */
365 /* The macros below update these on writes */
366 u16 intMask; /* interrupt mask */
367 u16 intClearMask; /* interrupt clear mask */
368 u8 utcCtrl[4]; /* crtl mode for 3 utc + read back */
369 u8 dioStatus; /* could be read back (dio0Ctrl) */
370 #ifdef USE_DMA
371 /*
372 * Always DMA 1/2 FIFO. Buffer (dmaBuff?) is (at least) twice that
373 * size. After transferring, interrupt processes 1/2 FIFO and
374 * passes to comedi
375 */
376 s16 dma0Offset; /* current processing offset (0, 1/2) */
377 uint16_t *dma0Buff[DMA_CHAIN_COUNT]; /* DMA buffers (for ADC) */
378 dma_addr_t dma0BuffPhysAddr[DMA_CHAIN_COUNT]; /* physical addresses */
379 struct plx_dma_desc *dma0Chain; /* DMA descriptor ring for dmaBuff */
380 dma_addr_t dma0ChainPhysAddr; /* physical addresses */
381 /* shadow registers */
382 u8 dma0Control;
383 u8 dma1Control;
384 #endif /* USE_DMA */
385 unsigned fifoLen;
386 };
387
388 /* bit defines for "flags" */
389 #define SEND_EOS 0x01 /* send End Of Scan events */
390 #define DMA0_ACTIVE 0x02 /* DMA0 is active */
391 #define DMA1_ACTIVE 0x04 /* DMA1 is active */
392
393 /* Macros for accessing channel list bit array */
394 #define CHAN_ARRAY_TEST(array, index) \
395 (((array)[(index)/8] >> ((index) & 0x7)) & 0x1)
396 #define CHAN_ARRAY_SET(array, index) \
397 (((array)[(index)/8] |= 1 << ((index) & 0x7)))
398 #define CHAN_ARRAY_CLEAR(array, index) \
399 (((array)[(index)/8] &= ~(1 << ((index) & 0x7))))
400
401 /*
402 * most drivers define the following macro to make it easy to
403 * access the private structure.
404 */
405 #define devpriv ((struct rtdPrivate *)dev->private)
406
407 /* Macros to access registers */
408
409 /* Reset board */
410 #define RtdResetBoard(dev) \
411 writel(0, devpriv->las0+LAS0_BOARD_RESET)
412
413 /* Reset channel gain table read pointer */
414 #define RtdResetCGT(dev) \
415 writel(0, devpriv->las0+LAS0_CGT_RESET)
416
417 /* Reset channel gain table read and write pointers */
418 #define RtdClearCGT(dev) \
419 writel(0, devpriv->las0+LAS0_CGT_CLEAR)
420
421 /* Reset channel gain table read and write pointers */
422 #define RtdEnableCGT(dev, v) \
423 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_CGT_ENABLE)
424
425 /* Write channel gain table entry */
426 #define RtdWriteCGTable(dev, v) \
427 writel(v, devpriv->las0+LAS0_CGT_WRITE)
428
429 /* Write Channel Gain Latch */
430 #define RtdWriteCGLatch(dev, v) \
431 writel(v, devpriv->las0+LAS0_CGL_WRITE)
432
433 /* Reset ADC FIFO */
434 #define RtdAdcClearFifo(dev) \
435 writel(0, devpriv->las0+LAS0_ADC_FIFO_CLEAR)
436
437 /* Set ADC start conversion source select (write only) */
438 #define RtdAdcConversionSource(dev, v) \
439 writel(v, devpriv->las0+LAS0_ADC_CONVERSION)
440
441 /* Set burst start source select (write only) */
442 #define RtdBurstStartSource(dev, v) \
443 writel(v, devpriv->las0+LAS0_BURST_START)
444
445 /* Set Pacer start source select (write only) */
446 #define RtdPacerStartSource(dev, v) \
447 writel(v, devpriv->las0+LAS0_PACER_START)
448
449 /* Set Pacer stop source select (write only) */
450 #define RtdPacerStopSource(dev, v) \
451 writel(v, devpriv->las0+LAS0_PACER_STOP)
452
453 /* Set Pacer clock source select (write only) 0=external 1=internal */
454 #define RtdPacerClockSource(dev, v) \
455 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_PACER_SELECT)
456
457 /* Set sample counter source select (write only) */
458 #define RtdAdcSampleCounterSource(dev, v) \
459 writel(v, devpriv->las0+LAS0_ADC_SCNT_SRC)
460
461 /* Set Pacer trigger mode select (write only) 0=single cycle, 1=repeat */
462 #define RtdPacerTriggerMode(dev, v) \
463 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_PACER_REPEAT)
464
465 /* Set About counter stop enable (write only) */
466 #define RtdAboutStopEnable(dev, v) \
467 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_ACNT_STOP_ENABLE)
468
469 /* Set external trigger polarity (write only) 0=positive edge, 1=negative */
470 #define RtdTriggerPolarity(dev, v) \
471 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_ETRG_POLARITY)
472
473 /* Start single ADC conversion */
474 #define RtdAdcStart(dev) \
475 writew(0, devpriv->las0+LAS0_ADC)
476
477 /* Read one ADC data value (12bit (with sign extend) as 16bit) */
478 /* Note: matches what DMA would get. Actual value >> 3 */
479 #define RtdAdcFifoGet(dev) \
480 readw(devpriv->las1+LAS1_ADC_FIFO)
481
482 /* Read two ADC data values (DOESN'T WORK) */
483 #define RtdAdcFifoGet2(dev) \
484 readl(devpriv->las1+LAS1_ADC_FIFO)
485
486 /* FIFO status */
487 #define RtdFifoStatus(dev) \
488 readl(devpriv->las0+LAS0_ADC)
489
490 /* pacer start/stop read=start, write=stop*/
491 #define RtdPacerStart(dev) \
492 readl(devpriv->las0+LAS0_PACER)
493 #define RtdPacerStop(dev) \
494 writel(0, devpriv->las0+LAS0_PACER)
495
496 /* Interrupt status */
497 #define RtdInterruptStatus(dev) \
498 readw(devpriv->las0+LAS0_IT)
499
500 /* Interrupt mask */
501 #define RtdInterruptMask(dev, v) \
502 writew((devpriv->intMask = (v)), devpriv->las0+LAS0_IT)
503
504 /* Interrupt status clear (only bits set in mask) */
505 #define RtdInterruptClear(dev) \
506 readw(devpriv->las0+LAS0_CLEAR)
507
508 /* Interrupt clear mask */
509 #define RtdInterruptClearMask(dev, v) \
510 writew((devpriv->intClearMask = (v)), devpriv->las0+LAS0_CLEAR)
511
512 /* Interrupt overrun status */
513 #define RtdInterruptOverrunStatus(dev) \
514 readl(devpriv->las0+LAS0_OVERRUN)
515
516 /* Interrupt overrun clear */
517 #define RtdInterruptOverrunClear(dev) \
518 writel(0, devpriv->las0+LAS0_OVERRUN)
519
520 /* Pacer counter, 24bit */
521 #define RtdPacerCount(dev) \
522 readl(devpriv->las0+LAS0_PCLK)
523 #define RtdPacerCounter(dev, v) \
524 writel((v) & 0xffffff, devpriv->las0+LAS0_PCLK)
525
526 /* Burst counter, 10bit */
527 #define RtdBurstCount(dev) \
528 readl(devpriv->las0+LAS0_BCLK)
529 #define RtdBurstCounter(dev, v) \
530 writel((v) & 0x3ff, devpriv->las0+LAS0_BCLK)
531
532 /* Delay counter, 16bit */
533 #define RtdDelayCount(dev) \
534 readl(devpriv->las0+LAS0_DCLK)
535 #define RtdDelayCounter(dev, v) \
536 writel((v) & 0xffff, devpriv->las0+LAS0_DCLK)
537
538 /* About counter, 16bit */
539 #define RtdAboutCount(dev) \
540 readl(devpriv->las0+LAS0_ACNT)
541 #define RtdAboutCounter(dev, v) \
542 writel((v) & 0xffff, devpriv->las0+LAS0_ACNT)
543
544 /* ADC sample counter, 10bit */
545 #define RtdAdcSampleCount(dev) \
546 readl(devpriv->las0+LAS0_ADC_SCNT)
547 #define RtdAdcSampleCounter(dev, v) \
548 writel((v) & 0x3ff, devpriv->las0+LAS0_ADC_SCNT)
549
550 /* User Timer/Counter (8254) */
551 #define RtdUtcCounterGet(dev, n) \
552 readb(devpriv->las0 \
553 + ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
554
555 #define RtdUtcCounterPut(dev, n, v) \
556 writeb((v) & 0xff, devpriv->las0 \
557 + ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
558
559 /* Set UTC (8254) control byte */
560 #define RtdUtcCtrlPut(dev, n, v) \
561 writeb(devpriv->utcCtrl[(n) & 3] = (((n) & 3) << 6) | ((v) & 0x3f), \
562 devpriv->las0 + LAS0_UTC_CTRL)
563
564 /* Set UTCn clock source (write only) */
565 #define RtdUtcClockSource(dev, n, v) \
566 writew(v, devpriv->las0 \
567 + ((n <= 0) ? LAS0_UTC0_CLOCK : \
568 ((1 == n) ? LAS0_UTC1_CLOCK : LAS0_UTC2_CLOCK)))
569
570 /* Set UTCn gate source (write only) */
571 #define RtdUtcGateSource(dev, n, v) \
572 writew(v, devpriv->las0 \
573 + ((n <= 0) ? LAS0_UTC0_GATE : \
574 ((1 == n) ? LAS0_UTC1_GATE : LAS0_UTC2_GATE)))
575
576 /* User output N source select (write only) */
577 #define RtdUsrOutSource(dev, n, v) \
578 writel(v, devpriv->las0+((n <= 0) ? LAS0_UOUT0_SELECT : \
579 LAS0_UOUT1_SELECT))
580
581 /* Digital IO */
582 #define RtdDio0Read(dev) \
583 (readw(devpriv->las0+LAS0_DIO0) & 0xff)
584 #define RtdDio0Write(dev, v) \
585 writew((v) & 0xff, devpriv->las0+LAS0_DIO0)
586
587 #define RtdDio1Read(dev) \
588 (readw(devpriv->las0+LAS0_DIO1) & 0xff)
589 #define RtdDio1Write(dev, v) \
590 writew((v) & 0xff, devpriv->las0+LAS0_DIO1)
591
592 #define RtdDioStatusRead(dev) \
593 (readw(devpriv->las0+LAS0_DIO_STATUS) & 0xff)
594 #define RtdDioStatusWrite(dev, v) \
595 writew((devpriv->dioStatus = (v)), devpriv->las0+LAS0_DIO_STATUS)
596
597 #define RtdDio0CtrlRead(dev) \
598 (readw(devpriv->las0+LAS0_DIO0_CTRL) & 0xff)
599 #define RtdDio0CtrlWrite(dev, v) \
600 writew((v) & 0xff, devpriv->las0+LAS0_DIO0_CTRL)
601
602 /* Digital to Analog converter */
603 /* Write one data value (sign + 12bit + marker bits) */
604 /* Note: matches what DMA would put. Actual value << 3 */
605 #define RtdDacFifoPut(dev, n, v) \
606 writew((v), devpriv->las1 + (((n) == 0) ? LAS1_DAC1_FIFO : \
607 LAS1_DAC2_FIFO))
608
609 /* Start single DAC conversion */
610 #define RtdDacUpdate(dev, n) \
611 writew(0, devpriv->las0 + (((n) == 0) ? LAS0_DAC1 : LAS0_DAC2))
612
613 /* Start single DAC conversion on both DACs */
614 #define RtdDacBothUpdate(dev) \
615 writew(0, devpriv->las0+LAS0_DAC)
616
617 /* Set DAC output type and range */
618 #define RtdDacRange(dev, n, v) \
619 writew((v) & 7, devpriv->las0 \
620 +(((n) == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL))
621
622 /* Reset DAC FIFO */
623 #define RtdDacClearFifo(dev, n) \
624 writel(0, devpriv->las0+(((n) == 0) ? LAS0_DAC1_RESET : \
625 LAS0_DAC2_RESET))
626
627 /* Set source for DMA 0 (write only, shadow?) */
628 #define RtdDma0Source(dev, n) \
629 writel((n) & 0xf, devpriv->las0+LAS0_DMA0_SRC)
630
631 /* Set source for DMA 1 (write only, shadow?) */
632 #define RtdDma1Source(dev, n) \
633 writel((n) & 0xf, devpriv->las0+LAS0_DMA1_SRC)
634
635 /* Reset board state for DMA 0 */
636 #define RtdDma0Reset(dev) \
637 writel(0, devpriv->las0+LAS0_DMA0_RESET)
638
639 /* Reset board state for DMA 1 */
640 #define RtdDma1Reset(dev) \
641 writel(0, devpriv->las0+LAS0_DMA1_SRC)
642
643 /* PLX9080 interrupt mask and status */
644 #define RtdPlxInterruptRead(dev) \
645 readl(devpriv->lcfg+LCFG_ITCSR)
646 #define RtdPlxInterruptWrite(dev, v) \
647 writel(v, devpriv->lcfg+LCFG_ITCSR)
648
649 /* Set mode for DMA 0 */
650 #define RtdDma0Mode(dev, m) \
651 writel((m), devpriv->lcfg+LCFG_DMAMODE0)
652
653 /* Set PCI address for DMA 0 */
654 #define RtdDma0PciAddr(dev, a) \
655 writel((a), devpriv->lcfg+LCFG_DMAPADR0)
656
657 /* Set local address for DMA 0 */
658 #define RtdDma0LocalAddr(dev, a) \
659 writel((a), devpriv->lcfg+LCFG_DMALADR0)
660
661 /* Set byte count for DMA 0 */
662 #define RtdDma0Count(dev, c) \
663 writel((c), devpriv->lcfg+LCFG_DMASIZ0)
664
665 /* Set next descriptor for DMA 0 */
666 #define RtdDma0Next(dev, a) \
667 writel((a), devpriv->lcfg+LCFG_DMADPR0)
668
669 /* Set mode for DMA 1 */
670 #define RtdDma1Mode(dev, m) \
671 writel((m), devpriv->lcfg+LCFG_DMAMODE1)
672
673 /* Set PCI address for DMA 1 */
674 #define RtdDma1PciAddr(dev, a) \
675 writel((a), devpriv->lcfg+LCFG_DMAADR1)
676
677 /* Set local address for DMA 1 */
678 #define RtdDma1LocalAddr(dev, a) \
679 writel((a), devpriv->lcfg+LCFG_DMALADR1)
680
681 /* Set byte count for DMA 1 */
682 #define RtdDma1Count(dev, c) \
683 writel((c), devpriv->lcfg+LCFG_DMASIZ1)
684
685 /* Set next descriptor for DMA 1 */
686 #define RtdDma1Next(dev, a) \
687 writel((a), devpriv->lcfg+LCFG_DMADPR1)
688
689 /* Set control for DMA 0 (write only, shadow?) */
690 #define RtdDma0Control(dev, n) \
691 writeb(devpriv->dma0Control = (n), devpriv->lcfg+LCFG_DMACSR0)
692
693 /* Get status for DMA 0 */
694 #define RtdDma0Status(dev) \
695 readb(devpriv->lcfg+LCFG_DMACSR0)
696
697 /* Set control for DMA 1 (write only, shadow?) */
698 #define RtdDma1Control(dev, n) \
699 writeb(devpriv->dma1Control = (n), devpriv->lcfg+LCFG_DMACSR1)
700
701 /* Get status for DMA 1 */
702 #define RtdDma1Status(dev) \
703 readb(devpriv->lcfg+LCFG_DMACSR1)
704
705 /*
706 Given a desired period and the clock period (both in ns),
707 return the proper counter value (divider-1).
708 Sets the original period to be the true value.
709 Note: you have to check if the value is larger than the counter range!
710 */
711 static int rtd_ns_to_timer_base(unsigned int *nanosec, /* desired period (in ns) */
712 int round_mode, int base)
713 { /* clock period (in ns) */
714 int divider;
715
716 switch (round_mode) {
717 case TRIG_ROUND_NEAREST:
718 default:
719 divider = (*nanosec + base / 2) / base;
720 break;
721 case TRIG_ROUND_DOWN:
722 divider = (*nanosec) / base;
723 break;
724 case TRIG_ROUND_UP:
725 divider = (*nanosec + base - 1) / base;
726 break;
727 }
728 if (divider < 2)
729 divider = 2; /* min is divide by 2 */
730
731 /* Note: we don't check for max, because different timers
732 have different ranges */
733
734 *nanosec = base * divider;
735 return divider - 1; /* countdown is divisor+1 */
736 }
737
738 /*
739 Given a desired period (in ns),
740 return the proper counter value (divider-1) for the internal clock.
741 Sets the original period to be the true value.
742 */
743 static int rtd_ns_to_timer(unsigned int *ns, int round_mode)
744 {
745 return rtd_ns_to_timer_base(ns, round_mode, RTD_CLOCK_BASE);
746 }
747
748 /*
749 Convert a single comedi channel-gain entry to a RTD520 table entry
750 */
751 static unsigned short rtdConvertChanGain(struct comedi_device *dev,
752 unsigned int comediChan, int chanIndex)
753 { /* index in channel list */
754 unsigned int chan, range, aref;
755 unsigned short r = 0;
756
757 chan = CR_CHAN(comediChan);
758 range = CR_RANGE(comediChan);
759 aref = CR_AREF(comediChan);
760
761 r |= chan & 0xf;
762
763 /* Note: we also setup the channel list bipolar flag array */
764 if (range < thisboard->range10Start) { /* first batch are +-5 */
765 r |= 0x000; /* +-5 range */
766 r |= (range & 0x7) << 4; /* gain */
767 CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
768 } else if (range < thisboard->rangeUniStart) { /* second batch are +-10 */
769 r |= 0x100; /* +-10 range */
770 /* gain */
771 r |= ((range - thisboard->range10Start) & 0x7) << 4;
772 CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
773 } else { /* last batch is +10 */
774 r |= 0x200; /* +10 range */
775 /* gain */
776 r |= ((range - thisboard->rangeUniStart) & 0x7) << 4;
777 CHAN_ARRAY_CLEAR(devpriv->chanBipolar, chanIndex);
778 }
779
780 switch (aref) {
781 case AREF_GROUND: /* on-board ground */
782 break;
783
784 case AREF_COMMON:
785 r |= 0x80; /* ref external analog common */
786 break;
787
788 case AREF_DIFF:
789 r |= 0x400; /* differential inputs */
790 break;
791
792 case AREF_OTHER: /* ??? */
793 break;
794 }
795 /*printk ("chan=%d r=%d a=%d -> 0x%x\n",
796 chan, range, aref, r); */
797 return r;
798 }
799
800 /*
801 Setup the channel-gain table from a comedi list
802 */
803 static void rtd_load_channelgain_list(struct comedi_device *dev,
804 unsigned int n_chan, unsigned int *list)
805 {
806 if (n_chan > 1) { /* setup channel gain table */
807 int ii;
808 RtdClearCGT(dev);
809 RtdEnableCGT(dev, 1); /* enable table */
810 for (ii = 0; ii < n_chan; ii++) {
811 RtdWriteCGTable(dev, rtdConvertChanGain(dev, list[ii],
812 ii));
813 }
814 } else { /* just use the channel gain latch */
815 RtdEnableCGT(dev, 0); /* disable table, enable latch */
816 RtdWriteCGLatch(dev, rtdConvertChanGain(dev, list[0], 0));
817 }
818 }
819
820 /* determine fifo size by doing adc conversions until the fifo half
821 empty status flag clears */
822 static int rtd520_probe_fifo_depth(struct comedi_device *dev)
823 {
824 unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
825 unsigned i;
826 static const unsigned limit = 0x2000;
827 unsigned fifo_size = 0;
828
829 RtdAdcClearFifo(dev);
830 rtd_load_channelgain_list(dev, 1, &chanspec);
831 RtdAdcConversionSource(dev, 0); /* software */
832 /* convert samples */
833 for (i = 0; i < limit; ++i) {
834 unsigned fifo_status;
835 /* trigger conversion */
836 RtdAdcStart(dev);
837 udelay(1);
838 fifo_status = RtdFifoStatus(dev);
839 if ((fifo_status & FS_ADC_HEMPTY) == 0) {
840 fifo_size = 2 * i;
841 break;
842 }
843 }
844 if (i == limit) {
845 printk(KERN_INFO "\ncomedi: %s: failed to probe fifo size.\n",
846 DRV_NAME);
847 return -EIO;
848 }
849 RtdAdcClearFifo(dev);
850 if (fifo_size != 0x400 && fifo_size != 0x2000) {
851 printk
852 (KERN_INFO "\ncomedi: %s: unexpected fifo size of %i, expected 1024 or 8192.\n",
853 DRV_NAME, fifo_size);
854 return -EIO;
855 }
856 return fifo_size;
857 }
858
859 /*
860 "instructions" read/write data in "one-shot" or "software-triggered"
861 mode (simplest case).
862 This doesn't use interrupts.
863
864 Note, we don't do any settling delays. Use a instruction list to
865 select, delay, then read.
866 */
867 static int rtd_ai_rinsn(struct comedi_device *dev,
868 struct comedi_subdevice *s, struct comedi_insn *insn,
869 unsigned int *data)
870 {
871 int n, ii;
872 int stat;
873
874 /* clear any old fifo data */
875 RtdAdcClearFifo(dev);
876
877 /* write channel to multiplexer and clear channel gain table */
878 rtd_load_channelgain_list(dev, 1, &insn->chanspec);
879
880 /* set conversion source */
881 RtdAdcConversionSource(dev, 0); /* software */
882
883 /* convert n samples */
884 for (n = 0; n < insn->n; n++) {
885 s16 d;
886 /* trigger conversion */
887 RtdAdcStart(dev);
888
889 for (ii = 0; ii < RTD_ADC_TIMEOUT; ++ii) {
890 stat = RtdFifoStatus(dev);
891 if (stat & FS_ADC_NOT_EMPTY) /* 1 -> not empty */
892 break;
893 WAIT_QUIETLY;
894 }
895 if (ii >= RTD_ADC_TIMEOUT) {
896 DPRINTK
897 ("rtd520: Error: ADC never finished! FifoStatus=0x%x\n",
898 stat ^ 0x6666);
899 return -ETIMEDOUT;
900 }
901
902 /* read data */
903 d = RtdAdcFifoGet(dev); /* get 2s comp value */
904 /*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */
905 d = d >> 3; /* low 3 bits are marker lines */
906 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, 0))
907 /* convert to comedi unsigned data */
908 data[n] = d + 2048;
909 else
910 data[n] = d;
911 }
912
913 /* return the number of samples read/written */
914 return n;
915 }
916
917 /*
918 Get what we know is there.... Fast!
919 This uses 1/2 the bus cycles of read_dregs (below).
920
921 The manual claims that we can do a lword read, but it doesn't work here.
922 */
923 static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
924 int count)
925 {
926 int ii;
927
928 for (ii = 0; ii < count; ii++) {
929 short sample;
930 s16 d;
931
932 if (0 == devpriv->aiCount) { /* done */
933 d = RtdAdcFifoGet(dev); /* Read N and discard */
934 continue;
935 }
936 #if 0
937 if (0 == (RtdFifoStatus(dev) & FS_ADC_NOT_EMPTY)) { /* DEBUG */
938 DPRINTK("comedi: READ OOPS on %d of %d\n", ii + 1,
939 count);
940 break;
941 }
942 #endif
943 d = RtdAdcFifoGet(dev); /* get 2s comp value */
944
945 d = d >> 3; /* low 3 bits are marker lines */
946 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
947 /* convert to comedi unsigned data */
948 sample = d + 2048;
949 } else
950 sample = d;
951
952 if (!comedi_buf_put(s->async, sample))
953 return -1;
954
955 if (devpriv->aiCount > 0) /* < 0, means read forever */
956 devpriv->aiCount--;
957 }
958 return 0;
959 }
960
961 /*
962 unknown amout of data is waiting in fifo.
963 */
964 static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
965 {
966 while (RtdFifoStatus(dev) & FS_ADC_NOT_EMPTY) { /* 1 -> not empty */
967 short sample;
968 s16 d = RtdAdcFifoGet(dev); /* get 2s comp value */
969
970 if (0 == devpriv->aiCount) { /* done */
971 continue; /* read rest */
972 }
973
974 d = d >> 3; /* low 3 bits are marker lines */
975 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
976 /* convert to comedi unsigned data */
977 sample = d + 2048;
978 } else
979 sample = d;
980
981 if (!comedi_buf_put(s->async, sample))
982 return -1;
983
984 if (devpriv->aiCount > 0) /* < 0, means read forever */
985 devpriv->aiCount--;
986 }
987 return 0;
988 }
989
990 #ifdef USE_DMA
991 /*
992 Terminate a DMA transfer and wait for everything to quiet down
993 */
994 void abort_dma(struct comedi_device *dev, unsigned int channel)
995 { /* DMA channel 0, 1 */
996 unsigned long dma_cs_addr; /* the control/status register */
997 uint8_t status;
998 unsigned int ii;
999 /* unsigned long flags; */
1000
1001 dma_cs_addr = (unsigned long)devpriv->lcfg
1002 + ((channel == 0) ? LCFG_DMACSR0 : LCFG_DMACSR1);
1003
1004 /* spinlock for plx dma control/status reg */
1005 /* spin_lock_irqsave( &dev->spinlock, flags ); */
1006
1007 /* abort dma transfer if necessary */
1008 status = readb(dma_cs_addr);
1009 if ((status & PLX_DMA_EN_BIT) == 0) { /* not enabled (Error?) */
1010 DPRINTK("rtd520: AbortDma on non-active channel %d (0x%x)\n",
1011 channel, status);
1012 goto abortDmaExit;
1013 }
1014
1015 /* wait to make sure done bit is zero (needed?) */
1016 for (ii = 0; (status & PLX_DMA_DONE_BIT) && ii < RTD_DMA_TIMEOUT; ii++) {
1017 WAIT_QUIETLY;
1018 status = readb(dma_cs_addr);
1019 }
1020 if (status & PLX_DMA_DONE_BIT) {
1021 printk("rtd520: Timeout waiting for dma %i done clear\n",
1022 channel);
1023 goto abortDmaExit;
1024 }
1025
1026 /* disable channel (required) */
1027 writeb(0, dma_cs_addr);
1028 udelay(1); /* needed?? */
1029 /* set abort bit for channel */
1030 writeb(PLX_DMA_ABORT_BIT, dma_cs_addr);
1031
1032 /* wait for dma done bit to be set */
1033 status = readb(dma_cs_addr);
1034 for (ii = 0;
1035 (status & PLX_DMA_DONE_BIT) == 0 && ii < RTD_DMA_TIMEOUT; ii++) {
1036 status = readb(dma_cs_addr);
1037 WAIT_QUIETLY;
1038 }
1039 if ((status & PLX_DMA_DONE_BIT) == 0) {
1040 printk("rtd520: Timeout waiting for dma %i done set\n",
1041 channel);
1042 }
1043
1044 abortDmaExit:
1045 /* spin_unlock_irqrestore( &dev->spinlock, flags ); */
1046 }
1047
1048 /*
1049 Process what is in the DMA transfer buffer and pass to comedi
1050 Note: this is not re-entrant
1051 */
1052 static int ai_process_dma(struct comedi_device *dev, struct comedi_subdevice *s)
1053 {
1054 int ii, n;
1055 s16 *dp;
1056
1057 if (devpriv->aiCount == 0) /* transfer already complete */
1058 return 0;
1059
1060 dp = devpriv->dma0Buff[devpriv->dma0Offset];
1061 for (ii = 0; ii < devpriv->fifoLen / 2;) { /* convert samples */
1062 short sample;
1063
1064 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
1065 sample = (*dp >> 3) + 2048; /* convert to comedi unsigned data */
1066 else
1067 sample = *dp >> 3; /* low 3 bits are marker lines */
1068
1069 *dp++ = sample; /* put processed value back */
1070
1071 if (++s->async->cur_chan >= s->async->cmd.chanlist_len)
1072 s->async->cur_chan = 0;
1073
1074 ++ii; /* number ready to transfer */
1075 if (devpriv->aiCount > 0) { /* < 0, means read forever */
1076 if (--devpriv->aiCount == 0) { /* done */
1077 /*DPRINTK ("rtd520: Final %d samples\n", ii); */
1078 break;
1079 }
1080 }
1081 }
1082
1083 /* now pass the whole array to the comedi buffer */
1084 dp = devpriv->dma0Buff[devpriv->dma0Offset];
1085 n = comedi_buf_write_alloc(s->async, ii * sizeof(s16));
1086 if (n < (ii * sizeof(s16))) { /* any residual is an error */
1087 DPRINTK("rtd520:ai_process_dma buffer overflow %d samples!\n",
1088 ii - (n / sizeof(s16)));
1089 s->async->events |= COMEDI_CB_ERROR;
1090 return -1;
1091 }
1092 comedi_buf_memcpy_to(s->async, 0, dp, n);
1093 comedi_buf_write_free(s->async, n);
1094
1095 /*
1096 * always at least 1 scan -- 1/2 FIFO is larger than our max scan list
1097 */
1098 s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOS;
1099
1100 if (++devpriv->dma0Offset >= DMA_CHAIN_COUNT) { /* next buffer */
1101 devpriv->dma0Offset = 0;
1102 }
1103 return 0;
1104 }
1105 #endif /* USE_DMA */
1106
1107 /*
1108 Handle all rtd520 interrupts.
1109 Runs atomically and is never re-entered.
1110 This is a "slow handler"; other interrupts may be active.
1111 The data conversion may someday happen in a "bottom half".
1112 */
1113 static irqreturn_t rtd_interrupt(int irq, /* interrupt number (ignored) */
1114 void *d)
1115 { /* our data *//* cpu context (ignored) */
1116 struct comedi_device *dev = d; /* must be called "dev" for devpriv */
1117 u16 status;
1118 u16 fifoStatus;
1119 struct comedi_subdevice *s = dev->subdevices + 0; /* analog in subdevice */
1120
1121 if (!dev->attached)
1122 return IRQ_NONE;
1123
1124 devpriv->intCount++; /* DEBUG statistics */
1125
1126 fifoStatus = RtdFifoStatus(dev);
1127 /* check for FIFO full, this automatically halts the ADC! */
1128 if (!(fifoStatus & FS_ADC_NOT_FULL)) { /* 0 -> full */
1129 DPRINTK("rtd520: FIFO full! fifo_status=0x%x\n", (fifoStatus ^ 0x6666) & 0x7777); /* should be all 0s */
1130 goto abortTransfer;
1131 }
1132 #ifdef USE_DMA
1133 if (devpriv->flags & DMA0_ACTIVE) { /* Check DMA */
1134 u32 istatus = RtdPlxInterruptRead(dev);
1135
1136 if (istatus & ICS_DMA0_A) {
1137 if (ai_process_dma(dev, s) < 0) {
1138 DPRINTK
1139 ("rtd520: comedi read buffer overflow (DMA) with %ld to go!\n",
1140 devpriv->aiCount);
1141 RtdDma0Control(dev,
1142 (devpriv->dma0Control &
1143 ~PLX_DMA_START_BIT)
1144 | PLX_CLEAR_DMA_INTR_BIT);
1145 goto abortTransfer;
1146 }
1147
1148 /*DPRINTK ("rtd520: DMA transfer: %ld to go, istatus %x\n",
1149 devpriv->aiCount, istatus); */
1150 RtdDma0Control(dev,
1151 (devpriv->
1152 dma0Control & ~PLX_DMA_START_BIT)
1153 | PLX_CLEAR_DMA_INTR_BIT);
1154 if (0 == devpriv->aiCount) { /* counted down */
1155 DPRINTK("rtd520: Samples Done (DMA).\n");
1156 goto transferDone;
1157 }
1158 comedi_event(dev, s);
1159 } else {
1160 /*DPRINTK ("rtd520: No DMA ready: istatus %x\n", istatus); */
1161 }
1162 }
1163 /* Fall through and check for other interrupt sources */
1164 #endif /* USE_DMA */
1165
1166 status = RtdInterruptStatus(dev);
1167 /* if interrupt was not caused by our board, or handled above */
1168 if (0 == status)
1169 return IRQ_HANDLED;
1170
1171 if (status & IRQM_ADC_ABOUT_CNT) { /* sample count -> read FIFO */
1172 /* since the priority interrupt controller may have queued a sample
1173 counter interrupt, even though we have already finished,
1174 we must handle the possibility that there is no data here */
1175 if (!(fifoStatus & FS_ADC_HEMPTY)) { /* 0 -> 1/2 full */
1176 /*DPRINTK("rtd520: Sample int, reading 1/2FIFO. fifo_status 0x%x\n",
1177 (fifoStatus ^ 0x6666) & 0x7777); */
1178 if (ai_read_n(dev, s, devpriv->fifoLen / 2) < 0) {
1179 DPRINTK
1180 ("rtd520: comedi read buffer overflow (1/2FIFO) with %ld to go!\n",
1181 devpriv->aiCount);
1182 goto abortTransfer;
1183 }
1184 if (0 == devpriv->aiCount) { /* counted down */
1185 DPRINTK("rtd520: Samples Done (1/2). fifo_status was 0x%x\n", (fifoStatus ^ 0x6666) & 0x7777); /* should be all 0s */
1186 goto transferDone;
1187 }
1188 comedi_event(dev, s);
1189 } else if (devpriv->transCount > 0) { /* read often */
1190 /*DPRINTK("rtd520: Sample int, reading %d fifo_status 0x%x\n",
1191 devpriv->transCount, (fifoStatus ^ 0x6666) & 0x7777); */
1192 if (fifoStatus & FS_ADC_NOT_EMPTY) { /* 1 -> not empty */
1193 if (ai_read_n(dev, s, devpriv->transCount) < 0) {
1194 DPRINTK
1195 ("rtd520: comedi read buffer overflow (N) with %ld to go!\n",
1196 devpriv->aiCount);
1197 goto abortTransfer;
1198 }
1199 if (0 == devpriv->aiCount) { /* counted down */
1200 DPRINTK
1201 ("rtd520: Samples Done (N). fifo_status was 0x%x\n",
1202 (fifoStatus ^ 0x6666) & 0x7777);
1203 goto transferDone;
1204 }
1205 comedi_event(dev, s);
1206 }
1207 } else { /* wait for 1/2 FIFO (old) */
1208 DPRINTK
1209 ("rtd520: Sample int. Wait for 1/2. fifo_status 0x%x\n",
1210 (fifoStatus ^ 0x6666) & 0x7777);
1211 }
1212 } else {
1213 DPRINTK("rtd520: unknown interrupt source!\n");
1214 }
1215
1216 if (0xffff & RtdInterruptOverrunStatus(dev)) { /* interrupt overrun */
1217 DPRINTK
1218 ("rtd520: Interrupt overrun with %ld to go! over_status=0x%x\n",
1219 devpriv->aiCount, 0xffff & RtdInterruptOverrunStatus(dev));
1220 goto abortTransfer;
1221 }
1222
1223 /* clear the interrupt */
1224 RtdInterruptClearMask(dev, status);
1225 RtdInterruptClear(dev);
1226 return IRQ_HANDLED;
1227
1228 abortTransfer:
1229 RtdAdcClearFifo(dev); /* clears full flag */
1230 s->async->events |= COMEDI_CB_ERROR;
1231 devpriv->aiCount = 0; /* stop and don't transfer any more */
1232 /* fall into transferDone */
1233
1234 transferDone:
1235 RtdPacerStopSource(dev, 0); /* stop on SOFTWARE stop */
1236 RtdPacerStop(dev); /* Stop PACER */
1237 RtdAdcConversionSource(dev, 0); /* software trigger only */
1238 RtdInterruptMask(dev, 0); /* mask out SAMPLE */
1239 #ifdef USE_DMA
1240 if (devpriv->flags & DMA0_ACTIVE) {
1241 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1242 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1243 abort_dma(dev, 0);
1244 devpriv->flags &= ~DMA0_ACTIVE;
1245 /* if Using DMA, then we should have read everything by now */
1246 if (devpriv->aiCount > 0) {
1247 DPRINTK("rtd520: Lost DMA data! %ld remain\n",
1248 devpriv->aiCount);
1249 }
1250 }
1251 #endif /* USE_DMA */
1252
1253 if (devpriv->aiCount > 0) { /* there shouldn't be anything left */
1254 fifoStatus = RtdFifoStatus(dev);
1255 DPRINTK("rtd520: Finishing up. %ld remain, fifoStat=%x\n", devpriv->aiCount, (fifoStatus ^ 0x6666) & 0x7777); /* should read all 0s */
1256 ai_read_dregs(dev, s); /* read anything left in FIFO */
1257 }
1258
1259 s->async->events |= COMEDI_CB_EOA; /* signal end to comedi */
1260 comedi_event(dev, s);
1261
1262 /* clear the interrupt */
1263 status = RtdInterruptStatus(dev);
1264 RtdInterruptClearMask(dev, status);
1265 RtdInterruptClear(dev);
1266
1267 fifoStatus = RtdFifoStatus(dev); /* DEBUG */
1268 DPRINTK
1269 ("rtd520: Acquisition complete. %ld ints, intStat=%x, overStat=%x\n",
1270 devpriv->intCount, status,
1271 0xffff & RtdInterruptOverrunStatus(dev));
1272
1273 return IRQ_HANDLED;
1274 }
1275
1276 #if 0
1277 /*
1278 return the number of samples available
1279 */
1280 static int rtd_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1281 {
1282 /* TODO: This needs to mask interrupts, read_dregs, and then re-enable */
1283 /* Not sure what to do if DMA is active */
1284 return s->async->buf_write_count - s->async->buf_read_count;
1285 }
1286 #endif
1287
1288 /*
1289 cmdtest tests a particular command to see if it is valid.
1290 Using the cmdtest ioctl, a user can create a valid cmd
1291 and then have it executed by the cmd ioctl (asyncronously).
1292
1293 cmdtest returns 1,2,3,4 or 0, depending on which tests
1294 the command passes.
1295 */
1296
1297 static int rtd_ai_cmdtest(struct comedi_device *dev,
1298 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1299 {
1300 int err = 0;
1301 int tmp;
1302
1303 /* step 1: make sure trigger sources are trivially valid */
1304
1305 tmp = cmd->start_src;
1306 cmd->start_src &= TRIG_NOW;
1307 if (!cmd->start_src || tmp != cmd->start_src)
1308 err++;
1309
1310 tmp = cmd->scan_begin_src;
1311 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
1312 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1313 err++;
1314
1315
1316 tmp = cmd->convert_src;
1317 cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
1318 if (!cmd->convert_src || tmp != cmd->convert_src)
1319 err++;
1320
1321
1322 tmp = cmd->scan_end_src;
1323 cmd->scan_end_src &= TRIG_COUNT;
1324 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1325 err++;
1326
1327
1328 tmp = cmd->stop_src;
1329 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
1330 if (!cmd->stop_src || tmp != cmd->stop_src)
1331 err++;
1332
1333
1334 if (err)
1335 return 1;
1336
1337 /* step 2: make sure trigger sources are unique
1338 and mutually compatible */
1339 /* note that mutual compatibility is not an issue here */
1340 if (cmd->scan_begin_src != TRIG_TIMER &&
1341 cmd->scan_begin_src != TRIG_EXT) {
1342 err++;
1343 }
1344 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
1345 err++;
1346
1347 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
1348 err++;
1349
1350 if (err)
1351 return 2;
1352
1353 /* step 3: make sure arguments are trivially compatible */
1354
1355 if (cmd->start_arg != 0) {
1356 cmd->start_arg = 0;
1357 err++;
1358 }
1359
1360 if (cmd->scan_begin_src == TRIG_TIMER) {
1361 /* Note: these are time periods, not actual rates */
1362 if (1 == cmd->chanlist_len) { /* no scanning */
1363 if (cmd->scan_begin_arg < RTD_MAX_SPEED_1) {
1364 cmd->scan_begin_arg = RTD_MAX_SPEED_1;
1365 rtd_ns_to_timer(&cmd->scan_begin_arg,
1366 TRIG_ROUND_UP);
1367 err++;
1368 }
1369 if (cmd->scan_begin_arg > RTD_MIN_SPEED_1) {
1370 cmd->scan_begin_arg = RTD_MIN_SPEED_1;
1371 rtd_ns_to_timer(&cmd->scan_begin_arg,
1372 TRIG_ROUND_DOWN);
1373 err++;
1374 }
1375 } else {
1376 if (cmd->scan_begin_arg < RTD_MAX_SPEED) {
1377 cmd->scan_begin_arg = RTD_MAX_SPEED;
1378 rtd_ns_to_timer(&cmd->scan_begin_arg,
1379 TRIG_ROUND_UP);
1380 err++;
1381 }
1382 if (cmd->scan_begin_arg > RTD_MIN_SPEED) {
1383 cmd->scan_begin_arg = RTD_MIN_SPEED;
1384 rtd_ns_to_timer(&cmd->scan_begin_arg,
1385 TRIG_ROUND_DOWN);
1386 err++;
1387 }
1388 }
1389 } else {
1390 /* external trigger */
1391 /* should be level/edge, hi/lo specification here */
1392 /* should specify multiple external triggers */
1393 if (cmd->scan_begin_arg > 9) {
1394 cmd->scan_begin_arg = 9;
1395 err++;
1396 }
1397 }
1398 if (cmd->convert_src == TRIG_TIMER) {
1399 if (1 == cmd->chanlist_len) { /* no scanning */
1400 if (cmd->convert_arg < RTD_MAX_SPEED_1) {
1401 cmd->convert_arg = RTD_MAX_SPEED_1;
1402 rtd_ns_to_timer(&cmd->convert_arg,
1403 TRIG_ROUND_UP);
1404 err++;
1405 }
1406 if (cmd->convert_arg > RTD_MIN_SPEED_1) {
1407 cmd->convert_arg = RTD_MIN_SPEED_1;
1408 rtd_ns_to_timer(&cmd->convert_arg,
1409 TRIG_ROUND_DOWN);
1410 err++;
1411 }
1412 } else {
1413 if (cmd->convert_arg < RTD_MAX_SPEED) {
1414 cmd->convert_arg = RTD_MAX_SPEED;
1415 rtd_ns_to_timer(&cmd->convert_arg,
1416 TRIG_ROUND_UP);
1417 err++;
1418 }
1419 if (cmd->convert_arg > RTD_MIN_SPEED) {
1420 cmd->convert_arg = RTD_MIN_SPEED;
1421 rtd_ns_to_timer(&cmd->convert_arg,
1422 TRIG_ROUND_DOWN);
1423 err++;
1424 }
1425 }
1426 } else {
1427 /* external trigger */
1428 /* see above */
1429 if (cmd->convert_arg > 9) {
1430 cmd->convert_arg = 9;
1431 err++;
1432 }
1433 }
1434
1435 #if 0
1436 if (cmd->scan_end_arg != cmd->chanlist_len) {
1437 cmd->scan_end_arg = cmd->chanlist_len;
1438 err++;
1439 }
1440 #endif
1441 if (cmd->stop_src == TRIG_COUNT) {
1442 /* TODO check for rounding error due to counter wrap */
1443
1444 } else {
1445 /* TRIG_NONE */
1446 if (cmd->stop_arg != 0) {
1447 cmd->stop_arg = 0;
1448 err++;
1449 }
1450 }
1451
1452 if (err)
1453 return 3;
1454
1455
1456 /* step 4: fix up any arguments */
1457
1458 if (cmd->chanlist_len > RTD_MAX_CHANLIST) {
1459 cmd->chanlist_len = RTD_MAX_CHANLIST;
1460 err++;
1461 }
1462 if (cmd->scan_begin_src == TRIG_TIMER) {
1463 tmp = cmd->scan_begin_arg;
1464 rtd_ns_to_timer(&cmd->scan_begin_arg,
1465 cmd->flags & TRIG_ROUND_MASK);
1466 if (tmp != cmd->scan_begin_arg)
1467 err++;
1468
1469 }
1470 if (cmd->convert_src == TRIG_TIMER) {
1471 tmp = cmd->convert_arg;
1472 rtd_ns_to_timer(&cmd->convert_arg,
1473 cmd->flags & TRIG_ROUND_MASK);
1474 if (tmp != cmd->convert_arg)
1475 err++;
1476
1477 if (cmd->scan_begin_src == TRIG_TIMER
1478 && (cmd->scan_begin_arg
1479 < (cmd->convert_arg * cmd->scan_end_arg))) {
1480 cmd->scan_begin_arg =
1481 cmd->convert_arg * cmd->scan_end_arg;
1482 err++;
1483 }
1484 }
1485
1486 if (err)
1487 return 4;
1488
1489 return 0;
1490 }
1491
1492 /*
1493 Execute a analog in command with many possible triggering options.
1494 The data get stored in the async structure of the subdevice.
1495 This is usually done by an interrupt handler.
1496 Userland gets to the data using read calls.
1497 */
1498 static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1499 {
1500 struct comedi_cmd *cmd = &s->async->cmd;
1501 int timer;
1502
1503 /* stop anything currently running */
1504 RtdPacerStopSource(dev, 0); /* stop on SOFTWARE stop */
1505 RtdPacerStop(dev); /* make sure PACER is stopped */
1506 RtdAdcConversionSource(dev, 0); /* software trigger only */
1507 RtdInterruptMask(dev, 0);
1508 #ifdef USE_DMA
1509 if (devpriv->flags & DMA0_ACTIVE) { /* cancel anything running */
1510 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1511 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1512 abort_dma(dev, 0);
1513 devpriv->flags &= ~DMA0_ACTIVE;
1514 if (RtdPlxInterruptRead(dev) & ICS_DMA0_A) { /*clear pending int */
1515 RtdDma0Control(dev, PLX_CLEAR_DMA_INTR_BIT);
1516 }
1517 }
1518 RtdDma0Reset(dev); /* reset onboard state */
1519 #endif /* USE_DMA */
1520 RtdAdcClearFifo(dev); /* clear any old data */
1521 RtdInterruptOverrunClear(dev);
1522 devpriv->intCount = 0;
1523
1524 if (!dev->irq) { /* we need interrupts for this */
1525 DPRINTK("rtd520: ERROR! No interrupt available!\n");
1526 return -ENXIO;
1527 }
1528
1529 /* start configuration */
1530 /* load channel list and reset CGT */
1531 rtd_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
1532
1533 /* setup the common case and override if needed */
1534 if (cmd->chanlist_len > 1) {
1535 /*DPRINTK ("rtd520: Multi channel setup\n"); */
1536 RtdPacerStartSource(dev, 0); /* software triggers pacer */
1537 RtdBurstStartSource(dev, 1); /* PACER triggers burst */
1538 RtdAdcConversionSource(dev, 2); /* BURST triggers ADC */
1539 } else { /* single channel */
1540 /*DPRINTK ("rtd520: single channel setup\n"); */
1541 RtdPacerStartSource(dev, 0); /* software triggers pacer */
1542 RtdAdcConversionSource(dev, 1); /* PACER triggers ADC */
1543 }
1544 RtdAboutCounter(dev, devpriv->fifoLen / 2 - 1); /* 1/2 FIFO */
1545
1546 if (TRIG_TIMER == cmd->scan_begin_src) {
1547 /* scan_begin_arg is in nanoseconds */
1548 /* find out how many samples to wait before transferring */
1549 if (cmd->flags & TRIG_WAKE_EOS) {
1550 /* this may generate un-sustainable interrupt rates */
1551 /* the application is responsible for doing the right thing */
1552 devpriv->transCount = cmd->chanlist_len;
1553 devpriv->flags |= SEND_EOS;
1554 } else {
1555 /* arrange to transfer data periodically */
1556 devpriv->transCount
1557 =
1558 (TRANS_TARGET_PERIOD * cmd->chanlist_len) /
1559 cmd->scan_begin_arg;
1560 if (devpriv->transCount < cmd->chanlist_len) {
1561 /* transfer after each scan (and avoid 0) */
1562 devpriv->transCount = cmd->chanlist_len;
1563 } else { /* make a multiple of scan length */
1564 devpriv->transCount =
1565 (devpriv->transCount +
1566 cmd->chanlist_len - 1)
1567 / cmd->chanlist_len;
1568 devpriv->transCount *= cmd->chanlist_len;
1569 }
1570 devpriv->flags |= SEND_EOS;
1571 }
1572 if (devpriv->transCount >= (devpriv->fifoLen / 2)) {
1573 /* out of counter range, use 1/2 fifo instead */
1574 devpriv->transCount = 0;
1575 devpriv->flags &= ~SEND_EOS;
1576 } else {
1577 /* interrupt for each transfer */
1578 RtdAboutCounter(dev, devpriv->transCount - 1);
1579 }
1580
1581 DPRINTK
1582 ("rtd520: scanLen=%d transferCount=%d fifoLen=%d\n scanTime(ns)=%d flags=0x%x\n",
1583 cmd->chanlist_len, devpriv->transCount, devpriv->fifoLen,
1584 cmd->scan_begin_arg, devpriv->flags);
1585 } else { /* unknown timing, just use 1/2 FIFO */
1586 devpriv->transCount = 0;
1587 devpriv->flags &= ~SEND_EOS;
1588 }
1589 RtdPacerClockSource(dev, 1); /* use INTERNAL 8Mhz clock source */
1590 RtdAboutStopEnable(dev, 1); /* just interrupt, dont stop */
1591
1592 /* BUG??? these look like enumerated values, but they are bit fields */
1593
1594 /* First, setup when to stop */
1595 switch (cmd->stop_src) {
1596 case TRIG_COUNT: /* stop after N scans */
1597 devpriv->aiCount = cmd->stop_arg * cmd->chanlist_len;
1598 if ((devpriv->transCount > 0)
1599 && (devpriv->transCount > devpriv->aiCount)) {
1600 devpriv->transCount = devpriv->aiCount;
1601 }
1602 break;
1603
1604 case TRIG_NONE: /* stop when cancel is called */
1605 devpriv->aiCount = -1; /* read forever */
1606 break;
1607
1608 default:
1609 DPRINTK("rtd520: Warning! ignoring stop_src mode %d\n",
1610 cmd->stop_src);
1611 }
1612
1613 /* Scan timing */
1614 switch (cmd->scan_begin_src) {
1615 case TRIG_TIMER: /* periodic scanning */
1616 timer = rtd_ns_to_timer(&cmd->scan_begin_arg,
1617 TRIG_ROUND_NEAREST);
1618 /* set PACER clock */
1619 /*DPRINTK ("rtd520: loading %d into pacer\n", timer); */
1620 RtdPacerCounter(dev, timer);
1621
1622 break;
1623
1624 case TRIG_EXT:
1625 RtdPacerStartSource(dev, 1); /* EXTERNALy trigger pacer */
1626 break;
1627
1628 default:
1629 DPRINTK("rtd520: Warning! ignoring scan_begin_src mode %d\n",
1630 cmd->scan_begin_src);
1631 }
1632
1633 /* Sample timing within a scan */
1634 switch (cmd->convert_src) {
1635 case TRIG_TIMER: /* periodic */
1636 if (cmd->chanlist_len > 1) { /* only needed for multi-channel */
1637 timer = rtd_ns_to_timer(&cmd->convert_arg,
1638 TRIG_ROUND_NEAREST);
1639 /* setup BURST clock */
1640 /*DPRINTK ("rtd520: loading %d into burst\n", timer); */
1641 RtdBurstCounter(dev, timer);
1642 }
1643
1644 break;
1645
1646 case TRIG_EXT: /* external */
1647 RtdBurstStartSource(dev, 2); /* EXTERNALy trigger burst */
1648 break;
1649
1650 default:
1651 DPRINTK("rtd520: Warning! ignoring convert_src mode %d\n",
1652 cmd->convert_src);
1653 }
1654 /* end configuration */
1655
1656 /* This doesn't seem to work. There is no way to clear an interrupt
1657 that the priority controller has queued! */
1658 RtdInterruptClearMask(dev, ~0); /* clear any existing flags */
1659 RtdInterruptClear(dev);
1660
1661 /* TODO: allow multiple interrupt sources */
1662 if (devpriv->transCount > 0) { /* transfer every N samples */
1663 RtdInterruptMask(dev, IRQM_ADC_ABOUT_CNT);
1664 DPRINTK("rtd520: Transferring every %d\n", devpriv->transCount);
1665 } else { /* 1/2 FIFO transfers */
1666 #ifdef USE_DMA
1667 devpriv->flags |= DMA0_ACTIVE;
1668
1669 /* point to first transfer in ring */
1670 devpriv->dma0Offset = 0;
1671 RtdDma0Mode(dev, DMA_MODE_BITS);
1672 RtdDma0Next(dev, /* point to first block */
1673 devpriv->dma0Chain[DMA_CHAIN_COUNT - 1].next);
1674 RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL); /* set DMA trigger source */
1675
1676 RtdPlxInterruptWrite(dev, /* enable interrupt */
1677 RtdPlxInterruptRead(dev) | ICS_DMA0_E);
1678 /* Must be 2 steps. See PLX app note about "Starting a DMA transfer" */
1679 RtdDma0Control(dev, PLX_DMA_EN_BIT); /* enable DMA (clear INTR?) */
1680 RtdDma0Control(dev, PLX_DMA_EN_BIT | PLX_DMA_START_BIT); /*start DMA */
1681 DPRINTK("rtd520: Using DMA0 transfers. plxInt %x RtdInt %x\n",
1682 RtdPlxInterruptRead(dev), devpriv->intMask);
1683 #else /* USE_DMA */
1684 RtdInterruptMask(dev, IRQM_ADC_ABOUT_CNT);
1685 DPRINTK("rtd520: Transferring every 1/2 FIFO\n");
1686 #endif /* USE_DMA */
1687 }
1688
1689 /* BUG: start_src is ASSUMED to be TRIG_NOW */
1690 /* BUG? it seems like things are running before the "start" */
1691 RtdPacerStart(dev); /* Start PACER */
1692 return 0;
1693 }
1694
1695 /*
1696 Stop a running data acquisition.
1697 */
1698 static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1699 {
1700 u16 status;
1701
1702 RtdPacerStopSource(dev, 0); /* stop on SOFTWARE stop */
1703 RtdPacerStop(dev); /* Stop PACER */
1704 RtdAdcConversionSource(dev, 0); /* software trigger only */
1705 RtdInterruptMask(dev, 0);
1706 devpriv->aiCount = 0; /* stop and don't transfer any more */
1707 #ifdef USE_DMA
1708 if (devpriv->flags & DMA0_ACTIVE) {
1709 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1710 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1711 abort_dma(dev, 0);
1712 devpriv->flags &= ~DMA0_ACTIVE;
1713 }
1714 #endif /* USE_DMA */
1715 status = RtdInterruptStatus(dev);
1716 DPRINTK
1717 ("rtd520: Acquisition canceled. %ld ints, intStat=%x, overStat=%x\n",
1718 devpriv->intCount, status,
1719 0xffff & RtdInterruptOverrunStatus(dev));
1720 return 0;
1721 }
1722
1723 /*
1724 Output one (or more) analog values to a single port as fast as possible.
1725 */
1726 static int rtd_ao_winsn(struct comedi_device *dev,
1727 struct comedi_subdevice *s, struct comedi_insn *insn,
1728 unsigned int *data)
1729 {
1730 int i;
1731 int chan = CR_CHAN(insn->chanspec);
1732 int range = CR_RANGE(insn->chanspec);
1733
1734 /* Configure the output range (table index matches the range values) */
1735 RtdDacRange(dev, chan, range);
1736
1737 /* Writing a list of values to an AO channel is probably not
1738 * very useful, but that's how the interface is defined. */
1739 for (i = 0; i < insn->n; ++i) {
1740 int val = data[i] << 3;
1741 int stat = 0; /* initialize to avoid bogus warning */
1742 int ii;
1743
1744 /* VERIFY: comedi range and offset conversions */
1745
1746 if ((range > 1) /* bipolar */
1747 && (data[i] < 2048)) {
1748 /* offset and sign extend */
1749 val = (((int)data[i]) - 2048) << 3;
1750 } else { /* unipolor */
1751 val = data[i] << 3;
1752 }
1753
1754 DPRINTK
1755 ("comedi: rtd520 DAC chan=%d range=%d writing %d as 0x%x\n",
1756 chan, range, data[i], val);
1757
1758 /* a typical programming sequence */
1759 RtdDacFifoPut(dev, chan, val); /* put the value in */
1760 RtdDacUpdate(dev, chan); /* trigger the conversion */
1761
1762 devpriv->aoValue[chan] = data[i]; /* save for read back */
1763
1764 for (ii = 0; ii < RTD_DAC_TIMEOUT; ++ii) {
1765 stat = RtdFifoStatus(dev);
1766 /* 1 -> not empty */
1767 if (stat & ((0 == chan) ? FS_DAC1_NOT_EMPTY :
1768 FS_DAC2_NOT_EMPTY))
1769 break;
1770 WAIT_QUIETLY;
1771 }
1772 if (ii >= RTD_DAC_TIMEOUT) {
1773 DPRINTK
1774 ("rtd520: Error: DAC never finished! FifoStatus=0x%x\n",
1775 stat ^ 0x6666);
1776 return -ETIMEDOUT;
1777 }
1778 }
1779
1780 /* return the number of samples read/written */
1781 return i;
1782 }
1783
1784 /* AO subdevices should have a read insn as well as a write insn.
1785 * Usually this means copying a value stored in devpriv. */
1786 static int rtd_ao_rinsn(struct comedi_device *dev,
1787 struct comedi_subdevice *s, struct comedi_insn *insn,
1788 unsigned int *data)
1789 {
1790 int i;
1791 int chan = CR_CHAN(insn->chanspec);
1792
1793 for (i = 0; i < insn->n; i++)
1794 data[i] = devpriv->aoValue[chan];
1795
1796
1797 return i;
1798 }
1799
1800 /*
1801 Write a masked set of bits and the read back the port.
1802 We track what the bits should be (i.e. we don't read the port first).
1803
1804 DIO devices are slightly special. Although it is possible to
1805 * implement the insn_read/insn_write interface, it is much more
1806 * useful to applications if you implement the insn_bits interface.
1807 * This allows packed reading/writing of the DIO channels. The
1808 * comedi core can convert between insn_bits and insn_read/write
1809 */
1810 static int rtd_dio_insn_bits(struct comedi_device *dev,
1811 struct comedi_subdevice *s,
1812 struct comedi_insn *insn, unsigned int *data)
1813 {
1814 /* The insn data is a mask in data[0] and the new data
1815 * in data[1], each channel cooresponding to a bit. */
1816 if (data[0]) {
1817 s->state &= ~data[0];
1818 s->state |= data[0] & data[1];
1819
1820 /* Write out the new digital output lines */
1821 RtdDio0Write(dev, s->state);
1822 }
1823 /* on return, data[1] contains the value of the digital
1824 * input lines. */
1825 data[1] = RtdDio0Read(dev);
1826
1827 /*DPRINTK("rtd520:port_0 wrote: 0x%x read: 0x%x\n", s->state, data[1]); */
1828
1829 return insn->n;
1830 }
1831
1832 /*
1833 Configure one bit on a IO port as Input or Output (hence the name :-).
1834 */
1835 static int rtd_dio_insn_config(struct comedi_device *dev,
1836 struct comedi_subdevice *s,
1837 struct comedi_insn *insn, unsigned int *data)
1838 {
1839 int chan = CR_CHAN(insn->chanspec);
1840
1841 /* The input or output configuration of each digital line is
1842 * configured by a special insn_config instruction. chanspec
1843 * contains the channel to be changed, and data[0] contains the
1844 * value COMEDI_INPUT or COMEDI_OUTPUT. */
1845 switch (data[0]) {
1846 case INSN_CONFIG_DIO_OUTPUT:
1847 s->io_bits |= 1 << chan; /* 1 means Out */
1848 break;
1849 case INSN_CONFIG_DIO_INPUT:
1850 s->io_bits &= ~(1 << chan);
1851 break;
1852 case INSN_CONFIG_DIO_QUERY:
1853 data[1] =
1854 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1855 return insn->n;
1856 break;
1857 default:
1858 return -EINVAL;
1859 }
1860
1861 DPRINTK("rtd520: port_0_direction=0x%x (1 means out)\n", s->io_bits);
1862 /* TODO support digital match interrupts and strobes */
1863 RtdDioStatusWrite(dev, 0x01); /* make Dio0Ctrl point to direction */
1864 RtdDio0CtrlWrite(dev, s->io_bits); /* set direction 1 means Out */
1865 RtdDioStatusWrite(dev, 0); /* make Dio0Ctrl clear interrupts */
1866
1867 /* port1 can only be all input or all output */
1868
1869 /* there are also 2 user input lines and 2 user output lines */
1870
1871 return 1;
1872 }
1873
1874 static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1875 { /* board name and options flags */
1876 struct comedi_subdevice *s;
1877 struct pci_dev *pcidev;
1878 int ret;
1879 resource_size_t physLas0; /* configuration */
1880 resource_size_t physLas1; /* data area */
1881 resource_size_t physLcfg; /* PLX9080 */
1882 #ifdef USE_DMA
1883 int index;
1884 #endif
1885
1886 printk(KERN_INFO "comedi%d: rtd520 attaching.\n", dev->minor);
1887
1888 #if defined(CONFIG_COMEDI_DEBUG) && defined(USE_DMA)
1889 /* You can set this a load time: modprobe comedi comedi_debug=1 */
1890 if (0 == comedi_debug) /* force DMA debug printks */
1891 comedi_debug = 1;
1892 #endif
1893
1894 /*
1895 * Allocate the private structure area. alloc_private() is a
1896 * convenient macro defined in comedidev.h.
1897 */
1898 if (alloc_private(dev, sizeof(struct rtdPrivate)) < 0)
1899 return -ENOMEM;
1900
1901 /*
1902 * Probe the device to determine what device in the series it is.
1903 */
1904 for (pcidev = pci_get_device(PCI_VENDOR_ID_RTD, PCI_ANY_ID, NULL);
1905 pcidev != NULL;
1906 pcidev = pci_get_device(PCI_VENDOR_ID_RTD, PCI_ANY_ID, pcidev)) {
1907 int i;
1908
1909 if (it->options[0] || it->options[1]) {
1910 if (pcidev->bus->number != it->options[0]
1911 || PCI_SLOT(pcidev->devfn) != it->options[1]) {
1912 continue;
1913 }
1914 }
1915 for (i = 0; i < ARRAY_SIZE(rtd520Boards); ++i) {
1916 if (pcidev->device == rtd520Boards[i].device_id) {
1917 dev->board_ptr = &rtd520Boards[i];
1918 break;
1919 }
1920 }
1921 if (dev->board_ptr)
1922 break; /* found one */
1923 }
1924 if (!pcidev) {
1925 if (it->options[0] && it->options[1]) {
1926 printk(KERN_INFO "No RTD card at bus=%d slot=%d.\n",
1927 it->options[0], it->options[1]);
1928 } else {
1929 printk(KERN_INFO "No RTD card found.\n");
1930 }
1931 return -EIO;
1932 }
1933 devpriv->pci_dev = pcidev;
1934 dev->board_name = thisboard->name;
1935
1936 ret = comedi_pci_enable(pcidev, DRV_NAME);
1937 if (ret < 0) {
1938 printk(KERN_INFO "Failed to enable PCI device and request regions.\n");
1939 return ret;
1940 }
1941 devpriv->got_regions = 1;
1942
1943 /*
1944 * Initialize base addresses
1945 */
1946 /* Get the physical address from PCI config */
1947 physLas0 = pci_resource_start(devpriv->pci_dev, LAS0_PCIINDEX);
1948 physLas1 = pci_resource_start(devpriv->pci_dev, LAS1_PCIINDEX);
1949 physLcfg = pci_resource_start(devpriv->pci_dev, LCFG_PCIINDEX);
1950 /* Now have the kernel map this into memory */
1951 /* ASSUME page aligned */
1952 devpriv->las0 = ioremap_nocache(physLas0, LAS0_PCISIZE);
1953 devpriv->las1 = ioremap_nocache(physLas1, LAS1_PCISIZE);
1954 devpriv->lcfg = ioremap_nocache(physLcfg, LCFG_PCISIZE);
1955
1956 if (!devpriv->las0 || !devpriv->las1 || !devpriv->lcfg)
1957 return -ENOMEM;
1958
1959
1960 DPRINTK("%s: LAS0=%llx, LAS1=%llx, CFG=%llx.\n", dev->board_name,
1961 (unsigned long long)physLas0, (unsigned long long)physLas1,
1962 (unsigned long long)physLcfg);
1963 { /* The RTD driver does this */
1964 unsigned char pci_latency;
1965 u16 revision;
1966 /*uint32_t epld_version; */
1967
1968 pci_read_config_word(devpriv->pci_dev, PCI_REVISION_ID,
1969 &revision);
1970 DPRINTK("%s: PCI revision %d.\n", dev->board_name, revision);
1971
1972 pci_read_config_byte(devpriv->pci_dev,
1973 PCI_LATENCY_TIMER, &pci_latency);
1974 if (pci_latency < 32) {
1975 printk(KERN_INFO "%s: PCI latency changed from %d to %d\n",
1976 dev->board_name, pci_latency, 32);
1977 pci_write_config_byte(devpriv->pci_dev,
1978 PCI_LATENCY_TIMER, 32);
1979 } else {
1980 DPRINTK("rtd520: PCI latency = %d\n", pci_latency);
1981 }
1982
1983 /*
1984 * Undocumented EPLD version (doesn't match RTD driver results)
1985 */
1986 /*DPRINTK ("rtd520: Reading epld from %p\n",
1987 devpriv->las0+0);
1988 epld_version = readl (devpriv->las0+0);
1989 if ((epld_version & 0xF0) >> 4 == 0x0F) {
1990 DPRINTK("rtd520: pre-v8 EPLD. (%x)\n", epld_version);
1991 } else {
1992 DPRINTK("rtd520: EPLD version %x.\n", epld_version >> 4);
1993 } */
1994 }
1995
1996 /* Show board configuration */
1997 printk(KERN_INFO "%s:", dev->board_name);
1998
1999 ret = comedi_alloc_subdevices(dev, 4);
2000 if (ret)
2001 return ret;
2002
2003 s = dev->subdevices + 0;
2004 dev->read_subdev = s;
2005 /* analog input subdevice */
2006 s->type = COMEDI_SUBD_AI;
2007 s->subdev_flags =
2008 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
2009 s->n_chan = thisboard->aiChans;
2010 s->maxdata = (1 << thisboard->aiBits) - 1;
2011 if (thisboard->aiMaxGain <= 32)
2012 s->range_table = &rtd_ai_7520_range;
2013 else
2014 s->range_table = &rtd_ai_4520_range;
2015
2016 s->len_chanlist = RTD_MAX_CHANLIST; /* devpriv->fifoLen */
2017 s->insn_read = rtd_ai_rinsn;
2018 s->do_cmd = rtd_ai_cmd;
2019 s->do_cmdtest = rtd_ai_cmdtest;
2020 s->cancel = rtd_ai_cancel;
2021 /* s->poll = rtd_ai_poll; *//* not ready yet */
2022
2023 s = dev->subdevices + 1;
2024 /* analog output subdevice */
2025 s->type = COMEDI_SUBD_AO;
2026 s->subdev_flags = SDF_WRITABLE;
2027 s->n_chan = 2;
2028 s->maxdata = (1 << thisboard->aiBits) - 1;
2029 s->range_table = &rtd_ao_range;
2030 s->insn_write = rtd_ao_winsn;
2031 s->insn_read = rtd_ao_rinsn;
2032
2033 s = dev->subdevices + 2;
2034 /* digital i/o subdevice */
2035 s->type = COMEDI_SUBD_DIO;
2036 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
2037 /* we only support port 0 right now. Ignoring port 1 and user IO */
2038 s->n_chan = 8;
2039 s->maxdata = 1;
2040 s->range_table = &range_digital;
2041 s->insn_bits = rtd_dio_insn_bits;
2042 s->insn_config = rtd_dio_insn_config;
2043
2044 /* timer/counter subdevices (not currently supported) */
2045 s = dev->subdevices + 3;
2046 s->type = COMEDI_SUBD_COUNTER;
2047 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
2048 s->n_chan = 3;
2049 s->maxdata = 0xffff;
2050
2051 /* initialize board, per RTD spec */
2052 /* also, initialize shadow registers */
2053 RtdResetBoard(dev);
2054 udelay(100); /* needed? */
2055 RtdPlxInterruptWrite(dev, 0);
2056 RtdInterruptMask(dev, 0); /* and sets shadow */
2057 RtdInterruptClearMask(dev, ~0); /* and sets shadow */
2058 RtdInterruptClear(dev); /* clears bits set by mask */
2059 RtdInterruptOverrunClear(dev);
2060 RtdClearCGT(dev);
2061 RtdAdcClearFifo(dev);
2062 RtdDacClearFifo(dev, 0);
2063 RtdDacClearFifo(dev, 1);
2064 /* clear digital IO fifo */
2065 RtdDioStatusWrite(dev, 0); /* safe state, set shadow */
2066 RtdUtcCtrlPut(dev, 0, 0x30); /* safe state, set shadow */
2067 RtdUtcCtrlPut(dev, 1, 0x30); /* safe state, set shadow */
2068 RtdUtcCtrlPut(dev, 2, 0x30); /* safe state, set shadow */
2069 RtdUtcCtrlPut(dev, 3, 0); /* safe state, set shadow */
2070 /* TODO: set user out source ??? */
2071
2072 /* check if our interrupt is available and get it */
2073 ret = request_irq(devpriv->pci_dev->irq, rtd_interrupt,
2074 IRQF_SHARED, DRV_NAME, dev);
2075
2076 if (ret < 0) {
2077 printk("Could not get interrupt! (%u)\n",
2078 devpriv->pci_dev->irq);
2079 return ret;
2080 }
2081 dev->irq = devpriv->pci_dev->irq;
2082 printk(KERN_INFO "( irq=%u )", dev->irq);
2083
2084 ret = rtd520_probe_fifo_depth(dev);
2085 if (ret < 0)
2086 return ret;
2087
2088 devpriv->fifoLen = ret;
2089 printk("( fifoLen=%d )", devpriv->fifoLen);
2090
2091 #ifdef USE_DMA
2092 if (dev->irq > 0) {
2093 printk("( DMA buff=%d )\n", DMA_CHAIN_COUNT);
2094 /*
2095 * The PLX9080 has 2 DMA controllers, but there could be
2096 * 4 sources: ADC, digital, DAC1, and DAC2. Since only the
2097 * ADC supports cmd mode right now, this isn't an issue (yet)
2098 */
2099 devpriv->dma0Offset = 0;
2100
2101 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2102 devpriv->dma0Buff[index] =
2103 pci_alloc_consistent(devpriv->pci_dev,
2104 sizeof(u16) *
2105 devpriv->fifoLen / 2,
2106 &devpriv->
2107 dma0BuffPhysAddr[index]);
2108 if (devpriv->dma0Buff[index] == NULL) {
2109 ret = -ENOMEM;
2110 goto rtd_attach_die_error;
2111 }
2112 /*DPRINTK ("buff[%d] @ %p virtual, %x PCI\n",
2113 index,
2114 devpriv->dma0Buff[index],
2115 devpriv->dma0BuffPhysAddr[index]); */
2116 }
2117
2118 /*
2119 * setup DMA descriptor ring (use cpu_to_le32 for byte
2120 * ordering?)
2121 */
2122 devpriv->dma0Chain =
2123 pci_alloc_consistent(devpriv->pci_dev,
2124 sizeof(struct plx_dma_desc) *
2125 DMA_CHAIN_COUNT,
2126 &devpriv->dma0ChainPhysAddr);
2127 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2128 devpriv->dma0Chain[index].pci_start_addr =
2129 devpriv->dma0BuffPhysAddr[index];
2130 devpriv->dma0Chain[index].local_start_addr =
2131 DMALADDR_ADC;
2132 devpriv->dma0Chain[index].transfer_size =
2133 sizeof(u16) * devpriv->fifoLen / 2;
2134 devpriv->dma0Chain[index].next =
2135 (devpriv->dma0ChainPhysAddr + ((index +
2136 1) %
2137 (DMA_CHAIN_COUNT))
2138 * sizeof(devpriv->dma0Chain[0]))
2139 | DMA_TRANSFER_BITS;
2140 /*DPRINTK ("ring[%d] @%lx PCI: %x, local: %x, N: 0x%x, next: %x\n",
2141 index,
2142 ((long)devpriv->dma0ChainPhysAddr
2143 + (index * sizeof(devpriv->dma0Chain[0]))),
2144 devpriv->dma0Chain[index].pci_start_addr,
2145 devpriv->dma0Chain[index].local_start_addr,
2146 devpriv->dma0Chain[index].transfer_size,
2147 devpriv->dma0Chain[index].next); */
2148 }
2149
2150 if (devpriv->dma0Chain == NULL) {
2151 ret = -ENOMEM;
2152 goto rtd_attach_die_error;
2153 }
2154
2155 RtdDma0Mode(dev, DMA_MODE_BITS);
2156 /* set DMA trigger source */
2157 RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL);
2158 } else {
2159 printk(KERN_INFO "( no IRQ->no DMA )");
2160 }
2161 #endif /* USE_DMA */
2162
2163 if (dev->irq) { /* enable plx9080 interrupts */
2164 RtdPlxInterruptWrite(dev, ICS_PIE | ICS_PLIE);
2165 }
2166
2167 printk("\ncomedi%d: rtd520 driver attached.\n", dev->minor);
2168
2169 return 1;
2170
2171 #if 0
2172 /* hit an error, clean up memory and return ret */
2173 /* rtd_attach_die_error: */
2174 #ifdef USE_DMA
2175 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2176 if (NULL != devpriv->dma0Buff[index]) { /* free buffer memory */
2177 pci_free_consistent(devpriv->pci_dev,
2178 sizeof(u16) * devpriv->fifoLen / 2,
2179 devpriv->dma0Buff[index],
2180 devpriv->dma0BuffPhysAddr[index]);
2181 devpriv->dma0Buff[index] = NULL;
2182 }
2183 }
2184 if (NULL != devpriv->dma0Chain) {
2185 pci_free_consistent(devpriv->pci_dev,
2186 sizeof(struct plx_dma_desc)
2187 * DMA_CHAIN_COUNT,
2188 devpriv->dma0Chain,
2189 devpriv->dma0ChainPhysAddr);
2190 devpriv->dma0Chain = NULL;
2191 }
2192 #endif /* USE_DMA */
2193 /* subdevices and priv are freed by the core */
2194 if (dev->irq) {
2195 /* disable interrupt controller */
2196 RtdPlxInterruptWrite(dev, RtdPlxInterruptRead(dev)
2197 & ~(ICS_PLIE | ICS_DMA0_E | ICS_DMA1_E));
2198 free_irq(dev->irq, dev);
2199 }
2200
2201 /* release all regions that were allocated */
2202 if (devpriv->las0)
2203 iounmap(devpriv->las0);
2204
2205 if (devpriv->las1)
2206 iounmap(devpriv->las1);
2207
2208 if (devpriv->lcfg)
2209 iounmap(devpriv->lcfg);
2210
2211 if (devpriv->pci_dev)
2212 pci_dev_put(devpriv->pci_dev);
2213
2214 return ret;
2215 #endif
2216 }
2217
2218 static void rtd_detach(struct comedi_device *dev)
2219 {
2220 #ifdef USE_DMA
2221 int index;
2222 #endif
2223
2224 if (devpriv) {
2225 /* Shut down any board ops by resetting it */
2226 #ifdef USE_DMA
2227 if (devpriv->lcfg) {
2228 RtdDma0Control(dev, 0); /* disable DMA */
2229 RtdDma1Control(dev, 0); /* disable DMA */
2230 RtdPlxInterruptWrite(dev, ICS_PIE | ICS_PLIE);
2231 }
2232 #endif /* USE_DMA */
2233 if (devpriv->las0) {
2234 RtdResetBoard(dev);
2235 RtdInterruptMask(dev, 0);
2236 RtdInterruptClearMask(dev, ~0);
2237 RtdInterruptClear(dev); /* clears bits set by mask */
2238 }
2239 #ifdef USE_DMA
2240 /* release DMA */
2241 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2242 if (NULL != devpriv->dma0Buff[index]) {
2243 pci_free_consistent(devpriv->pci_dev,
2244 sizeof(u16) *
2245 devpriv->fifoLen / 2,
2246 devpriv->dma0Buff[index],
2247 devpriv->
2248 dma0BuffPhysAddr[index]);
2249 devpriv->dma0Buff[index] = NULL;
2250 }
2251 }
2252 if (NULL != devpriv->dma0Chain) {
2253 pci_free_consistent(devpriv->pci_dev,
2254 sizeof(struct plx_dma_desc) *
2255 DMA_CHAIN_COUNT, devpriv->dma0Chain,
2256 devpriv->dma0ChainPhysAddr);
2257 devpriv->dma0Chain = NULL;
2258 }
2259 #endif /* USE_DMA */
2260 if (dev->irq) {
2261 RtdPlxInterruptWrite(dev, RtdPlxInterruptRead(dev)
2262 & ~(ICS_PLIE | ICS_DMA0_E |
2263 ICS_DMA1_E));
2264 free_irq(dev->irq, dev);
2265 }
2266 if (devpriv->las0)
2267 iounmap(devpriv->las0);
2268 if (devpriv->las1)
2269 iounmap(devpriv->las1);
2270 if (devpriv->lcfg)
2271 iounmap(devpriv->lcfg);
2272 if (devpriv->pci_dev) {
2273 if (devpriv->got_regions)
2274 comedi_pci_disable(devpriv->pci_dev);
2275 pci_dev_put(devpriv->pci_dev);
2276 }
2277 }
2278 }
2279
2280 static struct comedi_driver rtd520_driver = {
2281 .driver_name = "rtd520",
2282 .module = THIS_MODULE,
2283 .attach = rtd_attach,
2284 .detach = rtd_detach,
2285 };
2286
2287 static int __devinit rtd520_pci_probe(struct pci_dev *dev,
2288 const struct pci_device_id *ent)
2289 {
2290 return comedi_pci_auto_config(dev, &rtd520_driver);
2291 }
2292
2293 static void __devexit rtd520_pci_remove(struct pci_dev *dev)
2294 {
2295 comedi_pci_auto_unconfig(dev);
2296 }
2297
2298 static DEFINE_PCI_DEVICE_TABLE(rtd520_pci_table) = {
2299 { PCI_DEVICE(PCI_VENDOR_ID_RTD, 0x7520) },
2300 { PCI_DEVICE(PCI_VENDOR_ID_RTD, 0x4520) },
2301 { 0 }
2302 };
2303 MODULE_DEVICE_TABLE(pci, rtd520_pci_table);
2304
2305 static struct pci_driver rtd520_pci_driver = {
2306 .name = "rtd520",
2307 .id_table = rtd520_pci_table,
2308 .probe = rtd520_pci_probe,
2309 .remove = __devexit_p(rtd520_pci_remove),
2310 };
2311 module_comedi_pci_driver(rtd520_driver, rtd520_pci_driver);
2312
2313 MODULE_AUTHOR("Comedi http://www.comedi.org");
2314 MODULE_DESCRIPTION("Comedi low-level driver");
2315 MODULE_LICENSE("GPL");
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