drivers/staging/et131x/et1310_phy.c

   1 /*
   2  * Agere Systems Inc.
   3  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4  *
   5  * Copyright * 2005 Agere Systems Inc.
   6  * All rights reserved.
   7  *   http://www.agere.com
   8  *
   9  *------------------------------------------------------------------------------
  10  *
  11  * et1310_phy.c - Routines for configuring and accessing the PHY
  12  *
  13  *------------------------------------------------------------------------------
  14  *
  15  * SOFTWARE LICENSE
  16  *
  17  * This software is provided subject to the following terms and conditions,
  18  * which you should read carefully before using the software.  Using this
  19  * software indicates your acceptance of these terms and conditions.  If you do
  20  * not agree with these terms and conditions, do not use the software.
  21  *
  22  * Copyright * 2005 Agere Systems Inc.
  23  * All rights reserved.
  24  *
  25  * Redistribution and use in source or binary forms, with or without
  26  * modifications, are permitted provided that the following conditions are met:
  27  *
  28  * . Redistributions of source code must retain the above copyright notice, this
  29  *    list of conditions and the following Disclaimer as comments in the code as
  30  *    well as in the documentation and/or other materials provided with the
  31  *    distribution.
  32  *
  33  * . Redistributions in binary form must reproduce the above copyright notice,
  34  *    this list of conditions and the following Disclaimer in the documentation
  35  *    and/or other materials provided with the distribution.
  36  *
  37  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  38  *    may be used to endorse or promote products derived from this software
  39  *    without specific prior written permission.
  40  *
  41  * Disclaimer
  42  *
  43  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  44  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  45  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  46  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  47  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  48  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  49  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  50  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  51  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  52  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  53  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  54  * DAMAGE.
  55  *
  56  */
  57
  58 #include "et131x_version.h"
  59 #include "et131x_defs.h"
  60
  61 #include <linux/pci.h>
  62 #include <linux/init.h>
  63 #include <linux/module.h>
  64 #include <linux/types.h>
  65 #include <linux/kernel.h>
  66
  67 #include <linux/sched.h>
  68 #include <linux/ptrace.h>
  69 #include <linux/ctype.h>
  70 #include <linux/string.h>
  71 #include <linux/timer.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/in.h>
  74 #include <linux/delay.h>
  75 #include <linux/io.h>
  76 #include <linux/bitops.h>
  77 #include <asm/system.h>
  78
  79 #include <linux/netdevice.h>
  80 #include <linux/etherdevice.h>
  81 #include <linux/skbuff.h>
  82 #include <linux/if_arp.h>
  83 #include <linux/ioport.h>
  84 #include <linux/random.h>
  85
  86 #include "et1310_phy.h"
  87
  88 #include "et131x_adapter.h"
  89
  90 #include "et1310_address_map.h"
  91 #include "et1310_tx.h"
  92 #include "et1310_rx.h"
  93
  94 #include "et131x.h"
  95
  96 /* Prototypes for functions with local scope */
  97 static void et131x_xcvr_init(struct et131x_adapter *etdev);
  98
  99 /**
 100  * PhyMiRead - Read from the PHY through the MII Interface on the MAC
 101  * @etdev: pointer to our private adapter structure
 102  * @xcvrAddr: the address of the transciever
 103  * @xcvrReg: the register to read
 104  * @value: pointer to a 16-bit value in which the value will be stored
 105  *
 106  * Returns 0 on success, errno on failure (as defined in errno.h)
 107  */
 108 int PhyMiRead(struct et131x_adapter *etdev, u8 xcvrAddr,
 109               u8 xcvrReg, u16 *value)
 110 {
 111         struct _MAC_t __iomem *mac = &etdev->regs->mac;
 112         int status = 0;
 113         u32 delay;
 114         u32 miiAddr;
 115         u32 miiCmd;
 116         u32 miiIndicator;
 117
 118         /* Save a local copy of the registers we are dealing with so we can
 119          * set them back
 120          */
 121         miiAddr = readl(&mac->mii_mgmt_addr);
 122         miiCmd = readl(&mac->mii_mgmt_cmd);
 123
 124         /* Stop the current operation */
 125         writel(0, &mac->mii_mgmt_cmd);
 126
 127         /* Set up the register we need to read from on the correct PHY */
 128         writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr);
 129
 130         /* Kick the read cycle off */
 131         delay = 0;
 132
 133         writel(0x1, &mac->mii_mgmt_cmd);
 134
 135         do {
 136                 udelay(50);
 137                 delay++;
 138                 miiIndicator = readl(&mac->mii_mgmt_indicator);
 139         } while ((miiIndicator & MGMT_WAIT) && delay < 50);
 140
 141         /* If we hit the max delay, we could not read the register */
 142         if (delay == 50) {
 143                 dev_warn(&etdev->pdev->dev,
 144                             "xcvrReg 0x%08x could not be read\n", xcvrReg);
 145                 dev_warn(&etdev->pdev->dev, "status is  0x%08x\n",
 146                             miiIndicator);
 147
 148                 status = -EIO;
 149         }
 150
 151         /* If we hit here we were able to read the register and we need to
 152          * return the value to the caller */
 153         *value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
 154
 155         /* Stop the read operation */
 156         writel(0, &mac->mii_mgmt_cmd);
 157
 158         /* set the registers we touched back to the state at which we entered
 159          * this function
 160          */
 161         writel(miiAddr, &mac->mii_mgmt_addr);
 162         writel(miiCmd, &mac->mii_mgmt_cmd);
 163
 164         return status;
 165 }
 166
 167 /**
 168  * MiWrite - Write to a PHY register through the MII interface of the MAC
 169  * @etdev: pointer to our private adapter structure
 170  * @xcvrReg: the register to read
 171  * @value: 16-bit value to write
 172  *
 173  * FIXME: one caller in netdev still
 174  *
 175  * Return 0 on success, errno on failure (as defined in errno.h)
 176  */
 177 int MiWrite(struct et131x_adapter *etdev, u8 xcvrReg, u16 value)
 178 {
 179         struct _MAC_t __iomem *mac = &etdev->regs->mac;
 180         int status = 0;
 181         u8 xcvrAddr = etdev->Stats.xcvr_addr;
 182         u32 delay;
 183         u32 miiAddr;
 184         u32 miiCmd;
 185         u32 miiIndicator;
 186
 187         /* Save a local copy of the registers we are dealing with so we can
 188          * set them back
 189          */
 190         miiAddr = readl(&mac->mii_mgmt_addr);
 191         miiCmd = readl(&mac->mii_mgmt_cmd);
 192
 193         /* Stop the current operation */
 194         writel(0, &mac->mii_mgmt_cmd);
 195
 196         /* Set up the register we need to write to on the correct PHY */
 197         writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr);
 198
 199         /* Add the value to write to the registers to the mac */
 200         writel(value, &mac->mii_mgmt_ctrl);
 201         delay = 0;
 202
 203         do {
 204                 udelay(50);
 205                 delay++;
 206                 miiIndicator = readl(&mac->mii_mgmt_indicator);
 207         } while ((miiIndicator & MGMT_BUSY) && delay < 100);
 208
 209         /* If we hit the max delay, we could not write the register */
 210         if (delay == 100) {
 211                 u16 TempValue;
 212
 213                 dev_warn(&etdev->pdev->dev,
 214                     "xcvrReg 0x%08x could not be written", xcvrReg);
 215                 dev_warn(&etdev->pdev->dev, "status is  0x%08x\n",
 216                             miiIndicator);
 217                 dev_warn(&etdev->pdev->dev, "command is  0x%08x\n",
 218                             readl(&mac->mii_mgmt_cmd));
 219
 220                 MiRead(etdev, xcvrReg, &TempValue);
 221
 222                 status = -EIO;
 223         }
 224         /* Stop the write operation */
 225         writel(0, &mac->mii_mgmt_cmd);
 226
 227         /* set the registers we touched back to the state at which we entered
 228          * this function
 229          */
 230         writel(miiAddr, &mac->mii_mgmt_addr);
 231         writel(miiCmd, &mac->mii_mgmt_cmd);
 232
 233         return status;
 234 }
 235
 236 /**
 237  * et131x_xcvr_find - Find the PHY ID
 238  * @etdev: pointer to our private adapter structure
 239  *
 240  * Returns 0 on success, errno on failure (as defined in errno.h)
 241  */
 242 int et131x_xcvr_find(struct et131x_adapter *etdev)
 243 {
 244         u8 xcvr_addr;
 245         u16 idr1;
 246         u16 idr2;
 247         u32 xcvr_id;
 248
 249         /* We need to get xcvr id and address we just get the first one */
 250         for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
 251                 /* Read the ID from the PHY */
 252                 PhyMiRead(etdev, xcvr_addr,
 253                           (u8) offsetof(struct mi_regs, idr1),
 254                           &idr1);
 255                 PhyMiRead(etdev, xcvr_addr,
 256                           (u8) offsetof(struct mi_regs, idr2),
 257                           &idr2);
 258
 259                 xcvr_id = (u32) ((idr1 << 16) | idr2);
 260
 261                 if (idr1 != 0 && idr1 != 0xffff) {
 262                         etdev->Stats.xcvr_id = xcvr_id;
 263                         etdev->Stats.xcvr_addr = xcvr_addr;
 264                         return 0;
 265                 }
 266         }
 267         return -ENODEV;
 268 }
 269
 270 void ET1310_PhyReset(struct et131x_adapter *etdev)
 271 {
 272         MiWrite(etdev, PHY_CONTROL, 0x8000);
 273 }
 274
 275 /**
 276  *      ET1310_PhyPowerDown     -       PHY power control
 277  *      @etdev: device to control
 278  *      @down: true for off/false for back on
 279  *
 280  *      one hundred, ten, one thousand megs
 281  *      How would you like to have your LAN accessed
 282  *      Can't you see that this code processed
 283  *      Phy power, phy power..
 284  */
 285
 286 void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down)
 287 {
 288         u16 data;
 289
 290         MiRead(etdev, PHY_CONTROL, &data);
 291         data &= ~0x0800;        /* Power UP */
 292         if (down) /* Power DOWN */
 293                 data |= 0x0800;
 294         MiWrite(etdev, PHY_CONTROL, data);
 295 }
 296
 297 /**
 298  *      ET130_PhyAutoNEg        -       autonegotiate control
 299  *      @etdev: device to control
 300  *      @enabe: autoneg on/off
 301  *
 302  *      Set up the autonegotiation state according to whether we will be
 303  *      negotiating the state or forcing a speed.
 304  */
 305
 306 static void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable)
 307 {
 308         u16 data;
 309
 310         MiRead(etdev, PHY_CONTROL, &data);
 311         data &= ~0x1000;        /* Autonegotiation OFF */
 312         if (enable)
 313                 data |= 0x1000;         /* Autonegotiation ON */
 314         MiWrite(etdev, PHY_CONTROL, data);
 315 }
 316
 317 /**
 318  *      ET130_PhyDuplexMode     -       duplex control
 319  *      @etdev: device to control
 320  *      @duplex: duplex on/off
 321  *
 322  *      Set up the duplex state on the PHY
 323  */
 324
 325 static void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, u16 duplex)
 326 {
 327         u16 data;
 328
 329         MiRead(etdev, PHY_CONTROL, &data);
 330         data &= ~0x100;         /* Set Half Duplex */
 331         if (duplex == TRUEPHY_DUPLEX_FULL)
 332                 data |= 0x100;  /* Set Full Duplex */
 333         MiWrite(etdev, PHY_CONTROL, data);
 334 }
 335
 336 /**
 337  *      ET130_PhySpeedSelect    -       speed control
 338  *      @etdev: device to control
 339  *      @duplex: duplex on/off
 340  *
 341  *      Set the speed of our PHY.
 342  */
 343
 344 static void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, u16 speed)
 345 {
 346         u16 data;
 347         static const u16 bits[3] = {0x0000, 0x2000, 0x0040};
 348
 349         /* Read the PHY control register */
 350         MiRead(etdev, PHY_CONTROL, &data);
 351         /* Clear all Speed settings (Bits 6, 13) */
 352         data &= ~0x2040;
 353         /* Write back the new speed */
 354         MiWrite(etdev, PHY_CONTROL, data | bits[speed]);
 355 }
 356
 357 /**
 358  *      ET1310_PhyLinkStatus    -       read link state
 359  *      @etdev: device to read
 360  *      @link_status: reported link state
 361  *      @autoneg: reported autonegotiation state (complete/incomplete/disabled)
 362  *      @linkspeed: returnedlink speed in use
 363  *      @duplex_mode: reported half/full duplex state
 364  *      @mdi_mdix: not yet working
 365  *      @masterslave: report whether we are master or slave
 366  *      @polarity: link polarity
 367  *
 368  *      I can read your lan like a magazine
 369  *      I see if your up
 370  *      I know your link speed
 371  *      I see all the setting that you'd rather keep
 372  */
 373
 374 static void ET1310_PhyLinkStatus(struct et131x_adapter *etdev,
 375                           u8 *link_status,
 376                           u32 *autoneg,
 377                           u32 *linkspeed,
 378                           u32 *duplex_mode,
 379                           u32 *mdi_mdix,
 380                           u32 *masterslave, u32 *polarity)
 381 {
 382         u16 mistatus = 0;
 383         u16 is1000BaseT = 0;
 384         u16 vmi_phystatus = 0;
 385         u16 control = 0;
 386
 387         MiRead(etdev, PHY_STATUS, &mistatus);
 388         MiRead(etdev, PHY_1000_STATUS, &is1000BaseT);
 389         MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus);
 390         MiRead(etdev, PHY_CONTROL, &control);
 391
 392         *link_status = (vmi_phystatus & 0x0040) ? 1 : 0;
 393         *autoneg = (control & 0x1000) ? ((vmi_phystatus & 0x0020) ?
 394                                             TRUEPHY_ANEG_COMPLETE :
 395                                             TRUEPHY_ANEG_NOT_COMPLETE) :
 396                     TRUEPHY_ANEG_DISABLED;
 397         *linkspeed = (vmi_phystatus & 0x0300) >> 8;
 398         *duplex_mode = (vmi_phystatus & 0x0080) >> 7;
 399         /* NOTE: Need to complete this */
 400         *mdi_mdix = 0;
 401
 402         *masterslave = (is1000BaseT & 0x4000) ?
 403                         TRUEPHY_CFG_MASTER : TRUEPHY_CFG_SLAVE;
 404         *polarity = (vmi_phystatus & 0x0400) ?
 405                         TRUEPHY_POLARITY_INVERTED : TRUEPHY_POLARITY_NORMAL;
 406 }
 407
 408 static void ET1310_PhyAndOrReg(struct et131x_adapter *etdev,
 409                         u16 regnum, u16 andMask, u16 orMask)
 410 {
 411         u16 reg;
 412
 413         MiRead(etdev, regnum, &reg);
 414         reg &= andMask;
 415         reg |= orMask;
 416         MiWrite(etdev, regnum, reg);
 417 }
 418
 419 /* Still used from _mac  for BIT_READ */
 420 void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, u16 action,
 421                            u16 regnum, u16 bitnum, u8 *value)
 422 {
 423         u16 reg;
 424         u16 mask = 0x0001 << bitnum;
 425
 426         /* Read the requested register */
 427         MiRead(etdev, regnum, &reg);
 428
 429         switch (action) {
 430         case TRUEPHY_BIT_READ:
 431                 *value = (reg & mask) >> bitnum;
 432                 break;
 433
 434         case TRUEPHY_BIT_SET:
 435                 MiWrite(etdev, regnum, reg | mask);
 436                 break;
 437
 438         case TRUEPHY_BIT_CLEAR:
 439                 MiWrite(etdev, regnum, reg & ~mask);
 440                 break;
 441
 442         default:
 443                 break;
 444         }
 445 }
 446
 447 void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev,
 448                                   u16 duplex)
 449 {
 450         u16 data;
 451
 452         /* Read the PHY 1000 Base-T Control Register */
 453         MiRead(etdev, PHY_1000_CONTROL, &data);
 454
 455         /* Clear Bits 8,9 */
 456         data &= ~0x0300;
 457
 458         switch (duplex) {
 459         case TRUEPHY_ADV_DUPLEX_NONE:
 460                 /* Duplex already cleared, do nothing */
 461                 break;
 462
 463         case TRUEPHY_ADV_DUPLEX_FULL:
 464                 /* Set Bit 9 */
 465                 data |= 0x0200;
 466                 break;
 467
 468         case TRUEPHY_ADV_DUPLEX_HALF:
 469                 /* Set Bit 8 */
 470                 data |= 0x0100;
 471                 break;
 472
 473         case TRUEPHY_ADV_DUPLEX_BOTH:
 474         default:
 475                 data |= 0x0300;
 476                 break;
 477         }
 478
 479         /* Write back advertisement */
 480         MiWrite(etdev, PHY_1000_CONTROL, data);
 481 }
 482
 483 static void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev,
 484                                  u16 duplex)
 485 {
 486         u16 data;
 487
 488         /* Read the Autonegotiation Register (10/100) */
 489         MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
 490
 491         /* Clear bits 7,8 */
 492         data &= ~0x0180;
 493
 494         switch (duplex) {
 495         case TRUEPHY_ADV_DUPLEX_NONE:
 496                 /* Duplex already cleared, do nothing */
 497                 break;
 498
 499         case TRUEPHY_ADV_DUPLEX_FULL:
 500                 /* Set Bit 8 */
 501                 data |= 0x0100;
 502                 break;
 503
 504         case TRUEPHY_ADV_DUPLEX_HALF:
 505                 /* Set Bit 7 */
 506                 data |= 0x0080;
 507                 break;
 508
 509         case TRUEPHY_ADV_DUPLEX_BOTH:
 510         default:
 511                 /* Set Bits 7,8 */
 512                 data |= 0x0180;
 513                 break;
 514         }
 515
 516         /* Write back advertisement */
 517         MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
 518 }
 519
 520 static void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev,
 521                                 u16 duplex)
 522 {
 523         u16 data;
 524
 525         /* Read the Autonegotiation Register (10/100) */
 526         MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
 527
 528         /* Clear bits 5,6 */
 529         data &= ~0x0060;
 530
 531         switch (duplex) {
 532         case TRUEPHY_ADV_DUPLEX_NONE:
 533                 /* Duplex already cleared, do nothing */
 534                 break;
 535
 536         case TRUEPHY_ADV_DUPLEX_FULL:
 537                 /* Set Bit 6 */
 538                 data |= 0x0040;
 539                 break;
 540
 541         case TRUEPHY_ADV_DUPLEX_HALF:
 542                 /* Set Bit 5 */
 543                 data |= 0x0020;
 544                 break;
 545
 546         case TRUEPHY_ADV_DUPLEX_BOTH:
 547         default:
 548                 /* Set Bits 5,6 */
 549                 data |= 0x0060;
 550                 break;
 551         }
 552
 553         /* Write back advertisement */
 554         MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
 555 }
 556
 557 /**
 558  * et131x_setphy_normal - Set PHY for normal operation.
 559  * @etdev: pointer to our private adapter structure
 560  *
 561  * Used by Power Management to force the PHY into 10 Base T half-duplex mode,
 562  * when going to D3 in WOL mode. Also used during initialization to set the
 563  * PHY for normal operation.
 564  */
 565 void et131x_setphy_normal(struct et131x_adapter *etdev)
 566 {
 567         /* Make sure the PHY is powered up */
 568         ET1310_PhyPowerDown(etdev, 0);
 569         et131x_xcvr_init(etdev);
 570 }
 571
 572
 573 /**
 574  * et131x_xcvr_init - Init the phy if we are setting it into force mode
 575  * @etdev: pointer to our private adapter structure
 576  *
 577  */
 578 static void et131x_xcvr_init(struct et131x_adapter *etdev)
 579 {
 580         u16 imr;
 581         u16 isr;
 582         u16 lcr2;
 583
 584         /* Zero out the adapter structure variable representing BMSR */
 585         etdev->Bmsr.value = 0;
 586
 587         MiRead(etdev, (u8) offsetof(struct mi_regs, isr), &isr);
 588         MiRead(etdev, (u8) offsetof(struct mi_regs, imr), &imr);
 589
 590         /* Set the link status interrupt only.  Bad behavior when link status
 591          * and auto neg are set, we run into a nested interrupt problem
 592          */
 593         imr |= 0x0105;
 594
 595         MiWrite(etdev, (u8) offsetof(struct mi_regs, imr), imr);
 596
 597         /* Set the LED behavior such that LED 1 indicates speed (off =
 598          * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
 599          * link and activity (on for link, blink off for activity).
 600          *
 601          * NOTE: Some customizations have been added here for specific
 602          * vendors; The LED behavior is now determined by vendor data in the
 603          * EEPROM. However, the above description is the default.
 604          */
 605         if ((etdev->eeprom_data[1] & 0x4) == 0) {
 606                 MiRead(etdev, (u8) offsetof(struct mi_regs, lcr2),
 607                        &lcr2);
 608
 609                 lcr2 &= 0x00FF;
 610                 lcr2 |= 0xA000; /* led link */
 611
 612                 if ((etdev->eeprom_data[1] & 0x8) == 0)
 613                         lcr2 |= 0x0300;
 614                 else
 615                         lcr2 |= 0x0400;
 616
 617                 MiWrite(etdev, (u8) offsetof(struct mi_regs, lcr2),
 618                         lcr2);
 619         }
 620
 621         /* Determine if we need to go into a force mode and set it */
 622         if (etdev->AiForceSpeed == 0 && etdev->AiForceDpx == 0) {
 623                 if (etdev->wanted_flow == FLOW_TXONLY ||
 624                     etdev->wanted_flow == FLOW_BOTH)
 625                         ET1310_PhyAccessMiBit(etdev,
 626                                               TRUEPHY_BIT_SET, 4, 11, NULL);
 627                 else
 628                         ET1310_PhyAccessMiBit(etdev,
 629                                               TRUEPHY_BIT_CLEAR, 4, 11, NULL);
 630
 631                 if (etdev->wanted_flow == FLOW_BOTH)
 632                         ET1310_PhyAccessMiBit(etdev,
 633                                               TRUEPHY_BIT_SET, 4, 10, NULL);
 634                 else
 635                         ET1310_PhyAccessMiBit(etdev,
 636                                               TRUEPHY_BIT_CLEAR, 4, 10, NULL);
 637
 638                 /* Set the phy to autonegotiation */
 639                 ET1310_PhyAutoNeg(etdev, true);
 640
 641                 /* NOTE - Do we need this? */
 642                 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_SET, 0, 9, NULL);
 643                 return;
 644         }
 645
 646         ET1310_PhyAutoNeg(etdev, false);
 647
 648         /* Set to the correct force mode. */
 649         if (etdev->AiForceDpx != 1) {
 650                 if (etdev->wanted_flow == FLOW_TXONLY ||
 651                     etdev->wanted_flow == FLOW_BOTH)
 652                         ET1310_PhyAccessMiBit(etdev,
 653                                       TRUEPHY_BIT_SET, 4, 11, NULL);
 654                 else
 655                         ET1310_PhyAccessMiBit(etdev,
 656                                               TRUEPHY_BIT_CLEAR, 4, 11, NULL);
 657
 658                 if (etdev->wanted_flow == FLOW_BOTH)
 659                         ET1310_PhyAccessMiBit(etdev,
 660                                               TRUEPHY_BIT_SET, 4, 10, NULL);
 661                 else
 662                         ET1310_PhyAccessMiBit(etdev,
 663                                               TRUEPHY_BIT_CLEAR, 4, 10, NULL);
 664         } else {
 665                 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 10, NULL);
 666                 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 11, NULL);
 667         }
 668         ET1310_PhyPowerDown(etdev, 1);
 669         switch (etdev->AiForceSpeed) {
 670         case 10:
 671                 /* First we need to turn off all other advertisement */
 672                 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 673                 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 674                 if (etdev->AiForceDpx == 1) {
 675                         /* Set our advertise values accordingly */
 676                         ET1310_PhyAdvertise10BaseT(etdev,
 677                                                 TRUEPHY_ADV_DUPLEX_HALF);
 678                 } else if (etdev->AiForceDpx == 2) {
 679                         /* Set our advertise values accordingly */
 680                         ET1310_PhyAdvertise10BaseT(etdev,
 681                                                 TRUEPHY_ADV_DUPLEX_FULL);
 682                 } else {
 683                         /* Disable autoneg */
 684                         ET1310_PhyAutoNeg(etdev, false);
 685                         /* Disable rest of the advertisements */
 686                         ET1310_PhyAdvertise10BaseT(etdev,
 687                                         TRUEPHY_ADV_DUPLEX_NONE);
 688                         /* Force 10 Mbps */
 689                         ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_10MBPS);
 690                         /* Force Full duplex */
 691                         ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
 692                 }
 693                 break;
 694         case 100:
 695                 /* first we need to turn off all other advertisement */
 696                 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 697                 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 698                 if (etdev->AiForceDpx == 1) {
 699                         /* Set our advertise values accordingly */
 700                         ET1310_PhyAdvertise100BaseT(etdev,
 701                                                 TRUEPHY_ADV_DUPLEX_HALF);
 702                         /* Set speed */
 703                         ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
 704                 } else if (etdev->AiForceDpx == 2) {
 705                         /* Set our advertise values accordingly */
 706                         ET1310_PhyAdvertise100BaseT(etdev,
 707                                                 TRUEPHY_ADV_DUPLEX_FULL);
 708                 } else {
 709                         /* Disable autoneg */
 710                         ET1310_PhyAutoNeg(etdev, false);
 711                         /* Disable other advertisement */
 712                         ET1310_PhyAdvertise100BaseT(etdev,
 713                                                 TRUEPHY_ADV_DUPLEX_NONE);
 714                         /* Force 100 Mbps */
 715                         ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
 716                         /* Force Full duplex */
 717                         ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
 718                 }
 719                 break;
 720         case 1000:
 721                 /* first we need to turn off all other advertisement */
 722                 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 723                 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
 724                 /* set our advertise values accordingly */
 725                 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
 726                 break;
 727         }
 728         ET1310_PhyPowerDown(etdev, 0);
 729 }
 730
 731 void et131x_Mii_check(struct et131x_adapter *etdev,
 732                       MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints)
 733 {
 734         u8 link_status;
 735         u32 autoneg_status;
 736         u32 speed;
 737         u32 duplex;
 738         u32 mdi_mdix;
 739         u32 masterslave;
 740         u32 polarity;
 741         unsigned long flags;
 742
 743         if (bmsr_ints.bits.link_status) {
 744                 if (bmsr.bits.link_status) {
 745                         etdev->boot_coma = 20;
 746
 747                         /* Update our state variables and indicate the
 748                          * connected state
 749                          */
 750                         spin_lock_irqsave(&etdev->Lock, flags);
 751
 752                         etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT;
 753                         etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION;
 754
 755                         spin_unlock_irqrestore(&etdev->Lock, flags);
 756
 757                         netif_carrier_on(etdev->netdev);
 758                 } else {
 759                         dev_warn(&etdev->pdev->dev,
 760                             "Link down - cable problem ?\n");
 761
 762                         if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
 763                                 /* NOTE - Is there a way to query this without
 764                                  * TruePHY?
 765                                  * && TRU_QueryCoreType(etdev->hTruePhy, 0) ==
 766                                  * EMI_TRUEPHY_A13O) {
 767                                  */
 768                                 u16 Register18;
 769
 770                                 MiRead(etdev, 0x12, &Register18);
 771                                 MiWrite(etdev, 0x12, Register18 | 0x4);
 772                                 MiWrite(etdev, 0x10, Register18 | 0x8402);
 773                                 MiWrite(etdev, 0x11, Register18 | 511);
 774                                 MiWrite(etdev, 0x12, Register18);
 775                         }
 776
 777                         /* For the first N seconds of life, we are in "link
 778                          * detection" When we are in this state, we should
 779                          * only report "connected". When the LinkDetection
 780                          * Timer expires, we can report disconnected (handled
 781                          * in the LinkDetectionDPC).
 782                          */
 783                         if (!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) ||
 784                          (etdev->MediaState == NETIF_STATUS_MEDIA_DISCONNECT)) {
 785                                 spin_lock_irqsave(&etdev->Lock, flags);
 786                                 etdev->MediaState =
 787                                     NETIF_STATUS_MEDIA_DISCONNECT;
 788                                 spin_unlock_irqrestore(&etdev->Lock,
 789                                                        flags);
 790
 791                                 netif_carrier_off(etdev->netdev);
 792                         }
 793
 794                         etdev->linkspeed = 0;
 795                         etdev->duplex_mode = 0;
 796
 797                         /* Free the packets being actively sent & stopped */
 798                         et131x_free_busy_send_packets(etdev);
 799
 800                         /* Re-initialize the send structures */
 801                         et131x_init_send(etdev);
 802
 803                         /* Reset the RFD list and re-start RU */
 804                         et131x_reset_recv(etdev);
 805
 806                         /*
 807                          * Bring the device back to the state it was during
 808                          * init prior to autonegotiation being complete. This
 809                          * way, when we get the auto-neg complete interrupt,
 810                          * we can complete init by calling ConfigMacREGS2.
 811                          */
 812                         et131x_soft_reset(etdev);
 813
 814                         /* Setup ET1310 as per the documentation */
 815                         et131x_adapter_setup(etdev);
 816
 817                         /* Setup the PHY into coma mode until the cable is
 818                          * plugged back in
 819                          */
 820                         if (etdev->RegistryPhyComa == 1)
 821                                 EnablePhyComa(etdev);
 822                 }
 823         }
 824
 825         if (bmsr_ints.bits.auto_neg_complete ||
 826             (etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) {
 827                 if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) {
 828                         ET1310_PhyLinkStatus(etdev,
 829                                              &link_status, &autoneg_status,
 830                                              &speed, &duplex, &mdi_mdix,
 831                                              &masterslave, &polarity);
 832
 833                         etdev->linkspeed = speed;
 834                         etdev->duplex_mode = duplex;
 835
 836                         etdev->boot_coma = 20;
 837
 838                         if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
 839                                 /*
 840                                  * NOTE - Is there a way to query this without
 841                                  * TruePHY?
 842                                  * && TRU_QueryCoreType(etdev->hTruePhy, 0)==
 843                                  * EMI_TRUEPHY_A13O) {
 844                                  */
 845                                 u16 Register18;
 846
 847                                 MiRead(etdev, 0x12, &Register18);
 848                                 MiWrite(etdev, 0x12, Register18 | 0x4);
 849                                 MiWrite(etdev, 0x10, Register18 | 0x8402);
 850                                 MiWrite(etdev, 0x11, Register18 | 511);
 851                                 MiWrite(etdev, 0x12, Register18);
 852                         }
 853
 854                         ConfigFlowControl(etdev);
 855
 856                         if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS &&
 857                                         etdev->RegistryJumboPacket > 2048)
 858                                 ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff,
 859                                                                    0x2000);
 860
 861                         SetRxDmaTimer(etdev);
 862                         ConfigMACRegs2(etdev);
 863                 }
 864         }
 865 }
 866
 867 /*
 868  * The routines which follow provide low-level access to the PHY, and are used
 869  * primarily by the routines above (although there are a few places elsewhere
 870  * in the driver where this level of access is required).
 871  */
 872
 873 static const u16 ConfigPhy[25][2] = {
 874         /* Reg      Value      Register */
 875         /* Addr                         */
 876         {0x880B, 0x0926},       /* AfeIfCreg4B1000Msbs */
 877         {0x880C, 0x0926},       /* AfeIfCreg4B100Msbs */
 878         {0x880D, 0x0926},       /* AfeIfCreg4B10Msbs */
 879
 880         {0x880E, 0xB4D3},       /* AfeIfCreg4B1000Lsbs */
 881         {0x880F, 0xB4D3},       /* AfeIfCreg4B100Lsbs */
 882         {0x8810, 0xB4D3},       /* AfeIfCreg4B10Lsbs */
 883
 884         {0x8805, 0xB03E},       /* AfeIfCreg3B1000Msbs */
 885         {0x8806, 0xB03E},       /* AfeIfCreg3B100Msbs */
 886         {0x8807, 0xFF00},       /* AfeIfCreg3B10Msbs */
 887
 888         {0x8808, 0xE090},       /* AfeIfCreg3B1000Lsbs */
 889         {0x8809, 0xE110},       /* AfeIfCreg3B100Lsbs */
 890         {0x880A, 0x0000},       /* AfeIfCreg3B10Lsbs */
 891
 892         {0x300D, 1},            /* DisableNorm */
 893
 894         {0x280C, 0x0180},       /* LinkHoldEnd */
 895
 896         {0x1C21, 0x0002},       /* AlphaM */
 897
 898         {0x3821, 6},            /* FfeLkgTx0 */
 899         {0x381D, 1},            /* FfeLkg1g4 */
 900         {0x381E, 1},            /* FfeLkg1g5 */
 901         {0x381F, 1},            /* FfeLkg1g6 */
 902         {0x3820, 1},            /* FfeLkg1g7 */
 903
 904         {0x8402, 0x01F0},       /* Btinact */
 905         {0x800E, 20},           /* LftrainTime */
 906         {0x800F, 24},           /* DvguardTime */
 907         {0x8010, 46},           /* IdlguardTime */
 908
 909         {0, 0}
 910
 911 };
 912
 913 /* condensed version of the phy initialization routine */
 914 void ET1310_PhyInit(struct et131x_adapter *etdev)
 915 {
 916         u16 data, index;
 917
 918         if (etdev == NULL)
 919                 return;
 920
 921         /* get the identity (again ?) */
 922         MiRead(etdev, PHY_ID_1, &data);
 923         MiRead(etdev, PHY_ID_2, &data);
 924
 925         /* what does this do/achieve ? */
 926         MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
 927         MiWrite(etdev, PHY_MPHY_CONTROL_REG,    0x0006);
 928
 929         /* read modem register 0402, should I do something with the return
 930            data ? */
 931         MiWrite(etdev, PHY_INDEX_REG, 0x0402);
 932         MiRead(etdev, PHY_DATA_REG, &data);
 933
 934         /* what does this do/achieve ? */
 935         MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
 936
 937         /* get the identity (again ?) */
 938         MiRead(etdev, PHY_ID_1, &data);
 939         MiRead(etdev, PHY_ID_2, &data);
 940
 941         /* what does this achieve ? */
 942         MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
 943         MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
 944
 945         /* read modem register 0402, should I do something with
 946            the return data? */
 947         MiWrite(etdev, PHY_INDEX_REG, 0x0402);
 948         MiRead(etdev, PHY_DATA_REG, &data);
 949
 950         MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
 951
 952         /* what does this achieve (should return 0x1040) */
 953         MiRead(etdev, PHY_CONTROL, &data);
 954         MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
 955         MiWrite(etdev, PHY_CONTROL, 0x1840);
 956
 957         MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0007);
 958
 959         /* here the writing of the array starts.... */
 960         index = 0;
 961         while (ConfigPhy[index][0] != 0x0000) {
 962                 /* write value */
 963                 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
 964                 MiWrite(etdev, PHY_DATA_REG, ConfigPhy[index][1]);
 965
 966                 /* read it back */
 967                 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
 968                 MiRead(etdev, PHY_DATA_REG, &data);
 969
 970                 /* do a check on the value read back ? */
 971                 index++;
 972         }
 973         /* here the writing of the array ends... */
 974
 975         MiRead(etdev, PHY_CONTROL, &data);              /* 0x1840 */
 976         MiRead(etdev, PHY_MPHY_CONTROL_REG, &data);/* should read 0007 */
 977         MiWrite(etdev, PHY_CONTROL, 0x1040);
 978         MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
 979 }
 980