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3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et131x_isr.c - File which contains the ISR, ISR handler, and related routines
12 * for processing interrupts from the device.
14 *------------------------------------------------------------------------------
18 * This software is provided subject to the following terms and conditions,
19 * which you should read carefully before using the software. Using this
20 * software indicates your acceptance of these terms and conditions. If you do
21 * not agree with these terms and conditions, do not use the software.
23 * Copyright © 2005 Agere Systems Inc.
24 * All rights reserved.
26 * Redistribution and use in source or binary forms, with or without
27 * modifications, are permitted provided that the following conditions are met:
29 * . Redistributions of source code must retain the above copyright notice, this
30 * list of conditions and the following Disclaimer as comments in the code as
31 * well as in the documentation and/or other materials provided with the
34 * . Redistributions in binary form must reproduce the above copyright notice,
35 * this list of conditions and the following Disclaimer in the documentation
36 * and/or other materials provided with the distribution.
38 * . Neither the name of Agere Systems Inc. nor the names of the contributors
39 * may be used to endorse or promote products derived from this software
40 * without specific prior written permission.
44 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
45 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
46 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
47 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
48 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
49 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
50 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
51 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
52 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
54 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
59 #include "et131x_version.h"
60 #include "et131x_defs.h"
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/ctype.h>
70 #include <linux/string.h>
71 #include <linux/timer.h>
72 #include <linux/interrupt.h>
74 #include <linux/delay.h>
76 #include <linux/bitops.h>
77 #include <linux/pci.h>
78 #include <asm/system.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
86 #include "et1310_phy.h"
87 #include "et131x_adapter.h"
91 * For interrupts, normal running is:
92 * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
93 * watchdog_interrupt & txdma_xfer_done
95 * In both cases, when flow control is enabled for either Tx or bi-direction,
96 * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
97 * buffer rings are running low.
99 #define INT_MASK_DISABLE 0xffffffff
101 /* NOTE: Masking out MAC_STAT Interrupt for now...
102 * #define INT_MASK_ENABLE 0xfff6bf17
103 * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
105 #define INT_MASK_ENABLE 0xfffebf17
106 #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
110 * et131x_enable_interrupts - enable interrupt
111 * @adapter: et131x device
113 * Enable the appropriate interrupts on the ET131x according to our
117 void et131x_enable_interrupts(struct et131x_adapter
*adapter
)
121 /* Enable all global interrupts */
122 if (adapter
->FlowControl
== TxOnly
|| adapter
->FlowControl
== Both
)
123 mask
= INT_MASK_ENABLE
;
125 mask
= INT_MASK_ENABLE_NO_FLOW
;
127 adapter
->CachedMaskValue
= mask
;
128 writel(mask
, &adapter
->regs
->global
.int_mask
);
132 * et131x_disable_interrupts - interrupt disable
133 * @adapter: et131x device
135 * Block all interrupts from the et131x device at the device itself
138 void et131x_disable_interrupts(struct et131x_adapter
*adapter
)
140 /* Disable all global interrupts */
141 adapter
->CachedMaskValue
= INT_MASK_DISABLE
;
142 writel(INT_MASK_DISABLE
, &adapter
->regs
->global
.int_mask
);
147 * et131x_isr - The Interrupt Service Routine for the driver.
148 * @irq: the IRQ on which the interrupt was received.
149 * @dev_id: device-specific info (here a pointer to a net_device struct)
151 * Returns a value indicating if the interrupt was handled.
154 irqreturn_t
et131x_isr(int irq
, void *dev_id
)
157 struct net_device
*netdev
= (struct net_device
*)dev_id
;
158 struct et131x_adapter
*adapter
= NULL
;
161 if (!netif_device_present(netdev
)) {
166 adapter
= netdev_priv(netdev
);
168 /* If the adapter is in low power state, then it should not
169 * recognize any interrupt
172 /* Disable Device Interrupts */
173 et131x_disable_interrupts(adapter
);
175 /* Get a copy of the value in the interrupt status register
176 * so we can process the interrupting section
178 status
= readl(&adapter
->regs
->global
.int_status
);
180 if (adapter
->FlowControl
== TxOnly
||
181 adapter
->FlowControl
== Both
) {
182 status
&= ~INT_MASK_ENABLE
;
184 status
&= ~INT_MASK_ENABLE_NO_FLOW
;
187 /* Make sure this is our interrupt */
190 et131x_enable_interrupts(adapter
);
194 /* This is our interrupt, so process accordingly */
196 if (status
& ET_INTR_WATCHDOG
) {
197 struct tcb
*tcb
= adapter
->tx_ring
.send_head
;
200 if (++tcb
->stale
> 1)
201 status
|= ET_INTR_TXDMA_ISR
;
203 if (adapter
->rx_ring
.UnfinishedReceives
)
204 status
|= ET_INTR_RXDMA_XFR_DONE
;
205 else if (tcb
== NULL
)
206 writel(0, &adapter
->regs
->global
.watchdog_timer
);
208 status
&= ~ET_INTR_WATCHDOG
;
212 /* This interrupt has in some way been "handled" by
213 * the ISR. Either it was a spurious Rx interrupt, or
214 * it was a Tx interrupt that has been filtered by
217 et131x_enable_interrupts(adapter
);
221 /* We need to save the interrupt status value for use in our
222 * DPC. We will clear the software copy of that in that
225 adapter
->Stats
.InterruptStatus
= status
;
227 /* Schedule the ISR handler as a bottom-half task in the
228 * kernel's tq_immediate queue, and mark the queue for
231 schedule_work(&adapter
->task
);
233 return IRQ_RETVAL(handled
);
237 * et131x_isr_handler - The ISR handler
238 * @p_adapter, a pointer to the device's private adapter structure
240 * scheduled to run in a deferred context by the ISR. This is where the ISR's
241 * work actually gets done.
243 void et131x_isr_handler(struct work_struct
*work
)
245 struct et131x_adapter
*etdev
=
246 container_of(work
, struct et131x_adapter
, task
);
247 u32 status
= etdev
->Stats
.InterruptStatus
;
248 ADDRESS_MAP_t __iomem
*iomem
= etdev
->regs
;
251 * These first two are by far the most common. Once handled, we clear
252 * their two bits in the status word. If the word is now zero, we
255 /* Handle all the completed Transmit interrupts */
256 if (status
& ET_INTR_TXDMA_ISR
) {
257 et131x_handle_send_interrupt(etdev
);
260 /* Handle all the completed Receives interrupts */
261 if (status
& ET_INTR_RXDMA_XFR_DONE
) {
262 et131x_handle_recv_interrupt(etdev
);
265 status
&= 0xffffffd7;
268 /* Handle the TXDMA Error interrupt */
269 if (status
& ET_INTR_TXDMA_ERR
) {
272 /* Following read also clears the register (COR) */
273 txdma_err
= readl(&iomem
->txdma
.TxDmaError
);
275 dev_warn(&etdev
->pdev
->dev
,
276 "TXDMA_ERR interrupt, error = %d\n",
280 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
281 if (status
& (ET_INTR_RXDMA_FB_R0_LOW
| ET_INTR_RXDMA_FB_R1_LOW
)) {
283 * This indicates the number of unused buffers in
284 * RXDMA free buffer ring 0 is <= the limit you
285 * programmed. Free buffer resources need to be
286 * returned. Free buffers are consumed as packets
287 * are passed from the network to the host. The host
288 * becomes aware of the packets from the contents of
289 * the packet status ring. This ring is queried when
290 * the packet done interrupt occurs. Packets are then
291 * passed to the OS. When the OS is done with the
292 * packets the resources can be returned to the
293 * ET1310 for re-use. This interrupt is one method of
294 * returning resources.
297 /* If the user has flow control on, then we will
298 * send a pause packet, otherwise just exit
300 if (etdev
->FlowControl
== TxOnly
||
301 etdev
->FlowControl
== Both
) {
304 /* Tell the device to send a pause packet via
305 * the back pressure register (bp req and
308 pm_csr
= readl(&iomem
->global
.pm_csr
);
309 if ((pm_csr
& ET_PM_PHY_SW_COMA
) == 0)
310 writel(3, &iomem
->txmac
.bp_ctrl
);
314 /* Handle Packet Status Ring Low Interrupt */
315 if (status
& ET_INTR_RXDMA_STAT_LOW
) {
318 * Same idea as with the two Free Buffer Rings.
319 * Packets going from the network to the host each
320 * consume a free buffer resource and a packet status
321 * resource. These resoures are passed to the OS.
322 * When the OS is done with the resources, they need
323 * to be returned to the ET1310. This is one method
324 * of returning the resources.
328 /* Handle RXDMA Error Interrupt */
329 if (status
& ET_INTR_RXDMA_ERR
) {
331 * The rxdma_error interrupt is sent when a time-out
332 * on a request issued by the JAGCore has occurred or
333 * a completion is returned with an un-successful
334 * status. In both cases the request is considered
335 * complete. The JAGCore will automatically re-try the
336 * request in question. Normally information on events
337 * like these are sent to the host using the "Advanced
338 * Error Reporting" capability. This interrupt is
339 * another way of getting similar information. The
340 * only thing required is to clear the interrupt by
341 * reading the ISR in the global resources. The
342 * JAGCore will do a re-try on the request. Normally
343 * you should never see this interrupt. If you start
344 * to see this interrupt occurring frequently then
345 * something bad has occurred. A reset might be the
350 dev_warn(&etdev
->pdev
->dev
,
351 "RxDMA_ERR interrupt, error %x\n",
352 readl(&iomem
->txmac
.tx_test
));
355 /* Handle the Wake on LAN Event */
356 if (status
& ET_INTR_WOL
) {
358 * This is a secondary interrupt for wake on LAN.
359 * The driver should never see this, if it does,
360 * something serious is wrong. We will TRAP the
361 * message when we are in DBG mode, otherwise we
364 dev_err(&etdev
->pdev
->dev
, "WAKE_ON_LAN interrupt\n");
367 /* Handle the PHY interrupt */
368 if (status
& ET_INTR_PHY
) {
370 MI_BMSR_t BmsrInts
, BmsrData
;
373 /* If we are in coma mode when we get this interrupt,
374 * we need to disable it.
376 pm_csr
= readl(&iomem
->global
.pm_csr
);
377 if (pm_csr
& ET_PM_PHY_SW_COMA
) {
379 * Check to see if we are in coma mode and if
380 * so, disable it because we will not be able
381 * to read PHY values until we are out.
383 DisablePhyComa(etdev
);
386 /* Read the PHY ISR to clear the reason for the
389 MiRead(etdev
, (uint8_t) offsetof(MI_REGS_t
, isr
),
392 if (!etdev
->ReplicaPhyLoopbk
) {
394 (uint8_t) offsetof(MI_REGS_t
, bmsr
),
398 etdev
->Bmsr
.value
^ BmsrData
.value
;
399 etdev
->Bmsr
.value
= BmsrData
.value
;
401 /* Do all the cable in / cable out stuff */
402 et131x_Mii_check(etdev
, BmsrData
, BmsrInts
);
406 /* Let's move on to the TxMac */
407 if (status
& ET_INTR_TXMAC
) {
408 u32 err
= readl(&iomem
->txmac
.err
);
411 * When any of the errors occur and TXMAC generates
412 * an interrupt to report these errors, it usually
413 * means that TXMAC has detected an error in the data
414 * stream retrieved from the on-chip Tx Q. All of
415 * these errors are catastrophic and TXMAC won't be
416 * able to recover data when these errors occur. In
417 * a nutshell, the whole Tx path will have to be reset
418 * and re-configured afterwards.
420 dev_warn(&etdev
->pdev
->dev
,
421 "TXMAC interrupt, error 0x%08x\n",
424 /* If we are debugging, we want to see this error,
425 * otherwise we just want the device to be reset and
430 /* Handle RXMAC Interrupt */
431 if (status
& ET_INTR_RXMAC
) {
433 * These interrupts are catastrophic to the device,
434 * what we need to do is disable the interrupts and
435 * set the flag to cause us to reset so we can solve
438 /* MP_SET_FLAG( etdev,
439 fMP_ADAPTER_HARDWARE_ERROR); */
441 dev_warn(&etdev
->pdev
->dev
,
442 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
443 readl(&iomem
->rxmac
.err_reg
));
445 dev_warn(&etdev
->pdev
->dev
,
446 "Enable 0x%08x, Diag 0x%08x\n",
447 readl(&iomem
->rxmac
.ctrl
),
448 readl(&iomem
->rxmac
.rxq_diag
));
451 * If we are debugging, we want to see this error,
452 * otherwise we just want the device to be reset and
457 /* Handle MAC_STAT Interrupt */
458 if (status
& ET_INTR_MAC_STAT
) {
460 * This means at least one of the un-masked counters
461 * in the MAC_STAT block has rolled over. Use this
462 * to maintain the top, software managed bits of the
465 HandleMacStatInterrupt(etdev
);
468 /* Handle SLV Timeout Interrupt */
469 if (status
& ET_INTR_SLV_TIMEOUT
) {
471 * This means a timeout has occured on a read or
472 * write request to one of the JAGCore registers. The
473 * Global Resources block has terminated the request
474 * and on a read request, returned a "fake" value.
475 * The most likely reasons are: Bad Address or the
476 * addressed module is in a power-down state and
481 et131x_enable_interrupts(etdev
);