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git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/staging/fbtft/fb_ili9325.c
2 * FB driver for the ILI9325 LCD Controller
4 * Copyright (C) 2013 Noralf Tronnes
6 * Based on ili9325.c by Jeroen Domburg
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/gpio.h>
27 #include <linux/delay.h>
31 #define DRVNAME "fb_ili9325"
36 #define DEFAULT_GAMMA "0F 00 7 2 0 0 6 5 4 1\n" \
37 "04 16 2 7 6 3 2 1 7 7"
40 static unsigned bt
= 6; /* VGL=Vci*4 , VGH=Vci*4 */
41 module_param(bt
, uint
, 0);
42 MODULE_PARM_DESC(bt
, "Sets the factor used in the step-up circuits");
44 static unsigned vc
= 0b011; /* Vci1=Vci*0.80 */
45 module_param(vc
, uint
, 0);
47 "Sets the ratio factor of Vci to generate the reference voltages Vci1");
49 static unsigned vrh
= 0b1101; /* VREG1OUT=Vci*1.85 */
50 module_param(vrh
, uint
, 0);
52 "Set the amplifying rate (1.6 ~ 1.9) of Vci applied to output the VREG1OUT");
54 static unsigned vdv
= 0b10010; /* VCOMH amplitude=VREG1OUT*0.98 */
55 module_param(vdv
, uint
, 0);
57 "Select the factor of VREG1OUT to set the amplitude of Vcom");
59 static unsigned vcm
= 0b001010; /* VCOMH=VREG1OUT*0.735 */
60 module_param(vcm
, uint
, 0);
61 MODULE_PARM_DESC(vcm
, "Set the internal VcomH voltage");
65 Verify that this configuration is within the Voltage limits
67 Display module configuration: Vcc = IOVcc = Vci = 3.3V
72 Vci1 = Vci * 0.80 = 2.64
73 DDVDH = Vci1 * 2 = 5.28
75 VREG1OUT = Vci * 1.85 = 4.88
76 VCOMH = VREG1OUT * 0.735 = 3.59
77 VCOM amplitude = VREG1OUT * 0.98 = 4.79
79 VGL = -Vci * 4 = -13.2
84 1.65 < IOVcc < 3.30 => 1.65 < 3.3 < 3.30
85 2.40 < Vcc < 3.30 => 2.40 < 3.3 < 3.30
86 2.50 < Vci < 3.30 => 2.50 < 3.3 < 3.30
88 Source/VCOM power supply voltage
89 4.50 < DDVDH < 6.0 => 4.50 < 5.28 < 6.0
90 -3.0 < VCL < -2.0 => -3.0 < -2.64 < -2.0
91 VCI - VCL < 6.0 => 5.94 < 6.0
93 Gate driver output voltage
94 10 < VGH < 20 => 10 < 13.2 < 20
95 -15 < VGL < -5 => -15 < -13.2 < -5
96 VGH - VGL < 32 => 26.4 < 32
98 VCOM driver output voltage
99 VCOMH - VCOML < 6.0 => 4.79 < 6.0
102 static int init_display(struct fbtft_par
*par
)
104 fbtft_par_dbg(DEBUG_INIT_DISPLAY
, par
, "%s()\n", __func__
);
106 par
->fbtftops
.reset(par
);
108 if (par
->gpio
.cs
!= -1)
109 gpio_set_value(par
->gpio
.cs
, 0); /* Activate chip */
117 /* Initialization sequence from ILI9325 Application Notes */
119 /* ----------- Start Initial Sequence ----------- */
120 write_reg(par
, 0x00E3, 0x3008); /* Set internal timing */
121 write_reg(par
, 0x00E7, 0x0012); /* Set internal timing */
122 write_reg(par
, 0x00EF, 0x1231); /* Set internal timing */
123 write_reg(par
, 0x0001, 0x0100); /* set SS and SM bit */
124 write_reg(par
, 0x0002, 0x0700); /* set 1 line inversion */
125 write_reg(par
, 0x0004, 0x0000); /* Resize register */
126 write_reg(par
, 0x0008, 0x0207); /* set the back porch and front porch */
127 write_reg(par
, 0x0009, 0x0000); /* set non-display area refresh cycle */
128 write_reg(par
, 0x000A, 0x0000); /* FMARK function */
129 write_reg(par
, 0x000C, 0x0000); /* RGB interface setting */
130 write_reg(par
, 0x000D, 0x0000); /* Frame marker Position */
131 write_reg(par
, 0x000F, 0x0000); /* RGB interface polarity */
133 /* ----------- Power On sequence ----------- */
134 write_reg(par
, 0x0010, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
135 write_reg(par
, 0x0011, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */
136 write_reg(par
, 0x0012, 0x0000); /* VREG1OUT voltage */
137 write_reg(par
, 0x0013, 0x0000); /* VDV[4:0] for VCOM amplitude */
138 mdelay(200); /* Dis-charge capacitor power voltage */
139 write_reg(par
, 0x0010, /* SAP, BT[3:0], AP, DSTB, SLP, STB */
140 (1 << 12) | (bt
<< 8) | (1 << 7) | (0b001 << 4));
141 write_reg(par
, 0x0011, 0x220 | vc
); /* DC1[2:0], DC0[2:0], VC[2:0] */
142 mdelay(50); /* Delay 50ms */
143 write_reg(par
, 0x0012, vrh
); /* Internal reference voltage= Vci; */
144 mdelay(50); /* Delay 50ms */
145 write_reg(par
, 0x0013, vdv
<< 8); /* Set VDV[4:0] for VCOM amplitude */
146 write_reg(par
, 0x0029, vcm
); /* Set VCM[5:0] for VCOMH */
147 write_reg(par
, 0x002B, 0x000C); /* Set Frame Rate */
148 mdelay(50); /* Delay 50ms */
149 write_reg(par
, 0x0020, 0x0000); /* GRAM horizontal Address */
150 write_reg(par
, 0x0021, 0x0000); /* GRAM Vertical Address */
152 /*------------------ Set GRAM area --------------- */
153 write_reg(par
, 0x0050, 0x0000); /* Horizontal GRAM Start Address */
154 write_reg(par
, 0x0051, 0x00EF); /* Horizontal GRAM End Address */
155 write_reg(par
, 0x0052, 0x0000); /* Vertical GRAM Start Address */
156 write_reg(par
, 0x0053, 0x013F); /* Vertical GRAM Start Address */
157 write_reg(par
, 0x0060, 0xA700); /* Gate Scan Line */
158 write_reg(par
, 0x0061, 0x0001); /* NDL,VLE, REV */
159 write_reg(par
, 0x006A, 0x0000); /* set scrolling line */
161 /*-------------- Partial Display Control --------- */
162 write_reg(par
, 0x0080, 0x0000);
163 write_reg(par
, 0x0081, 0x0000);
164 write_reg(par
, 0x0082, 0x0000);
165 write_reg(par
, 0x0083, 0x0000);
166 write_reg(par
, 0x0084, 0x0000);
167 write_reg(par
, 0x0085, 0x0000);
169 /*-------------- Panel Control ------------------- */
170 write_reg(par
, 0x0090, 0x0010);
171 write_reg(par
, 0x0092, 0x0600);
172 write_reg(par
, 0x0007, 0x0133); /* 262K color and display ON */
177 static void set_addr_win(struct fbtft_par
*par
, int xs
, int ys
, int xe
, int ye
)
179 fbtft_par_dbg(DEBUG_SET_ADDR_WIN
, par
,
180 "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__
, xs
, ys
, xe
, ye
);
181 switch (par
->info
->var
.rotate
) {
182 /* R20h = Horizontal GRAM Start Address */
183 /* R21h = Vertical GRAM Start Address */
185 write_reg(par
, 0x0020, xs
);
186 write_reg(par
, 0x0021, ys
);
189 write_reg(par
, 0x0020, WIDTH
- 1 - xs
);
190 write_reg(par
, 0x0021, HEIGHT
- 1 - ys
);
193 write_reg(par
, 0x0020, WIDTH
- 1 - ys
);
194 write_reg(par
, 0x0021, xs
);
197 write_reg(par
, 0x0020, ys
);
198 write_reg(par
, 0x0021, HEIGHT
- 1 - xs
);
201 write_reg(par
, 0x0022); /* Write Data to GRAM */
204 static int set_var(struct fbtft_par
*par
)
206 fbtft_par_dbg(DEBUG_INIT_DISPLAY
, par
, "%s()\n", __func__
);
208 switch (par
->info
->var
.rotate
) {
209 /* AM: GRAM update direction */
211 write_reg(par
, 0x03, 0x0030 | (par
->bgr
<< 12));
214 write_reg(par
, 0x03, 0x0000 | (par
->bgr
<< 12));
217 write_reg(par
, 0x03, 0x0028 | (par
->bgr
<< 12));
220 write_reg(par
, 0x03, 0x0018 | (par
->bgr
<< 12));
229 VRP0 VRP1 RP0 RP1 KP0 KP1 KP2 KP3 KP4 KP5
230 VRN0 VRN1 RN0 RN1 KN0 KN1 KN2 KN3 KN4 KN5
232 #define CURVE(num, idx) curves[num*par->gamma.num_values + idx]
233 static int set_gamma(struct fbtft_par
*par
, unsigned long *curves
)
235 unsigned long mask
[] = {
236 0b11111, 0b11111, 0b111, 0b111, 0b111,
237 0b111, 0b111, 0b111, 0b111, 0b111,
238 0b11111, 0b11111, 0b111, 0b111, 0b111,
239 0b111, 0b111, 0b111, 0b111, 0b111 };
242 fbtft_par_dbg(DEBUG_INIT_DISPLAY
, par
, "%s()\n", __func__
);
245 for (i
= 0; i
< 2; i
++)
246 for (j
= 0; j
< 10; j
++)
247 CURVE(i
, j
) &= mask
[i
*par
->gamma
.num_values
+ j
];
249 write_reg(par
, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4));
250 write_reg(par
, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6));
251 write_reg(par
, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8));
252 write_reg(par
, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2));
253 write_reg(par
, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0));
255 write_reg(par
, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4));
256 write_reg(par
, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6));
257 write_reg(par
, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8));
258 write_reg(par
, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2));
259 write_reg(par
, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0));
266 static struct fbtft_display display
= {
274 .gamma
= DEFAULT_GAMMA
,
276 .init_display
= init_display
,
277 .set_addr_win
= set_addr_win
,
279 .set_gamma
= set_gamma
,
282 FBTFT_REGISTER_DRIVER(DRVNAME
, "ilitek,ili9325", &display
);
284 MODULE_ALIAS("spi:" DRVNAME
);
285 MODULE_ALIAS("platform:" DRVNAME
);
286 MODULE_ALIAS("spi:ili9325");
287 MODULE_ALIAS("platform:ili9325");
289 MODULE_DESCRIPTION("FB driver for the ILI9325 LCD Controller");
290 MODULE_AUTHOR("Noralf Tronnes");
291 MODULE_LICENSE("GPL");