drivers/staging/fbtft/fb_ssd1306.c

   1 /*
   2  * FB driver for the SSD1306 OLED Controller
   3  *
   4  * Copyright (C) 2013 Noralf Tronnes
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/gpio.h>
  21 #include <linux/delay.h>
  22
  23 #include "fbtft.h"
  24
  25 #define DRVNAME         "fb_ssd1306"
  26 #define WIDTH           128
  27 #define HEIGHT          64
  28
  29 /*
  30  * write_reg() caveat:
  31  *
  32  * This doesn't work because D/C has to be LOW for both values:
  33  * write_reg(par, val1, val2);
  34  *
  35  * Do it like this:
  36  * write_reg(par, val1);
  37  * write_reg(par, val2);
  38  */
  39
  40 /* Init sequence taken from the Adafruit SSD1306 Arduino library */
  41 static int init_display(struct fbtft_par *par)
  42 {
  43         par->fbtftops.reset(par);
  44
  45         if (par->gamma.curves[0] == 0) {
  46                 mutex_lock(&par->gamma.lock);
  47                 if (par->info->var.yres == 64)
  48                         par->gamma.curves[0] = 0xCF;
  49                 else
  50                         par->gamma.curves[0] = 0x8F;
  51                 mutex_unlock(&par->gamma.lock);
  52         }
  53
  54         /* Set Display OFF */
  55         write_reg(par, 0xAE);
  56
  57         /* Set Display Clock Divide Ratio/ Oscillator Frequency */
  58         write_reg(par, 0xD5);
  59         write_reg(par, 0x80);
  60
  61         /* Set Multiplex Ratio */
  62         write_reg(par, 0xA8);
  63         if (par->info->var.yres == 64)
  64                 write_reg(par, 0x3F);
  65         else if (par->info->var.yres == 48)
  66                 write_reg(par, 0x2F);
  67         else
  68                 write_reg(par, 0x1F);
  69
  70         /* Set Display Offset */
  71         write_reg(par, 0xD3);
  72         write_reg(par, 0x0);
  73
  74         /* Set Display Start Line */
  75         write_reg(par, 0x40 | 0x0);
  76
  77         /* Charge Pump Setting */
  78         write_reg(par, 0x8D);
  79         /* A[2] = 1b, Enable charge pump during display on */
  80         write_reg(par, 0x14);
  81
  82         /* Set Memory Addressing Mode */
  83         write_reg(par, 0x20);
  84         /* Vertical addressing mode  */
  85         write_reg(par, 0x01);
  86
  87         /* Set Segment Re-map */
  88         /* column address 127 is mapped to SEG0 */
  89         write_reg(par, 0xA0 | 0x1);
  90
  91         /* Set COM Output Scan Direction */
  92         /* remapped mode. Scan from COM[N-1] to COM0 */
  93         write_reg(par, 0xC8);
  94
  95         /* Set COM Pins Hardware Configuration */
  96         write_reg(par, 0xDA);
  97         if (par->info->var.yres == 64)
  98                 /* A[4]=1b, Alternative COM pin configuration */
  99                 write_reg(par, 0x12);
 100         else if (par->info->var.yres == 48)
 101                 /* A[4]=1b, Alternative COM pin configuration */
 102                 write_reg(par, 0x12);
 103         else
 104                 /* A[4]=0b, Sequential COM pin configuration */
 105                 write_reg(par, 0x02);
 106
 107         /* Set Pre-charge Period */
 108         write_reg(par, 0xD9);
 109         write_reg(par, 0xF1);
 110
 111         /* Set VCOMH Deselect Level */
 112         write_reg(par, 0xDB);
 113         /* according to the datasheet, this value is out of bounds */
 114         write_reg(par, 0x40);
 115
 116         /* Entire Display ON */
 117         /* Resume to RAM content display. Output follows RAM content */
 118         write_reg(par, 0xA4);
 119
 120         /* Set Normal Display
 121          * 0 in RAM: OFF in display panel
 122          * 1 in RAM: ON in display panel
 123          */
 124         write_reg(par, 0xA6);
 125
 126         /* Set Display ON */
 127         write_reg(par, 0xAF);
 128
 129         return 0;
 130 }
 131
 132 static void set_addr_win_64x48(struct fbtft_par *par)
 133 {
 134         /* Set Column Address */
 135         write_reg(par, 0x21);
 136         write_reg(par, 0x20);
 137         write_reg(par, 0x5F);
 138
 139         /* Set Page Address */
 140         write_reg(par, 0x22);
 141         write_reg(par, 0x0);
 142         write_reg(par, 0x5);
 143 }
 144
 145 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
 146 {
 147         /* Set Lower Column Start Address for Page Addressing Mode */
 148         write_reg(par, 0x00 | 0x0);
 149         /* Set Higher Column Start Address for Page Addressing Mode */
 150         write_reg(par, 0x10 | 0x0);
 151         /* Set Display Start Line */
 152         write_reg(par, 0x40 | 0x0);
 153
 154         if (par->info->var.xres == 64 && par->info->var.yres == 48)
 155                 set_addr_win_64x48(par);
 156 }
 157
 158 static int blank(struct fbtft_par *par, bool on)
 159 {
 160         fbtft_par_dbg(DEBUG_BLANK, par, "%s(blank=%s)\n",
 161                       __func__, on ? "true" : "false");
 162
 163         if (on)
 164                 write_reg(par, 0xAE);
 165         else
 166                 write_reg(par, 0xAF);
 167         return 0;
 168 }
 169
 170 /* Gamma is used to control Contrast */
 171 static int set_gamma(struct fbtft_par *par, u32 *curves)
 172 {
 173         /* apply mask */
 174         curves[0] &= 0xFF;
 175
 176         /* Set Contrast Control for BANK0 */
 177         write_reg(par, 0x81);
 178         write_reg(par, curves[0]);
 179
 180         return 0;
 181 }
 182
 183 static int write_vmem(struct fbtft_par *par, size_t offset, size_t len)
 184 {
 185         u16 *vmem16 = (u16 *)par->info->screen_buffer;
 186         u32 xres = par->info->var.xres;
 187         u32 yres = par->info->var.yres;
 188         u8 *buf = par->txbuf.buf;
 189         int x, y, i;
 190         int ret = 0;
 191
 192         for (x = 0; x < xres; x++) {
 193                 for (y = 0; y < yres / 8; y++) {
 194                         *buf = 0x00;
 195                         for (i = 0; i < 8; i++)
 196                                 *buf |= (vmem16[(y * 8 + i) * xres + x] ? 1 : 0) << i;
 197                         buf++;
 198                 }
 199         }
 200
 201         /* Write data */
 202         gpio_set_value(par->gpio.dc, 1);
 203         ret = par->fbtftops.write(par, par->txbuf.buf, xres * yres / 8);
 204         if (ret < 0)
 205                 dev_err(par->info->device, "write failed and returned: %d\n",
 206                         ret);
 207
 208         return ret;
 209 }
 210
 211 static struct fbtft_display display = {
 212         .regwidth = 8,
 213         .width = WIDTH,
 214         .height = HEIGHT,
 215         .gamma_num = 1,
 216         .gamma_len = 1,
 217         .gamma = "00",
 218         .fbtftops = {
 219                 .write_vmem = write_vmem,
 220                 .init_display = init_display,
 221                 .set_addr_win = set_addr_win,
 222                 .blank = blank,
 223                 .set_gamma = set_gamma,
 224         },
 225 };
 226
 227 FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1306", &display);
 228
 229 MODULE_ALIAS("spi:" DRVNAME);
 230 MODULE_ALIAS("platform:" DRVNAME);
 231 MODULE_ALIAS("spi:ssd1306");
 232 MODULE_ALIAS("platform:ssd1306");
 233
 234 MODULE_DESCRIPTION("SSD1306 OLED Driver");
 235 MODULE_AUTHOR("Noralf Tronnes");
 236 MODULE_LICENSE("GPL");