2 * Copyright (c) 2006-2007 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Eric Anholt <eric@anholt.net>
21 #include <linux/i2c.h>
22 #include <linux/delay.h>
23 /* #include <drm/drm_crtc.h> */
26 #include "psb_intel_drv.h"
27 #include "psb_intel_reg.h"
28 #include "psb_intel_sdvo_regs.h"
30 struct psb_intel_sdvo_priv
{
31 struct psb_intel_i2c_chan
*i2c_bus
;
37 struct psb_intel_sdvo_caps caps
;
38 int pixel_clock_min
, pixel_clock_max
;
41 u16 save_active_outputs
;
42 struct psb_intel_sdvo_dtd save_input_dtd_1
, save_input_dtd_2
;
43 struct psb_intel_sdvo_dtd save_output_dtd
[16];
52 * Writes the SDVOB or SDVOC with the given value, but always writes both
53 * SDVOB and SDVOC to work around apparent hardware issues (according to
54 * comments in the BIOS).
56 void psb_intel_sdvo_write_sdvox(struct psb_intel_output
*psb_intel_output
,
59 struct drm_device
*dev
= psb_intel_output
->base
.dev
;
60 struct psb_intel_sdvo_priv
*sdvo_priv
= psb_intel_output
->dev_priv
;
61 u32 bval
= val
, cval
= val
;
64 if (sdvo_priv
->output_device
== SDVOB
)
65 cval
= REG_READ(SDVOC
);
67 bval
= REG_READ(SDVOB
);
69 * Write the registers twice for luck. Sometimes,
70 * writing them only once doesn't appear to 'stick'.
71 * The BIOS does this too. Yay, magic
73 for (i
= 0; i
< 2; i
++) {
74 REG_WRITE(SDVOB
, bval
);
76 REG_WRITE(SDVOC
, cval
);
81 static bool psb_intel_sdvo_read_byte(
82 struct psb_intel_output
*psb_intel_output
,
85 struct psb_intel_sdvo_priv
*sdvo_priv
= psb_intel_output
->dev_priv
;
90 struct i2c_msg msgs
[] = {
92 .addr
= sdvo_priv
->i2c_bus
->slave_addr
,
98 .addr
= sdvo_priv
->i2c_bus
->slave_addr
,
108 ret
= i2c_transfer(&sdvo_priv
->i2c_bus
->adapter
, msgs
, 2);
110 /* DRM_DEBUG("got back from addr %02X = %02x\n",
111 * out_buf[0], buf[0]);
117 DRM_DEBUG("i2c transfer returned %d\n", ret
);
121 static bool psb_intel_sdvo_write_byte(
122 struct psb_intel_output
*psb_intel_output
,
126 struct i2c_msg msgs
[] = {
128 .addr
= psb_intel_output
->i2c_bus
->slave_addr
,
138 if (i2c_transfer(&psb_intel_output
->i2c_bus
->adapter
, msgs
, 1) == 1)
143 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
144 /** Mapping of command numbers to names, for debug output */
145 static const struct _sdvo_cmd_name
{
148 } sdvo_cmd_names
[] = {
149 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET
),
150 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS
),
151 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV
),
152 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS
),
153 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS
),
154 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS
),
155 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP
),
156 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP
),
157 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS
),
158 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT
),
159 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG
),
160 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG
),
162 (SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE
),
163 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT
),
164 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT
),
165 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1
),
166 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2
),
167 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1
),
168 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2
),
169 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1
),
170 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1
),
171 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2
),
172 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1
),
173 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2
),
175 (SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING
),
177 (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1
),
179 (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2
),
181 (SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE
),
183 (SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE
),
185 (SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS
),
186 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT
),
187 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT
),
188 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS
),
189 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT
),
190 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT
),
192 (SDVO_CMD_SET_TV_RESOLUTION_SUPPORT
),
193 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH
),};
195 #define SDVO_NAME(dev_priv) \
196 ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
197 #define SDVO_PRIV(output) ((struct psb_intel_sdvo_priv *) (output)->dev_priv)
199 static void psb_intel_sdvo_write_cmd(struct psb_intel_output
*psb_intel_output
,
204 struct psb_intel_sdvo_priv
*sdvo_priv
= psb_intel_output
->dev_priv
;
208 DRM_DEBUG("%s: W: %02X ", SDVO_NAME(sdvo_priv
), cmd
);
209 for (i
= 0; i
< args_len
; i
++)
210 printk(KERN_INFO
"%02X ", ((u8
*) args
)[i
]);
215 sizeof(sdvo_cmd_names
) / sizeof(sdvo_cmd_names
[0]);
217 if (cmd
== sdvo_cmd_names
[i
].cmd
) {
218 printk("(%s)", sdvo_cmd_names
[i
].name
);
223 sizeof(sdvo_cmd_names
) / sizeof(sdvo_cmd_names
[0]))
224 printk("(%02X)", cmd
);
228 for (i
= 0; i
< args_len
; i
++) {
229 psb_intel_sdvo_write_byte(psb_intel_output
,
234 psb_intel_sdvo_write_byte(psb_intel_output
, SDVO_I2C_OPCODE
, cmd
);
237 static const char *const cmd_status_names
[] = {
243 "Target not specified",
244 "Scaling not supported"
247 static u8
psb_intel_sdvo_read_response(
248 struct psb_intel_output
*psb_intel_output
,
249 void *response
, int response_len
)
251 struct psb_intel_sdvo_priv
*sdvo_priv
= psb_intel_output
->dev_priv
;
257 /* Read the command response */
258 for (i
= 0; i
< response_len
; i
++) {
259 psb_intel_sdvo_read_byte(psb_intel_output
,
260 SDVO_I2C_RETURN_0
+ i
,
261 &((u8
*) response
)[i
]);
264 /* read the return status */
265 psb_intel_sdvo_read_byte(psb_intel_output
,
270 DRM_DEBUG("%s: R: ", SDVO_NAME(sdvo_priv
));
271 for (i
= 0; i
< response_len
; i
++)
272 printk(KERN_INFO
"%02X ", ((u8
*) response
)[i
]);
275 if (status
<= SDVO_CMD_STATUS_SCALING_NOT_SUPP
)
276 printk(KERN_INFO
"(%s)",
277 cmd_status_names
[status
]);
279 printk(KERN_INFO
"(??? %d)", status
);
283 if (status
!= SDVO_CMD_STATUS_PENDING
)
292 int psb_intel_sdvo_get_pixel_multiplier(struct drm_display_mode
*mode
)
294 if (mode
->clock
>= 100000)
296 else if (mode
->clock
>= 50000)
303 * Don't check status code from this as it switches the bus back to the
304 * SDVO chips which defeats the purpose of doing a bus switch in the first
307 void psb_intel_sdvo_set_control_bus_switch(
308 struct psb_intel_output
*psb_intel_output
,
311 psb_intel_sdvo_write_cmd(psb_intel_output
,
312 SDVO_CMD_SET_CONTROL_BUS_SWITCH
,
317 static bool psb_intel_sdvo_set_target_input(
318 struct psb_intel_output
*psb_intel_output
,
319 bool target_0
, bool target_1
)
321 struct psb_intel_sdvo_set_target_input_args targets
= { 0 };
324 if (target_0
&& target_1
)
325 return SDVO_CMD_STATUS_NOTSUPP
;
328 targets
.target_1
= 1;
330 psb_intel_sdvo_write_cmd(psb_intel_output
, SDVO_CMD_SET_TARGET_INPUT
,
331 &targets
, sizeof(targets
));
333 status
= psb_intel_sdvo_read_response(psb_intel_output
, NULL
, 0);
335 return status
== SDVO_CMD_STATUS_SUCCESS
;
339 * Return whether each input is trained.
341 * This function is making an assumption about the layout of the response,
342 * which should be checked against the docs.
344 static bool psb_intel_sdvo_get_trained_inputs(struct psb_intel_output
345 *psb_intel_output
, bool *input_1
,
348 struct psb_intel_sdvo_get_trained_inputs_response response
;
351 psb_intel_sdvo_write_cmd(psb_intel_output
, SDVO_CMD_GET_TRAINED_INPUTS
,
354 psb_intel_sdvo_read_response(psb_intel_output
, &response
,
356 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
359 *input_1
= response
.input0_trained
;
360 *input_2
= response
.input1_trained
;
364 static bool psb_intel_sdvo_get_active_outputs(struct psb_intel_output
365 *psb_intel_output
, u16
*outputs
)
369 psb_intel_sdvo_write_cmd(psb_intel_output
, SDVO_CMD_GET_ACTIVE_OUTPUTS
,
372 psb_intel_sdvo_read_response(psb_intel_output
, outputs
,
375 return status
== SDVO_CMD_STATUS_SUCCESS
;
378 static bool psb_intel_sdvo_set_active_outputs(struct psb_intel_output
379 *psb_intel_output
, u16 outputs
)
383 psb_intel_sdvo_write_cmd(psb_intel_output
, SDVO_CMD_SET_ACTIVE_OUTPUTS
,
384 &outputs
, sizeof(outputs
));
385 status
= psb_intel_sdvo_read_response(psb_intel_output
, NULL
, 0);
386 return status
== SDVO_CMD_STATUS_SUCCESS
;
389 static bool psb_intel_sdvo_set_encoder_power_state(struct psb_intel_output
390 *psb_intel_output
, int mode
)
392 u8 status
, state
= SDVO_ENCODER_STATE_ON
;
395 case DRM_MODE_DPMS_ON
:
396 state
= SDVO_ENCODER_STATE_ON
;
398 case DRM_MODE_DPMS_STANDBY
:
399 state
= SDVO_ENCODER_STATE_STANDBY
;
401 case DRM_MODE_DPMS_SUSPEND
:
402 state
= SDVO_ENCODER_STATE_SUSPEND
;
404 case DRM_MODE_DPMS_OFF
:
405 state
= SDVO_ENCODER_STATE_OFF
;
409 psb_intel_sdvo_write_cmd(psb_intel_output
,
410 SDVO_CMD_SET_ENCODER_POWER_STATE
, &state
,
412 status
= psb_intel_sdvo_read_response(psb_intel_output
, NULL
, 0);
414 return status
== SDVO_CMD_STATUS_SUCCESS
;
417 static bool psb_intel_sdvo_get_input_pixel_clock_range(struct psb_intel_output
422 struct psb_intel_sdvo_pixel_clock_range clocks
;
425 psb_intel_sdvo_write_cmd(psb_intel_output
,
426 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE
, NULL
,
430 psb_intel_sdvo_read_response(psb_intel_output
, &clocks
,
433 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
436 /* Convert the values from units of 10 kHz to kHz. */
437 *clock_min
= clocks
.min
* 10;
438 *clock_max
= clocks
.max
* 10;
443 static bool psb_intel_sdvo_set_target_output(
444 struct psb_intel_output
*psb_intel_output
,
449 psb_intel_sdvo_write_cmd(psb_intel_output
, SDVO_CMD_SET_TARGET_OUTPUT
,
450 &outputs
, sizeof(outputs
));
452 status
= psb_intel_sdvo_read_response(psb_intel_output
, NULL
, 0);
453 return status
== SDVO_CMD_STATUS_SUCCESS
;
456 static bool psb_intel_sdvo_get_timing(struct psb_intel_output
*psb_intel_output
,
457 u8 cmd
, struct psb_intel_sdvo_dtd
*dtd
)
461 psb_intel_sdvo_write_cmd(psb_intel_output
, cmd
, NULL
, 0);
462 status
= psb_intel_sdvo_read_response(psb_intel_output
, &dtd
->part1
,
464 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
467 psb_intel_sdvo_write_cmd(psb_intel_output
, cmd
+ 1, NULL
, 0);
468 status
= psb_intel_sdvo_read_response(psb_intel_output
, &dtd
->part2
,
470 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
476 static bool psb_intel_sdvo_get_input_timing(
477 struct psb_intel_output
*psb_intel_output
,
478 struct psb_intel_sdvo_dtd
*dtd
)
480 return psb_intel_sdvo_get_timing(psb_intel_output
,
481 SDVO_CMD_GET_INPUT_TIMINGS_PART1
,
485 static bool psb_intel_sdvo_set_timing(
486 struct psb_intel_output
*psb_intel_output
,
488 struct psb_intel_sdvo_dtd
*dtd
)
492 psb_intel_sdvo_write_cmd(psb_intel_output
, cmd
, &dtd
->part1
,
494 status
= psb_intel_sdvo_read_response(psb_intel_output
, NULL
, 0);
495 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
498 psb_intel_sdvo_write_cmd(psb_intel_output
, cmd
+ 1, &dtd
->part2
,
500 status
= psb_intel_sdvo_read_response(psb_intel_output
, NULL
, 0);
501 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
507 static bool psb_intel_sdvo_set_input_timing(
508 struct psb_intel_output
*psb_intel_output
,
509 struct psb_intel_sdvo_dtd
*dtd
)
511 return psb_intel_sdvo_set_timing(psb_intel_output
,
512 SDVO_CMD_SET_INPUT_TIMINGS_PART1
,
516 static bool psb_intel_sdvo_set_output_timing(
517 struct psb_intel_output
*psb_intel_output
,
518 struct psb_intel_sdvo_dtd
*dtd
)
520 return psb_intel_sdvo_set_timing(psb_intel_output
,
521 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1
,
525 static int psb_intel_sdvo_get_clock_rate_mult(struct psb_intel_output
530 psb_intel_sdvo_write_cmd(psb_intel_output
,
531 SDVO_CMD_GET_CLOCK_RATE_MULT
,
535 status
= psb_intel_sdvo_read_response(psb_intel_output
, &response
, 1);
537 if (status
!= SDVO_CMD_STATUS_SUCCESS
) {
538 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
539 return SDVO_CLOCK_RATE_MULT_1X
;
541 DRM_DEBUG("Current clock rate multiplier: %d\n", response
);
547 static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_output
548 *psb_intel_output
, u8 val
)
552 psb_intel_sdvo_write_cmd(psb_intel_output
,
553 SDVO_CMD_SET_CLOCK_RATE_MULT
,
557 status
= psb_intel_sdvo_read_response(psb_intel_output
, NULL
, 0);
558 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
564 static bool psb_sdvo_set_current_inoutmap(struct psb_intel_output
*output
,
571 struct psb_intel_sdvo_priv
*sdvo_priv
= output
->dev_priv
;
573 /* Make all fields of the args/ret to zero */
574 memset(byArgs
, 0, sizeof(byArgs
));
576 /* Fill up the argument values; */
577 byArgs
[0] = (u8
) (in0outputmask
& 0xFF);
578 byArgs
[1] = (u8
) ((in0outputmask
>> 8) & 0xFF);
579 byArgs
[2] = (u8
) (in1outputmask
& 0xFF);
580 byArgs
[3] = (u8
) ((in1outputmask
>> 8) & 0xFF);
583 /*save inoutmap arg here*/
584 for (i
= 0; i
< 4; i
++)
585 sdvo_priv
->in_out_map
[i
] = byArgs
[0];
587 psb_intel_sdvo_write_cmd(output
, SDVO_CMD_SET_IN_OUT_MAP
, byArgs
, 4);
588 status
= psb_intel_sdvo_read_response(output
, NULL
, 0);
590 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
596 static void psb_intel_sdvo_set_iomap(struct psb_intel_output
*output
)
598 u32 dwCurrentSDVOIn0
= 0;
599 u32 dwCurrentSDVOIn1
= 0;
603 struct psb_intel_sdvo_priv
*sdvo_priv
= output
->dev_priv
;
605 /* Please DO NOT change the following code. */
606 /* SDVOB_IN0 or SDVOB_IN1 ==> sdvo_in0 */
607 /* SDVOC_IN0 or SDVOC_IN1 ==> sdvo_in1 */
608 if (sdvo_priv
->by_input_wiring
& (SDVOB_IN0
| SDVOC_IN0
)) {
609 switch (sdvo_priv
->active_device
) {
610 case SDVO_DEVICE_LVDS
:
611 dwDevMask
= SDVO_OUTPUT_LVDS0
| SDVO_OUTPUT_LVDS1
;
613 case SDVO_DEVICE_TMDS
:
614 dwDevMask
= SDVO_OUTPUT_TMDS0
| SDVO_OUTPUT_TMDS1
;
618 SDVO_OUTPUT_YPRPB0
| SDVO_OUTPUT_SVID0
|
619 SDVO_OUTPUT_CVBS0
| SDVO_OUTPUT_YPRPB1
|
620 SDVO_OUTPUT_SVID1
| SDVO_OUTPUT_CVBS1
|
621 SDVO_OUTPUT_SCART0
| SDVO_OUTPUT_SCART1
;
623 case SDVO_DEVICE_CRT
:
624 dwDevMask
= SDVO_OUTPUT_RGB0
| SDVO_OUTPUT_RGB1
;
627 dwCurrentSDVOIn0
= (sdvo_priv
->active_outputs
& dwDevMask
);
628 } else if (sdvo_priv
->by_input_wiring
& (SDVOB_IN1
| SDVOC_IN1
)) {
629 switch (sdvo_priv
->active_device
) {
630 case SDVO_DEVICE_LVDS
:
631 dwDevMask
= SDVO_OUTPUT_LVDS0
| SDVO_OUTPUT_LVDS1
;
633 case SDVO_DEVICE_TMDS
:
634 dwDevMask
= SDVO_OUTPUT_TMDS0
| SDVO_OUTPUT_TMDS1
;
638 SDVO_OUTPUT_YPRPB0
| SDVO_OUTPUT_SVID0
|
639 SDVO_OUTPUT_CVBS0
| SDVO_OUTPUT_YPRPB1
|
640 SDVO_OUTPUT_SVID1
| SDVO_OUTPUT_CVBS1
|
641 SDVO_OUTPUT_SCART0
| SDVO_OUTPUT_SCART1
;
643 case SDVO_DEVICE_CRT
:
644 dwDevMask
= SDVO_OUTPUT_RGB0
| SDVO_OUTPUT_RGB1
;
647 dwCurrentSDVOIn1
= (sdvo_priv
->active_outputs
& dwDevMask
);
650 psb_sdvo_set_current_inoutmap(output
, dwCurrentSDVOIn0
,
655 static bool psb_intel_sdvo_mode_fixup(struct drm_encoder
*encoder
,
656 struct drm_display_mode
*mode
,
657 struct drm_display_mode
*adjusted_mode
)
659 /* Make the CRTC code factor in the SDVO pixel multiplier. The SDVO
660 * device will be told of the multiplier during mode_set.
662 adjusted_mode
->clock
*= psb_intel_sdvo_get_pixel_multiplier(mode
);
666 static void psb_intel_sdvo_mode_set(struct drm_encoder
*encoder
,
667 struct drm_display_mode
*mode
,
668 struct drm_display_mode
*adjusted_mode
)
670 struct drm_device
*dev
= encoder
->dev
;
671 struct drm_crtc
*crtc
= encoder
->crtc
;
672 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
673 struct psb_intel_output
*psb_intel_output
=
674 enc_to_psb_intel_output(encoder
);
675 struct psb_intel_sdvo_priv
*sdvo_priv
= psb_intel_output
->dev_priv
;
677 u16 h_blank_len
, h_sync_len
, v_blank_len
, v_sync_len
;
678 u16 h_sync_offset
, v_sync_offset
;
680 struct psb_intel_sdvo_dtd output_dtd
;
681 int sdvo_pixel_multiply
;
686 psb_intel_sdvo_set_target_output(psb_intel_output
, 0);
688 width
= mode
->crtc_hdisplay
;
689 height
= mode
->crtc_vdisplay
;
691 /* do some mode translations */
692 h_blank_len
= mode
->crtc_hblank_end
- mode
->crtc_hblank_start
;
693 h_sync_len
= mode
->crtc_hsync_end
- mode
->crtc_hsync_start
;
695 v_blank_len
= mode
->crtc_vblank_end
- mode
->crtc_vblank_start
;
696 v_sync_len
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
698 h_sync_offset
= mode
->crtc_hsync_start
- mode
->crtc_hblank_start
;
699 v_sync_offset
= mode
->crtc_vsync_start
- mode
->crtc_vblank_start
;
701 output_dtd
.part1
.clock
= mode
->clock
/ 10;
702 output_dtd
.part1
.h_active
= width
& 0xff;
703 output_dtd
.part1
.h_blank
= h_blank_len
& 0xff;
704 output_dtd
.part1
.h_high
= (((width
>> 8) & 0xf) << 4) |
705 ((h_blank_len
>> 8) & 0xf);
706 output_dtd
.part1
.v_active
= height
& 0xff;
707 output_dtd
.part1
.v_blank
= v_blank_len
& 0xff;
708 output_dtd
.part1
.v_high
= (((height
>> 8) & 0xf) << 4) |
709 ((v_blank_len
>> 8) & 0xf);
711 output_dtd
.part2
.h_sync_off
= h_sync_offset
;
712 output_dtd
.part2
.h_sync_width
= h_sync_len
& 0xff;
713 output_dtd
.part2
.v_sync_off_width
= (v_sync_offset
& 0xf) << 4 |
715 output_dtd
.part2
.sync_off_width_high
=
716 ((h_sync_offset
& 0x300) >> 2) | ((h_sync_len
& 0x300) >> 4) |
717 ((v_sync_offset
& 0x30) >> 2) | ((v_sync_len
& 0x30) >> 4);
719 output_dtd
.part2
.dtd_flags
= 0x18;
720 if (mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
721 output_dtd
.part2
.dtd_flags
|= 0x2;
722 if (mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
723 output_dtd
.part2
.dtd_flags
|= 0x4;
725 output_dtd
.part2
.sdvo_flags
= 0;
726 output_dtd
.part2
.v_sync_off_high
= v_sync_offset
& 0xc0;
727 output_dtd
.part2
.reserved
= 0;
729 /* Set the output timing to the screen */
730 psb_intel_sdvo_set_target_output(psb_intel_output
,
731 sdvo_priv
->active_outputs
);
733 /* Set the input timing to the screen. Assume always input 0. */
734 psb_intel_sdvo_set_target_input(psb_intel_output
, true, false);
736 psb_intel_sdvo_set_output_timing(psb_intel_output
, &output_dtd
);
738 /* We would like to use i830_sdvo_create_preferred_input_timing() to
739 * provide the device with a timing it can support, if it supports that
740 * feature. However, presumably we would need to adjust the CRTC to
741 * output the preferred timing, and we don't support that currently.
743 psb_intel_sdvo_set_input_timing(psb_intel_output
, &output_dtd
);
745 switch (psb_intel_sdvo_get_pixel_multiplier(mode
)) {
747 psb_intel_sdvo_set_clock_rate_mult(psb_intel_output
,
748 SDVO_CLOCK_RATE_MULT_1X
);
751 psb_intel_sdvo_set_clock_rate_mult(psb_intel_output
,
752 SDVO_CLOCK_RATE_MULT_2X
);
755 psb_intel_sdvo_set_clock_rate_mult(psb_intel_output
,
756 SDVO_CLOCK_RATE_MULT_4X
);
760 /* Set the SDVO control regs. */
761 sdvox
= REG_READ(sdvo_priv
->output_device
);
762 switch (sdvo_priv
->output_device
) {
764 sdvox
&= SDVOB_PRESERVE_MASK
;
767 sdvox
&= SDVOC_PRESERVE_MASK
;
770 sdvox
|= (9 << 19) | SDVO_BORDER_ENABLE
;
771 if (psb_intel_crtc
->pipe
== 1)
772 sdvox
|= SDVO_PIPE_B_SELECT
;
774 sdvo_pixel_multiply
= psb_intel_sdvo_get_pixel_multiplier(mode
);
776 psb_intel_sdvo_write_sdvox(psb_intel_output
, sdvox
);
778 psb_intel_sdvo_set_iomap(psb_intel_output
);
781 static void psb_intel_sdvo_dpms(struct drm_encoder
*encoder
, int mode
)
783 struct drm_device
*dev
= encoder
->dev
;
784 struct psb_intel_output
*psb_intel_output
=
785 enc_to_psb_intel_output(encoder
);
786 struct psb_intel_sdvo_priv
*sdvo_priv
= psb_intel_output
->dev_priv
;
789 if (mode
!= DRM_MODE_DPMS_ON
) {
790 psb_intel_sdvo_set_active_outputs(psb_intel_output
, 0);
792 psb_intel_sdvo_set_encoder_power_state(
796 if (mode
== DRM_MODE_DPMS_OFF
) {
797 temp
= REG_READ(sdvo_priv
->output_device
);
798 if ((temp
& SDVO_ENABLE
) != 0) {
799 psb_intel_sdvo_write_sdvox(psb_intel_output
,
809 temp
= REG_READ(sdvo_priv
->output_device
);
810 if ((temp
& SDVO_ENABLE
) == 0)
811 psb_intel_sdvo_write_sdvox(psb_intel_output
,
813 for (i
= 0; i
< 2; i
++)
814 psb_intel_wait_for_vblank(dev
);
817 psb_intel_sdvo_get_trained_inputs(psb_intel_output
,
822 /* Warn if the device reported failure to sync.
823 * A lot of SDVO devices fail to notify of sync, but it's
824 * a given it the status is a success, we succeeded.
826 if (status
== SDVO_CMD_STATUS_SUCCESS
&& !input1
) {
828 ("First %s output reported failure to sync\n",
829 SDVO_NAME(sdvo_priv
));
833 psb_intel_sdvo_set_encoder_power_state(
836 psb_intel_sdvo_set_active_outputs(psb_intel_output
,
837 sdvo_priv
->active_outputs
);
842 static void psb_intel_sdvo_save(struct drm_connector
*connector
)
844 struct drm_device
*dev
= connector
->dev
;
845 struct psb_intel_output
*psb_intel_output
=
846 to_psb_intel_output(connector
);
847 struct psb_intel_sdvo_priv
*sdvo_priv
= psb_intel_output
->dev_priv
;
850 sdvo_priv
->save_sdvo_mult
=
851 psb_intel_sdvo_get_clock_rate_mult(psb_intel_output
);
852 psb_intel_sdvo_get_active_outputs(psb_intel_output
,
853 &sdvo_priv
->save_active_outputs
);
855 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x1) {
856 psb_intel_sdvo_set_target_input(psb_intel_output
,
859 psb_intel_sdvo_get_input_timing(psb_intel_output
,
860 &sdvo_priv
->save_input_dtd_1
);
863 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x2) {
864 psb_intel_sdvo_set_target_input(psb_intel_output
,
867 psb_intel_sdvo_get_input_timing(psb_intel_output
,
868 &sdvo_priv
->save_input_dtd_2
);
870 sdvo_priv
->save_SDVOX
= REG_READ(sdvo_priv
->output_device
);
872 /*TODO: save the in_out_map state*/
875 static void psb_intel_sdvo_restore(struct drm_connector
*connector
)
877 struct drm_device
*dev
= connector
->dev
;
878 struct psb_intel_output
*psb_intel_output
=
879 to_psb_intel_output(connector
);
880 struct psb_intel_sdvo_priv
*sdvo_priv
= psb_intel_output
->dev_priv
;
886 psb_intel_sdvo_set_active_outputs(psb_intel_output
, 0);
888 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x1) {
889 psb_intel_sdvo_set_target_input(psb_intel_output
, true, false);
890 psb_intel_sdvo_set_input_timing(psb_intel_output
,
891 &sdvo_priv
->save_input_dtd_1
);
894 if (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x2) {
895 psb_intel_sdvo_set_target_input(psb_intel_output
, false, true);
896 psb_intel_sdvo_set_input_timing(psb_intel_output
,
897 &sdvo_priv
->save_input_dtd_2
);
900 psb_intel_sdvo_set_clock_rate_mult(psb_intel_output
,
901 sdvo_priv
->save_sdvo_mult
);
903 REG_WRITE(sdvo_priv
->output_device
, sdvo_priv
->save_SDVOX
);
905 if (sdvo_priv
->save_SDVOX
& SDVO_ENABLE
) {
906 for (i
= 0; i
< 2; i
++)
907 psb_intel_wait_for_vblank(dev
);
909 psb_intel_sdvo_get_trained_inputs(psb_intel_output
,
912 if (status
== SDVO_CMD_STATUS_SUCCESS
&& !input1
)
914 ("First %s output reported failure to sync\n",
915 SDVO_NAME(sdvo_priv
));
918 psb_intel_sdvo_set_active_outputs(psb_intel_output
,
919 sdvo_priv
->save_active_outputs
);
921 /*TODO: restore in_out_map*/
922 psb_intel_sdvo_write_cmd(psb_intel_output
,
923 SDVO_CMD_SET_IN_OUT_MAP
,
924 sdvo_priv
->in_out_map
,
927 psb_intel_sdvo_read_response(psb_intel_output
, NULL
, 0);
930 static int psb_intel_sdvo_mode_valid(struct drm_connector
*connector
,
931 struct drm_display_mode
*mode
)
933 struct psb_intel_output
*psb_intel_output
=
934 to_psb_intel_output(connector
);
935 struct psb_intel_sdvo_priv
*sdvo_priv
= psb_intel_output
->dev_priv
;
937 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)
938 return MODE_NO_DBLESCAN
;
940 if (sdvo_priv
->pixel_clock_min
> mode
->clock
)
941 return MODE_CLOCK_LOW
;
943 if (sdvo_priv
->pixel_clock_max
< mode
->clock
)
944 return MODE_CLOCK_HIGH
;
949 static bool psb_intel_sdvo_get_capabilities(
950 struct psb_intel_output
*psb_intel_output
,
951 struct psb_intel_sdvo_caps
*caps
)
955 psb_intel_sdvo_write_cmd(psb_intel_output
,
956 SDVO_CMD_GET_DEVICE_CAPS
,
959 status
= psb_intel_sdvo_read_response(psb_intel_output
,
962 if (status
!= SDVO_CMD_STATUS_SUCCESS
)
968 struct drm_connector
*psb_intel_sdvo_find(struct drm_device
*dev
, int sdvoB
)
970 struct drm_connector
*connector
= NULL
;
971 struct psb_intel_output
*iout
= NULL
;
972 struct psb_intel_sdvo_priv
*sdvo
;
974 /* find the sdvo connector */
975 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
977 iout
= to_psb_intel_output(connector
);
979 if (iout
->type
!= INTEL_OUTPUT_SDVO
)
982 sdvo
= iout
->dev_priv
;
984 if (sdvo
->output_device
== SDVOB
&& sdvoB
)
987 if (sdvo
->output_device
== SDVOC
&& !sdvoB
)
995 int psb_intel_sdvo_supports_hotplug(struct drm_connector
*connector
)
999 struct psb_intel_output
*psb_intel_output
;
1005 psb_intel_output
= to_psb_intel_output(connector
);
1007 psb_intel_sdvo_write_cmd(psb_intel_output
,
1008 SDVO_CMD_GET_HOT_PLUG_SUPPORT
,
1011 status
= psb_intel_sdvo_read_response(psb_intel_output
,
1015 if (response
[0] != 0)
1021 void psb_intel_sdvo_set_hotplug(struct drm_connector
*connector
, int on
)
1025 struct psb_intel_output
*psb_intel_output
=
1026 to_psb_intel_output(connector
);
1028 psb_intel_sdvo_write_cmd(psb_intel_output
,
1029 SDVO_CMD_GET_ACTIVE_HOT_PLUG
,
1032 psb_intel_sdvo_read_response(psb_intel_output
, &response
, 2);
1035 psb_intel_sdvo_write_cmd(psb_intel_output
,
1036 SDVO_CMD_GET_HOT_PLUG_SUPPORT
, NULL
,
1038 status
= psb_intel_sdvo_read_response(psb_intel_output
,
1042 psb_intel_sdvo_write_cmd(psb_intel_output
,
1043 SDVO_CMD_SET_ACTIVE_HOT_PLUG
,
1048 psb_intel_sdvo_write_cmd(psb_intel_output
,
1049 SDVO_CMD_SET_ACTIVE_HOT_PLUG
,
1053 psb_intel_sdvo_write_cmd(psb_intel_output
,
1054 SDVO_CMD_GET_ACTIVE_HOT_PLUG
,
1057 psb_intel_sdvo_read_response(psb_intel_output
, &response
, 2);
1060 static enum drm_connector_status
psb_intel_sdvo_detect(struct drm_connector
1061 *connector
, bool force
)
1065 struct psb_intel_output
*psb_intel_output
=
1066 to_psb_intel_output(connector
);
1068 psb_intel_sdvo_write_cmd(psb_intel_output
,
1069 SDVO_CMD_GET_ATTACHED_DISPLAYS
,
1072 status
= psb_intel_sdvo_read_response(psb_intel_output
, &response
, 2);
1074 DRM_DEBUG("SDVO response %d %d\n", response
[0], response
[1]);
1075 if ((response
[0] != 0) || (response
[1] != 0))
1076 return connector_status_connected
;
1078 return connector_status_disconnected
;
1081 static int psb_intel_sdvo_get_modes(struct drm_connector
*connector
)
1083 struct psb_intel_output
*psb_intel_output
=
1084 to_psb_intel_output(connector
);
1086 /* set the bus switch and get the modes */
1087 psb_intel_sdvo_set_control_bus_switch(psb_intel_output
,
1088 SDVO_CONTROL_BUS_DDC2
);
1089 psb_intel_ddc_get_modes(psb_intel_output
);
1091 if (list_empty(&connector
->probed_modes
))
1096 static void psb_intel_sdvo_destroy(struct drm_connector
*connector
)
1098 struct psb_intel_output
*psb_intel_output
=
1099 to_psb_intel_output(connector
);
1101 if (psb_intel_output
->i2c_bus
)
1102 psb_intel_i2c_destroy(psb_intel_output
->i2c_bus
);
1103 drm_sysfs_connector_remove(connector
);
1104 drm_connector_cleanup(connector
);
1105 kfree(psb_intel_output
);
1108 static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs
= {
1109 .dpms
= psb_intel_sdvo_dpms
,
1110 .mode_fixup
= psb_intel_sdvo_mode_fixup
,
1111 .prepare
= psb_intel_encoder_prepare
,
1112 .mode_set
= psb_intel_sdvo_mode_set
,
1113 .commit
= psb_intel_encoder_commit
,
1116 static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs
= {
1117 .dpms
= drm_helper_connector_dpms
,
1118 .save
= psb_intel_sdvo_save
,
1119 .restore
= psb_intel_sdvo_restore
,
1120 .detect
= psb_intel_sdvo_detect
,
1121 .fill_modes
= drm_helper_probe_single_connector_modes
,
1122 .destroy
= psb_intel_sdvo_destroy
,
1125 static const struct drm_connector_helper_funcs
1126 psb_intel_sdvo_connector_helper_funcs
= {
1127 .get_modes
= psb_intel_sdvo_get_modes
,
1128 .mode_valid
= psb_intel_sdvo_mode_valid
,
1129 .best_encoder
= psb_intel_best_encoder
,
1132 void psb_intel_sdvo_enc_destroy(struct drm_encoder
*encoder
)
1134 drm_encoder_cleanup(encoder
);
1137 static const struct drm_encoder_funcs psb_intel_sdvo_enc_funcs
= {
1138 .destroy
= psb_intel_sdvo_enc_destroy
,
1142 void psb_intel_sdvo_init(struct drm_device
*dev
, int output_device
)
1144 struct drm_connector
*connector
;
1145 struct psb_intel_output
*psb_intel_output
;
1146 struct psb_intel_sdvo_priv
*sdvo_priv
;
1147 struct psb_intel_i2c_chan
*i2cbus
= NULL
;
1151 int encoder_type
, output_id
;
1154 kcalloc(sizeof(struct psb_intel_output
) +
1155 sizeof(struct psb_intel_sdvo_priv
), 1, GFP_KERNEL
);
1156 if (!psb_intel_output
)
1159 connector
= &psb_intel_output
->base
;
1161 drm_connector_init(dev
, connector
, &psb_intel_sdvo_connector_funcs
,
1162 DRM_MODE_CONNECTOR_Unknown
);
1163 drm_connector_helper_add(connector
,
1164 &psb_intel_sdvo_connector_helper_funcs
);
1165 sdvo_priv
= (struct psb_intel_sdvo_priv
*) (psb_intel_output
+ 1);
1166 psb_intel_output
->type
= INTEL_OUTPUT_SDVO
;
1168 connector
->interlace_allowed
= 0;
1169 connector
->doublescan_allowed
= 0;
1171 /* setup the DDC bus. */
1172 if (output_device
== SDVOB
)
1174 psb_intel_i2c_create(dev
, GPIOE
, "SDVOCTRL_E for SDVOB");
1177 psb_intel_i2c_create(dev
, GPIOE
, "SDVOCTRL_E for SDVOC");
1182 sdvo_priv
->i2c_bus
= i2cbus
;
1184 if (output_device
== SDVOB
) {
1186 sdvo_priv
->by_input_wiring
= SDVOB_IN0
;
1187 sdvo_priv
->i2c_bus
->slave_addr
= 0x38;
1190 sdvo_priv
->i2c_bus
->slave_addr
= 0x39;
1193 sdvo_priv
->output_device
= output_device
;
1194 psb_intel_output
->i2c_bus
= i2cbus
;
1195 psb_intel_output
->dev_priv
= sdvo_priv
;
1198 /* Read the regs to test if we can talk to the device */
1199 for (i
= 0; i
< 0x40; i
++) {
1200 if (!psb_intel_sdvo_read_byte(psb_intel_output
, i
, &ch
[i
])) {
1201 DRM_DEBUG("No SDVO device found on SDVO%c\n",
1202 output_device
== SDVOB
? 'B' : 'C');
1207 psb_intel_sdvo_get_capabilities(psb_intel_output
, &sdvo_priv
->caps
);
1209 memset(&sdvo_priv
->active_outputs
, 0,
1210 sizeof(sdvo_priv
->active_outputs
));
1212 /* TODO, CVBS, SVID, YPRPB & SCART outputs. */
1213 if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_RGB0
) {
1214 sdvo_priv
->active_outputs
= SDVO_OUTPUT_RGB0
;
1215 sdvo_priv
->active_device
= SDVO_DEVICE_CRT
;
1216 connector
->display_info
.subpixel_order
=
1217 SubPixelHorizontalRGB
;
1218 encoder_type
= DRM_MODE_ENCODER_DAC
;
1219 connector_type
= DRM_MODE_CONNECTOR_VGA
;
1220 } else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_RGB1
) {
1221 sdvo_priv
->active_outputs
= SDVO_OUTPUT_RGB1
;
1222 sdvo_priv
->active_outputs
= SDVO_DEVICE_CRT
;
1223 connector
->display_info
.subpixel_order
=
1224 SubPixelHorizontalRGB
;
1225 encoder_type
= DRM_MODE_ENCODER_DAC
;
1226 connector_type
= DRM_MODE_CONNECTOR_VGA
;
1227 } else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_TMDS0
) {
1228 sdvo_priv
->active_outputs
= SDVO_OUTPUT_TMDS0
;
1229 sdvo_priv
->active_device
= SDVO_DEVICE_TMDS
;
1230 connector
->display_info
.subpixel_order
=
1231 SubPixelHorizontalRGB
;
1232 encoder_type
= DRM_MODE_ENCODER_TMDS
;
1233 connector_type
= DRM_MODE_CONNECTOR_DVID
;
1234 } else if (sdvo_priv
->caps
.output_flags
& SDVO_OUTPUT_TMDS1
) {
1235 sdvo_priv
->active_outputs
= SDVO_OUTPUT_TMDS1
;
1236 sdvo_priv
->active_device
= SDVO_DEVICE_TMDS
;
1237 connector
->display_info
.subpixel_order
=
1238 SubPixelHorizontalRGB
;
1239 encoder_type
= DRM_MODE_ENCODER_TMDS
;
1240 connector_type
= DRM_MODE_CONNECTOR_DVID
;
1242 unsigned char bytes
[2];
1244 memcpy(bytes
, &sdvo_priv
->caps
.output_flags
, 2);
1246 ("%s: No active RGB or TMDS outputs (0x%02x%02x)\n",
1247 SDVO_NAME(sdvo_priv
), bytes
[0], bytes
[1]);
1251 drm_encoder_init(dev
, &psb_intel_output
->enc
, &psb_intel_sdvo_enc_funcs
,
1253 drm_encoder_helper_add(&psb_intel_output
->enc
,
1254 &psb_intel_sdvo_helper_funcs
);
1255 connector
->connector_type
= connector_type
;
1257 drm_mode_connector_attach_encoder(&psb_intel_output
->base
,
1258 &psb_intel_output
->enc
);
1259 drm_sysfs_connector_add(connector
);
1261 /* Set the input timing to the screen. Assume always input 0. */
1262 psb_intel_sdvo_set_target_input(psb_intel_output
, true, false);
1264 psb_intel_sdvo_get_input_pixel_clock_range(psb_intel_output
,
1265 &sdvo_priv
->pixel_clock_min
,
1270 DRM_DEBUG("%s device VID/DID: %02X:%02X.%02X, "
1271 "clock range %dMHz - %dMHz, "
1272 "input 1: %c, input 2: %c, "
1273 "output 1: %c, output 2: %c\n",
1274 SDVO_NAME(sdvo_priv
),
1275 sdvo_priv
->caps
.vendor_id
, sdvo_priv
->caps
.device_id
,
1276 sdvo_priv
->caps
.device_rev_id
,
1277 sdvo_priv
->pixel_clock_min
/ 1000,
1278 sdvo_priv
->pixel_clock_max
/ 1000,
1279 (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x1) ? 'Y' : 'N',
1280 (sdvo_priv
->caps
.sdvo_inputs_mask
& 0x2) ? 'Y' : 'N',
1281 /* check currently supported outputs */
1282 sdvo_priv
->caps
.output_flags
&
1283 (SDVO_OUTPUT_TMDS0
| SDVO_OUTPUT_RGB0
) ? 'Y' : 'N',
1284 sdvo_priv
->caps
.output_flags
&
1285 (SDVO_OUTPUT_TMDS1
| SDVO_OUTPUT_RGB1
) ? 'Y' : 'N');
1287 psb_intel_output
->ddc_bus
= i2cbus
;
1292 psb_intel_i2c_destroy(psb_intel_output
->i2c_bus
);
1294 drm_connector_cleanup(connector
);
1295 kfree(psb_intel_output
);