drivers/staging/iio/adc/ad7192.c

   1 /*
   2  * AD7190 AD7192 AD7193 AD7195 SPI ADC driver
   3  *
   4  * Copyright 2011-2015 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2.
   7  */
   8
   9 #include <linux/interrupt.h>
  10 #include <linux/device.h>
  11 #include <linux/kernel.h>
  12 #include <linux/slab.h>
  13 #include <linux/sysfs.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/regulator/consumer.h>
  16 #include <linux/err.h>
  17 #include <linux/sched.h>
  18 #include <linux/delay.h>
  19
  20 #include <linux/iio/iio.h>
  21 #include <linux/iio/sysfs.h>
  22 #include <linux/iio/buffer.h>
  23 #include <linux/iio/trigger.h>
  24 #include <linux/iio/trigger_consumer.h>
  25 #include <linux/iio/triggered_buffer.h>
  26 #include <linux/iio/adc/ad_sigma_delta.h>
  27
  28 #include "ad7192.h"
  29
  30 /* Registers */
  31 #define AD7192_REG_COMM         0 /* Communications Register (WO, 8-bit) */
  32 #define AD7192_REG_STAT         0 /* Status Register         (RO, 8-bit) */
  33 #define AD7192_REG_MODE         1 /* Mode Register           (RW, 24-bit */
  34 #define AD7192_REG_CONF         2 /* Configuration Register  (RW, 24-bit) */
  35 #define AD7192_REG_DATA         3 /* Data Register           (RO, 24/32-bit) */
  36 #define AD7192_REG_ID           4 /* ID Register             (RO, 8-bit) */
  37 #define AD7192_REG_GPOCON       5 /* GPOCON Register         (RO, 8-bit) */
  38 #define AD7192_REG_OFFSET       6 /* Offset Register         (RW, 16-bit */
  39                                   /* (AD7792)/24-bit (AD7192)) */
  40 #define AD7192_REG_FULLSALE     7 /* Full-Scale Register */
  41                                   /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
  42
  43 /* Communications Register Bit Designations (AD7192_REG_COMM) */
  44 #define AD7192_COMM_WEN         BIT(7) /* Write Enable */
  45 #define AD7192_COMM_WRITE       0 /* Write Operation */
  46 #define AD7192_COMM_READ        BIT(6) /* Read Operation */
  47 #define AD7192_COMM_ADDR(x)     (((x) & 0x7) << 3) /* Register Address */
  48 #define AD7192_COMM_CREAD       BIT(2) /* Continuous Read of Data Register */
  49
  50 /* Status Register Bit Designations (AD7192_REG_STAT) */
  51 #define AD7192_STAT_RDY         BIT(7) /* Ready */
  52 #define AD7192_STAT_ERR         BIT(6) /* Error (Overrange, Underrange) */
  53 #define AD7192_STAT_NOREF       BIT(5) /* Error no external reference */
  54 #define AD7192_STAT_PARITY      BIT(4) /* Parity */
  55 #define AD7192_STAT_CH3         BIT(2) /* Channel 3 */
  56 #define AD7192_STAT_CH2         BIT(1) /* Channel 2 */
  57 #define AD7192_STAT_CH1         BIT(0) /* Channel 1 */
  58
  59 /* Mode Register Bit Designations (AD7192_REG_MODE) */
  60 #define AD7192_MODE_SEL(x)      (((x) & 0x7) << 21) /* Operation Mode Select */
  61 #define AD7192_MODE_SEL_MASK    (0x7 << 21) /* Operation Mode Select Mask */
  62 #define AD7192_MODE_DAT_STA     BIT(20) /* Status Register transmission */
  63 #define AD7192_MODE_CLKSRC(x)   (((x) & 0x3) << 18) /* Clock Source Select */
  64 #define AD7192_MODE_SINC3       BIT(15) /* SINC3 Filter Select */
  65 #define AD7192_MODE_ACX         BIT(14) /* AC excitation enable(AD7195 only)*/
  66 #define AD7192_MODE_ENPAR       BIT(13) /* Parity Enable */
  67 #define AD7192_MODE_CLKDIV      BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
  68 #define AD7192_MODE_SCYCLE      BIT(11) /* Single cycle conversion */
  69 #define AD7192_MODE_REJ60       BIT(10) /* 50/60Hz notch filter */
  70 #define AD7192_MODE_RATE(x)     ((x) & 0x3FF) /* Filter Update Rate Select */
  71
  72 /* Mode Register: AD7192_MODE_SEL options */
  73 #define AD7192_MODE_CONT                0 /* Continuous Conversion Mode */
  74 #define AD7192_MODE_SINGLE              1 /* Single Conversion Mode */
  75 #define AD7192_MODE_IDLE                2 /* Idle Mode */
  76 #define AD7192_MODE_PWRDN               3 /* Power-Down Mode */
  77 #define AD7192_MODE_CAL_INT_ZERO        4 /* Internal Zero-Scale Calibration */
  78 #define AD7192_MODE_CAL_INT_FULL        5 /* Internal Full-Scale Calibration */
  79 #define AD7192_MODE_CAL_SYS_ZERO        6 /* System Zero-Scale Calibration */
  80 #define AD7192_MODE_CAL_SYS_FULL        7 /* System Full-Scale Calibration */
  81
  82 /* Mode Register: AD7192_MODE_CLKSRC options */
  83 #define AD7192_CLK_EXT_MCLK1_2          0 /* External 4.92 MHz Clock connected*/
  84                                           /* from MCLK1 to MCLK2 */
  85 #define AD7192_CLK_EXT_MCLK2            1 /* External Clock applied to MCLK2 */
  86 #define AD7192_CLK_INT                  2 /* Internal 4.92 MHz Clock not */
  87                                           /* available at the MCLK2 pin */
  88 #define AD7192_CLK_INT_CO               3 /* Internal 4.92 MHz Clock available*/
  89                                           /* at the MCLK2 pin */
  90
  91 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
  92
  93 #define AD7192_CONF_CHOP        BIT(23) /* CHOP enable */
  94 #define AD7192_CONF_REFSEL      BIT(20) /* REFIN1/REFIN2 Reference Select */
  95 #define AD7192_CONF_CHAN(x)     ((x) << 8) /* Channel select */
  96 #define AD7192_CONF_CHAN_MASK   (0x7FF << 8) /* Channel select mask */
  97 #define AD7192_CONF_BURN        BIT(7) /* Burnout current enable */
  98 #define AD7192_CONF_REFDET      BIT(6) /* Reference detect enable */
  99 #define AD7192_CONF_BUF         BIT(4) /* Buffered Mode Enable */
 100 #define AD7192_CONF_UNIPOLAR    BIT(3) /* Unipolar/Bipolar Enable */
 101 #define AD7192_CONF_GAIN(x)     ((x) & 0x7) /* Gain Select */
 102
 103 #define AD7192_CH_AIN1P_AIN2M   BIT(0) /* AIN1(+) - AIN2(-) */
 104 #define AD7192_CH_AIN3P_AIN4M   BIT(1) /* AIN3(+) - AIN4(-) */
 105 #define AD7192_CH_TEMP          BIT(2) /* Temp Sensor */
 106 #define AD7192_CH_AIN2P_AIN2M   BIT(3) /* AIN2(+) - AIN2(-) */
 107 #define AD7192_CH_AIN1          BIT(4) /* AIN1 - AINCOM */
 108 #define AD7192_CH_AIN2          BIT(5) /* AIN2 - AINCOM */
 109 #define AD7192_CH_AIN3          BIT(6) /* AIN3 - AINCOM */
 110 #define AD7192_CH_AIN4          BIT(7) /* AIN4 - AINCOM */
 111
 112 #define AD7193_CH_AIN1P_AIN2M   0x000  /* AIN1(+) - AIN2(-) */
 113 #define AD7193_CH_AIN3P_AIN4M   0x001  /* AIN3(+) - AIN4(-) */
 114 #define AD7193_CH_AIN5P_AIN6M   0x002  /* AIN5(+) - AIN6(-) */
 115 #define AD7193_CH_AIN7P_AIN8M   0x004  /* AIN7(+) - AIN8(-) */
 116 #define AD7193_CH_TEMP          0x100 /* Temp senseor */
 117 #define AD7193_CH_AIN2P_AIN2M   0x200 /* AIN2(+) - AIN2(-) */
 118 #define AD7193_CH_AIN1          0x401 /* AIN1 - AINCOM */
 119 #define AD7193_CH_AIN2          0x402 /* AIN2 - AINCOM */
 120 #define AD7193_CH_AIN3          0x404 /* AIN3 - AINCOM */
 121 #define AD7193_CH_AIN4          0x408 /* AIN4 - AINCOM */
 122 #define AD7193_CH_AIN5          0x410 /* AIN5 - AINCOM */
 123 #define AD7193_CH_AIN6          0x420 /* AIN6 - AINCOM */
 124 #define AD7193_CH_AIN7          0x440 /* AIN7 - AINCOM */
 125 #define AD7193_CH_AIN8          0x480 /* AIN7 - AINCOM */
 126 #define AD7193_CH_AINCOM        0x600 /* AINCOM - AINCOM */
 127
 128 /* ID Register Bit Designations (AD7192_REG_ID) */
 129 #define ID_AD7190               0x4
 130 #define ID_AD7192               0x0
 131 #define ID_AD7193               0x2
 132 #define ID_AD7195               0x6
 133 #define AD7192_ID_MASK          0x0F
 134
 135 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
 136 #define AD7192_GPOCON_BPDSW     BIT(6) /* Bridge power-down switch enable */
 137 #define AD7192_GPOCON_GP32EN    BIT(5) /* Digital Output P3 and P2 enable */
 138 #define AD7192_GPOCON_GP10EN    BIT(4) /* Digital Output P1 and P0 enable */
 139 #define AD7192_GPOCON_P3DAT     BIT(3) /* P3 state */
 140 #define AD7192_GPOCON_P2DAT     BIT(2) /* P2 state */
 141 #define AD7192_GPOCON_P1DAT     BIT(1) /* P1 state */
 142 #define AD7192_GPOCON_P0DAT     BIT(0) /* P0 state */
 143
 144 #define AD7192_INT_FREQ_MHZ     4915200
 145
 146 /* NOTE:
 147  * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
 148  * In order to avoid contentions on the SPI bus, it's therefore necessary
 149  * to use spi bus locking.
 150  *
 151  * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
 152  */
 153
 154 struct ad7192_state {
 155         struct regulator                *avdd;
 156         struct regulator                *dvdd;
 157         u16                             int_vref_mv;
 158         u32                             mclk;
 159         u32                             f_order;
 160         u32                             mode;
 161         u32                             conf;
 162         u32                             scale_avail[8][2];
 163         u8                              gpocon;
 164         u8                              devid;
 165
 166         struct ad_sigma_delta           sd;
 167 };
 168
 169 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
 170 {
 171         return container_of(sd, struct ad7192_state, sd);
 172 }
 173
 174 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
 175 {
 176         struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
 177
 178         st->conf &= ~AD7192_CONF_CHAN_MASK;
 179         st->conf |= AD7192_CONF_CHAN(channel);
 180
 181         return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
 182 }
 183
 184 static int ad7192_set_mode(struct ad_sigma_delta *sd,
 185                            enum ad_sigma_delta_mode mode)
 186 {
 187         struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
 188
 189         st->mode &= ~AD7192_MODE_SEL_MASK;
 190         st->mode |= AD7192_MODE_SEL(mode);
 191
 192         return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
 193 }
 194
 195 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
 196         .set_channel = ad7192_set_channel,
 197         .set_mode = ad7192_set_mode,
 198         .has_registers = true,
 199         .addr_shift = 3,
 200         .read_mask = BIT(6),
 201 };
 202
 203 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
 204         {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
 205         {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
 206         {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
 207         {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
 208         {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
 209         {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
 210         {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
 211         {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
 212 };
 213
 214 static int ad7192_calibrate_all(struct ad7192_state *st)
 215 {
 216                 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
 217                                 ARRAY_SIZE(ad7192_calib_arr));
 218 }
 219
 220 static int ad7192_setup(struct ad7192_state *st,
 221                         const struct ad7192_platform_data *pdata)
 222 {
 223         struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);
 224         unsigned long long scale_uv;
 225         int i, ret, id;
 226
 227         /* reset the serial interface */
 228         ret = ad_sd_reset(&st->sd, 48);
 229         if (ret < 0)
 230                 goto out;
 231         usleep_range(500, 1000); /* Wait for at least 500us */
 232
 233         /* write/read test for device presence */
 234         ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
 235         if (ret)
 236                 goto out;
 237
 238         id &= AD7192_ID_MASK;
 239
 240         if (id != st->devid)
 241                 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",
 242                          id);
 243
 244         switch (pdata->clock_source_sel) {
 245         case AD7192_CLK_EXT_MCLK1_2:
 246         case AD7192_CLK_EXT_MCLK2:
 247                 st->mclk = AD7192_INT_FREQ_MHZ;
 248                 break;
 249         case AD7192_CLK_INT:
 250         case AD7192_CLK_INT_CO:
 251                 if (pdata->ext_clk_hz)
 252                         st->mclk = pdata->ext_clk_hz;
 253                 else
 254                         st->mclk = AD7192_INT_FREQ_MHZ;
 255                 break;
 256         default:
 257                 ret = -EINVAL;
 258                 goto out;
 259         }
 260
 261         st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
 262                 AD7192_MODE_CLKSRC(pdata->clock_source_sel) |
 263                 AD7192_MODE_RATE(480);
 264
 265         st->conf = AD7192_CONF_GAIN(0);
 266
 267         if (pdata->rej60_en)
 268                 st->mode |= AD7192_MODE_REJ60;
 269
 270         if (pdata->sinc3_en)
 271                 st->mode |= AD7192_MODE_SINC3;
 272
 273         if (pdata->refin2_en && (st->devid != ID_AD7195))
 274                 st->conf |= AD7192_CONF_REFSEL;
 275
 276         if (pdata->chop_en) {
 277                 st->conf |= AD7192_CONF_CHOP;
 278                 if (pdata->sinc3_en)
 279                         st->f_order = 3; /* SINC 3rd order */
 280                 else
 281                         st->f_order = 4; /* SINC 4th order */
 282         } else {
 283                 st->f_order = 1;
 284         }
 285
 286         if (pdata->buf_en)
 287                 st->conf |= AD7192_CONF_BUF;
 288
 289         if (pdata->unipolar_en)
 290                 st->conf |= AD7192_CONF_UNIPOLAR;
 291
 292         if (pdata->burnout_curr_en)
 293                 st->conf |= AD7192_CONF_BURN;
 294
 295         ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
 296         if (ret)
 297                 goto out;
 298
 299         ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
 300         if (ret)
 301                 goto out;
 302
 303         ret = ad7192_calibrate_all(st);
 304         if (ret)
 305                 goto out;
 306
 307         /* Populate available ADC input ranges */
 308         for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
 309                 scale_uv = ((u64)st->int_vref_mv * 100000000)
 310                         >> (indio_dev->channels[0].scan_type.realbits -
 311                         ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
 312                 scale_uv >>= i;
 313
 314                 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
 315                 st->scale_avail[i][0] = scale_uv;
 316         }
 317
 318         return 0;
 319 out:
 320         dev_err(&st->sd.spi->dev, "setup failed\n");
 321         return ret;
 322 }
 323
 324 static ssize_t
 325 ad7192_show_scale_available(struct device *dev,
 326                             struct device_attribute *attr, char *buf)
 327 {
 328         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 329         struct ad7192_state *st = iio_priv(indio_dev);
 330         int i, len = 0;
 331
 332         for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
 333                 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
 334                                st->scale_avail[i][1]);
 335
 336         len += sprintf(buf + len, "\n");
 337
 338         return len;
 339 }
 340
 341 static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available,
 342                              in_voltage-voltage_scale_available,
 343                              0444, ad7192_show_scale_available, NULL, 0);
 344
 345 static IIO_DEVICE_ATTR(in_voltage_scale_available, 0444,
 346                        ad7192_show_scale_available, NULL, 0);
 347
 348 static ssize_t ad7192_show_ac_excitation(struct device *dev,
 349                                          struct device_attribute *attr,
 350                                          char *buf)
 351 {
 352         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 353         struct ad7192_state *st = iio_priv(indio_dev);
 354
 355         return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
 356 }
 357
 358 static ssize_t ad7192_show_bridge_switch(struct device *dev,
 359                                          struct device_attribute *attr,
 360                                          char *buf)
 361 {
 362         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 363         struct ad7192_state *st = iio_priv(indio_dev);
 364
 365         return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
 366 }
 367
 368 static ssize_t ad7192_set(struct device *dev,
 369                           struct device_attribute *attr,
 370                           const char *buf,
 371                           size_t len)
 372 {
 373         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 374         struct ad7192_state *st = iio_priv(indio_dev);
 375         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 376         int ret;
 377         bool val;
 378
 379         ret = strtobool(buf, &val);
 380         if (ret < 0)
 381                 return ret;
 382
 383         ret = iio_device_claim_direct_mode(indio_dev);
 384         if (ret)
 385                 return ret;
 386
 387         switch ((u32)this_attr->address) {
 388         case AD7192_REG_GPOCON:
 389                 if (val)
 390                         st->gpocon |= AD7192_GPOCON_BPDSW;
 391                 else
 392                         st->gpocon &= ~AD7192_GPOCON_BPDSW;
 393
 394                 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
 395                 break;
 396         case AD7192_REG_MODE:
 397                 if (val)
 398                         st->mode |= AD7192_MODE_ACX;
 399                 else
 400                         st->mode &= ~AD7192_MODE_ACX;
 401
 402                 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
 403                 break;
 404         default:
 405                 ret = -EINVAL;
 406         }
 407
 408         iio_device_release_direct_mode(indio_dev);
 409
 410         return ret ? ret : len;
 411 }
 412
 413 static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
 414                        ad7192_show_bridge_switch, ad7192_set,
 415                        AD7192_REG_GPOCON);
 416
 417 static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
 418                        ad7192_show_ac_excitation, ad7192_set,
 419                        AD7192_REG_MODE);
 420
 421 static struct attribute *ad7192_attributes[] = {
 422         &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
 423         &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
 424         &iio_dev_attr_bridge_switch_en.dev_attr.attr,
 425         &iio_dev_attr_ac_excitation_en.dev_attr.attr,
 426         NULL
 427 };
 428
 429 static const struct attribute_group ad7192_attribute_group = {
 430         .attrs = ad7192_attributes,
 431 };
 432
 433 static struct attribute *ad7195_attributes[] = {
 434         &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
 435         &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
 436         &iio_dev_attr_bridge_switch_en.dev_attr.attr,
 437         NULL
 438 };
 439
 440 static const struct attribute_group ad7195_attribute_group = {
 441         .attrs = ad7195_attributes,
 442 };
 443
 444 static unsigned int ad7192_get_temp_scale(bool unipolar)
 445 {
 446         return unipolar ? 2815 * 2 : 2815;
 447 }
 448
 449 static int ad7192_read_raw(struct iio_dev *indio_dev,
 450                            struct iio_chan_spec const *chan,
 451                            int *val,
 452                            int *val2,
 453                            long m)
 454 {
 455         struct ad7192_state *st = iio_priv(indio_dev);
 456         bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
 457
 458         switch (m) {
 459         case IIO_CHAN_INFO_RAW:
 460                 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
 461         case IIO_CHAN_INFO_SCALE:
 462                 switch (chan->type) {
 463                 case IIO_VOLTAGE:
 464                         mutex_lock(&indio_dev->mlock);
 465                         *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
 466                         *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
 467                         mutex_unlock(&indio_dev->mlock);
 468                         return IIO_VAL_INT_PLUS_NANO;
 469                 case IIO_TEMP:
 470                         *val = 0;
 471                         *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
 472                         return IIO_VAL_INT_PLUS_NANO;
 473                 default:
 474                         return -EINVAL;
 475                 }
 476         case IIO_CHAN_INFO_OFFSET:
 477                 if (!unipolar)
 478                         *val = -(1 << (chan->scan_type.realbits - 1));
 479                 else
 480                         *val = 0;
 481                 /* Kelvin to Celsius */
 482                 if (chan->type == IIO_TEMP)
 483                         *val -= 273 * ad7192_get_temp_scale(unipolar);
 484                 return IIO_VAL_INT;
 485         case IIO_CHAN_INFO_SAMP_FREQ:
 486                 *val = st->mclk /
 487                         (st->f_order * 1024 * AD7192_MODE_RATE(st->mode));
 488                 return IIO_VAL_INT;
 489         }
 490
 491         return -EINVAL;
 492 }
 493
 494 static int ad7192_write_raw(struct iio_dev *indio_dev,
 495                             struct iio_chan_spec const *chan,
 496                             int val,
 497                             int val2,
 498                             long mask)
 499 {
 500         struct ad7192_state *st = iio_priv(indio_dev);
 501         int ret, i, div;
 502         unsigned int tmp;
 503
 504         ret = iio_device_claim_direct_mode(indio_dev);
 505         if (ret)
 506                 return ret;
 507
 508         switch (mask) {
 509         case IIO_CHAN_INFO_SCALE:
 510                 ret = -EINVAL;
 511                 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
 512                         if (val2 == st->scale_avail[i][1]) {
 513                                 ret = 0;
 514                                 tmp = st->conf;
 515                                 st->conf &= ~AD7192_CONF_GAIN(-1);
 516                                 st->conf |= AD7192_CONF_GAIN(i);
 517                                 if (tmp == st->conf)
 518                                         break;
 519                                 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
 520                                                 3, st->conf);
 521                                 ad7192_calibrate_all(st);
 522                                 break;
 523                         }
 524                 break;
 525         case IIO_CHAN_INFO_SAMP_FREQ:
 526                 if (!val) {
 527                         ret = -EINVAL;
 528                         break;
 529                 }
 530
 531                 div = st->mclk / (val * st->f_order * 1024);
 532                 if (div < 1 || div > 1023) {
 533                         ret = -EINVAL;
 534                         break;
 535                 }
 536
 537                 st->mode &= ~AD7192_MODE_RATE(-1);
 538                 st->mode |= AD7192_MODE_RATE(div);
 539                 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
 540                 break;
 541         default:
 542                 ret = -EINVAL;
 543         }
 544
 545         iio_device_release_direct_mode(indio_dev);
 546
 547         return ret;
 548 }
 549
 550 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
 551                                     struct iio_chan_spec const *chan,
 552                                     long mask)
 553 {
 554         switch (mask) {
 555         case IIO_CHAN_INFO_SCALE:
 556                 return IIO_VAL_INT_PLUS_NANO;
 557         case IIO_CHAN_INFO_SAMP_FREQ:
 558                 return IIO_VAL_INT;
 559         default:
 560                 return -EINVAL;
 561         }
 562 }
 563
 564 static const struct iio_info ad7192_info = {
 565         .read_raw = ad7192_read_raw,
 566         .write_raw = ad7192_write_raw,
 567         .write_raw_get_fmt = ad7192_write_raw_get_fmt,
 568         .attrs = &ad7192_attribute_group,
 569         .validate_trigger = ad_sd_validate_trigger,
 570         .driver_module = THIS_MODULE,
 571 };
 572
 573 static const struct iio_info ad7195_info = {
 574         .read_raw = ad7192_read_raw,
 575         .write_raw = ad7192_write_raw,
 576         .write_raw_get_fmt = ad7192_write_raw_get_fmt,
 577         .attrs = &ad7195_attribute_group,
 578         .validate_trigger = ad_sd_validate_trigger,
 579         .driver_module = THIS_MODULE,
 580 };
 581
 582 static const struct iio_chan_spec ad7192_channels[] = {
 583         AD_SD_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M, 24, 32, 0),
 584         AD_SD_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M, 24, 32, 0),
 585         AD_SD_TEMP_CHANNEL(2, AD7192_CH_TEMP, 24, 32, 0),
 586         AD_SD_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M, 24, 32, 0),
 587         AD_SD_CHANNEL(4, 1, AD7192_CH_AIN1, 24, 32, 0),
 588         AD_SD_CHANNEL(5, 2, AD7192_CH_AIN2, 24, 32, 0),
 589         AD_SD_CHANNEL(6, 3, AD7192_CH_AIN3, 24, 32, 0),
 590         AD_SD_CHANNEL(7, 4, AD7192_CH_AIN4, 24, 32, 0),
 591         IIO_CHAN_SOFT_TIMESTAMP(8),
 592 };
 593
 594 static const struct iio_chan_spec ad7193_channels[] = {
 595         AD_SD_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M, 24, 32, 0),
 596         AD_SD_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M, 24, 32, 0),
 597         AD_SD_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M, 24, 32, 0),
 598         AD_SD_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M, 24, 32, 0),
 599         AD_SD_TEMP_CHANNEL(4, AD7193_CH_TEMP, 24, 32, 0),
 600         AD_SD_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M, 24, 32, 0),
 601         AD_SD_CHANNEL(6, 1, AD7193_CH_AIN1, 24, 32, 0),
 602         AD_SD_CHANNEL(7, 2, AD7193_CH_AIN2, 24, 32, 0),
 603         AD_SD_CHANNEL(8, 3, AD7193_CH_AIN3, 24, 32, 0),
 604         AD_SD_CHANNEL(9, 4, AD7193_CH_AIN4, 24, 32, 0),
 605         AD_SD_CHANNEL(10, 5, AD7193_CH_AIN5, 24, 32, 0),
 606         AD_SD_CHANNEL(11, 6, AD7193_CH_AIN6, 24, 32, 0),
 607         AD_SD_CHANNEL(12, 7, AD7193_CH_AIN7, 24, 32, 0),
 608         AD_SD_CHANNEL(13, 8, AD7193_CH_AIN8, 24, 32, 0),
 609         IIO_CHAN_SOFT_TIMESTAMP(14),
 610 };
 611
 612 static int ad7192_probe(struct spi_device *spi)
 613 {
 614         const struct ad7192_platform_data *pdata = dev_get_platdata(&spi->dev);
 615         struct ad7192_state *st;
 616         struct iio_dev *indio_dev;
 617         int ret, voltage_uv = 0;
 618
 619         if (!pdata) {
 620                 dev_err(&spi->dev, "no platform data?\n");
 621                 return -ENODEV;
 622         }
 623
 624         if (!spi->irq) {
 625                 dev_err(&spi->dev, "no IRQ?\n");
 626                 return -ENODEV;
 627         }
 628
 629         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 630         if (!indio_dev)
 631                 return -ENOMEM;
 632
 633         st = iio_priv(indio_dev);
 634
 635         st->avdd = devm_regulator_get(&spi->dev, "avdd");
 636         if (IS_ERR(st->avdd))
 637                 return PTR_ERR(st->avdd);
 638
 639         ret = regulator_enable(st->avdd);
 640         if (ret) {
 641                 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
 642                 return ret;
 643         }
 644
 645         st->dvdd = devm_regulator_get(&spi->dev, "dvdd");
 646         if (IS_ERR(st->dvdd)) {
 647                 ret = PTR_ERR(st->dvdd);
 648                 goto error_disable_avdd;
 649         }
 650
 651         ret = regulator_enable(st->dvdd);
 652         if (ret) {
 653                 dev_err(&spi->dev, "Failed to enable specified DVdd supply\n");
 654                 goto error_disable_avdd;
 655         }
 656
 657         voltage_uv = regulator_get_voltage(st->avdd);
 658
 659         if (pdata->vref_mv)
 660                 st->int_vref_mv = pdata->vref_mv;
 661         else if (voltage_uv)
 662                 st->int_vref_mv = voltage_uv / 1000;
 663         else
 664                 dev_warn(&spi->dev, "reference voltage undefined\n");
 665
 666         spi_set_drvdata(spi, indio_dev);
 667         st->devid = spi_get_device_id(spi)->driver_data;
 668         indio_dev->dev.parent = &spi->dev;
 669         indio_dev->name = spi_get_device_id(spi)->name;
 670         indio_dev->modes = INDIO_DIRECT_MODE;
 671
 672         switch (st->devid) {
 673         case ID_AD7193:
 674                 indio_dev->channels = ad7193_channels;
 675                 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
 676                 break;
 677         default:
 678                 indio_dev->channels = ad7192_channels;
 679                 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
 680                 break;
 681         }
 682
 683         if (st->devid == ID_AD7195)
 684                 indio_dev->info = &ad7195_info;
 685         else
 686                 indio_dev->info = &ad7192_info;
 687
 688         ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
 689
 690         ret = ad_sd_setup_buffer_and_trigger(indio_dev);
 691         if (ret)
 692                 goto error_disable_dvdd;
 693
 694         ret = ad7192_setup(st, pdata);
 695         if (ret)
 696                 goto error_remove_trigger;
 697
 698         ret = iio_device_register(indio_dev);
 699         if (ret < 0)
 700                 goto error_remove_trigger;
 701         return 0;
 702
 703 error_remove_trigger:
 704         ad_sd_cleanup_buffer_and_trigger(indio_dev);
 705 error_disable_dvdd:
 706         regulator_disable(st->dvdd);
 707 error_disable_avdd:
 708         regulator_disable(st->avdd);
 709
 710         return ret;
 711 }
 712
 713 static int ad7192_remove(struct spi_device *spi)
 714 {
 715         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 716         struct ad7192_state *st = iio_priv(indio_dev);
 717
 718         iio_device_unregister(indio_dev);
 719         ad_sd_cleanup_buffer_and_trigger(indio_dev);
 720
 721         regulator_disable(st->dvdd);
 722         regulator_disable(st->avdd);
 723
 724         return 0;
 725 }
 726
 727 static const struct spi_device_id ad7192_id[] = {
 728         {"ad7190", ID_AD7190},
 729         {"ad7192", ID_AD7192},
 730         {"ad7193", ID_AD7193},
 731         {"ad7195", ID_AD7195},
 732         {}
 733 };
 734 MODULE_DEVICE_TABLE(spi, ad7192_id);
 735
 736 static struct spi_driver ad7192_driver = {
 737         .driver = {
 738                 .name   = "ad7192",
 739         },
 740         .probe          = ad7192_probe,
 741         .remove         = ad7192_remove,
 742         .id_table       = ad7192_id,
 743 };
 744 module_spi_driver(ad7192_driver);
 745
 746 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
 747 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
 748 MODULE_LICENSE("GPL v2");