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staging:iio: prevent removal of module connected to trigger.
[mirror_ubuntu-bionic-kernel.git] / drivers / staging / iio / adc / ad7192.c
1 /*
2 * AD7190 AD7192 AD7195 SPI ADC driver
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
19
20 #include "../iio.h"
21 #include "../sysfs.h"
22 #include "../ring_generic.h"
23 #include "../ring_sw.h"
24 #include "../trigger.h"
25
26 #include "ad7192.h"
27
28 /* Registers */
29 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
30 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
31 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
32 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
33 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
34 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
35 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
36 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit
37 * (AD7792)/24-bit (AD7192)) */
38 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register
39 * (RW, 16-bit (AD7792)/24-bit (AD7192)) */
40
41 /* Communications Register Bit Designations (AD7192_REG_COMM) */
42 #define AD7192_COMM_WEN (1 << 7) /* Write Enable */
43 #define AD7192_COMM_WRITE (0 << 6) /* Write Operation */
44 #define AD7192_COMM_READ (1 << 6) /* Read Operation */
45 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
46 #define AD7192_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */
47
48 /* Status Register Bit Designations (AD7192_REG_STAT) */
49 #define AD7192_STAT_RDY (1 << 7) /* Ready */
50 #define AD7192_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */
51 #define AD7192_STAT_NOREF (1 << 5) /* Error no external reference */
52 #define AD7192_STAT_PARITY (1 << 4) /* Parity */
53 #define AD7192_STAT_CH3 (1 << 2) /* Channel 3 */
54 #define AD7192_STAT_CH2 (1 << 1) /* Channel 2 */
55 #define AD7192_STAT_CH1 (1 << 0) /* Channel 1 */
56
57 /* Mode Register Bit Designations (AD7192_REG_MODE) */
58 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
59 #define AD7192_MODE_DAT_STA (1 << 20) /* Status Register transmission */
60 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
61 #define AD7192_MODE_SINC3 (1 << 15) /* SINC3 Filter Select */
62 #define AD7192_MODE_ACX (1 << 14) /* AC excitation enable(AD7195 only)*/
63 #define AD7192_MODE_ENPAR (1 << 13) /* Parity Enable */
64 #define AD7192_MODE_CLKDIV (1 << 12) /* Clock divide by 2 (AD7190/2 only)*/
65 #define AD7192_MODE_SCYCLE (1 << 11) /* Single cycle conversion */
66 #define AD7192_MODE_REJ60 (1 << 10) /* 50/60Hz notch filter */
67 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
68
69 /* Mode Register: AD7192_MODE_SEL options */
70 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
71 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
72 #define AD7192_MODE_IDLE 2 /* Idle Mode */
73 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
74 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
75 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
76 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
77 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
78
79 /* Mode Register: AD7192_MODE_CLKSRC options */
80 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected
81 * from MCLK1 to MCLK2 */
82 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
83 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not
84 * available at the MCLK2 pin */
85 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available
86 * at the MCLK2 pin */
87
88
89 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
90
91 #define AD7192_CONF_CHOP (1 << 23) /* CHOP enable */
92 #define AD7192_CONF_REFSEL (1 << 20) /* REFIN1/REFIN2 Reference Select */
93 #define AD7192_CONF_CHAN(x) (((x) & 0xFF) << 8) /* Channel select */
94 #define AD7192_CONF_BURN (1 << 7) /* Burnout current enable */
95 #define AD7192_CONF_REFDET (1 << 6) /* Reference detect enable */
96 #define AD7192_CONF_BUF (1 << 4) /* Buffered Mode Enable */
97 #define AD7192_CONF_UNIPOLAR (1 << 3) /* Unipolar/Bipolar Enable */
98 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
99
100 #define AD7192_CH_AIN1P_AIN2M 0 /* AIN1(+) - AIN2(-) */
101 #define AD7192_CH_AIN3P_AIN4M 1 /* AIN3(+) - AIN4(-) */
102 #define AD7192_CH_TEMP 2 /* Temp Sensor */
103 #define AD7192_CH_AIN2P_AIN2M 3 /* AIN2(+) - AIN2(-) */
104 #define AD7192_CH_AIN1 4 /* AIN1 - AINCOM */
105 #define AD7192_CH_AIN2 5 /* AIN2 - AINCOM */
106 #define AD7192_CH_AIN3 6 /* AIN3 - AINCOM */
107 #define AD7192_CH_AIN4 7 /* AIN4 - AINCOM */
108
109 /* ID Register Bit Designations (AD7192_REG_ID) */
110 #define ID_AD7190 0x4
111 #define ID_AD7192 0x0
112 #define ID_AD7195 0x6
113 #define AD7192_ID_MASK 0x0F
114
115 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
116 #define AD7192_GPOCON_BPDSW (1 << 6) /* Bridge power-down switch enable */
117 #define AD7192_GPOCON_GP32EN (1 << 5) /* Digital Output P3 and P2 enable */
118 #define AD7192_GPOCON_GP10EN (1 << 4) /* Digital Output P1 and P0 enable */
119 #define AD7192_GPOCON_P3DAT (1 << 3) /* P3 state */
120 #define AD7192_GPOCON_P2DAT (1 << 2) /* P2 state */
121 #define AD7192_GPOCON_P1DAT (1 << 1) /* P1 state */
122 #define AD7192_GPOCON_P0DAT (1 << 0) /* P0 state */
123
124 #define AD7192_INT_FREQ_MHz 4915200
125
126 /* NOTE:
127 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
128 * In order to avoid contentions on the SPI bus, it's therefore necessary
129 * to use spi bus locking.
130 *
131 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
132 */
133
134 struct ad7192_state {
135 struct spi_device *spi;
136 struct iio_trigger *trig;
137 struct regulator *reg;
138 struct ad7192_platform_data *pdata;
139 wait_queue_head_t wq_data_avail;
140 bool done;
141 bool irq_dis;
142 u16 int_vref_mv;
143 u32 mclk;
144 u32 f_order;
145 u32 mode;
146 u32 conf;
147 u32 scale_avail[8][2];
148 u32 available_scan_masks[9];
149 u8 gpocon;
150 u8 devid;
151 /*
152 * DMA (thus cache coherency maintenance) requires the
153 * transfer buffers to live in their own cache lines.
154 */
155 u8 data[4] ____cacheline_aligned;
156 };
157
158 static int __ad7192_write_reg(struct ad7192_state *st, bool locked,
159 bool cs_change, unsigned char reg,
160 unsigned size, unsigned val)
161 {
162 u8 *data = st->data;
163 struct spi_transfer t = {
164 .tx_buf = data,
165 .len = size + 1,
166 .cs_change = cs_change,
167 };
168 struct spi_message m;
169
170 data[0] = AD7192_COMM_WRITE | AD7192_COMM_ADDR(reg);
171
172 switch (size) {
173 case 3:
174 data[1] = val >> 16;
175 data[2] = val >> 8;
176 data[3] = val;
177 break;
178 case 2:
179 data[1] = val >> 8;
180 data[2] = val;
181 break;
182 case 1:
183 data[1] = val;
184 break;
185 default:
186 return -EINVAL;
187 }
188
189 spi_message_init(&m);
190 spi_message_add_tail(&t, &m);
191
192 if (locked)
193 return spi_sync_locked(st->spi, &m);
194 else
195 return spi_sync(st->spi, &m);
196 }
197
198 static int ad7192_write_reg(struct ad7192_state *st,
199 unsigned reg, unsigned size, unsigned val)
200 {
201 return __ad7192_write_reg(st, false, false, reg, size, val);
202 }
203
204 static int __ad7192_read_reg(struct ad7192_state *st, bool locked,
205 bool cs_change, unsigned char reg,
206 int *val, unsigned size)
207 {
208 u8 *data = st->data;
209 int ret;
210 struct spi_transfer t[] = {
211 {
212 .tx_buf = data,
213 .len = 1,
214 }, {
215 .rx_buf = data,
216 .len = size,
217 .cs_change = cs_change,
218 },
219 };
220 struct spi_message m;
221
222 data[0] = AD7192_COMM_READ | AD7192_COMM_ADDR(reg);
223
224 spi_message_init(&m);
225 spi_message_add_tail(&t[0], &m);
226 spi_message_add_tail(&t[1], &m);
227
228 if (locked)
229 ret = spi_sync_locked(st->spi, &m);
230 else
231 ret = spi_sync(st->spi, &m);
232
233 if (ret < 0)
234 return ret;
235
236 switch (size) {
237 case 3:
238 *val = data[0] << 16 | data[1] << 8 | data[2];
239 break;
240 case 2:
241 *val = data[0] << 8 | data[1];
242 break;
243 case 1:
244 *val = data[0];
245 break;
246 default:
247 return -EINVAL;
248 }
249
250 return 0;
251 }
252
253 static int ad7192_read_reg(struct ad7192_state *st,
254 unsigned reg, int *val, unsigned size)
255 {
256 return __ad7192_read_reg(st, 0, 0, reg, val, size);
257 }
258
259 static int ad7192_read(struct ad7192_state *st, unsigned ch,
260 unsigned len, int *val)
261 {
262 int ret;
263 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
264 AD7192_CONF_CHAN(1 << ch);
265 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
266 AD7192_MODE_SEL(AD7192_MODE_SINGLE);
267
268 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
269
270 spi_bus_lock(st->spi->master);
271 st->done = false;
272
273 ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode);
274 if (ret < 0)
275 goto out;
276
277 st->irq_dis = false;
278 enable_irq(st->spi->irq);
279 wait_event_interruptible(st->wq_data_avail, st->done);
280
281 ret = __ad7192_read_reg(st, 1, 0, AD7192_REG_DATA, val, len);
282 out:
283 spi_bus_unlock(st->spi->master);
284
285 return ret;
286 }
287
288 static int ad7192_calibrate(struct ad7192_state *st, unsigned mode, unsigned ch)
289 {
290 int ret;
291
292 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
293 AD7192_CONF_CHAN(1 << ch);
294 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | AD7192_MODE_SEL(mode);
295
296 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
297
298 spi_bus_lock(st->spi->master);
299 st->done = false;
300
301 ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3,
302 (st->devid != ID_AD7195) ?
303 st->mode | AD7192_MODE_CLKDIV :
304 st->mode);
305 if (ret < 0)
306 goto out;
307
308 st->irq_dis = false;
309 enable_irq(st->spi->irq);
310 wait_event_interruptible(st->wq_data_avail, st->done);
311
312 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
313 AD7192_MODE_SEL(AD7192_MODE_IDLE);
314
315 ret = __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode);
316 out:
317 spi_bus_unlock(st->spi->master);
318
319 return ret;
320 }
321
322 static const u8 ad7192_calib_arr[8][2] = {
323 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
324 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
325 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
326 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
327 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
328 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
329 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
330 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
331 };
332
333 static int ad7192_calibrate_all(struct ad7192_state *st)
334 {
335 int i, ret;
336
337 for (i = 0; i < ARRAY_SIZE(ad7192_calib_arr); i++) {
338 ret = ad7192_calibrate(st, ad7192_calib_arr[i][0],
339 ad7192_calib_arr[i][1]);
340 if (ret)
341 goto out;
342 }
343
344 return 0;
345 out:
346 dev_err(&st->spi->dev, "Calibration failed\n");
347 return ret;
348 }
349
350 static int ad7192_setup(struct ad7192_state *st)
351 {
352 struct iio_dev *indio_dev = spi_get_drvdata(st->spi);
353 struct ad7192_platform_data *pdata = st->pdata;
354 unsigned long long scale_uv;
355 int i, ret, id;
356 u8 ones[6];
357
358 /* reset the serial interface */
359 memset(&ones, 0xFF, 6);
360 ret = spi_write(st->spi, &ones, 6);
361 if (ret < 0)
362 goto out;
363 msleep(1); /* Wait for at least 500us */
364
365 /* write/read test for device presence */
366 ret = ad7192_read_reg(st, AD7192_REG_ID, &id, 1);
367 if (ret)
368 goto out;
369
370 id &= AD7192_ID_MASK;
371
372 if (id != st->devid)
373 dev_warn(&st->spi->dev, "device ID query failed (0x%X)\n", id);
374
375 switch (pdata->clock_source_sel) {
376 case AD7192_CLK_EXT_MCLK1_2:
377 case AD7192_CLK_EXT_MCLK2:
378 st->mclk = AD7192_INT_FREQ_MHz;
379 break;
380 case AD7192_CLK_INT:
381 case AD7192_CLK_INT_CO:
382 if (pdata->ext_clk_Hz)
383 st->mclk = pdata->ext_clk_Hz;
384 else
385 st->mclk = AD7192_INT_FREQ_MHz;
386 break;
387 default:
388 ret = -EINVAL;
389 goto out;
390 }
391
392 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
393 AD7192_MODE_CLKSRC(pdata->clock_source_sel) |
394 AD7192_MODE_RATE(480);
395
396 st->conf = AD7192_CONF_GAIN(0);
397
398 if (pdata->rej60_en)
399 st->mode |= AD7192_MODE_REJ60;
400
401 if (pdata->sinc3_en)
402 st->mode |= AD7192_MODE_SINC3;
403
404 if (pdata->refin2_en && (st->devid != ID_AD7195))
405 st->conf |= AD7192_CONF_REFSEL;
406
407 if (pdata->chop_en) {
408 st->conf |= AD7192_CONF_CHOP;
409 if (pdata->sinc3_en)
410 st->f_order = 3; /* SINC 3rd order */
411 else
412 st->f_order = 4; /* SINC 4th order */
413 } else {
414 st->f_order = 1;
415 }
416
417 if (pdata->buf_en)
418 st->conf |= AD7192_CONF_BUF;
419
420 if (pdata->unipolar_en)
421 st->conf |= AD7192_CONF_UNIPOLAR;
422
423 if (pdata->burnout_curr_en)
424 st->conf |= AD7192_CONF_BURN;
425
426 ret = ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode);
427 if (ret)
428 goto out;
429
430 ret = ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
431 if (ret)
432 goto out;
433
434 ret = ad7192_calibrate_all(st);
435 if (ret)
436 goto out;
437
438 /* Populate available ADC input ranges */
439 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
440 scale_uv = ((u64)st->int_vref_mv * 100000000)
441 >> (indio_dev->channels[0].scan_type.realbits -
442 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
443 scale_uv >>= i;
444
445 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
446 st->scale_avail[i][0] = scale_uv;
447 }
448
449 return 0;
450 out:
451 dev_err(&st->spi->dev, "setup failed\n");
452 return ret;
453 }
454
455 static int ad7192_scan_from_ring(struct ad7192_state *st, unsigned ch, int *val)
456 {
457 struct iio_ring_buffer *ring = iio_priv_to_dev(st)->ring;
458 int ret;
459 s64 dat64[2];
460 u32 *dat32 = (u32 *)dat64;
461
462 if (!(ring->scan_mask & (1 << ch)))
463 return -EBUSY;
464
465 ret = ring->access->read_last(ring, (u8 *) &dat64);
466 if (ret)
467 return ret;
468
469 *val = *dat32;
470
471 return 0;
472 }
473
474 static int ad7192_ring_preenable(struct iio_dev *indio_dev)
475 {
476 struct ad7192_state *st = iio_priv(indio_dev);
477 struct iio_ring_buffer *ring = indio_dev->ring;
478 size_t d_size;
479 unsigned channel;
480
481 if (!ring->scan_count)
482 return -EINVAL;
483
484 channel = __ffs(ring->scan_mask);
485
486 d_size = ring->scan_count *
487 indio_dev->channels[0].scan_type.storagebits / 8;
488
489 if (ring->scan_timestamp) {
490 d_size += sizeof(s64);
491
492 if (d_size % sizeof(s64))
493 d_size += sizeof(s64) - (d_size % sizeof(s64));
494 }
495
496 if (indio_dev->ring->access->set_bytes_per_datum)
497 indio_dev->ring->access->set_bytes_per_datum(indio_dev->ring,
498 d_size);
499
500 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
501 AD7192_MODE_SEL(AD7192_MODE_CONT);
502 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
503 AD7192_CONF_CHAN(1 << indio_dev->channels[channel].address);
504
505 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
506
507 spi_bus_lock(st->spi->master);
508 __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode);
509
510 st->irq_dis = false;
511 enable_irq(st->spi->irq);
512
513 return 0;
514 }
515
516 static int ad7192_ring_postdisable(struct iio_dev *indio_dev)
517 {
518 struct ad7192_state *st = iio_priv(indio_dev);
519
520 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
521 AD7192_MODE_SEL(AD7192_MODE_IDLE);
522
523 st->done = false;
524 wait_event_interruptible(st->wq_data_avail, st->done);
525
526 if (!st->irq_dis)
527 disable_irq_nosync(st->spi->irq);
528
529 __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode);
530
531 return spi_bus_unlock(st->spi->master);
532 }
533
534 /**
535 * ad7192_trigger_handler() bh of trigger launched polling to ring buffer
536 **/
537 static irqreturn_t ad7192_trigger_handler(int irq, void *p)
538 {
539 struct iio_poll_func *pf = p;
540 struct iio_dev *indio_dev = pf->indio_dev;
541 struct iio_ring_buffer *ring = indio_dev->ring;
542 struct ad7192_state *st = iio_priv(indio_dev);
543 s64 dat64[2];
544 s32 *dat32 = (s32 *)dat64;
545
546 if (ring->scan_count)
547 __ad7192_read_reg(st, 1, 1, AD7192_REG_DATA,
548 dat32,
549 indio_dev->channels[0].scan_type.realbits/8);
550
551 /* Guaranteed to be aligned with 8 byte boundary */
552 if (ring->scan_timestamp)
553 dat64[1] = pf->timestamp;
554
555 ring->access->store_to(ring, (u8 *)dat64, pf->timestamp);
556
557 iio_trigger_notify_done(indio_dev->trig);
558 st->irq_dis = false;
559 enable_irq(st->spi->irq);
560
561 return IRQ_HANDLED;
562 }
563
564 static const struct iio_ring_setup_ops ad7192_ring_setup_ops = {
565 .preenable = &ad7192_ring_preenable,
566 .postenable = &iio_triggered_ring_postenable,
567 .predisable = &iio_triggered_ring_predisable,
568 .postdisable = &ad7192_ring_postdisable,
569 };
570
571 static int ad7192_register_ring_funcs_and_init(struct iio_dev *indio_dev)
572 {
573 int ret;
574
575 indio_dev->ring = iio_sw_rb_allocate(indio_dev);
576 if (!indio_dev->ring) {
577 ret = -ENOMEM;
578 goto error_ret;
579 }
580 /* Effectively select the ring buffer implementation */
581 indio_dev->ring->access = &ring_sw_access_funcs;
582 indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
583 &ad7192_trigger_handler,
584 IRQF_ONESHOT,
585 indio_dev,
586 "ad7192_consumer%d",
587 indio_dev->id);
588 if (indio_dev->pollfunc == NULL) {
589 ret = -ENOMEM;
590 goto error_deallocate_sw_rb;
591 }
592
593 /* Ring buffer functions - here trigger setup related */
594 indio_dev->ring->setup_ops = &ad7192_ring_setup_ops;
595
596 /* Flag that polled ring buffering is possible */
597 indio_dev->modes |= INDIO_RING_TRIGGERED;
598 return 0;
599
600 error_deallocate_sw_rb:
601 iio_sw_rb_free(indio_dev->ring);
602 error_ret:
603 return ret;
604 }
605
606 static void ad7192_ring_cleanup(struct iio_dev *indio_dev)
607 {
608 iio_dealloc_pollfunc(indio_dev->pollfunc);
609 iio_sw_rb_free(indio_dev->ring);
610 }
611
612 /**
613 * ad7192_data_rdy_trig_poll() the event handler for the data rdy trig
614 **/
615 static irqreturn_t ad7192_data_rdy_trig_poll(int irq, void *private)
616 {
617 struct ad7192_state *st = iio_priv(private);
618
619 st->done = true;
620 wake_up_interruptible(&st->wq_data_avail);
621 disable_irq_nosync(irq);
622 st->irq_dis = true;
623 iio_trigger_poll(st->trig, iio_get_time_ns());
624
625 return IRQ_HANDLED;
626 }
627
628 static int ad7192_probe_trigger(struct iio_dev *indio_dev)
629 {
630 struct ad7192_state *st = iio_priv(indio_dev);
631 int ret;
632
633 st->trig = iio_allocate_trigger("%s-dev%d",
634 spi_get_device_id(st->spi)->name,
635 indio_dev->id);
636 if (st->trig == NULL) {
637 ret = -ENOMEM;
638 goto error_ret;
639 }
640
641 ret = request_irq(st->spi->irq,
642 ad7192_data_rdy_trig_poll,
643 IRQF_TRIGGER_LOW,
644 spi_get_device_id(st->spi)->name,
645 indio_dev);
646 if (ret)
647 goto error_free_trig;
648
649 disable_irq_nosync(st->spi->irq);
650 st->irq_dis = true;
651 st->trig->dev.parent = &st->spi->dev;
652 st->trig->owner = THIS_MODULE;
653 st->trig->private_data = indio_dev;
654
655 ret = iio_trigger_register(st->trig);
656
657 /* select default trigger */
658 indio_dev->trig = st->trig;
659 if (ret)
660 goto error_free_irq;
661
662 return 0;
663
664 error_free_irq:
665 free_irq(st->spi->irq, indio_dev);
666 error_free_trig:
667 iio_free_trigger(st->trig);
668 error_ret:
669 return ret;
670 }
671
672 static void ad7192_remove_trigger(struct iio_dev *indio_dev)
673 {
674 struct ad7192_state *st = iio_priv(indio_dev);
675
676 iio_trigger_unregister(st->trig);
677 free_irq(st->spi->irq, indio_dev);
678 iio_free_trigger(st->trig);
679 }
680
681 static ssize_t ad7192_read_frequency(struct device *dev,
682 struct device_attribute *attr,
683 char *buf)
684 {
685 struct iio_dev *indio_dev = dev_get_drvdata(dev);
686 struct ad7192_state *st = iio_priv(indio_dev);
687
688 return sprintf(buf, "%d\n", st->mclk /
689 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)));
690 }
691
692 static ssize_t ad7192_write_frequency(struct device *dev,
693 struct device_attribute *attr,
694 const char *buf,
695 size_t len)
696 {
697 struct iio_dev *indio_dev = dev_get_drvdata(dev);
698 struct ad7192_state *st = iio_priv(indio_dev);
699 unsigned long lval;
700 int div, ret;
701
702 ret = strict_strtoul(buf, 10, &lval);
703 if (ret)
704 return ret;
705
706 mutex_lock(&indio_dev->mlock);
707 if (iio_ring_enabled(indio_dev)) {
708 mutex_unlock(&indio_dev->mlock);
709 return -EBUSY;
710 }
711
712 div = st->mclk / (lval * st->f_order * 1024);
713 if (div < 1 || div > 1023) {
714 ret = -EINVAL;
715 goto out;
716 }
717
718 st->mode &= ~AD7192_MODE_RATE(-1);
719 st->mode |= AD7192_MODE_RATE(div);
720 ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode);
721
722 out:
723 mutex_unlock(&indio_dev->mlock);
724
725 return ret ? ret : len;
726 }
727
728 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
729 ad7192_read_frequency,
730 ad7192_write_frequency);
731
732
733 static ssize_t ad7192_show_scale_available(struct device *dev,
734 struct device_attribute *attr, char *buf)
735 {
736 struct iio_dev *indio_dev = dev_get_drvdata(dev);
737 struct ad7192_state *st = iio_priv(indio_dev);
738 int i, len = 0;
739
740 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
741 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
742 st->scale_avail[i][1]);
743
744 len += sprintf(buf + len, "\n");
745
746 return len;
747 }
748
749 static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available, in-in_scale_available,
750 S_IRUGO, ad7192_show_scale_available, NULL, 0);
751
752 static IIO_DEVICE_ATTR(in_scale_available, S_IRUGO,
753 ad7192_show_scale_available, NULL, 0);
754
755 static ssize_t ad7192_show_ac_excitation(struct device *dev,
756 struct device_attribute *attr,
757 char *buf)
758 {
759 struct iio_dev *indio_dev = dev_get_drvdata(dev);
760 struct ad7192_state *st = iio_priv(indio_dev);
761
762 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
763 }
764
765 static ssize_t ad7192_show_bridge_switch(struct device *dev,
766 struct device_attribute *attr,
767 char *buf)
768 {
769 struct iio_dev *indio_dev = dev_get_drvdata(dev);
770 struct ad7192_state *st = iio_priv(indio_dev);
771
772 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
773 }
774
775 static ssize_t ad7192_set(struct device *dev,
776 struct device_attribute *attr,
777 const char *buf,
778 size_t len)
779 {
780 struct iio_dev *indio_dev = dev_get_drvdata(dev);
781 struct ad7192_state *st = iio_priv(indio_dev);
782 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
783 int ret;
784 bool val;
785
786 ret = strtobool(buf, &val);
787 if (ret < 0)
788 return ret;
789
790 mutex_lock(&indio_dev->mlock);
791 if (iio_ring_enabled(indio_dev)) {
792 mutex_unlock(&indio_dev->mlock);
793 return -EBUSY;
794 }
795
796 switch (this_attr->address) {
797 case AD7192_REG_GPOCON:
798 if (val)
799 st->gpocon |= AD7192_GPOCON_BPDSW;
800 else
801 st->gpocon &= ~AD7192_GPOCON_BPDSW;
802
803 ad7192_write_reg(st, AD7192_REG_GPOCON, 1, st->gpocon);
804 break;
805 case AD7192_REG_MODE:
806 if (val)
807 st->mode |= AD7192_MODE_ACX;
808 else
809 st->mode &= ~AD7192_MODE_ACX;
810
811 ad7192_write_reg(st, AD7192_REG_GPOCON, 3, st->mode);
812 break;
813 default:
814 ret = -EINVAL;
815 }
816
817 mutex_unlock(&indio_dev->mlock);
818
819 return ret ? ret : len;
820 }
821
822 static IIO_DEVICE_ATTR(bridge_switch_en, S_IRUGO | S_IWUSR,
823 ad7192_show_bridge_switch, ad7192_set,
824 AD7192_REG_GPOCON);
825
826 static IIO_DEVICE_ATTR(ac_excitation_en, S_IRUGO | S_IWUSR,
827 ad7192_show_ac_excitation, ad7192_set,
828 AD7192_REG_MODE);
829
830 static struct attribute *ad7192_attributes[] = {
831 &iio_dev_attr_sampling_frequency.dev_attr.attr,
832 &iio_dev_attr_in_m_in_scale_available.dev_attr.attr,
833 &iio_dev_attr_in_scale_available.dev_attr.attr,
834 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
835 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
836 NULL
837 };
838
839 static mode_t ad7192_attr_is_visible(struct kobject *kobj,
840 struct attribute *attr, int n)
841 {
842 struct device *dev = container_of(kobj, struct device, kobj);
843 struct iio_dev *dev_info = dev_get_drvdata(dev);
844 struct ad7192_state *st = iio_priv(dev_info);
845
846 mode_t mode = attr->mode;
847
848 if ((st->devid != ID_AD7195) &&
849 (attr == &iio_dev_attr_ac_excitation_en.dev_attr.attr))
850 mode = 0;
851
852 return mode;
853 }
854
855 static const struct attribute_group ad7192_attribute_group = {
856 .attrs = ad7192_attributes,
857 .is_visible = ad7192_attr_is_visible,
858 };
859
860 static int ad7192_read_raw(struct iio_dev *indio_dev,
861 struct iio_chan_spec const *chan,
862 int *val,
863 int *val2,
864 long m)
865 {
866 struct ad7192_state *st = iio_priv(indio_dev);
867 int ret, smpl = 0;
868 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
869
870 switch (m) {
871 case 0:
872 mutex_lock(&indio_dev->mlock);
873 if (iio_ring_enabled(indio_dev))
874 ret = ad7192_scan_from_ring(st,
875 chan->scan_index, &smpl);
876 else
877 ret = ad7192_read(st, chan->address,
878 chan->scan_type.realbits / 8, &smpl);
879 mutex_unlock(&indio_dev->mlock);
880
881 if (ret < 0)
882 return ret;
883
884 *val = (smpl >> chan->scan_type.shift) &
885 ((1 << (chan->scan_type.realbits)) - 1);
886
887 switch (chan->type) {
888 case IIO_IN:
889 case IIO_IN_DIFF:
890 if (!unipolar)
891 *val -= (1 << (chan->scan_type.realbits - 1));
892 break;
893 case IIO_TEMP:
894 *val -= 0x800000;
895 *val /= 2815; /* temp Kelvin */
896 *val -= 273; /* temp Celsius */
897 break;
898 default:
899 return -EINVAL;
900 }
901 return IIO_VAL_INT;
902
903 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
904 mutex_lock(&indio_dev->mlock);
905 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
906 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
907 mutex_unlock(&indio_dev->mlock);
908
909 return IIO_VAL_INT_PLUS_NANO;
910
911 case (1 << IIO_CHAN_INFO_SCALE_SEPARATE):
912 *val = 1000;
913
914 return IIO_VAL_INT;
915 }
916
917 return -EINVAL;
918 }
919
920 static int ad7192_write_raw(struct iio_dev *indio_dev,
921 struct iio_chan_spec const *chan,
922 int val,
923 int val2,
924 long mask)
925 {
926 struct ad7192_state *st = iio_priv(indio_dev);
927 int ret, i;
928 unsigned int tmp;
929
930 mutex_lock(&indio_dev->mlock);
931 if (iio_ring_enabled(indio_dev)) {
932 mutex_unlock(&indio_dev->mlock);
933 return -EBUSY;
934 }
935
936 switch (mask) {
937 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
938 ret = -EINVAL;
939 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
940 if (val2 == st->scale_avail[i][1]) {
941 tmp = st->conf;
942 st->conf &= ~AD7192_CONF_GAIN(-1);
943 st->conf |= AD7192_CONF_GAIN(i);
944
945 if (tmp != st->conf) {
946 ad7192_write_reg(st, AD7192_REG_CONF,
947 3, st->conf);
948 ad7192_calibrate_all(st);
949 }
950 ret = 0;
951 }
952
953 default:
954 ret = -EINVAL;
955 }
956
957 mutex_unlock(&indio_dev->mlock);
958
959 return ret;
960 }
961
962 static int ad7192_validate_trigger(struct iio_dev *indio_dev,
963 struct iio_trigger *trig)
964 {
965 if (indio_dev->trig != trig)
966 return -EINVAL;
967
968 return 0;
969 }
970
971 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
972 struct iio_chan_spec const *chan,
973 long mask)
974 {
975 return IIO_VAL_INT_PLUS_NANO;
976 }
977
978 static const struct iio_info ad7192_info = {
979 .read_raw = &ad7192_read_raw,
980 .write_raw = &ad7192_write_raw,
981 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
982 .attrs = &ad7192_attribute_group,
983 .validate_trigger = ad7192_validate_trigger,
984 .driver_module = THIS_MODULE,
985 };
986
987 #define AD7192_CHAN_DIFF(_chan, _chan2, _name, _address, _si) \
988 { .type = IIO_IN_DIFF, \
989 .indexed = 1, \
990 .extend_name = _name, \
991 .channel = _chan, \
992 .channel2 = _chan2, \
993 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED), \
994 .address = _address, \
995 .scan_index = _si, \
996 .scan_type = IIO_ST('s', 24, 32, 0)}
997
998 #define AD7192_CHAN(_chan, _address, _si) \
999 { .type = IIO_IN, \
1000 .indexed = 1, \
1001 .channel = _chan, \
1002 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED), \
1003 .address = _address, \
1004 .scan_index = _si, \
1005 .scan_type = IIO_ST('s', 24, 32, 0)}
1006
1007 #define AD7192_CHAN_TEMP(_chan, _address, _si) \
1008 { .type = IIO_TEMP, \
1009 .indexed = 1, \
1010 .channel = _chan, \
1011 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SEPARATE), \
1012 .address = _address, \
1013 .scan_index = _si, \
1014 .scan_type = IIO_ST('s', 24, 32, 0)}
1015
1016 static struct iio_chan_spec ad7192_channels[] = {
1017 AD7192_CHAN_DIFF(1, 2, NULL, AD7192_CH_AIN1P_AIN2M, 0),
1018 AD7192_CHAN_DIFF(3, 4, NULL, AD7192_CH_AIN3P_AIN4M, 1),
1019 AD7192_CHAN_TEMP(0, AD7192_CH_TEMP, 2),
1020 AD7192_CHAN_DIFF(2, 2, "shorted", AD7192_CH_AIN2P_AIN2M, 3),
1021 AD7192_CHAN(1, AD7192_CH_AIN1, 4),
1022 AD7192_CHAN(2, AD7192_CH_AIN2, 5),
1023 AD7192_CHAN(3, AD7192_CH_AIN3, 6),
1024 AD7192_CHAN(4, AD7192_CH_AIN4, 7),
1025 IIO_CHAN_SOFT_TIMESTAMP(8),
1026 };
1027
1028 static int __devinit ad7192_probe(struct spi_device *spi)
1029 {
1030 struct ad7192_platform_data *pdata = spi->dev.platform_data;
1031 struct ad7192_state *st;
1032 struct iio_dev *indio_dev;
1033 int ret, i , voltage_uv = 0, regdone = 0;
1034
1035 if (!pdata) {
1036 dev_err(&spi->dev, "no platform data?\n");
1037 return -ENODEV;
1038 }
1039
1040 if (!spi->irq) {
1041 dev_err(&spi->dev, "no IRQ?\n");
1042 return -ENODEV;
1043 }
1044
1045 indio_dev = iio_allocate_device(sizeof(*st));
1046 if (indio_dev == NULL)
1047 return -ENOMEM;
1048
1049 st = iio_priv(indio_dev);
1050
1051 st->reg = regulator_get(&spi->dev, "vcc");
1052 if (!IS_ERR(st->reg)) {
1053 ret = regulator_enable(st->reg);
1054 if (ret)
1055 goto error_put_reg;
1056
1057 voltage_uv = regulator_get_voltage(st->reg);
1058 }
1059
1060 st->pdata = pdata;
1061
1062 if (pdata && pdata->vref_mv)
1063 st->int_vref_mv = pdata->vref_mv;
1064 else if (voltage_uv)
1065 st->int_vref_mv = voltage_uv / 1000;
1066 else
1067 dev_warn(&spi->dev, "reference voltage undefined\n");
1068
1069 spi_set_drvdata(spi, indio_dev);
1070 st->spi = spi;
1071 st->devid = spi_get_device_id(spi)->driver_data;
1072 indio_dev->dev.parent = &spi->dev;
1073 indio_dev->name = spi_get_device_id(spi)->name;
1074 indio_dev->modes = INDIO_DIRECT_MODE;
1075 indio_dev->channels = ad7192_channels;
1076 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
1077 indio_dev->available_scan_masks = st->available_scan_masks;
1078 indio_dev->info = &ad7192_info;
1079
1080 for (i = 0; i < indio_dev->num_channels; i++)
1081 st->available_scan_masks[i] = (1 << i) | (1 <<
1082 indio_dev->channels[indio_dev->num_channels - 1].
1083 scan_index);
1084
1085 init_waitqueue_head(&st->wq_data_avail);
1086
1087 ret = ad7192_register_ring_funcs_and_init(indio_dev);
1088 if (ret)
1089 goto error_disable_reg;
1090
1091 ret = iio_device_register(indio_dev);
1092 if (ret)
1093 goto error_unreg_ring;
1094 regdone = 1;
1095
1096 ret = ad7192_probe_trigger(indio_dev);
1097 if (ret)
1098 goto error_unreg_ring;
1099
1100 ret = iio_ring_buffer_register_ex(indio_dev->ring, 0,
1101 indio_dev->channels,
1102 indio_dev->num_channels);
1103 if (ret)
1104 goto error_remove_trigger;
1105
1106 ret = ad7192_setup(st);
1107 if (ret)
1108 goto error_uninitialize_ring;
1109
1110 return 0;
1111
1112 error_uninitialize_ring:
1113 iio_ring_buffer_unregister(indio_dev->ring);
1114 error_remove_trigger:
1115 ad7192_remove_trigger(indio_dev);
1116 error_unreg_ring:
1117 ad7192_ring_cleanup(indio_dev);
1118 error_disable_reg:
1119 if (!IS_ERR(st->reg))
1120 regulator_disable(st->reg);
1121 error_put_reg:
1122 if (!IS_ERR(st->reg))
1123 regulator_put(st->reg);
1124
1125 if (regdone)
1126 iio_device_unregister(indio_dev);
1127 else
1128 iio_free_device(indio_dev);
1129
1130 return ret;
1131 }
1132
1133 static int ad7192_remove(struct spi_device *spi)
1134 {
1135 struct iio_dev *indio_dev = spi_get_drvdata(spi);
1136 struct ad7192_state *st = iio_priv(indio_dev);
1137
1138 iio_ring_buffer_unregister(indio_dev->ring);
1139 ad7192_remove_trigger(indio_dev);
1140 ad7192_ring_cleanup(indio_dev);
1141
1142 if (!IS_ERR(st->reg)) {
1143 regulator_disable(st->reg);
1144 regulator_put(st->reg);
1145 }
1146
1147 iio_device_unregister(indio_dev);
1148
1149 return 0;
1150 }
1151
1152 static const struct spi_device_id ad7192_id[] = {
1153 {"ad7190", ID_AD7190},
1154 {"ad7192", ID_AD7192},
1155 {"ad7195", ID_AD7195},
1156 {}
1157 };
1158
1159 static struct spi_driver ad7192_driver = {
1160 .driver = {
1161 .name = "ad7192",
1162 .owner = THIS_MODULE,
1163 },
1164 .probe = ad7192_probe,
1165 .remove = __devexit_p(ad7192_remove),
1166 .id_table = ad7192_id,
1167 };
1168
1169 static int __init ad7192_init(void)
1170 {
1171 return spi_register_driver(&ad7192_driver);
1172 }
1173 module_init(ad7192_init);
1174
1175 static void __exit ad7192_exit(void)
1176 {
1177 spi_unregister_driver(&ad7192_driver);
1178 }
1179 module_exit(ad7192_exit);
1180
1181 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
1182 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7195 ADC");
1183 MODULE_LICENSE("GPL v2");
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