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staging:iio:various move default scan mask setting after ring register or remove
[mirror_ubuntu-bionic-kernel.git] / drivers / staging / iio / adc / max1363_core.c
1 /*
2 * iio/adc/max1363.c
3 * Copyright (C) 2008-2010 Jonathan Cameron
4 *
5 * based on linux/drivers/i2c/chips/max123x
6 * Copyright (C) 2002-2004 Stefan Eletzhofer
7 *
8 * based on linux/drivers/acron/char/pcf8583.c
9 * Copyright (C) 2000 Russell King
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * max1363.c
16 *
17 * Partial support for max1363 and similar chips.
18 *
19 * Not currently implemented.
20 *
21 * - Control of internal reference.
22 */
23
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/kernel.h>
27 #include <linux/sysfs.h>
28 #include <linux/list.h>
29 #include <linux/i2c.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/slab.h>
32 #include <linux/err.h>
33 #include <linux/module.h>
34
35 #include "../iio.h"
36 #include "../sysfs.h"
37 #include "../ring_generic.h"
38
39 #include "max1363.h"
40
41 #define MAX1363_MODE_SINGLE(_num, _mask) { \
42 .conf = MAX1363_CHANNEL_SEL(_num) \
43 | MAX1363_CONFIG_SCAN_SINGLE_1 \
44 | MAX1363_CONFIG_SE, \
45 .modemask = _mask, \
46 }
47
48 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
49 .conf = MAX1363_CHANNEL_SEL(_num) \
50 | MAX1363_CONFIG_SCAN_TO_CS \
51 | MAX1363_CONFIG_SE, \
52 .modemask = _mask, \
53 }
54
55 /* note not available for max1363 hence naming */
56 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
57 .conf = MAX1363_CHANNEL_SEL(_num) \
58 | MAX1236_SCAN_MID_TO_CHANNEL \
59 | MAX1363_CONFIG_SE, \
60 .modemask = _mask \
61 }
62
63 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
64 .conf = MAX1363_CHANNEL_SEL(_nump) \
65 | MAX1363_CONFIG_SCAN_SINGLE_1 \
66 | MAX1363_CONFIG_DE, \
67 .modemask = _mask \
68 }
69
70 /* Can't think how to automate naming so specify for now */
71 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
72 .conf = MAX1363_CHANNEL_SEL(_num) \
73 | MAX1363_CONFIG_SCAN_TO_CS \
74 | MAX1363_CONFIG_DE, \
75 .modemask = _mask \
76 }
77
78 /* note only available for max1363 hence naming */
79 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
80 .conf = MAX1363_CHANNEL_SEL(_num) \
81 | MAX1236_SCAN_MID_TO_CHANNEL \
82 | MAX1363_CONFIG_SE, \
83 .modemask = _mask \
84 }
85
86 static const struct max1363_mode max1363_mode_table[] = {
87 /* All of the single channel options first */
88 MAX1363_MODE_SINGLE(0, 1 << 0),
89 MAX1363_MODE_SINGLE(1, 1 << 1),
90 MAX1363_MODE_SINGLE(2, 1 << 2),
91 MAX1363_MODE_SINGLE(3, 1 << 3),
92 MAX1363_MODE_SINGLE(4, 1 << 4),
93 MAX1363_MODE_SINGLE(5, 1 << 5),
94 MAX1363_MODE_SINGLE(6, 1 << 6),
95 MAX1363_MODE_SINGLE(7, 1 << 7),
96 MAX1363_MODE_SINGLE(8, 1 << 8),
97 MAX1363_MODE_SINGLE(9, 1 << 9),
98 MAX1363_MODE_SINGLE(10, 1 << 10),
99 MAX1363_MODE_SINGLE(11, 1 << 11),
100
101 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
102 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
103 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
104 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
105 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
106 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
107 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
108 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
109 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
110 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
111 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
112 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
113
114 /* The multichannel scans next */
115 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
116 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
117 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
118 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
119 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
120 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
121 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
122 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
123 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
124 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
125 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
126 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
127 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
128 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
129 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
130 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
131 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
132
133 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
134 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
135 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
136 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
137 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
138 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
139 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
140 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
141 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
142 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
143 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
144 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
145 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
146 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
147 };
148
149 const struct max1363_mode
150 *max1363_match_mode(u32 mask, const struct max1363_chip_info *ci)
151 {
152 int i;
153 if (mask)
154 for (i = 0; i < ci->num_modes; i++)
155 if (!((~max1363_mode_table[ci->mode_list[i]].modemask) &
156 mask))
157 return &max1363_mode_table[ci->mode_list[i]];
158 return NULL;
159 }
160
161 static int max1363_write_basic_config(struct i2c_client *client,
162 unsigned char d1,
163 unsigned char d2)
164 {
165 u8 tx_buf[2] = {d1, d2};
166
167 return i2c_master_send(client, tx_buf, 2);
168 }
169
170 int max1363_set_scan_mode(struct max1363_state *st)
171 {
172 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
173 | MAX1363_SCAN_MASK
174 | MAX1363_SE_DE_MASK);
175 st->configbyte |= st->current_mode->conf;
176
177 return max1363_write_basic_config(st->client,
178 st->setupbyte,
179 st->configbyte);
180 }
181
182 static int max1363_read_single_chan(struct iio_dev *indio_dev,
183 struct iio_chan_spec const *chan,
184 int *val,
185 long m)
186 {
187 int ret = 0;
188 s32 data;
189 char rxbuf[2];
190 long mask;
191 struct max1363_state *st = iio_priv(indio_dev);
192 struct i2c_client *client = st->client;
193
194 mutex_lock(&indio_dev->mlock);
195 /*
196 * If monitor mode is enabled, the method for reading a single
197 * channel will have to be rather different and has not yet
198 * been implemented.
199 */
200 if (st->monitor_on) {
201 ret = -EBUSY;
202 goto error_ret;
203 }
204
205 /* If ring buffer capture is occurring, query the buffer */
206 if (iio_ring_enabled(indio_dev)) {
207 mask = max1363_mode_table[chan->address].modemask;
208 data = max1363_single_channel_from_ring(mask, st);
209 if (data < 0) {
210 ret = data;
211 goto error_ret;
212 }
213 } else {
214 /* Check to see if current scan mode is correct */
215 if (st->current_mode != &max1363_mode_table[chan->address]) {
216 /* Update scan mode if needed */
217 st->current_mode = &max1363_mode_table[chan->address];
218 ret = max1363_set_scan_mode(st);
219 if (ret < 0)
220 goto error_ret;
221 }
222 if (st->chip_info->bits != 8) {
223 /* Get reading */
224 data = i2c_master_recv(client, rxbuf, 2);
225 if (data < 0) {
226 ret = data;
227 goto error_ret;
228 }
229 data = (s32)(rxbuf[1]) | ((s32)(rxbuf[0] & 0x0F)) << 8;
230 } else {
231 /* Get reading */
232 data = i2c_master_recv(client, rxbuf, 1);
233 if (data < 0) {
234 ret = data;
235 goto error_ret;
236 }
237 data = rxbuf[0];
238 }
239 }
240 *val = data;
241 error_ret:
242 mutex_unlock(&indio_dev->mlock);
243 return ret;
244
245 }
246
247 static int max1363_read_raw(struct iio_dev *indio_dev,
248 struct iio_chan_spec const *chan,
249 int *val,
250 int *val2,
251 long m)
252 {
253 struct max1363_state *st = iio_priv(indio_dev);
254 int ret;
255 switch (m) {
256 case 0:
257 ret = max1363_read_single_chan(indio_dev, chan, val, m);
258 if (ret < 0)
259 return ret;
260 return IIO_VAL_INT;
261 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
262 if ((1 << (st->chip_info->bits + 1)) >
263 st->chip_info->int_vref_mv) {
264 *val = 0;
265 *val2 = 500000;
266 return IIO_VAL_INT_PLUS_MICRO;
267 } else {
268 *val = (st->chip_info->int_vref_mv)
269 >> st->chip_info->bits;
270 return IIO_VAL_INT;
271 }
272 default:
273 return -EINVAL;
274 }
275 return 0;
276 }
277
278 /* Applies to max1363 */
279 static const enum max1363_modes max1363_mode_list[] = {
280 _s0, _s1, _s2, _s3,
281 s0to1, s0to2, s0to3,
282 d0m1, d2m3, d1m0, d3m2,
283 d0m1to2m3, d1m0to3m2,
284 };
285
286 #define MAX1363_EV_M \
287 (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) \
288 | IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
289 #define MAX1363_INFO_MASK (1 << IIO_CHAN_INFO_SCALE_SHARED)
290
291 static struct iio_chan_spec max1363_channels[] = {
292 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0, MAX1363_INFO_MASK,
293 _s0, 0, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
294 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
295 _s1, 1, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
296 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0, MAX1363_INFO_MASK,
297 _s2, 2, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
298 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0, MAX1363_INFO_MASK,
299 _s3, 3, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
300 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 0, 1, MAX1363_INFO_MASK,
301 d0m1, 4, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
302 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 2, 3, MAX1363_INFO_MASK,
303 d2m3, 5, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
304 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
305 d1m0, 6, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
306 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 3, 2, MAX1363_INFO_MASK,
307 d3m2, 7, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
308 IIO_CHAN_SOFT_TIMESTAMP(8)
309 };
310
311 static struct iio_chan_spec max1361_channels[] = {
312 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0, MAX1363_INFO_MASK,
313 _s0, 0, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
314 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
315 _s1, 1, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
316 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0, MAX1363_INFO_MASK,
317 _s2, 2, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
318 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0, MAX1363_INFO_MASK,
319 _s3, 3, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
320 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 0, 1, MAX1363_INFO_MASK,
321 d0m1, 4, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
322 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 2, 3, MAX1363_INFO_MASK,
323 d2m3, 5, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
324 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
325 d1m0, 6, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
326 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 3, 2, MAX1363_INFO_MASK,
327 d3m2, 7, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
328 IIO_CHAN_SOFT_TIMESTAMP(8)
329 };
330
331 #define MAX1363_CHAN_U(num, address, scan_index, bits) \
332 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, num, 0, MAX1363_INFO_MASK, \
333 address, scan_index, IIO_ST('u', bits, \
334 (bits == 8) ? 8 : 16, 0), 0)
335 /* bipolar channel */
336 #define MAX1363_CHAN_B(num, num2, address, scan_index, bits) \
337 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, num, num2, MAX1363_INFO_MASK,\
338 address, scan_index, IIO_ST('s', bits, \
339 (bits == 8) ? 8 : 16, 0), 0)
340
341 #define MAX1363_4X_CHANS(bits) { \
342 MAX1363_CHAN_U(0, _s0, 0, bits), \
343 MAX1363_CHAN_U(1, _s1, 1, bits), \
344 MAX1363_CHAN_U(2, _s2, 2, bits), \
345 MAX1363_CHAN_U(3, _s3, 3, bits), \
346 MAX1363_CHAN_B(0, 1, d0m1, 4, bits), \
347 MAX1363_CHAN_B(2, 3, d2m3, 5, bits), \
348 MAX1363_CHAN_B(1, 0, d1m0, 6, bits), \
349 MAX1363_CHAN_B(3, 2, d3m2, 7, bits), \
350 IIO_CHAN_SOFT_TIMESTAMP(8) \
351 }
352
353 static struct iio_chan_spec max1036_channels[] = MAX1363_4X_CHANS(8);
354 static struct iio_chan_spec max1136_channels[] = MAX1363_4X_CHANS(10);
355 static struct iio_chan_spec max1236_channels[] = MAX1363_4X_CHANS(12);
356
357 /* Appies to max1236, max1237 */
358 static const enum max1363_modes max1236_mode_list[] = {
359 _s0, _s1, _s2, _s3,
360 s0to1, s0to2, s0to3,
361 d0m1, d2m3, d1m0, d3m2,
362 d0m1to2m3, d1m0to3m2,
363 s2to3,
364 };
365
366 /* Applies to max1238, max1239 */
367 static const enum max1363_modes max1238_mode_list[] = {
368 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
369 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
370 s0to7, s0to8, s0to9, s0to10, s0to11,
371 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
372 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
373 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
374 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
375 s6to7, s6to8, s6to9, s6to10, s6to11,
376 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
377 };
378
379 #define MAX1363_12X_CHANS(bits) { \
380 MAX1363_CHAN_U(0, _s0, 0, bits), \
381 MAX1363_CHAN_U(1, _s1, 1, bits), \
382 MAX1363_CHAN_U(2, _s2, 2, bits), \
383 MAX1363_CHAN_U(3, _s3, 3, bits), \
384 MAX1363_CHAN_U(4, _s4, 4, bits), \
385 MAX1363_CHAN_U(5, _s5, 5, bits), \
386 MAX1363_CHAN_U(6, _s6, 6, bits), \
387 MAX1363_CHAN_U(7, _s7, 7, bits), \
388 MAX1363_CHAN_U(8, _s8, 8, bits), \
389 MAX1363_CHAN_U(9, _s9, 9, bits), \
390 MAX1363_CHAN_U(10, _s10, 10, bits), \
391 MAX1363_CHAN_U(11, _s11, 11, bits), \
392 MAX1363_CHAN_B(0, 1, d0m1, 12, bits), \
393 MAX1363_CHAN_B(2, 3, d2m3, 13, bits), \
394 MAX1363_CHAN_B(4, 5, d4m5, 14, bits), \
395 MAX1363_CHAN_B(6, 7, d6m7, 15, bits), \
396 MAX1363_CHAN_B(8, 9, d8m9, 16, bits), \
397 MAX1363_CHAN_B(10, 11, d10m11, 17, bits), \
398 MAX1363_CHAN_B(1, 0, d1m0, 18, bits), \
399 MAX1363_CHAN_B(3, 2, d3m2, 19, bits), \
400 MAX1363_CHAN_B(5, 4, d5m4, 20, bits), \
401 MAX1363_CHAN_B(7, 6, d7m6, 21, bits), \
402 MAX1363_CHAN_B(9, 8, d9m8, 22, bits), \
403 MAX1363_CHAN_B(11, 10, d11m10, 23, bits), \
404 IIO_CHAN_SOFT_TIMESTAMP(24) \
405 }
406 static struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
407 static struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
408 static struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
409
410 static const enum max1363_modes max11607_mode_list[] = {
411 _s0, _s1, _s2, _s3,
412 s0to1, s0to2, s0to3,
413 s2to3,
414 d0m1, d2m3, d1m0, d3m2,
415 d0m1to2m3, d1m0to3m2,
416 };
417
418 static const enum max1363_modes max11608_mode_list[] = {
419 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
420 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
421 s6to7,
422 d0m1, d2m3, d4m5, d6m7,
423 d1m0, d3m2, d5m4, d7m6,
424 d0m1to2m3, d0m1to4m5, d0m1to6m7,
425 d1m0to3m2, d1m0to5m4, d1m0to7m6,
426 };
427
428 #define MAX1363_8X_CHANS(bits) { \
429 MAX1363_CHAN_U(0, _s0, 0, bits), \
430 MAX1363_CHAN_U(1, _s1, 1, bits), \
431 MAX1363_CHAN_U(2, _s2, 2, bits), \
432 MAX1363_CHAN_U(3, _s3, 3, bits), \
433 MAX1363_CHAN_U(4, _s4, 4, bits), \
434 MAX1363_CHAN_U(5, _s5, 5, bits), \
435 MAX1363_CHAN_U(6, _s6, 6, bits), \
436 MAX1363_CHAN_U(7, _s7, 7, bits), \
437 MAX1363_CHAN_B(0, 1, d0m1, 8, bits), \
438 MAX1363_CHAN_B(2, 3, d2m3, 9, bits), \
439 MAX1363_CHAN_B(4, 5, d4m5, 10, bits), \
440 MAX1363_CHAN_B(6, 7, d6m7, 11, bits), \
441 MAX1363_CHAN_B(1, 0, d1m0, 12, bits), \
442 MAX1363_CHAN_B(3, 2, d3m2, 13, bits), \
443 MAX1363_CHAN_B(5, 4, d5m4, 14, bits), \
444 MAX1363_CHAN_B(7, 6, d7m6, 15, bits), \
445 IIO_CHAN_SOFT_TIMESTAMP(16) \
446 }
447 static struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
448 static struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
449 static struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
450
451 static const enum max1363_modes max11644_mode_list[] = {
452 _s0, _s1, s0to1, d0m1, d1m0,
453 };
454
455 #define MAX1363_2X_CHANS(bits) { \
456 MAX1363_CHAN_U(0, _s0, 0, bits), \
457 MAX1363_CHAN_U(1, _s1, 1, bits), \
458 MAX1363_CHAN_B(0, 1, d0m1, 2, bits), \
459 MAX1363_CHAN_B(1, 0, d1m0, 3, bits), \
460 IIO_CHAN_SOFT_TIMESTAMP(4) \
461 }
462
463 static struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
464 static struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
465
466 enum { max1361,
467 max1362,
468 max1363,
469 max1364,
470 max1036,
471 max1037,
472 max1038,
473 max1039,
474 max1136,
475 max1137,
476 max1138,
477 max1139,
478 max1236,
479 max1237,
480 max1238,
481 max1239,
482 max11600,
483 max11601,
484 max11602,
485 max11603,
486 max11604,
487 max11605,
488 max11606,
489 max11607,
490 max11608,
491 max11609,
492 max11610,
493 max11611,
494 max11612,
495 max11613,
496 max11614,
497 max11615,
498 max11616,
499 max11617,
500 max11644,
501 max11645,
502 max11646,
503 max11647
504 };
505
506 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
507 8300, 4200, 2000, 1000 };
508
509 static ssize_t max1363_monitor_show_freq(struct device *dev,
510 struct device_attribute *attr,
511 char *buf)
512 {
513 struct max1363_state *st = iio_priv(dev_get_drvdata(dev));
514 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
515 }
516
517 static ssize_t max1363_monitor_store_freq(struct device *dev,
518 struct device_attribute *attr,
519 const char *buf,
520 size_t len)
521 {
522 struct iio_dev *indio_dev = dev_get_drvdata(dev);
523 struct max1363_state *st = iio_priv(indio_dev);
524 int i, ret;
525 unsigned long val;
526 bool found = false;
527
528 ret = strict_strtoul(buf, 10, &val);
529 if (ret)
530 return -EINVAL;
531 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
532 if (val == max1363_monitor_speeds[i]) {
533 found = true;
534 break;
535 }
536 if (!found)
537 return -EINVAL;
538
539 mutex_lock(&indio_dev->mlock);
540 st->monitor_speed = i;
541 mutex_unlock(&indio_dev->mlock);
542
543 return 0;
544 }
545
546 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
547 max1363_monitor_show_freq,
548 max1363_monitor_store_freq);
549
550 static IIO_CONST_ATTR(sampling_frequency_available,
551 "133000 665000 33300 16600 8300 4200 2000 1000");
552
553 static int max1363_read_thresh(struct iio_dev *indio_dev,
554 int event_code,
555 int *val)
556 {
557 struct max1363_state *st = iio_priv(indio_dev);
558 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
559 *val = st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)];
560 else
561 *val = st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)];
562 return 0;
563 }
564
565 static int max1363_write_thresh(struct iio_dev *indio_dev,
566 int event_code,
567 int val)
568 {
569 struct max1363_state *st = iio_priv(indio_dev);
570 /* make it handle signed correctly as well */
571 switch (st->chip_info->bits) {
572 case 10:
573 if (val > 0x3FF)
574 return -EINVAL;
575 break;
576 case 12:
577 if (val > 0xFFF)
578 return -EINVAL;
579 break;
580 }
581
582 switch (IIO_EVENT_CODE_EXTRACT_DIR(event_code)) {
583 case IIO_EV_DIR_FALLING:
584 st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val;
585 break;
586 case IIO_EV_DIR_RISING:
587 st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val;
588 break;
589 }
590
591 return 0;
592 }
593
594 static const int max1363_event_codes[] = {
595 IIO_UNMOD_EVENT_CODE(IIO_IN, 0, IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
596 IIO_UNMOD_EVENT_CODE(IIO_IN, 1, IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
597 IIO_UNMOD_EVENT_CODE(IIO_IN, 2, IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
598 IIO_UNMOD_EVENT_CODE(IIO_IN, 3, IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
599 IIO_UNMOD_EVENT_CODE(IIO_IN, 0, IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
600 IIO_UNMOD_EVENT_CODE(IIO_IN, 1, IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
601 IIO_UNMOD_EVENT_CODE(IIO_IN, 2, IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
602 IIO_UNMOD_EVENT_CODE(IIO_IN, 3, IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
603 };
604
605 static irqreturn_t max1363_event_handler(int irq, void *private)
606 {
607 struct iio_dev *indio_dev = private;
608 struct max1363_state *st = iio_priv(indio_dev);
609 s64 timestamp = iio_get_time_ns();
610 unsigned long mask, loc;
611 u8 rx;
612 u8 tx[2] = { st->setupbyte,
613 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
614
615 i2c_master_recv(st->client, &rx, 1);
616 mask = rx;
617 for_each_set_bit(loc, &mask, 8)
618 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
619 i2c_master_send(st->client, tx, 2);
620
621 return IRQ_HANDLED;
622 }
623
624 static int max1363_read_event_config(struct iio_dev *indio_dev,
625 int event_code)
626 {
627 struct max1363_state *st = iio_priv(indio_dev);
628
629 int val;
630 int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code);
631 mutex_lock(&indio_dev->mlock);
632 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
633 val = (1 << number) & st->mask_low;
634 else
635 val = (1 << number) & st->mask_high;
636 mutex_unlock(&indio_dev->mlock);
637
638 return val;
639 }
640
641 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
642 {
643 u8 *tx_buf;
644 int ret, i = 3, j;
645 unsigned long numelements;
646 int len;
647 long modemask;
648
649 if (!enabled) {
650 /* transition to ring capture is not currently supported */
651 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
652 st->configbyte &= ~MAX1363_SCAN_MASK;
653 st->monitor_on = false;
654 return max1363_write_basic_config(st->client,
655 st->setupbyte,
656 st->configbyte);
657 }
658
659 /* Ensure we are in the relevant mode */
660 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
661 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
662 | MAX1363_SCAN_MASK
663 | MAX1363_SE_DE_MASK);
664 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
665 if ((st->mask_low | st->mask_high) & 0x0F) {
666 st->configbyte |= max1363_mode_table[s0to3].conf;
667 modemask = max1363_mode_table[s0to3].modemask;
668 } else if ((st->mask_low | st->mask_high) & 0x30) {
669 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
670 modemask = max1363_mode_table[d0m1to2m3].modemask;
671 } else {
672 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
673 modemask = max1363_mode_table[d1m0to3m2].modemask;
674 }
675 numelements = hweight_long(modemask);
676 len = 3 * numelements + 3;
677 tx_buf = kmalloc(len, GFP_KERNEL);
678 if (!tx_buf) {
679 ret = -ENOMEM;
680 goto error_ret;
681 }
682 tx_buf[0] = st->configbyte;
683 tx_buf[1] = st->setupbyte;
684 tx_buf[2] = (st->monitor_speed << 1);
685
686 /*
687 * So we need to do yet another bit of nefarious scan mode
688 * setup to match what we need.
689 */
690 for (j = 0; j < 8; j++)
691 if (modemask & (1 << j)) {
692 /* Establish the mode is in the scan */
693 if (st->mask_low & (1 << j)) {
694 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
695 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
696 } else if (j < 4) {
697 tx_buf[i] = 0;
698 tx_buf[i + 1] = 0;
699 } else {
700 tx_buf[i] = 0x80;
701 tx_buf[i + 1] = 0;
702 }
703 if (st->mask_high & (1 << j)) {
704 tx_buf[i + 1] |=
705 (st->thresh_high[j] >> 8) & 0x0F;
706 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
707 } else if (j < 4) {
708 tx_buf[i + 1] |= 0x0F;
709 tx_buf[i + 2] = 0xFF;
710 } else {
711 tx_buf[i + 1] |= 0x07;
712 tx_buf[i + 2] = 0xFF;
713 }
714 i += 3;
715 }
716
717
718 ret = i2c_master_send(st->client, tx_buf, len);
719 if (ret < 0)
720 goto error_ret;
721 if (ret != len) {
722 ret = -EIO;
723 goto error_ret;
724 }
725
726 /*
727 * Now that we hopefully have sensible thresholds in place it is
728 * time to turn the interrupts on.
729 * It is unclear from the data sheet if this should be necessary
730 * (i.e. whether monitor mode setup is atomic) but it appears to
731 * be in practice.
732 */
733 tx_buf[0] = st->setupbyte;
734 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
735 ret = i2c_master_send(st->client, tx_buf, 2);
736 if (ret < 0)
737 goto error_ret;
738 if (ret != 2) {
739 ret = -EIO;
740 goto error_ret;
741 }
742 ret = 0;
743 st->monitor_on = true;
744 error_ret:
745
746 kfree(tx_buf);
747
748 return ret;
749 }
750
751 /*
752 * To keep this manageable we always use one of 3 scan modes.
753 * Scan 0...3, 0-1,2-3 and 1-0,3-2
754 */
755
756 static inline int __max1363_check_event_mask(int thismask, int checkmask)
757 {
758 int ret = 0;
759 /* Is it unipolar */
760 if (thismask < 4) {
761 if (checkmask & ~0x0F) {
762 ret = -EBUSY;
763 goto error_ret;
764 }
765 } else if (thismask < 6) {
766 if (checkmask & ~0x30) {
767 ret = -EBUSY;
768 goto error_ret;
769 }
770 } else if (checkmask & ~0xC0)
771 ret = -EBUSY;
772 error_ret:
773 return ret;
774 }
775
776 static int max1363_write_event_config(struct iio_dev *indio_dev,
777 int event_code,
778 int state)
779 {
780 int ret = 0;
781 struct max1363_state *st = iio_priv(indio_dev);
782 u16 unifiedmask;
783 int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code);
784
785 mutex_lock(&indio_dev->mlock);
786 unifiedmask = st->mask_low | st->mask_high;
787 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING) {
788
789 if (state == 0)
790 st->mask_low &= ~(1 << number);
791 else {
792 ret = __max1363_check_event_mask((1 << number),
793 unifiedmask);
794 if (ret)
795 goto error_ret;
796 st->mask_low |= (1 << number);
797 }
798 } else {
799 if (state == 0)
800 st->mask_high &= ~(1 << number);
801 else {
802 ret = __max1363_check_event_mask((1 << number),
803 unifiedmask);
804 if (ret)
805 goto error_ret;
806 st->mask_high |= (1 << number);
807 }
808 }
809
810 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
811 error_ret:
812 mutex_unlock(&indio_dev->mlock);
813
814 return ret;
815 }
816
817 /*
818 * As with scan_elements, only certain sets of these can
819 * be combined.
820 */
821 static struct attribute *max1363_event_attributes[] = {
822 &iio_dev_attr_sampling_frequency.dev_attr.attr,
823 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
824 NULL,
825 };
826
827 static struct attribute_group max1363_event_attribute_group = {
828 .attrs = max1363_event_attributes,
829 .name = "events",
830 };
831
832 #define MAX1363_EVENT_FUNCS \
833
834
835 static const struct iio_info max1238_info = {
836 .read_raw = &max1363_read_raw,
837 .driver_module = THIS_MODULE,
838 };
839
840 static const struct iio_info max1363_info = {
841 .read_event_value = &max1363_read_thresh,
842 .write_event_value = &max1363_write_thresh,
843 .read_event_config = &max1363_read_event_config,
844 .write_event_config = &max1363_write_event_config,
845 .read_raw = &max1363_read_raw,
846 .driver_module = THIS_MODULE,
847 .event_attrs = &max1363_event_attribute_group,
848 };
849
850 /* max1363 and max1368 tested - rest from data sheet */
851 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
852 [max1361] = {
853 .bits = 10,
854 .int_vref_mv = 2048,
855 .mode_list = max1363_mode_list,
856 .num_modes = ARRAY_SIZE(max1363_mode_list),
857 .default_mode = s0to3,
858 .channels = max1361_channels,
859 .num_channels = ARRAY_SIZE(max1361_channels),
860 .info = &max1363_info,
861 },
862 [max1362] = {
863 .bits = 10,
864 .int_vref_mv = 4096,
865 .mode_list = max1363_mode_list,
866 .num_modes = ARRAY_SIZE(max1363_mode_list),
867 .default_mode = s0to3,
868 .channels = max1361_channels,
869 .num_channels = ARRAY_SIZE(max1361_channels),
870 .info = &max1363_info,
871 },
872 [max1363] = {
873 .bits = 12,
874 .int_vref_mv = 2048,
875 .mode_list = max1363_mode_list,
876 .num_modes = ARRAY_SIZE(max1363_mode_list),
877 .default_mode = s0to3,
878 .channels = max1363_channels,
879 .num_channels = ARRAY_SIZE(max1363_channels),
880 .info = &max1363_info,
881 },
882 [max1364] = {
883 .bits = 12,
884 .int_vref_mv = 4096,
885 .mode_list = max1363_mode_list,
886 .num_modes = ARRAY_SIZE(max1363_mode_list),
887 .default_mode = s0to3,
888 .channels = max1363_channels,
889 .num_channels = ARRAY_SIZE(max1363_channels),
890 .info = &max1363_info,
891 },
892 [max1036] = {
893 .bits = 8,
894 .int_vref_mv = 4096,
895 .mode_list = max1236_mode_list,
896 .num_modes = ARRAY_SIZE(max1236_mode_list),
897 .default_mode = s0to3,
898 .info = &max1238_info,
899 .channels = max1036_channels,
900 .num_channels = ARRAY_SIZE(max1036_channels),
901 },
902 [max1037] = {
903 .bits = 8,
904 .int_vref_mv = 2048,
905 .mode_list = max1236_mode_list,
906 .num_modes = ARRAY_SIZE(max1236_mode_list),
907 .default_mode = s0to3,
908 .info = &max1238_info,
909 .channels = max1036_channels,
910 .num_channels = ARRAY_SIZE(max1036_channels),
911 },
912 [max1038] = {
913 .bits = 8,
914 .int_vref_mv = 4096,
915 .mode_list = max1238_mode_list,
916 .num_modes = ARRAY_SIZE(max1238_mode_list),
917 .default_mode = s0to11,
918 .info = &max1238_info,
919 .channels = max1038_channels,
920 .num_channels = ARRAY_SIZE(max1038_channels),
921 },
922 [max1039] = {
923 .bits = 8,
924 .int_vref_mv = 2048,
925 .mode_list = max1238_mode_list,
926 .num_modes = ARRAY_SIZE(max1238_mode_list),
927 .default_mode = s0to11,
928 .info = &max1238_info,
929 .channels = max1038_channels,
930 .num_channels = ARRAY_SIZE(max1038_channels),
931 },
932 [max1136] = {
933 .bits = 10,
934 .int_vref_mv = 4096,
935 .mode_list = max1236_mode_list,
936 .num_modes = ARRAY_SIZE(max1236_mode_list),
937 .default_mode = s0to3,
938 .info = &max1238_info,
939 .channels = max1136_channels,
940 .num_channels = ARRAY_SIZE(max1136_channels),
941 },
942 [max1137] = {
943 .bits = 10,
944 .int_vref_mv = 2048,
945 .mode_list = max1236_mode_list,
946 .num_modes = ARRAY_SIZE(max1236_mode_list),
947 .default_mode = s0to3,
948 .info = &max1238_info,
949 .channels = max1136_channels,
950 .num_channels = ARRAY_SIZE(max1136_channels),
951 },
952 [max1138] = {
953 .bits = 10,
954 .int_vref_mv = 4096,
955 .mode_list = max1238_mode_list,
956 .num_modes = ARRAY_SIZE(max1238_mode_list),
957 .default_mode = s0to11,
958 .info = &max1238_info,
959 .channels = max1138_channels,
960 .num_channels = ARRAY_SIZE(max1138_channels),
961 },
962 [max1139] = {
963 .bits = 10,
964 .int_vref_mv = 2048,
965 .mode_list = max1238_mode_list,
966 .num_modes = ARRAY_SIZE(max1238_mode_list),
967 .default_mode = s0to11,
968 .info = &max1238_info,
969 .channels = max1138_channels,
970 .num_channels = ARRAY_SIZE(max1138_channels),
971 },
972 [max1236] = {
973 .bits = 12,
974 .int_vref_mv = 4096,
975 .mode_list = max1236_mode_list,
976 .num_modes = ARRAY_SIZE(max1236_mode_list),
977 .default_mode = s0to3,
978 .info = &max1238_info,
979 .channels = max1236_channels,
980 .num_channels = ARRAY_SIZE(max1236_channels),
981 },
982 [max1237] = {
983 .bits = 12,
984 .int_vref_mv = 2048,
985 .mode_list = max1236_mode_list,
986 .num_modes = ARRAY_SIZE(max1236_mode_list),
987 .default_mode = s0to3,
988 .info = &max1238_info,
989 .channels = max1236_channels,
990 .num_channels = ARRAY_SIZE(max1236_channels),
991 },
992 [max1238] = {
993 .bits = 12,
994 .int_vref_mv = 4096,
995 .mode_list = max1238_mode_list,
996 .num_modes = ARRAY_SIZE(max1238_mode_list),
997 .default_mode = s0to11,
998 .info = &max1238_info,
999 .channels = max1238_channels,
1000 .num_channels = ARRAY_SIZE(max1238_channels),
1001 },
1002 [max1239] = {
1003 .bits = 12,
1004 .int_vref_mv = 2048,
1005 .mode_list = max1238_mode_list,
1006 .num_modes = ARRAY_SIZE(max1238_mode_list),
1007 .default_mode = s0to11,
1008 .info = &max1238_info,
1009 .channels = max1238_channels,
1010 .num_channels = ARRAY_SIZE(max1238_channels),
1011 },
1012 [max11600] = {
1013 .bits = 8,
1014 .int_vref_mv = 4096,
1015 .mode_list = max11607_mode_list,
1016 .num_modes = ARRAY_SIZE(max11607_mode_list),
1017 .default_mode = s0to3,
1018 .info = &max1238_info,
1019 .channels = max1036_channels,
1020 .num_channels = ARRAY_SIZE(max1036_channels),
1021 },
1022 [max11601] = {
1023 .bits = 8,
1024 .int_vref_mv = 2048,
1025 .mode_list = max11607_mode_list,
1026 .num_modes = ARRAY_SIZE(max11607_mode_list),
1027 .default_mode = s0to3,
1028 .info = &max1238_info,
1029 .channels = max1036_channels,
1030 .num_channels = ARRAY_SIZE(max1036_channels),
1031 },
1032 [max11602] = {
1033 .bits = 8,
1034 .int_vref_mv = 4096,
1035 .mode_list = max11608_mode_list,
1036 .num_modes = ARRAY_SIZE(max11608_mode_list),
1037 .default_mode = s0to7,
1038 .info = &max1238_info,
1039 .channels = max11602_channels,
1040 .num_channels = ARRAY_SIZE(max11602_channels),
1041 },
1042 [max11603] = {
1043 .bits = 8,
1044 .int_vref_mv = 2048,
1045 .mode_list = max11608_mode_list,
1046 .num_modes = ARRAY_SIZE(max11608_mode_list),
1047 .default_mode = s0to7,
1048 .info = &max1238_info,
1049 .channels = max11602_channels,
1050 .num_channels = ARRAY_SIZE(max11602_channels),
1051 },
1052 [max11604] = {
1053 .bits = 8,
1054 .int_vref_mv = 4098,
1055 .mode_list = max1238_mode_list,
1056 .num_modes = ARRAY_SIZE(max1238_mode_list),
1057 .default_mode = s0to11,
1058 .info = &max1238_info,
1059 .channels = max1238_channels,
1060 .num_channels = ARRAY_SIZE(max1238_channels),
1061 },
1062 [max11605] = {
1063 .bits = 8,
1064 .int_vref_mv = 2048,
1065 .mode_list = max1238_mode_list,
1066 .num_modes = ARRAY_SIZE(max1238_mode_list),
1067 .default_mode = s0to11,
1068 .info = &max1238_info,
1069 .channels = max1238_channels,
1070 .num_channels = ARRAY_SIZE(max1238_channels),
1071 },
1072 [max11606] = {
1073 .bits = 10,
1074 .int_vref_mv = 4096,
1075 .mode_list = max11607_mode_list,
1076 .num_modes = ARRAY_SIZE(max11607_mode_list),
1077 .default_mode = s0to3,
1078 .info = &max1238_info,
1079 .channels = max1136_channels,
1080 .num_channels = ARRAY_SIZE(max1136_channels),
1081 },
1082 [max11607] = {
1083 .bits = 10,
1084 .int_vref_mv = 2048,
1085 .mode_list = max11607_mode_list,
1086 .num_modes = ARRAY_SIZE(max11607_mode_list),
1087 .default_mode = s0to3,
1088 .info = &max1238_info,
1089 .channels = max1136_channels,
1090 .num_channels = ARRAY_SIZE(max1136_channels),
1091 },
1092 [max11608] = {
1093 .bits = 10,
1094 .int_vref_mv = 4096,
1095 .mode_list = max11608_mode_list,
1096 .num_modes = ARRAY_SIZE(max11608_mode_list),
1097 .default_mode = s0to7,
1098 .info = &max1238_info,
1099 .channels = max11608_channels,
1100 .num_channels = ARRAY_SIZE(max11608_channels),
1101 },
1102 [max11609] = {
1103 .bits = 10,
1104 .int_vref_mv = 2048,
1105 .mode_list = max11608_mode_list,
1106 .num_modes = ARRAY_SIZE(max11608_mode_list),
1107 .default_mode = s0to7,
1108 .info = &max1238_info,
1109 .channels = max11608_channels,
1110 .num_channels = ARRAY_SIZE(max11608_channels),
1111 },
1112 [max11610] = {
1113 .bits = 10,
1114 .int_vref_mv = 4098,
1115 .mode_list = max1238_mode_list,
1116 .num_modes = ARRAY_SIZE(max1238_mode_list),
1117 .default_mode = s0to11,
1118 .info = &max1238_info,
1119 .channels = max1238_channels,
1120 .num_channels = ARRAY_SIZE(max1238_channels),
1121 },
1122 [max11611] = {
1123 .bits = 10,
1124 .int_vref_mv = 2048,
1125 .mode_list = max1238_mode_list,
1126 .num_modes = ARRAY_SIZE(max1238_mode_list),
1127 .default_mode = s0to11,
1128 .info = &max1238_info,
1129 .channels = max1238_channels,
1130 .num_channels = ARRAY_SIZE(max1238_channels),
1131 },
1132 [max11612] = {
1133 .bits = 12,
1134 .int_vref_mv = 4096,
1135 .mode_list = max11607_mode_list,
1136 .num_modes = ARRAY_SIZE(max11607_mode_list),
1137 .default_mode = s0to3,
1138 .info = &max1238_info,
1139 .channels = max1363_channels,
1140 .num_channels = ARRAY_SIZE(max1363_channels),
1141 },
1142 [max11613] = {
1143 .bits = 12,
1144 .int_vref_mv = 2048,
1145 .mode_list = max11607_mode_list,
1146 .num_modes = ARRAY_SIZE(max11607_mode_list),
1147 .default_mode = s0to3,
1148 .info = &max1238_info,
1149 .channels = max1363_channels,
1150 .num_channels = ARRAY_SIZE(max1363_channels),
1151 },
1152 [max11614] = {
1153 .bits = 12,
1154 .int_vref_mv = 4096,
1155 .mode_list = max11608_mode_list,
1156 .num_modes = ARRAY_SIZE(max11608_mode_list),
1157 .default_mode = s0to7,
1158 .info = &max1238_info,
1159 .channels = max11614_channels,
1160 .num_channels = ARRAY_SIZE(max11614_channels),
1161 },
1162 [max11615] = {
1163 .bits = 12,
1164 .int_vref_mv = 2048,
1165 .mode_list = max11608_mode_list,
1166 .num_modes = ARRAY_SIZE(max11608_mode_list),
1167 .default_mode = s0to7,
1168 .info = &max1238_info,
1169 .channels = max11614_channels,
1170 .num_channels = ARRAY_SIZE(max11614_channels),
1171 },
1172 [max11616] = {
1173 .bits = 12,
1174 .int_vref_mv = 4098,
1175 .mode_list = max1238_mode_list,
1176 .num_modes = ARRAY_SIZE(max1238_mode_list),
1177 .default_mode = s0to11,
1178 .info = &max1238_info,
1179 .channels = max1238_channels,
1180 .num_channels = ARRAY_SIZE(max1238_channels),
1181 },
1182 [max11617] = {
1183 .bits = 12,
1184 .int_vref_mv = 2048,
1185 .mode_list = max1238_mode_list,
1186 .num_modes = ARRAY_SIZE(max1238_mode_list),
1187 .default_mode = s0to11,
1188 .info = &max1238_info,
1189 .channels = max1238_channels,
1190 .num_channels = ARRAY_SIZE(max1238_channels),
1191 },
1192 [max11644] = {
1193 .bits = 12,
1194 .int_vref_mv = 2048,
1195 .mode_list = max11644_mode_list,
1196 .num_modes = ARRAY_SIZE(max11644_mode_list),
1197 .default_mode = s0to1,
1198 .info = &max1238_info,
1199 .channels = max11644_channels,
1200 .num_channels = ARRAY_SIZE(max11644_channels),
1201 },
1202 [max11645] = {
1203 .bits = 12,
1204 .int_vref_mv = 4096,
1205 .mode_list = max11644_mode_list,
1206 .num_modes = ARRAY_SIZE(max11644_mode_list),
1207 .default_mode = s0to1,
1208 .info = &max1238_info,
1209 .channels = max11644_channels,
1210 .num_channels = ARRAY_SIZE(max11644_channels),
1211 },
1212 [max11646] = {
1213 .bits = 10,
1214 .int_vref_mv = 2048,
1215 .mode_list = max11644_mode_list,
1216 .num_modes = ARRAY_SIZE(max11644_mode_list),
1217 .default_mode = s0to1,
1218 .info = &max1238_info,
1219 .channels = max11646_channels,
1220 .num_channels = ARRAY_SIZE(max11646_channels),
1221 },
1222 [max11647] = {
1223 .bits = 10,
1224 .int_vref_mv = 4096,
1225 .mode_list = max11644_mode_list,
1226 .num_modes = ARRAY_SIZE(max11644_mode_list),
1227 .default_mode = s0to1,
1228 .info = &max1238_info,
1229 .channels = max11646_channels,
1230 .num_channels = ARRAY_SIZE(max11646_channels),
1231 },
1232 };
1233
1234
1235
1236 static int max1363_initial_setup(struct max1363_state *st)
1237 {
1238 st->setupbyte = MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD
1239 | MAX1363_SETUP_POWER_UP_INT_REF
1240 | MAX1363_SETUP_INT_CLOCK
1241 | MAX1363_SETUP_UNIPOLAR
1242 | MAX1363_SETUP_NORESET;
1243
1244 /* Set scan mode writes the config anyway so wait until then*/
1245 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1246 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1247 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1248
1249 return max1363_set_scan_mode(st);
1250 }
1251
1252 static int __devinit max1363_probe(struct i2c_client *client,
1253 const struct i2c_device_id *id)
1254 {
1255 int ret, i, regdone = 0;
1256 struct max1363_state *st;
1257 struct iio_dev *indio_dev;
1258 struct regulator *reg;
1259
1260 reg = regulator_get(&client->dev, "vcc");
1261 if (IS_ERR(reg)) {
1262 ret = PTR_ERR(reg);
1263 goto error_out;
1264 }
1265
1266 ret = regulator_enable(reg);
1267 if (ret)
1268 goto error_put_reg;
1269
1270 indio_dev = iio_allocate_device(sizeof(struct max1363_state));
1271 if (indio_dev == NULL) {
1272 ret = -ENOMEM;
1273 goto error_disable_reg;
1274 }
1275 st = iio_priv(indio_dev);
1276 st->reg = reg;
1277 /* this is only used for device removal purposes */
1278 i2c_set_clientdata(client, indio_dev);
1279
1280 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1281 st->client = client;
1282
1283 indio_dev->available_scan_masks
1284 = kzalloc(sizeof(*indio_dev->available_scan_masks)*
1285 (st->chip_info->num_modes + 1), GFP_KERNEL);
1286 if (!indio_dev->available_scan_masks) {
1287 ret = -ENOMEM;
1288 goto error_free_device;
1289 }
1290
1291 for (i = 0; i < st->chip_info->num_modes; i++)
1292 indio_dev->available_scan_masks[i] =
1293 max1363_mode_table[st->chip_info->mode_list[i]]
1294 .modemask;
1295 /* Estabilish that the iio_dev is a child of the i2c device */
1296 indio_dev->dev.parent = &client->dev;
1297 indio_dev->name = id->name;
1298 indio_dev->channels = st->chip_info->channels;
1299 indio_dev->num_channels = st->chip_info->num_channels;
1300 indio_dev->info = st->chip_info->info;
1301 indio_dev->modes = INDIO_DIRECT_MODE;
1302 indio_dev->channels = st->chip_info->channels;
1303 indio_dev->num_channels = st->chip_info->num_channels;
1304 ret = max1363_initial_setup(st);
1305 if (ret < 0)
1306 goto error_free_available_scan_masks;
1307
1308 ret = max1363_register_ring_funcs_and_init(indio_dev);
1309 if (ret)
1310 goto error_free_available_scan_masks;
1311
1312 ret = iio_device_register(indio_dev);
1313 if (ret)
1314 goto error_cleanup_ring;
1315 regdone = 1;
1316 ret = iio_ring_buffer_register(indio_dev,
1317 st->chip_info->channels,
1318 st->chip_info->num_channels);
1319 if (ret)
1320 goto error_cleanup_ring;
1321
1322 if (client->irq) {
1323 ret = request_threaded_irq(st->client->irq,
1324 NULL,
1325 &max1363_event_handler,
1326 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1327 "max1363_event",
1328 indio_dev);
1329
1330 if (ret)
1331 goto error_uninit_ring;
1332 }
1333
1334 return 0;
1335
1336 error_uninit_ring:
1337 iio_ring_buffer_unregister(indio_dev);
1338 error_cleanup_ring:
1339 max1363_ring_cleanup(indio_dev);
1340 error_free_available_scan_masks:
1341 kfree(indio_dev->available_scan_masks);
1342 error_free_device:
1343 if (!regdone)
1344 iio_free_device(indio_dev);
1345 else
1346 iio_device_unregister(indio_dev);
1347 error_disable_reg:
1348 regulator_disable(reg);
1349 error_put_reg:
1350 regulator_put(reg);
1351 error_out:
1352 return ret;
1353 }
1354
1355 static int max1363_remove(struct i2c_client *client)
1356 {
1357 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1358 struct max1363_state *st = iio_priv(indio_dev);
1359 struct regulator *reg = st->reg;
1360
1361 if (client->irq)
1362 free_irq(st->client->irq, indio_dev);
1363 iio_ring_buffer_unregister(indio_dev);
1364 max1363_ring_cleanup(indio_dev);
1365 kfree(indio_dev->available_scan_masks);
1366 if (!IS_ERR(reg)) {
1367 regulator_disable(reg);
1368 regulator_put(reg);
1369 }
1370 iio_device_unregister(indio_dev);
1371
1372 return 0;
1373 }
1374
1375 static const struct i2c_device_id max1363_id[] = {
1376 { "max1361", max1361 },
1377 { "max1362", max1362 },
1378 { "max1363", max1363 },
1379 { "max1364", max1364 },
1380 { "max1036", max1036 },
1381 { "max1037", max1037 },
1382 { "max1038", max1038 },
1383 { "max1039", max1039 },
1384 { "max1136", max1136 },
1385 { "max1137", max1137 },
1386 { "max1138", max1138 },
1387 { "max1139", max1139 },
1388 { "max1236", max1236 },
1389 { "max1237", max1237 },
1390 { "max1238", max1238 },
1391 { "max1239", max1239 },
1392 { "max11600", max11600 },
1393 { "max11601", max11601 },
1394 { "max11602", max11602 },
1395 { "max11603", max11603 },
1396 { "max11604", max11604 },
1397 { "max11605", max11605 },
1398 { "max11606", max11606 },
1399 { "max11607", max11607 },
1400 { "max11608", max11608 },
1401 { "max11609", max11609 },
1402 { "max11610", max11610 },
1403 { "max11611", max11611 },
1404 { "max11612", max11612 },
1405 { "max11613", max11613 },
1406 { "max11614", max11614 },
1407 { "max11615", max11615 },
1408 { "max11616", max11616 },
1409 { "max11617", max11617 },
1410 {}
1411 };
1412
1413 MODULE_DEVICE_TABLE(i2c, max1363_id);
1414
1415 static struct i2c_driver max1363_driver = {
1416 .driver = {
1417 .name = "max1363",
1418 },
1419 .probe = max1363_probe,
1420 .remove = max1363_remove,
1421 .id_table = max1363_id,
1422 };
1423
1424 static __init int max1363_init(void)
1425 {
1426 return i2c_add_driver(&max1363_driver);
1427 }
1428
1429 static __exit void max1363_exit(void)
1430 {
1431 i2c_del_driver(&max1363_driver);
1432 }
1433
1434 MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
1435 MODULE_DESCRIPTION("Maxim 1363 ADC");
1436 MODULE_LICENSE("GPL v2");
1437
1438 module_init(max1363_init);
1439 module_exit(max1363_exit);
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