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iio: mxs-lradc: make ADC reads not disable touchscreen interrupts
[mirror_ubuntu-bionic-kernel.git] / drivers / staging / iio / adc / mxs-lradc.c
1 /*
2 * Freescale i.MX28 LRADC driver
3 *
4 * Copyright (c) 2012 DENX Software Engineering, GmbH.
5 * Marek Vasut <marex@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/device.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/sysfs.h>
26 #include <linux/list.h>
27 #include <linux/io.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/spinlock.h>
31 #include <linux/wait.h>
32 #include <linux/sched.h>
33 #include <linux/stmp_device.h>
34 #include <linux/bitops.h>
35 #include <linux/completion.h>
36 #include <linux/delay.h>
37 #include <linux/input.h>
38 #include <linux/clk.h>
39
40 #include <linux/iio/iio.h>
41 #include <linux/iio/sysfs.h>
42 #include <linux/iio/buffer.h>
43 #include <linux/iio/trigger.h>
44 #include <linux/iio/trigger_consumer.h>
45 #include <linux/iio/triggered_buffer.h>
46
47 #define DRIVER_NAME "mxs-lradc"
48
49 #define LRADC_MAX_DELAY_CHANS 4
50 #define LRADC_MAX_MAPPED_CHANS 8
51 #define LRADC_MAX_TOTAL_CHANS 16
52
53 #define LRADC_DELAY_TIMER_HZ 2000
54
55 /*
56 * Make this runtime configurable if necessary. Currently, if the buffered mode
57 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
58 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
59 * seconds. The result is that the samples arrive every 500mS.
60 */
61 #define LRADC_DELAY_TIMER_PER 200
62 #define LRADC_DELAY_TIMER_LOOP 5
63
64 /*
65 * Once the pen touches the touchscreen, the touchscreen switches from
66 * IRQ-driven mode to polling mode to prevent interrupt storm. The polling
67 * is realized by worker thread, which is called every 20 or so milliseconds.
68 * This gives the touchscreen enough fluence and does not strain the system
69 * too much.
70 */
71 #define LRADC_TS_SAMPLE_DELAY_MS 5
72
73 /*
74 * The LRADC reads the following amount of samples from each touchscreen
75 * channel and the driver then computes avarage of these.
76 */
77 #define LRADC_TS_SAMPLE_AMOUNT 4
78
79 enum mxs_lradc_id {
80 IMX23_LRADC,
81 IMX28_LRADC,
82 };
83
84 static const char * const mx23_lradc_irq_names[] = {
85 "mxs-lradc-touchscreen",
86 "mxs-lradc-channel0",
87 "mxs-lradc-channel1",
88 "mxs-lradc-channel2",
89 "mxs-lradc-channel3",
90 "mxs-lradc-channel4",
91 "mxs-lradc-channel5",
92 "mxs-lradc-channel6",
93 "mxs-lradc-channel7",
94 };
95
96 static const char * const mx28_lradc_irq_names[] = {
97 "mxs-lradc-touchscreen",
98 "mxs-lradc-thresh0",
99 "mxs-lradc-thresh1",
100 "mxs-lradc-channel0",
101 "mxs-lradc-channel1",
102 "mxs-lradc-channel2",
103 "mxs-lradc-channel3",
104 "mxs-lradc-channel4",
105 "mxs-lradc-channel5",
106 "mxs-lradc-channel6",
107 "mxs-lradc-channel7",
108 "mxs-lradc-button0",
109 "mxs-lradc-button1",
110 };
111
112 struct mxs_lradc_of_config {
113 const int irq_count;
114 const char * const *irq_name;
115 const uint32_t *vref_mv;
116 };
117
118 #define VREF_MV_BASE 1850
119
120 static const uint32_t mx23_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
121 VREF_MV_BASE, /* CH0 */
122 VREF_MV_BASE, /* CH1 */
123 VREF_MV_BASE, /* CH2 */
124 VREF_MV_BASE, /* CH3 */
125 VREF_MV_BASE, /* CH4 */
126 VREF_MV_BASE, /* CH5 */
127 VREF_MV_BASE * 2, /* CH6 VDDIO */
128 VREF_MV_BASE * 4, /* CH7 VBATT */
129 VREF_MV_BASE, /* CH8 Temp sense 0 */
130 VREF_MV_BASE, /* CH9 Temp sense 1 */
131 VREF_MV_BASE, /* CH10 */
132 VREF_MV_BASE, /* CH11 */
133 VREF_MV_BASE, /* CH12 USB_DP */
134 VREF_MV_BASE, /* CH13 USB_DN */
135 VREF_MV_BASE, /* CH14 VBG */
136 VREF_MV_BASE * 4, /* CH15 VDD5V */
137 };
138
139 static const uint32_t mx28_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
140 VREF_MV_BASE, /* CH0 */
141 VREF_MV_BASE, /* CH1 */
142 VREF_MV_BASE, /* CH2 */
143 VREF_MV_BASE, /* CH3 */
144 VREF_MV_BASE, /* CH4 */
145 VREF_MV_BASE, /* CH5 */
146 VREF_MV_BASE, /* CH6 */
147 VREF_MV_BASE * 4, /* CH7 VBATT */
148 VREF_MV_BASE, /* CH8 Temp sense 0 */
149 VREF_MV_BASE, /* CH9 Temp sense 1 */
150 VREF_MV_BASE * 2, /* CH10 VDDIO */
151 VREF_MV_BASE, /* CH11 VTH */
152 VREF_MV_BASE * 2, /* CH12 VDDA */
153 VREF_MV_BASE, /* CH13 VDDD */
154 VREF_MV_BASE, /* CH14 VBG */
155 VREF_MV_BASE * 4, /* CH15 VDD5V */
156 };
157
158 static const struct mxs_lradc_of_config mxs_lradc_of_config[] = {
159 [IMX23_LRADC] = {
160 .irq_count = ARRAY_SIZE(mx23_lradc_irq_names),
161 .irq_name = mx23_lradc_irq_names,
162 .vref_mv = mx23_vref_mv,
163 },
164 [IMX28_LRADC] = {
165 .irq_count = ARRAY_SIZE(mx28_lradc_irq_names),
166 .irq_name = mx28_lradc_irq_names,
167 .vref_mv = mx28_vref_mv,
168 },
169 };
170
171 enum mxs_lradc_ts {
172 MXS_LRADC_TOUCHSCREEN_NONE = 0,
173 MXS_LRADC_TOUCHSCREEN_4WIRE,
174 MXS_LRADC_TOUCHSCREEN_5WIRE,
175 };
176
177 /*
178 * Touchscreen handling
179 */
180 enum lradc_ts_plate {
181 LRADC_TOUCH = 0,
182 LRADC_SAMPLE_X,
183 LRADC_SAMPLE_Y,
184 LRADC_SAMPLE_PRESSURE,
185 LRADC_SAMPLE_VALID,
186 };
187
188 enum mxs_lradc_divbytwo {
189 MXS_LRADC_DIV_DISABLED = 0,
190 MXS_LRADC_DIV_ENABLED,
191 };
192
193 struct mxs_lradc_scale {
194 unsigned int integer;
195 unsigned int nano;
196 };
197
198 struct mxs_lradc {
199 struct device *dev;
200 void __iomem *base;
201 int irq[13];
202
203 struct clk *clk;
204
205 uint32_t *buffer;
206 struct iio_trigger *trig;
207
208 struct mutex lock;
209
210 struct completion completion;
211
212 const uint32_t *vref_mv;
213 struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
214 unsigned long is_divided;
215
216 /*
217 * When the touchscreen is enabled, we give it two private virtual
218 * channels: #6 and #7. This means that only 6 virtual channels (instead
219 * of 8) will be available for buffered capture.
220 */
221 #define TOUCHSCREEN_VCHANNEL1 7
222 #define TOUCHSCREEN_VCHANNEL2 6
223 #define BUFFER_VCHANS_LIMITED 0x3f
224 #define BUFFER_VCHANS_ALL 0xff
225 u8 buffer_vchans;
226
227 /*
228 * Furthermore, certain LRADC channels are shared between touchscreen
229 * and/or touch-buttons and generic LRADC block. Therefore when using
230 * either of these, these channels are not available for the regular
231 * sampling. The shared channels are as follows:
232 *
233 * CH0 -- Touch button #0
234 * CH1 -- Touch button #1
235 * CH2 -- Touch screen XPUL
236 * CH3 -- Touch screen YPLL
237 * CH4 -- Touch screen XNUL
238 * CH5 -- Touch screen YNLR
239 * CH6 -- Touch screen WIPER (5-wire only)
240 *
241 * The bitfields below represents which parts of the LRADC block are
242 * switched into special mode of operation. These channels can not
243 * be sampled as regular LRADC channels. The driver will refuse any
244 * attempt to sample these channels.
245 */
246 #define CHAN_MASK_TOUCHBUTTON (0x3 << 0)
247 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 2)
248 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 2)
249 enum mxs_lradc_ts use_touchscreen;
250 bool use_touchbutton;
251
252 struct input_dev *ts_input;
253
254 enum mxs_lradc_id soc;
255 enum lradc_ts_plate cur_plate; /* statemachine */
256 bool ts_valid;
257 unsigned ts_x_pos;
258 unsigned ts_y_pos;
259 unsigned ts_pressure;
260
261 /* handle touchscreen's physical behaviour */
262 /* samples per coordinate */
263 unsigned over_sample_cnt;
264 /* time clocks between samples */
265 unsigned over_sample_delay;
266 /* time in clocks to wait after the plates where switched */
267 unsigned settling_delay;
268 };
269
270 #define LRADC_CTRL0 0x00
271 # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE (1 << 23)
272 # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE (1 << 22)
273 # define LRADC_CTRL0_MX28_YNNSW /* YM */ (1 << 21)
274 # define LRADC_CTRL0_MX28_YPNSW /* YP */ (1 << 20)
275 # define LRADC_CTRL0_MX28_YPPSW /* YP */ (1 << 19)
276 # define LRADC_CTRL0_MX28_XNNSW /* XM */ (1 << 18)
277 # define LRADC_CTRL0_MX28_XNPSW /* XM */ (1 << 17)
278 # define LRADC_CTRL0_MX28_XPPSW /* XP */ (1 << 16)
279
280 # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE (1 << 20)
281 # define LRADC_CTRL0_MX23_YM (1 << 19)
282 # define LRADC_CTRL0_MX23_XM (1 << 18)
283 # define LRADC_CTRL0_MX23_YP (1 << 17)
284 # define LRADC_CTRL0_MX23_XP (1 << 16)
285
286 # define LRADC_CTRL0_MX28_PLATE_MASK \
287 (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \
288 LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \
289 LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \
290 LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW)
291
292 # define LRADC_CTRL0_MX23_PLATE_MASK \
293 (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \
294 LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \
295 LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP)
296
297 #define LRADC_CTRL1 0x10
298 #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24)
299 #define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16))
300 #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK (0x1fff << 16)
301 #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK (0x01ff << 16)
302 #define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET 16
303 #define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8)
304 #define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n))
305 #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff
306 #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK 0x01ff
307 #define LRADC_CTRL1_LRADC_IRQ_OFFSET 0
308
309 #define LRADC_CTRL2 0x20
310 #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24
311 #define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15)
312
313 #define LRADC_STATUS 0x40
314 #define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0)
315
316 #define LRADC_CH(n) (0x50 + (0x10 * (n)))
317 #define LRADC_CH_ACCUMULATE (1 << 29)
318 #define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
319 #define LRADC_CH_NUM_SAMPLES_OFFSET 24
320 #define LRADC_CH_NUM_SAMPLES(x) \
321 ((x) << LRADC_CH_NUM_SAMPLES_OFFSET)
322 #define LRADC_CH_VALUE_MASK 0x3ffff
323 #define LRADC_CH_VALUE_OFFSET 0
324
325 #define LRADC_DELAY(n) (0xd0 + (0x10 * (n)))
326 #define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24)
327 #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
328 #define LRADC_DELAY_TRIGGER(x) \
329 (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \
330 LRADC_DELAY_TRIGGER_LRADCS_MASK)
331 #define LRADC_DELAY_KICK (1 << 20)
332 #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
333 #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
334 #define LRADC_DELAY_TRIGGER_DELAYS(x) \
335 (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \
336 LRADC_DELAY_TRIGGER_DELAYS_MASK)
337 #define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
338 #define LRADC_DELAY_LOOP_COUNT_OFFSET 11
339 #define LRADC_DELAY_LOOP(x) \
340 (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \
341 LRADC_DELAY_LOOP_COUNT_MASK)
342 #define LRADC_DELAY_DELAY_MASK 0x7ff
343 #define LRADC_DELAY_DELAY_OFFSET 0
344 #define LRADC_DELAY_DELAY(x) \
345 (((x) << LRADC_DELAY_DELAY_OFFSET) & \
346 LRADC_DELAY_DELAY_MASK)
347
348 #define LRADC_CTRL4 0x140
349 #define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4))
350 #define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4)
351 #define LRADC_CTRL4_LRADCSELECT(n, x) \
352 (((x) << LRADC_CTRL4_LRADCSELECT_OFFSET(n)) & \
353 LRADC_CTRL4_LRADCSELECT_MASK(n))
354
355 #define LRADC_RESOLUTION 12
356 #define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1)
357
358 static void mxs_lradc_reg_set(struct mxs_lradc *lradc, u32 val, u32 reg)
359 {
360 writel(val, lradc->base + reg + STMP_OFFSET_REG_SET);
361 }
362
363 static void mxs_lradc_reg_clear(struct mxs_lradc *lradc, u32 val, u32 reg)
364 {
365 writel(val, lradc->base + reg + STMP_OFFSET_REG_CLR);
366 }
367
368 static void mxs_lradc_reg_wrt(struct mxs_lradc *lradc, u32 val, u32 reg)
369 {
370 writel(val, lradc->base + reg);
371 }
372
373 static u32 mxs_lradc_plate_mask(struct mxs_lradc *lradc)
374 {
375 if (lradc->soc == IMX23_LRADC)
376 return LRADC_CTRL0_MX23_PLATE_MASK;
377 return LRADC_CTRL0_MX28_PLATE_MASK;
378 }
379
380 static u32 mxs_lradc_irq_en_mask(struct mxs_lradc *lradc)
381 {
382 if (lradc->soc == IMX23_LRADC)
383 return LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK;
384 return LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK;
385 }
386
387 static u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc)
388 {
389 if (lradc->soc == IMX23_LRADC)
390 return LRADC_CTRL1_MX23_LRADC_IRQ_MASK;
391 return LRADC_CTRL1_MX28_LRADC_IRQ_MASK;
392 }
393
394 static u32 mxs_lradc_touch_detect_bit(struct mxs_lradc *lradc)
395 {
396 if (lradc->soc == IMX23_LRADC)
397 return LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE;
398 return LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE;
399 }
400
401 static u32 mxs_lradc_drive_x_plate(struct mxs_lradc *lradc)
402 {
403 if (lradc->soc == IMX23_LRADC)
404 return LRADC_CTRL0_MX23_XP | LRADC_CTRL0_MX23_XM;
405 return LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW;
406 }
407
408 static u32 mxs_lradc_drive_y_plate(struct mxs_lradc *lradc)
409 {
410 if (lradc->soc == IMX23_LRADC)
411 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_YM;
412 return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW;
413 }
414
415 static u32 mxs_lradc_drive_pressure(struct mxs_lradc *lradc)
416 {
417 if (lradc->soc == IMX23_LRADC)
418 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XM;
419 return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW;
420 }
421
422 static bool mxs_lradc_check_touch_event(struct mxs_lradc *lradc)
423 {
424 return !!(readl(lradc->base + LRADC_STATUS) &
425 LRADC_STATUS_TOUCH_DETECT_RAW);
426 }
427
428 static void mxs_lradc_map_channel(struct mxs_lradc *lradc, unsigned vch,
429 unsigned ch)
430 {
431 mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(vch),
432 LRADC_CTRL4);
433 mxs_lradc_reg_set(lradc, LRADC_CTRL4_LRADCSELECT(vch, ch), LRADC_CTRL4);
434 }
435
436 static void mxs_lradc_setup_ts_channel(struct mxs_lradc *lradc, unsigned ch)
437 {
438 /*
439 * prepare for oversampling conversion
440 *
441 * from the datasheet:
442 * "The ACCUMULATE bit in the appropriate channel register
443 * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
444 * otherwise, the IRQs will not fire."
445 */
446 mxs_lradc_reg_wrt(lradc, LRADC_CH_ACCUMULATE |
447 LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1),
448 LRADC_CH(ch));
449
450 /* from the datasheet:
451 * "Software must clear this register in preparation for a
452 * multi-cycle accumulation.
453 */
454 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch));
455
456 /* prepare the delay/loop unit according to the oversampling count */
457 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch) |
458 LRADC_DELAY_TRIGGER_DELAYS(0) |
459 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
460 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
461 LRADC_DELAY(3));
462
463 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(ch), LRADC_CTRL1);
464
465 /*
466 * after changing the touchscreen plates setting
467 * the signals need some initial time to settle. Start the
468 * SoC's delay unit and start the conversion later
469 * and automatically.
470 */
471 mxs_lradc_reg_wrt(lradc,
472 LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
473 LRADC_DELAY_TRIGGER_DELAYS(1 << 3) | /* trigger DELAY unit#3 */
474 LRADC_DELAY_KICK |
475 LRADC_DELAY_DELAY(lradc->settling_delay),
476 LRADC_DELAY(2));
477 }
478
479 /*
480 * Pressure detection is special:
481 * We want to do both required measurements for the pressure detection in
482 * one turn. Use the hardware features to chain both conversions and let the
483 * hardware report one interrupt if both conversions are done
484 */
485 static void mxs_lradc_setup_ts_pressure(struct mxs_lradc *lradc, unsigned ch1,
486 unsigned ch2)
487 {
488 u32 reg;
489
490 /*
491 * prepare for oversampling conversion
492 *
493 * from the datasheet:
494 * "The ACCUMULATE bit in the appropriate channel register
495 * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
496 * otherwise, the IRQs will not fire."
497 */
498 reg = LRADC_CH_ACCUMULATE |
499 LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1);
500 mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch1));
501 mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch2));
502
503 /* from the datasheet:
504 * "Software must clear this register in preparation for a
505 * multi-cycle accumulation.
506 */
507 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch1));
508 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch2));
509
510 /* prepare the delay/loop unit according to the oversampling count */
511 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch1) |
512 LRADC_DELAY_TRIGGER(1 << ch2) | /* start both channels */
513 LRADC_DELAY_TRIGGER_DELAYS(0) |
514 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
515 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
516 LRADC_DELAY(3));
517
518 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(ch2), LRADC_CTRL1);
519
520 /*
521 * after changing the touchscreen plates setting
522 * the signals need some initial time to settle. Start the
523 * SoC's delay unit and start the conversion later
524 * and automatically.
525 */
526 mxs_lradc_reg_wrt(lradc,
527 LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
528 LRADC_DELAY_TRIGGER_DELAYS(1 << 3) | /* trigger DELAY unit#3 */
529 LRADC_DELAY_KICK |
530 LRADC_DELAY_DELAY(lradc->settling_delay), LRADC_DELAY(2));
531 }
532
533 static unsigned mxs_lradc_read_raw_channel(struct mxs_lradc *lradc,
534 unsigned channel)
535 {
536 u32 reg;
537 unsigned num_samples, val;
538
539 reg = readl(lradc->base + LRADC_CH(channel));
540 if (reg & LRADC_CH_ACCUMULATE)
541 num_samples = lradc->over_sample_cnt;
542 else
543 num_samples = 1;
544
545 val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET;
546 return val / num_samples;
547 }
548
549 static unsigned mxs_lradc_read_ts_pressure(struct mxs_lradc *lradc,
550 unsigned ch1, unsigned ch2)
551 {
552 u32 reg, mask;
553 unsigned pressure, m1, m2;
554
555 mask = LRADC_CTRL1_LRADC_IRQ(ch1) | LRADC_CTRL1_LRADC_IRQ(ch2);
556 reg = readl(lradc->base + LRADC_CTRL1) & mask;
557
558 while (reg != mask) {
559 reg = readl(lradc->base + LRADC_CTRL1) & mask;
560 dev_dbg(lradc->dev, "One channel is still busy: %X\n", reg);
561 }
562
563 m1 = mxs_lradc_read_raw_channel(lradc, ch1);
564 m2 = mxs_lradc_read_raw_channel(lradc, ch2);
565
566 if (m2 == 0) {
567 dev_warn(lradc->dev, "Cannot calculate pressure\n");
568 return 1 << (LRADC_RESOLUTION - 1);
569 }
570
571 /* simply scale the value from 0 ... max ADC resolution */
572 pressure = m1;
573 pressure *= (1 << LRADC_RESOLUTION);
574 pressure /= m2;
575
576 dev_dbg(lradc->dev, "Pressure = %u\n", pressure);
577 return pressure;
578 }
579
580 #define TS_CH_XP 2
581 #define TS_CH_YP 3
582 #define TS_CH_XM 4
583 #define TS_CH_YM 5
584
585 /*
586 * YP(open)--+-------------+
587 * | |--+
588 * | | |
589 * YM(-)--+-------------+ |
590 * +--------------+
591 * | |
592 * XP(weak+) XM(open)
593 *
594 * "weak+" means 200k Ohm VDDIO
595 * (-) means GND
596 */
597 static void mxs_lradc_setup_touch_detection(struct mxs_lradc *lradc)
598 {
599 /*
600 * In order to detect a touch event the 'touch detect enable' bit
601 * enables:
602 * - a weak pullup to the X+ connector
603 * - a strong ground at the Y- connector
604 */
605 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
606 mxs_lradc_reg_set(lradc, mxs_lradc_touch_detect_bit(lradc),
607 LRADC_CTRL0);
608 }
609
610 /*
611 * YP(meas)--+-------------+
612 * | |--+
613 * | | |
614 * YM(open)--+-------------+ |
615 * +--------------+
616 * | |
617 * XP(+) XM(-)
618 *
619 * (+) means here 1.85 V
620 * (-) means here GND
621 */
622 static void mxs_lradc_prepare_x_pos(struct mxs_lradc *lradc)
623 {
624 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
625 mxs_lradc_reg_set(lradc, mxs_lradc_drive_x_plate(lradc), LRADC_CTRL0);
626
627 lradc->cur_plate = LRADC_SAMPLE_X;
628 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_YP);
629 mxs_lradc_setup_ts_channel(lradc, TOUCHSCREEN_VCHANNEL1);
630 }
631
632 /*
633 * YP(+)--+-------------+
634 * | |--+
635 * | | |
636 * YM(-)--+-------------+ |
637 * +--------------+
638 * | |
639 * XP(open) XM(meas)
640 *
641 * (+) means here 1.85 V
642 * (-) means here GND
643 */
644 static void mxs_lradc_prepare_y_pos(struct mxs_lradc *lradc)
645 {
646 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
647 mxs_lradc_reg_set(lradc, mxs_lradc_drive_y_plate(lradc), LRADC_CTRL0);
648
649 lradc->cur_plate = LRADC_SAMPLE_Y;
650 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_XM);
651 mxs_lradc_setup_ts_channel(lradc, TOUCHSCREEN_VCHANNEL1);
652 }
653
654 /*
655 * YP(+)--+-------------+
656 * | |--+
657 * | | |
658 * YM(meas)--+-------------+ |
659 * +--------------+
660 * | |
661 * XP(meas) XM(-)
662 *
663 * (+) means here 1.85 V
664 * (-) means here GND
665 */
666 static void mxs_lradc_prepare_pressure(struct mxs_lradc *lradc)
667 {
668 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
669 mxs_lradc_reg_set(lradc, mxs_lradc_drive_pressure(lradc), LRADC_CTRL0);
670
671 lradc->cur_plate = LRADC_SAMPLE_PRESSURE;
672 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_YM);
673 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL2, TS_CH_XP);
674 mxs_lradc_setup_ts_pressure(lradc, TOUCHSCREEN_VCHANNEL2,
675 TOUCHSCREEN_VCHANNEL1);
676 }
677
678 static void mxs_lradc_enable_touch_detection(struct mxs_lradc *lradc)
679 {
680 mxs_lradc_setup_touch_detection(lradc);
681
682 lradc->cur_plate = LRADC_TOUCH;
683 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ |
684 LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
685 mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
686 }
687
688 static void mxs_lradc_start_touch_event(struct mxs_lradc *lradc)
689 {
690 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
691 LRADC_CTRL1);
692 mxs_lradc_reg_set(lradc,
693 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1), LRADC_CTRL1);
694 /*
695 * start with the Y-pos, because it uses nearly the same plate
696 * settings like the touch detection
697 */
698 mxs_lradc_prepare_y_pos(lradc);
699 }
700
701 static void mxs_lradc_report_ts_event(struct mxs_lradc *lradc)
702 {
703 input_report_abs(lradc->ts_input, ABS_X, lradc->ts_x_pos);
704 input_report_abs(lradc->ts_input, ABS_Y, lradc->ts_y_pos);
705 input_report_abs(lradc->ts_input, ABS_PRESSURE, lradc->ts_pressure);
706 input_report_key(lradc->ts_input, BTN_TOUCH, 1);
707 input_sync(lradc->ts_input);
708 }
709
710 static void mxs_lradc_complete_touch_event(struct mxs_lradc *lradc)
711 {
712 mxs_lradc_setup_touch_detection(lradc);
713 lradc->cur_plate = LRADC_SAMPLE_VALID;
714 /*
715 * start a dummy conversion to burn time to settle the signals
716 * note: we are not interested in the conversion's value
717 */
718 mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(TOUCHSCREEN_VCHANNEL1));
719 mxs_lradc_reg_clear(lradc,
720 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
721 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2), LRADC_CTRL1);
722 mxs_lradc_reg_wrt(lradc,
723 LRADC_DELAY_TRIGGER(1 << TOUCHSCREEN_VCHANNEL1) |
724 LRADC_DELAY_KICK | LRADC_DELAY_DELAY(10), /* waste 5 ms */
725 LRADC_DELAY(2));
726 }
727
728 /*
729 * in order to avoid false measurements, report only samples where
730 * the surface is still touched after the position measurement
731 */
732 static void mxs_lradc_finish_touch_event(struct mxs_lradc *lradc, bool valid)
733 {
734 /* if it is still touched, report the sample */
735 if (valid && mxs_lradc_check_touch_event(lradc)) {
736 lradc->ts_valid = true;
737 mxs_lradc_report_ts_event(lradc);
738 }
739
740 /* if it is even still touched, continue with the next measurement */
741 if (mxs_lradc_check_touch_event(lradc)) {
742 mxs_lradc_prepare_y_pos(lradc);
743 return;
744 }
745
746 if (lradc->ts_valid) {
747 /* signal the release */
748 lradc->ts_valid = false;
749 input_report_key(lradc->ts_input, BTN_TOUCH, 0);
750 input_sync(lradc->ts_input);
751 }
752
753 /* if it is released, wait for the next touch via IRQ */
754 lradc->cur_plate = LRADC_TOUCH;
755 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
756 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
757 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ |
758 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) |
759 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1), LRADC_CTRL1);
760 mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
761 }
762
763 /* touchscreen's state machine */
764 static void mxs_lradc_handle_touch(struct mxs_lradc *lradc)
765 {
766 switch (lradc->cur_plate) {
767 case LRADC_TOUCH:
768 if (mxs_lradc_check_touch_event(lradc))
769 mxs_lradc_start_touch_event(lradc);
770 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ,
771 LRADC_CTRL1);
772 return;
773
774 case LRADC_SAMPLE_Y:
775 lradc->ts_y_pos = mxs_lradc_read_raw_channel(lradc,
776 TOUCHSCREEN_VCHANNEL1);
777 mxs_lradc_prepare_x_pos(lradc);
778 return;
779
780 case LRADC_SAMPLE_X:
781 lradc->ts_x_pos = mxs_lradc_read_raw_channel(lradc,
782 TOUCHSCREEN_VCHANNEL1);
783 mxs_lradc_prepare_pressure(lradc);
784 return;
785
786 case LRADC_SAMPLE_PRESSURE:
787 lradc->ts_pressure = mxs_lradc_read_ts_pressure(lradc,
788 TOUCHSCREEN_VCHANNEL2,
789 TOUCHSCREEN_VCHANNEL1);
790 mxs_lradc_complete_touch_event(lradc);
791 return;
792
793 case LRADC_SAMPLE_VALID:
794 mxs_lradc_finish_touch_event(lradc, 1);
795 break;
796 }
797 }
798
799 /*
800 * Raw I/O operations
801 */
802 static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val)
803 {
804 struct mxs_lradc *lradc = iio_priv(iio_dev);
805 int ret;
806
807 /*
808 * See if there is no buffered operation in progess. If there is, simply
809 * bail out. This can be improved to support both buffered and raw IO at
810 * the same time, yet the code becomes horribly complicated. Therefore I
811 * applied KISS principle here.
812 */
813 ret = mutex_trylock(&lradc->lock);
814 if (!ret)
815 return -EBUSY;
816
817 reinit_completion(&lradc->completion);
818
819 /*
820 * No buffered operation in progress, map the channel and trigger it.
821 * Virtual channel 0 is always used here as the others are always not
822 * used if doing raw sampling.
823 */
824 if (lradc->soc == IMX28_LRADC)
825 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0),
826 LRADC_CTRL1);
827 mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
828
829 /* Enable / disable the divider per requirement */
830 if (test_bit(chan, &lradc->is_divided))
831 mxs_lradc_reg_set(lradc, 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
832 LRADC_CTRL2);
833 else
834 mxs_lradc_reg_clear(lradc,
835 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, LRADC_CTRL2);
836
837 /* Clean the slot's previous content, then set new one. */
838 mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0),
839 LRADC_CTRL4);
840 mxs_lradc_reg_set(lradc, chan, LRADC_CTRL4);
841
842 mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(0));
843
844 /* Enable the IRQ and start sampling the channel. */
845 mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
846 mxs_lradc_reg_set(lradc, 1 << 0, LRADC_CTRL0);
847
848 /* Wait for completion on the channel, 1 second max. */
849 ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
850 if (!ret)
851 ret = -ETIMEDOUT;
852 if (ret < 0)
853 goto err;
854
855 /* Read the data. */
856 *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
857 ret = IIO_VAL_INT;
858
859 err:
860 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
861
862 mutex_unlock(&lradc->lock);
863
864 return ret;
865 }
866
867 static int mxs_lradc_read_temp(struct iio_dev *iio_dev, int *val)
868 {
869 int ret, min, max;
870
871 ret = mxs_lradc_read_single(iio_dev, 8, &min);
872 if (ret != IIO_VAL_INT)
873 return ret;
874
875 ret = mxs_lradc_read_single(iio_dev, 9, &max);
876 if (ret != IIO_VAL_INT)
877 return ret;
878
879 *val = max - min;
880
881 return IIO_VAL_INT;
882 }
883
884 static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
885 const struct iio_chan_spec *chan,
886 int *val, int *val2, long m)
887 {
888 struct mxs_lradc *lradc = iio_priv(iio_dev);
889
890 switch (m) {
891 case IIO_CHAN_INFO_RAW:
892 if (chan->type == IIO_TEMP)
893 return mxs_lradc_read_temp(iio_dev, val);
894
895 return mxs_lradc_read_single(iio_dev, chan->channel, val);
896
897 case IIO_CHAN_INFO_SCALE:
898 if (chan->type == IIO_TEMP) {
899 /* From the datasheet, we have to multiply by 1.012 and
900 * divide by 4
901 */
902 *val = 0;
903 *val2 = 253000;
904 return IIO_VAL_INT_PLUS_MICRO;
905 }
906
907 *val = lradc->vref_mv[chan->channel];
908 *val2 = chan->scan_type.realbits -
909 test_bit(chan->channel, &lradc->is_divided);
910 return IIO_VAL_FRACTIONAL_LOG2;
911
912 case IIO_CHAN_INFO_OFFSET:
913 if (chan->type == IIO_TEMP) {
914 /* The calculated value from the ADC is in Kelvin, we
915 * want Celsius for hwmon so the offset is
916 * -272.15 * scale
917 */
918 *val = -1075;
919 *val2 = 691699;
920
921 return IIO_VAL_INT_PLUS_MICRO;
922 }
923
924 return -EINVAL;
925
926 default:
927 break;
928 }
929
930 return -EINVAL;
931 }
932
933 static int mxs_lradc_write_raw(struct iio_dev *iio_dev,
934 const struct iio_chan_spec *chan,
935 int val, int val2, long m)
936 {
937 struct mxs_lradc *lradc = iio_priv(iio_dev);
938 struct mxs_lradc_scale *scale_avail =
939 lradc->scale_avail[chan->channel];
940 int ret;
941
942 ret = mutex_trylock(&lradc->lock);
943 if (!ret)
944 return -EBUSY;
945
946 switch (m) {
947 case IIO_CHAN_INFO_SCALE:
948 ret = -EINVAL;
949 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
950 val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
951 /* divider by two disabled */
952 clear_bit(chan->channel, &lradc->is_divided);
953 ret = 0;
954 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
955 val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
956 /* divider by two enabled */
957 set_bit(chan->channel, &lradc->is_divided);
958 ret = 0;
959 }
960
961 break;
962 default:
963 ret = -EINVAL;
964 break;
965 }
966
967 mutex_unlock(&lradc->lock);
968
969 return ret;
970 }
971
972 static int mxs_lradc_write_raw_get_fmt(struct iio_dev *iio_dev,
973 const struct iio_chan_spec *chan,
974 long m)
975 {
976 return IIO_VAL_INT_PLUS_NANO;
977 }
978
979 static ssize_t mxs_lradc_show_scale_available_ch(struct device *dev,
980 struct device_attribute *attr,
981 char *buf,
982 int ch)
983 {
984 struct iio_dev *iio = dev_to_iio_dev(dev);
985 struct mxs_lradc *lradc = iio_priv(iio);
986 int i, len = 0;
987
988 for (i = 0; i < ARRAY_SIZE(lradc->scale_avail[ch]); i++)
989 len += sprintf(buf + len, "%d.%09u ",
990 lradc->scale_avail[ch][i].integer,
991 lradc->scale_avail[ch][i].nano);
992
993 len += sprintf(buf + len, "\n");
994
995 return len;
996 }
997
998 static ssize_t mxs_lradc_show_scale_available(struct device *dev,
999 struct device_attribute *attr,
1000 char *buf)
1001 {
1002 struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
1003
1004 return mxs_lradc_show_scale_available_ch(dev, attr, buf,
1005 iio_attr->address);
1006 }
1007
1008 #define SHOW_SCALE_AVAILABLE_ATTR(ch) \
1009 static IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, S_IRUGO, \
1010 mxs_lradc_show_scale_available, NULL, ch)
1011
1012 SHOW_SCALE_AVAILABLE_ATTR(0);
1013 SHOW_SCALE_AVAILABLE_ATTR(1);
1014 SHOW_SCALE_AVAILABLE_ATTR(2);
1015 SHOW_SCALE_AVAILABLE_ATTR(3);
1016 SHOW_SCALE_AVAILABLE_ATTR(4);
1017 SHOW_SCALE_AVAILABLE_ATTR(5);
1018 SHOW_SCALE_AVAILABLE_ATTR(6);
1019 SHOW_SCALE_AVAILABLE_ATTR(7);
1020 SHOW_SCALE_AVAILABLE_ATTR(10);
1021 SHOW_SCALE_AVAILABLE_ATTR(11);
1022 SHOW_SCALE_AVAILABLE_ATTR(12);
1023 SHOW_SCALE_AVAILABLE_ATTR(13);
1024 SHOW_SCALE_AVAILABLE_ATTR(14);
1025 SHOW_SCALE_AVAILABLE_ATTR(15);
1026
1027 static struct attribute *mxs_lradc_attributes[] = {
1028 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
1029 &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
1030 &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
1031 &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
1032 &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
1033 &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
1034 &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
1035 &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
1036 &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
1037 &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
1038 &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
1039 &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
1040 &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
1041 &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
1042 NULL
1043 };
1044
1045 static const struct attribute_group mxs_lradc_attribute_group = {
1046 .attrs = mxs_lradc_attributes,
1047 };
1048
1049 static const struct iio_info mxs_lradc_iio_info = {
1050 .driver_module = THIS_MODULE,
1051 .read_raw = mxs_lradc_read_raw,
1052 .write_raw = mxs_lradc_write_raw,
1053 .write_raw_get_fmt = mxs_lradc_write_raw_get_fmt,
1054 .attrs = &mxs_lradc_attribute_group,
1055 };
1056
1057 static int mxs_lradc_ts_open(struct input_dev *dev)
1058 {
1059 struct mxs_lradc *lradc = input_get_drvdata(dev);
1060
1061 /* Enable the touch-detect circuitry. */
1062 mxs_lradc_enable_touch_detection(lradc);
1063
1064 return 0;
1065 }
1066
1067 static void mxs_lradc_disable_ts(struct mxs_lradc *lradc)
1068 {
1069 /* stop all interrupts from firing */
1070 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN |
1071 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) |
1072 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL2), LRADC_CTRL1);
1073
1074 /* Power-down touchscreen touch-detect circuitry. */
1075 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
1076 }
1077
1078 static void mxs_lradc_ts_close(struct input_dev *dev)
1079 {
1080 struct mxs_lradc *lradc = input_get_drvdata(dev);
1081
1082 mxs_lradc_disable_ts(lradc);
1083 }
1084
1085 static int mxs_lradc_ts_register(struct mxs_lradc *lradc)
1086 {
1087 struct input_dev *input;
1088 struct device *dev = lradc->dev;
1089 int ret;
1090
1091 if (!lradc->use_touchscreen)
1092 return 0;
1093
1094 input = input_allocate_device();
1095 if (!input)
1096 return -ENOMEM;
1097
1098 input->name = DRIVER_NAME;
1099 input->id.bustype = BUS_HOST;
1100 input->dev.parent = dev;
1101 input->open = mxs_lradc_ts_open;
1102 input->close = mxs_lradc_ts_close;
1103
1104 __set_bit(EV_ABS, input->evbit);
1105 __set_bit(EV_KEY, input->evbit);
1106 __set_bit(BTN_TOUCH, input->keybit);
1107 input_set_abs_params(input, ABS_X, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1108 input_set_abs_params(input, ABS_Y, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1109 input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_SINGLE_SAMPLE_MASK,
1110 0, 0);
1111
1112 lradc->ts_input = input;
1113 input_set_drvdata(input, lradc);
1114 ret = input_register_device(input);
1115 if (ret)
1116 input_free_device(lradc->ts_input);
1117
1118 return ret;
1119 }
1120
1121 static void mxs_lradc_ts_unregister(struct mxs_lradc *lradc)
1122 {
1123 if (!lradc->use_touchscreen)
1124 return;
1125
1126 mxs_lradc_disable_ts(lradc);
1127 input_unregister_device(lradc->ts_input);
1128 }
1129
1130 /*
1131 * IRQ Handling
1132 */
1133 static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
1134 {
1135 struct iio_dev *iio = data;
1136 struct mxs_lradc *lradc = iio_priv(iio);
1137 unsigned long reg = readl(lradc->base + LRADC_CTRL1);
1138 uint32_t clr_irq = mxs_lradc_irq_mask(lradc);
1139 const uint32_t ts_irq_mask =
1140 LRADC_CTRL1_TOUCH_DETECT_IRQ |
1141 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
1142 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2);
1143
1144 if (!(reg & mxs_lradc_irq_mask(lradc)))
1145 return IRQ_NONE;
1146
1147 if (lradc->use_touchscreen && (reg & ts_irq_mask)) {
1148 mxs_lradc_handle_touch(lradc);
1149
1150 /* Make sure we don't clear the next conversion's interrupt. */
1151 clr_irq &= ~(LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
1152 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2));
1153 }
1154
1155 if (iio_buffer_enabled(iio))
1156 iio_trigger_poll(iio->trig);
1157 else if (reg & LRADC_CTRL1_LRADC_IRQ(0))
1158 complete(&lradc->completion);
1159
1160 mxs_lradc_reg_clear(lradc, reg & clr_irq, LRADC_CTRL1);
1161
1162 return IRQ_HANDLED;
1163 }
1164
1165 /*
1166 * Trigger handling
1167 */
1168 static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
1169 {
1170 struct iio_poll_func *pf = p;
1171 struct iio_dev *iio = pf->indio_dev;
1172 struct mxs_lradc *lradc = iio_priv(iio);
1173 const uint32_t chan_value = LRADC_CH_ACCUMULATE |
1174 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1175 unsigned int i, j = 0;
1176
1177 for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1178 lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
1179 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(j));
1180 lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
1181 lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
1182 j++;
1183 }
1184
1185 iio_push_to_buffers_with_timestamp(iio, lradc->buffer, pf->timestamp);
1186
1187 iio_trigger_notify_done(iio->trig);
1188
1189 return IRQ_HANDLED;
1190 }
1191
1192 static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
1193 {
1194 struct iio_dev *iio = iio_trigger_get_drvdata(trig);
1195 struct mxs_lradc *lradc = iio_priv(iio);
1196 const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
1197
1198 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_KICK, LRADC_DELAY(0) + st);
1199
1200 return 0;
1201 }
1202
1203 static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
1204 .owner = THIS_MODULE,
1205 .set_trigger_state = &mxs_lradc_configure_trigger,
1206 };
1207
1208 static int mxs_lradc_trigger_init(struct iio_dev *iio)
1209 {
1210 int ret;
1211 struct iio_trigger *trig;
1212 struct mxs_lradc *lradc = iio_priv(iio);
1213
1214 trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
1215 if (trig == NULL)
1216 return -ENOMEM;
1217
1218 trig->dev.parent = lradc->dev;
1219 iio_trigger_set_drvdata(trig, iio);
1220 trig->ops = &mxs_lradc_trigger_ops;
1221
1222 ret = iio_trigger_register(trig);
1223 if (ret) {
1224 iio_trigger_free(trig);
1225 return ret;
1226 }
1227
1228 lradc->trig = trig;
1229
1230 return 0;
1231 }
1232
1233 static void mxs_lradc_trigger_remove(struct iio_dev *iio)
1234 {
1235 struct mxs_lradc *lradc = iio_priv(iio);
1236
1237 iio_trigger_unregister(lradc->trig);
1238 iio_trigger_free(lradc->trig);
1239 }
1240
1241 static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
1242 {
1243 struct mxs_lradc *lradc = iio_priv(iio);
1244 int ret = 0, chan, ofs = 0;
1245 unsigned long enable = 0;
1246 uint32_t ctrl4_set = 0;
1247 uint32_t ctrl4_clr = 0;
1248 uint32_t ctrl1_irq = 0;
1249 const uint32_t chan_value = LRADC_CH_ACCUMULATE |
1250 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1251 const int len = bitmap_weight(iio->active_scan_mask,
1252 LRADC_MAX_TOTAL_CHANS);
1253
1254 if (!len)
1255 return -EINVAL;
1256
1257 /*
1258 * Lock the driver so raw access can not be done during buffered
1259 * operation. This simplifies the code a lot.
1260 */
1261 ret = mutex_trylock(&lradc->lock);
1262 if (!ret)
1263 return -EBUSY;
1264
1265 lradc->buffer = kmalloc_array(len, sizeof(*lradc->buffer), GFP_KERNEL);
1266 if (!lradc->buffer) {
1267 ret = -ENOMEM;
1268 goto err_mem;
1269 }
1270
1271 if (lradc->soc == IMX28_LRADC)
1272 mxs_lradc_reg_clear(lradc,
1273 lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
1274 LRADC_CTRL1);
1275 mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
1276
1277 for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1278 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
1279 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
1280 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
1281 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(ofs));
1282 bitmap_set(&enable, ofs, 1);
1283 ofs++;
1284 }
1285
1286 mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1287 LRADC_DELAY_KICK, LRADC_DELAY(0));
1288 mxs_lradc_reg_clear(lradc, ctrl4_clr, LRADC_CTRL4);
1289 mxs_lradc_reg_set(lradc, ctrl4_set, LRADC_CTRL4);
1290 mxs_lradc_reg_set(lradc, ctrl1_irq, LRADC_CTRL1);
1291 mxs_lradc_reg_set(lradc, enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
1292 LRADC_DELAY(0));
1293
1294 return 0;
1295
1296 err_mem:
1297 mutex_unlock(&lradc->lock);
1298 return ret;
1299 }
1300
1301 static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
1302 {
1303 struct mxs_lradc *lradc = iio_priv(iio);
1304
1305 mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1306 LRADC_DELAY_KICK, LRADC_DELAY(0));
1307
1308 mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0);
1309 if (lradc->soc == IMX28_LRADC)
1310 mxs_lradc_reg_clear(lradc,
1311 lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
1312 LRADC_CTRL1);
1313
1314 kfree(lradc->buffer);
1315 mutex_unlock(&lradc->lock);
1316
1317 return 0;
1318 }
1319
1320 static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
1321 const unsigned long *mask)
1322 {
1323 struct mxs_lradc *lradc = iio_priv(iio);
1324 const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
1325 int rsvd_chans = 0;
1326 unsigned long rsvd_mask = 0;
1327
1328 if (lradc->use_touchbutton)
1329 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
1330 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_4WIRE)
1331 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
1332 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1333 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
1334
1335 if (lradc->use_touchbutton)
1336 rsvd_chans++;
1337 if (lradc->use_touchscreen)
1338 rsvd_chans += 2;
1339
1340 /* Test for attempts to map channels with special mode of operation. */
1341 if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
1342 return false;
1343
1344 /* Test for attempts to map more channels then available slots. */
1345 if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
1346 return false;
1347
1348 return true;
1349 }
1350
1351 static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
1352 .preenable = &mxs_lradc_buffer_preenable,
1353 .postenable = &iio_triggered_buffer_postenable,
1354 .predisable = &iio_triggered_buffer_predisable,
1355 .postdisable = &mxs_lradc_buffer_postdisable,
1356 .validate_scan_mask = &mxs_lradc_validate_scan_mask,
1357 };
1358
1359 /*
1360 * Driver initialization
1361 */
1362
1363 #define MXS_ADC_CHAN(idx, chan_type) { \
1364 .type = (chan_type), \
1365 .indexed = 1, \
1366 .scan_index = (idx), \
1367 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1368 BIT(IIO_CHAN_INFO_SCALE), \
1369 .channel = (idx), \
1370 .address = (idx), \
1371 .scan_type = { \
1372 .sign = 'u', \
1373 .realbits = LRADC_RESOLUTION, \
1374 .storagebits = 32, \
1375 }, \
1376 }
1377
1378 static const struct iio_chan_spec mxs_lradc_chan_spec[] = {
1379 MXS_ADC_CHAN(0, IIO_VOLTAGE),
1380 MXS_ADC_CHAN(1, IIO_VOLTAGE),
1381 MXS_ADC_CHAN(2, IIO_VOLTAGE),
1382 MXS_ADC_CHAN(3, IIO_VOLTAGE),
1383 MXS_ADC_CHAN(4, IIO_VOLTAGE),
1384 MXS_ADC_CHAN(5, IIO_VOLTAGE),
1385 MXS_ADC_CHAN(6, IIO_VOLTAGE),
1386 MXS_ADC_CHAN(7, IIO_VOLTAGE), /* VBATT */
1387 /* Combined Temperature sensors */
1388 {
1389 .type = IIO_TEMP,
1390 .indexed = 1,
1391 .scan_index = 8,
1392 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1393 BIT(IIO_CHAN_INFO_OFFSET) |
1394 BIT(IIO_CHAN_INFO_SCALE),
1395 .channel = 8,
1396 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
1397 },
1398 MXS_ADC_CHAN(10, IIO_VOLTAGE), /* VDDIO */
1399 MXS_ADC_CHAN(11, IIO_VOLTAGE), /* VTH */
1400 MXS_ADC_CHAN(12, IIO_VOLTAGE), /* VDDA */
1401 MXS_ADC_CHAN(13, IIO_VOLTAGE), /* VDDD */
1402 MXS_ADC_CHAN(14, IIO_VOLTAGE), /* VBG */
1403 MXS_ADC_CHAN(15, IIO_VOLTAGE), /* VDD5V */
1404 };
1405
1406 static int mxs_lradc_hw_init(struct mxs_lradc *lradc)
1407 {
1408 /* The ADC always uses DELAY CHANNEL 0. */
1409 const uint32_t adc_cfg =
1410 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
1411 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
1412
1413 int ret = stmp_reset_block(lradc->base);
1414
1415 if (ret)
1416 return ret;
1417
1418 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
1419 mxs_lradc_reg_wrt(lradc, adc_cfg, LRADC_DELAY(0));
1420
1421 /* Disable remaining DELAY CHANNELs */
1422 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(1));
1423 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
1424 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
1425
1426 /* Configure the touchscreen type */
1427 if (lradc->soc == IMX28_LRADC) {
1428 mxs_lradc_reg_clear(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1429 LRADC_CTRL0);
1430
1431 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1432 mxs_lradc_reg_set(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1433 LRADC_CTRL0);
1434 }
1435
1436 /* Start internal temperature sensing. */
1437 mxs_lradc_reg_wrt(lradc, 0, LRADC_CTRL2);
1438
1439 return 0;
1440 }
1441
1442 static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
1443 {
1444 int i;
1445
1446 mxs_lradc_reg_clear(lradc, mxs_lradc_irq_en_mask(lradc), LRADC_CTRL1);
1447
1448 for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
1449 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(i));
1450 }
1451
1452 static const struct of_device_id mxs_lradc_dt_ids[] = {
1453 { .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, },
1454 { .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, },
1455 { /* sentinel */ }
1456 };
1457 MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
1458
1459 static int mxs_lradc_probe_touchscreen(struct mxs_lradc *lradc,
1460 struct device_node *lradc_node)
1461 {
1462 int ret;
1463 u32 ts_wires = 0, adapt;
1464
1465 ret = of_property_read_u32(lradc_node, "fsl,lradc-touchscreen-wires",
1466 &ts_wires);
1467 if (ret)
1468 return -ENODEV; /* touchscreen feature disabled */
1469
1470 switch (ts_wires) {
1471 case 4:
1472 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_4WIRE;
1473 break;
1474 case 5:
1475 if (lradc->soc == IMX28_LRADC) {
1476 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_5WIRE;
1477 break;
1478 }
1479 /* fall through an error message for i.MX23 */
1480 default:
1481 dev_err(lradc->dev,
1482 "Unsupported number of touchscreen wires (%d)\n",
1483 ts_wires);
1484 return -EINVAL;
1485 }
1486
1487 lradc->over_sample_cnt = 4;
1488 ret = of_property_read_u32(lradc_node, "fsl,ave-ctrl", &adapt);
1489 if (ret == 0)
1490 lradc->over_sample_cnt = adapt;
1491
1492 lradc->over_sample_delay = 2;
1493 ret = of_property_read_u32(lradc_node, "fsl,ave-delay", &adapt);
1494 if (ret == 0)
1495 lradc->over_sample_delay = adapt;
1496
1497 lradc->settling_delay = 10;
1498 ret = of_property_read_u32(lradc_node, "fsl,settling", &adapt);
1499 if (ret == 0)
1500 lradc->settling_delay = adapt;
1501
1502 return 0;
1503 }
1504
1505 static int mxs_lradc_probe(struct platform_device *pdev)
1506 {
1507 const struct of_device_id *of_id =
1508 of_match_device(mxs_lradc_dt_ids, &pdev->dev);
1509 const struct mxs_lradc_of_config *of_cfg =
1510 &mxs_lradc_of_config[(enum mxs_lradc_id)of_id->data];
1511 struct device *dev = &pdev->dev;
1512 struct device_node *node = dev->of_node;
1513 struct mxs_lradc *lradc;
1514 struct iio_dev *iio;
1515 struct resource *iores;
1516 int ret = 0, touch_ret;
1517 int i, s;
1518 uint64_t scale_uv;
1519
1520 /* Allocate the IIO device. */
1521 iio = devm_iio_device_alloc(dev, sizeof(*lradc));
1522 if (!iio) {
1523 dev_err(dev, "Failed to allocate IIO device\n");
1524 return -ENOMEM;
1525 }
1526
1527 lradc = iio_priv(iio);
1528 lradc->soc = (enum mxs_lradc_id)of_id->data;
1529
1530 /* Grab the memory area */
1531 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1532 lradc->dev = &pdev->dev;
1533 lradc->base = devm_ioremap_resource(dev, iores);
1534 if (IS_ERR(lradc->base))
1535 return PTR_ERR(lradc->base);
1536
1537 lradc->clk = devm_clk_get(&pdev->dev, NULL);
1538 if (IS_ERR(lradc->clk)) {
1539 dev_err(dev, "Failed to get the delay unit clock\n");
1540 return PTR_ERR(lradc->clk);
1541 }
1542 ret = clk_prepare_enable(lradc->clk);
1543 if (ret != 0) {
1544 dev_err(dev, "Failed to enable the delay unit clock\n");
1545 return ret;
1546 }
1547
1548 touch_ret = mxs_lradc_probe_touchscreen(lradc, node);
1549
1550 if (touch_ret == 0)
1551 lradc->buffer_vchans = BUFFER_VCHANS_LIMITED;
1552 else
1553 lradc->buffer_vchans = BUFFER_VCHANS_ALL;
1554
1555 /* Grab all IRQ sources */
1556 for (i = 0; i < of_cfg->irq_count; i++) {
1557 lradc->irq[i] = platform_get_irq(pdev, i);
1558 if (lradc->irq[i] < 0) {
1559 ret = lradc->irq[i];
1560 goto err_clk;
1561 }
1562
1563 ret = devm_request_irq(dev, lradc->irq[i],
1564 mxs_lradc_handle_irq, 0,
1565 of_cfg->irq_name[i], iio);
1566 if (ret)
1567 goto err_clk;
1568 }
1569
1570 lradc->vref_mv = of_cfg->vref_mv;
1571
1572 platform_set_drvdata(pdev, iio);
1573
1574 init_completion(&lradc->completion);
1575 mutex_init(&lradc->lock);
1576
1577 iio->name = pdev->name;
1578 iio->dev.parent = &pdev->dev;
1579 iio->info = &mxs_lradc_iio_info;
1580 iio->modes = INDIO_DIRECT_MODE;
1581 iio->channels = mxs_lradc_chan_spec;
1582 iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
1583 iio->masklength = LRADC_MAX_TOTAL_CHANS;
1584
1585 ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
1586 &mxs_lradc_trigger_handler,
1587 &mxs_lradc_buffer_ops);
1588 if (ret)
1589 goto err_clk;
1590
1591 ret = mxs_lradc_trigger_init(iio);
1592 if (ret)
1593 goto err_trig;
1594
1595 /* Populate available ADC input ranges */
1596 for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
1597 for (s = 0; s < ARRAY_SIZE(lradc->scale_avail[i]); s++) {
1598 /*
1599 * [s=0] = optional divider by two disabled (default)
1600 * [s=1] = optional divider by two enabled
1601 *
1602 * The scale is calculated by doing:
1603 * Vref >> (realbits - s)
1604 * which multiplies by two on the second component
1605 * of the array.
1606 */
1607 scale_uv = ((u64)lradc->vref_mv[i] * 100000000) >>
1608 (LRADC_RESOLUTION - s);
1609 lradc->scale_avail[i][s].nano =
1610 do_div(scale_uv, 100000000) * 10;
1611 lradc->scale_avail[i][s].integer = scale_uv;
1612 }
1613 }
1614
1615 /* Configure the hardware. */
1616 ret = mxs_lradc_hw_init(lradc);
1617 if (ret)
1618 goto err_dev;
1619
1620 /* Register the touchscreen input device. */
1621 if (touch_ret == 0) {
1622 ret = mxs_lradc_ts_register(lradc);
1623 if (ret)
1624 goto err_ts_register;
1625 }
1626
1627 /* Register IIO device. */
1628 ret = iio_device_register(iio);
1629 if (ret) {
1630 dev_err(dev, "Failed to register IIO device\n");
1631 goto err_ts;
1632 }
1633
1634 return 0;
1635
1636 err_ts:
1637 mxs_lradc_ts_unregister(lradc);
1638 err_ts_register:
1639 mxs_lradc_hw_stop(lradc);
1640 err_dev:
1641 mxs_lradc_trigger_remove(iio);
1642 err_trig:
1643 iio_triggered_buffer_cleanup(iio);
1644 err_clk:
1645 clk_disable_unprepare(lradc->clk);
1646 return ret;
1647 }
1648
1649 static int mxs_lradc_remove(struct platform_device *pdev)
1650 {
1651 struct iio_dev *iio = platform_get_drvdata(pdev);
1652 struct mxs_lradc *lradc = iio_priv(iio);
1653
1654 iio_device_unregister(iio);
1655 mxs_lradc_ts_unregister(lradc);
1656 mxs_lradc_hw_stop(lradc);
1657 mxs_lradc_trigger_remove(iio);
1658 iio_triggered_buffer_cleanup(iio);
1659
1660 clk_disable_unprepare(lradc->clk);
1661 return 0;
1662 }
1663
1664 static struct platform_driver mxs_lradc_driver = {
1665 .driver = {
1666 .name = DRIVER_NAME,
1667 .of_match_table = mxs_lradc_dt_ids,
1668 },
1669 .probe = mxs_lradc_probe,
1670 .remove = mxs_lradc_remove,
1671 };
1672
1673 module_platform_driver(mxs_lradc_driver);
1674
1675 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1676 MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver");
1677 MODULE_LICENSE("GPL v2");
1678 MODULE_ALIAS("platform:" DRIVER_NAME);
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