drivers/staging/iio/meter/ade7854.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ADE7854_H
   3 #define _ADE7854_H
   4
   5 #define ADE7854_AIGAIN    0x4380
   6 #define ADE7854_AVGAIN    0x4381
   7 #define ADE7854_BIGAIN    0x4382
   8 #define ADE7854_BVGAIN    0x4383
   9 #define ADE7854_CIGAIN    0x4384
  10 #define ADE7854_CVGAIN    0x4385
  11 #define ADE7854_NIGAIN    0x4386
  12 #define ADE7854_AIRMSOS   0x4387
  13 #define ADE7854_AVRMSOS   0x4388
  14 #define ADE7854_BIRMSOS   0x4389
  15 #define ADE7854_BVRMSOS   0x438A
  16 #define ADE7854_CIRMSOS   0x438B
  17 #define ADE7854_CVRMSOS   0x438C
  18 #define ADE7854_NIRMSOS   0x438D
  19 #define ADE7854_AVAGAIN   0x438E
  20 #define ADE7854_BVAGAIN   0x438F
  21 #define ADE7854_CVAGAIN   0x4390
  22 #define ADE7854_AWGAIN    0x4391
  23 #define ADE7854_AWATTOS   0x4392
  24 #define ADE7854_BWGAIN    0x4393
  25 #define ADE7854_BWATTOS   0x4394
  26 #define ADE7854_CWGAIN    0x4395
  27 #define ADE7854_CWATTOS   0x4396
  28 #define ADE7854_AVARGAIN  0x4397
  29 #define ADE7854_AVAROS    0x4398
  30 #define ADE7854_BVARGAIN  0x4399
  31 #define ADE7854_BVAROS    0x439A
  32 #define ADE7854_CVARGAIN  0x439B
  33 #define ADE7854_CVAROS    0x439C
  34 #define ADE7854_AFWGAIN   0x439D
  35 #define ADE7854_AFWATTOS  0x439E
  36 #define ADE7854_BFWGAIN   0x439F
  37 #define ADE7854_BFWATTOS  0x43A0
  38 #define ADE7854_CFWGAIN   0x43A1
  39 #define ADE7854_CFWATTOS  0x43A2
  40 #define ADE7854_AFVARGAIN 0x43A3
  41 #define ADE7854_AFVAROS   0x43A4
  42 #define ADE7854_BFVARGAIN 0x43A5
  43 #define ADE7854_BFVAROS   0x43A6
  44 #define ADE7854_CFVARGAIN 0x43A7
  45 #define ADE7854_CFVAROS   0x43A8
  46 #define ADE7854_VATHR1    0x43A9
  47 #define ADE7854_VATHR0    0x43AA
  48 #define ADE7854_WTHR1     0x43AB
  49 #define ADE7854_WTHR0     0x43AC
  50 #define ADE7854_VARTHR1   0x43AD
  51 #define ADE7854_VARTHR0   0x43AE
  52 #define ADE7854_RSV       0x43AF
  53 #define ADE7854_VANOLOAD  0x43B0
  54 #define ADE7854_APNOLOAD  0x43B1
  55 #define ADE7854_VARNOLOAD 0x43B2
  56 #define ADE7854_VLEVEL    0x43B3
  57 #define ADE7854_DICOEFF   0x43B5
  58 #define ADE7854_HPFDIS    0x43B6
  59 #define ADE7854_ISUMLVL   0x43B8
  60 #define ADE7854_ISUM      0x43BF
  61 #define ADE7854_AIRMS     0x43C0
  62 #define ADE7854_AVRMS     0x43C1
  63 #define ADE7854_BIRMS     0x43C2
  64 #define ADE7854_BVRMS     0x43C3
  65 #define ADE7854_CIRMS     0x43C4
  66 #define ADE7854_CVRMS     0x43C5
  67 #define ADE7854_NIRMS     0x43C6
  68 #define ADE7854_RUN       0xE228
  69 #define ADE7854_AWATTHR   0xE400
  70 #define ADE7854_BWATTHR   0xE401
  71 #define ADE7854_CWATTHR   0xE402
  72 #define ADE7854_AFWATTHR  0xE403
  73 #define ADE7854_BFWATTHR  0xE404
  74 #define ADE7854_CFWATTHR  0xE405
  75 #define ADE7854_AVARHR    0xE406
  76 #define ADE7854_BVARHR    0xE407
  77 #define ADE7854_CVARHR    0xE408
  78 #define ADE7854_AFVARHR   0xE409
  79 #define ADE7854_BFVARHR   0xE40A
  80 #define ADE7854_CFVARHR   0xE40B
  81 #define ADE7854_AVAHR     0xE40C
  82 #define ADE7854_BVAHR     0xE40D
  83 #define ADE7854_CVAHR     0xE40E
  84 #define ADE7854_IPEAK     0xE500
  85 #define ADE7854_VPEAK     0xE501
  86 #define ADE7854_STATUS0   0xE502
  87 #define ADE7854_STATUS1   0xE503
  88 #define ADE7854_OILVL     0xE507
  89 #define ADE7854_OVLVL     0xE508
  90 #define ADE7854_SAGLVL    0xE509
  91 #define ADE7854_MASK0     0xE50A
  92 #define ADE7854_MASK1     0xE50B
  93 #define ADE7854_IAWV      0xE50C
  94 #define ADE7854_IBWV      0xE50D
  95 #define ADE7854_ICWV      0xE50E
  96 #define ADE7854_VAWV      0xE510
  97 #define ADE7854_VBWV      0xE511
  98 #define ADE7854_VCWV      0xE512
  99 #define ADE7854_AWATT     0xE513
 100 #define ADE7854_BWATT     0xE514
 101 #define ADE7854_CWATT     0xE515
 102 #define ADE7854_AVA       0xE519
 103 #define ADE7854_BVA       0xE51A
 104 #define ADE7854_CVA       0xE51B
 105 #define ADE7854_CHECKSUM  0xE51F
 106 #define ADE7854_VNOM      0xE520
 107 #define ADE7854_PHSTATUS  0xE600
 108 #define ADE7854_ANGLE0    0xE601
 109 #define ADE7854_ANGLE1    0xE602
 110 #define ADE7854_ANGLE2    0xE603
 111 #define ADE7854_PERIOD    0xE607
 112 #define ADE7854_PHNOLOAD  0xE608
 113 #define ADE7854_LINECYC   0xE60C
 114 #define ADE7854_ZXTOUT    0xE60D
 115 #define ADE7854_COMPMODE  0xE60E
 116 #define ADE7854_GAIN      0xE60F
 117 #define ADE7854_CFMODE    0xE610
 118 #define ADE7854_CF1DEN    0xE611
 119 #define ADE7854_CF2DEN    0xE612
 120 #define ADE7854_CF3DEN    0xE613
 121 #define ADE7854_APHCAL    0xE614
 122 #define ADE7854_BPHCAL    0xE615
 123 #define ADE7854_CPHCAL    0xE616
 124 #define ADE7854_PHSIGN    0xE617
 125 #define ADE7854_CONFIG    0xE618
 126 #define ADE7854_MMODE     0xE700
 127 #define ADE7854_ACCMODE   0xE701
 128 #define ADE7854_LCYCMODE  0xE702
 129 #define ADE7854_PEAKCYC   0xE703
 130 #define ADE7854_SAGCYC    0xE704
 131 #define ADE7854_CFCYC     0xE705
 132 #define ADE7854_HSDC_CFG  0xE706
 133 #define ADE7854_CONFIG2   0xEC01
 134
 135 #define ADE7854_READ_REG   0x1
 136 #define ADE7854_WRITE_REG  0x0
 137
 138 #define ADE7854_MAX_TX    7
 139 #define ADE7854_MAX_RX    7
 140 #define ADE7854_STARTUP_DELAY 1000
 141
 142 #define ADE7854_SPI_SLOW        (u32)(300 * 1000)
 143 #define ADE7854_SPI_BURST       (u32)(1000 * 1000)
 144 #define ADE7854_SPI_FAST        (u32)(2000 * 1000)
 145
 146 /**
 147  * struct ade7854_state - device instance specific data
 148  * @spi:                        actual spi_device
 149  * @indio_dev:          industrial I/O device structure
 150  * @buf_lock:           mutex to protect tx and rx
 151  * @tx:                 transmit buffer
 152  * @rx:                 receive buffer
 153  **/
 154 struct ade7854_state {
 155         struct spi_device       *spi;
 156         struct i2c_client       *i2c;
 157         int                     (*read_reg_8)(struct device *, u16, u8 *);
 158         int                     (*read_reg_16)(struct device *, u16, u16 *);
 159         int                     (*read_reg_24)(struct device *, u16, u32 *);
 160         int                     (*read_reg_32)(struct device *, u16, u32 *);
 161         int                     (*write_reg_8)(struct device *, u16, u8);
 162         int                     (*write_reg_16)(struct device *, u16, u16);
 163         int                     (*write_reg_24)(struct device *, u16, u32);
 164         int                     (*write_reg_32)(struct device *, u16, u32);
 165         int                     irq;
 166         struct mutex            buf_lock;
 167         u8                      tx[ADE7854_MAX_TX] ____cacheline_aligned;
 168         u8                      rx[ADE7854_MAX_RX];
 169
 170 };
 171
 172 int ade7854_probe(struct iio_dev *indio_dev, struct device *dev);
 173 int ade7854_remove(struct iio_dev *indio_dev);
 174
 175 #endif