drivers/staging/media/atomisp/i2c/gc0310.h

   1 /*
   2  * Support for GalaxyCore GC0310 VGA camera sensor.
   3  *
   4  * Copyright (c) 2013 Intel Corporation. All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License version
   8  * 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  18  * 02110-1301, USA.
  19  *
  20  */
  21
  22 #ifndef __GC0310_H__
  23 #define __GC0310_H__
  24 #include <linux/kernel.h>
  25 #include <linux/types.h>
  26 #include <linux/i2c.h>
  27 #include <linux/acpi.h>
  28 #include <linux/delay.h>
  29 #include <linux/videodev2.h>
  30 #include <linux/spinlock.h>
  31 #include <media/v4l2-subdev.h>
  32 #include <media/v4l2-device.h>
  33 #include <media/v4l2-ctrls.h>
  34 #include <linux/v4l2-mediabus.h>
  35 #include <media/media-entity.h>
  36
  37 #include "../include/linux/atomisp_platform.h"
  38
  39 /* Defines for register writes and register array processing */
  40 #define I2C_MSG_LENGTH          1
  41 #define I2C_RETRY_COUNT         5
  42
  43 #define GC0310_FOCAL_LENGTH_NUM 278     /*2.78mm*/
  44 #define GC0310_FOCAL_LENGTH_DEM 100
  45 #define GC0310_F_NUMBER_DEFAULT_NUM     26
  46 #define GC0310_F_NUMBER_DEM     10
  47
  48 #define MAX_FMTS                1
  49
  50 /*
  51  * focal length bits definition:
  52  * bits 31-16: numerator, bits 15-0: denominator
  53  */
  54 #define GC0310_FOCAL_LENGTH_DEFAULT 0x1160064
  55
  56 /*
  57  * current f-number bits definition:
  58  * bits 31-16: numerator, bits 15-0: denominator
  59  */
  60 #define GC0310_F_NUMBER_DEFAULT 0x1a000a
  61
  62 /*
  63  * f-number range bits definition:
  64  * bits 31-24: max f-number numerator
  65  * bits 23-16: max f-number denominator
  66  * bits 15-8: min f-number numerator
  67  * bits 7-0: min f-number denominator
  68  */
  69 #define GC0310_F_NUMBER_RANGE 0x1a0a1a0a
  70 #define GC0310_ID       0xa310
  71
  72 #define GC0310_RESET_RELATED            0xFE
  73 #define GC0310_REGISTER_PAGE_0          0x0
  74 #define GC0310_REGISTER_PAGE_3          0x3
  75
  76 #define GC0310_FINE_INTG_TIME_MIN 0
  77 #define GC0310_FINE_INTG_TIME_MAX_MARGIN 0
  78 #define GC0310_COARSE_INTG_TIME_MIN 1
  79 #define GC0310_COARSE_INTG_TIME_MAX_MARGIN 6
  80
  81 /*
  82  * GC0310 System control registers
  83  */
  84 #define GC0310_SW_STREAM                        0x10
  85
  86 #define GC0310_SC_CMMN_CHIP_ID_H                0xf0
  87 #define GC0310_SC_CMMN_CHIP_ID_L                0xf1
  88
  89 #define GC0310_AEC_PK_EXPO_H                    0x03
  90 #define GC0310_AEC_PK_EXPO_L                    0x04
  91 #define GC0310_AGC_ADJ                  0x48
  92 #define GC0310_DGC_ADJ                  0x71
  93 #if 0
  94 #define GC0310_GROUP_ACCESS                     0x3208
  95 #endif
  96
  97 #define GC0310_H_CROP_START_H                   0x09
  98 #define GC0310_H_CROP_START_L                   0x0A
  99 #define GC0310_V_CROP_START_H                   0x0B
 100 #define GC0310_V_CROP_START_L                   0x0C
 101 #define GC0310_H_OUTSIZE_H                      0x0F
 102 #define GC0310_H_OUTSIZE_L                      0x10
 103 #define GC0310_V_OUTSIZE_H                      0x0D
 104 #define GC0310_V_OUTSIZE_L                      0x0E
 105 #define GC0310_H_BLANKING_H                     0x05
 106 #define GC0310_H_BLANKING_L                     0x06
 107 #define GC0310_V_BLANKING_H                     0x07
 108 #define GC0310_V_BLANKING_L                     0x08
 109 #define GC0310_SH_DELAY                 0x11
 110
 111 #define GC0310_START_STREAMING                  0x94 /* 8-bit enable */
 112 #define GC0310_STOP_STREAMING                   0x0 /* 8-bit disable */
 113
 114 #define GC0310_BIN_FACTOR_MAX                   3
 115
 116 struct regval_list {
 117         u16 reg_num;
 118         u8 value;
 119 };
 120
 121 struct gc0310_resolution {
 122         u8 *desc;
 123         const struct gc0310_reg *regs;
 124         int res;
 125         int width;
 126         int height;
 127         int fps;
 128         int pix_clk_freq;
 129         u32 skip_frames;
 130         u16 pixels_per_line;
 131         u16 lines_per_frame;
 132         u8 bin_factor_x;
 133         u8 bin_factor_y;
 134         u8 bin_mode;
 135         bool used;
 136 };
 137
 138 struct gc0310_format {
 139         u8 *desc;
 140         u32 pixelformat;
 141         struct gc0310_reg *regs;
 142 };
 143
 144 /*
 145  * gc0310 device structure.
 146  */
 147 struct gc0310_device {
 148         struct v4l2_subdev sd;
 149         struct media_pad pad;
 150         struct v4l2_mbus_framefmt format;
 151         struct mutex input_lock;
 152         struct v4l2_ctrl_handler ctrl_handler;
 153
 154         struct camera_sensor_platform_data *platform_data;
 155         int vt_pix_clk_freq_mhz;
 156         int fmt_idx;
 157         int run_mode;
 158         u8 res;
 159         u8 type;
 160 };
 161
 162 enum gc0310_tok_type {
 163         GC0310_8BIT  = 0x0001,
 164         GC0310_TOK_TERM   = 0xf000,     /* terminating token for reg list */
 165         GC0310_TOK_DELAY  = 0xfe00,     /* delay token for reg list */
 166         GC0310_TOK_MASK = 0xfff0
 167 };
 168
 169 /**
 170  * struct gc0310_reg - MI sensor  register format
 171  * @type: type of the register
 172  * @reg: 16-bit offset to register
 173  * @val: 8/16/32-bit register value
 174  *
 175  * Define a structure for sensor register initialization values
 176  */
 177 struct gc0310_reg {
 178         enum gc0310_tok_type type;
 179         u8 reg;
 180         u8 val; /* @set value for read/mod/write, @mask */
 181 };
 182
 183 #define to_gc0310_sensor(x) container_of(x, struct gc0310_device, sd)
 184
 185 #define GC0310_MAX_WRITE_BUF_SIZE       30
 186
 187 struct gc0310_write_buffer {
 188         u8 addr;
 189         u8 data[GC0310_MAX_WRITE_BUF_SIZE];
 190 };
 191
 192 struct gc0310_write_ctrl {
 193         int index;
 194         struct gc0310_write_buffer buffer;
 195 };
 196
 197 /*
 198  * Register settings for various resolution
 199  */
 200 static const struct gc0310_reg gc0310_reset_register[] = {
 201 /////////////////////////////////////////////////
 202 /////////////////       system reg      /////////////////
 203 /////////////////////////////////////////////////
 204         {GC0310_8BIT, 0xfe, 0xf0},
 205         {GC0310_8BIT, 0xfe, 0xf0},
 206         {GC0310_8BIT, 0xfe, 0x00},
 207
 208         {GC0310_8BIT, 0xfc, 0x0e}, //4e
 209         {GC0310_8BIT, 0xfc, 0x0e}, //16//4e // [0]apwd [6]regf_clk_gate
 210         {GC0310_8BIT, 0xf2, 0x80}, //sync output
 211         {GC0310_8BIT, 0xf3, 0x00}, //1f//01 data output
 212         {GC0310_8BIT, 0xf7, 0x33}, //f9
 213         {GC0310_8BIT, 0xf8, 0x05}, //00
 214         {GC0310_8BIT, 0xf9, 0x0e}, // 0x8e //0f
 215         {GC0310_8BIT, 0xfa, 0x11},
 216
 217 /////////////////////////////////////////////////
 218 ///////////////////   MIPI       ////////////////////
 219 /////////////////////////////////////////////////
 220         {GC0310_8BIT, 0xfe, 0x03},
 221         {GC0310_8BIT, 0x01, 0x03}, ///mipi 1lane
 222         {GC0310_8BIT, 0x02, 0x22}, // 0x33
 223         {GC0310_8BIT, 0x03, 0x94},
 224         {GC0310_8BIT, 0x04, 0x01}, // fifo_prog
 225         {GC0310_8BIT, 0x05, 0x00}, //fifo_prog
 226         {GC0310_8BIT, 0x06, 0x80}, //b0  //YUV ISP data
 227         {GC0310_8BIT, 0x11, 0x2a},//1e //LDI set YUV422
 228         {GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0]  //
 229         {GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8]
 230         {GC0310_8BIT, 0x15, 0x12}, // 0x10 //DPHYY_MODE read_ready
 231         {GC0310_8BIT, 0x17, 0x01},
 232         {GC0310_8BIT, 0x40, 0x08},
 233         {GC0310_8BIT, 0x41, 0x00},
 234         {GC0310_8BIT, 0x42, 0x00},
 235         {GC0310_8BIT, 0x43, 0x00},
 236         {GC0310_8BIT, 0x21, 0x02}, // 0x01
 237         {GC0310_8BIT, 0x22, 0x02}, // 0x01
 238         {GC0310_8BIT, 0x23, 0x01}, // 0x05 //Nor:0x05 DOU:0x06
 239         {GC0310_8BIT, 0x29, 0x00},
 240         {GC0310_8BIT, 0x2A, 0x25}, // 0x05 //data zero 0x7a de
 241         {GC0310_8BIT, 0x2B, 0x02},
 242
 243         {GC0310_8BIT, 0xfe, 0x00},
 244
 245 /////////////////////////////////////////////////
 246 /////////////////       CISCTL reg      /////////////////
 247 /////////////////////////////////////////////////
 248         {GC0310_8BIT, 0x00, 0x2f}, //2f//0f//02//01
 249         {GC0310_8BIT, 0x01, 0x0f}, //06
 250         {GC0310_8BIT, 0x02, 0x04},
 251         {GC0310_8BIT, 0x4f, 0x00}, //AEC 0FF
 252         {GC0310_8BIT, 0x03, 0x01}, // 0x03 //04
 253         {GC0310_8BIT, 0x04, 0xc0}, // 0xe8 //58
 254         {GC0310_8BIT, 0x05, 0x00},
 255         {GC0310_8BIT, 0x06, 0xb2}, // 0x0a //HB
 256         {GC0310_8BIT, 0x07, 0x00},
 257         {GC0310_8BIT, 0x08, 0x0c}, // 0x89 //VB
 258         {GC0310_8BIT, 0x09, 0x00}, //row start
 259         {GC0310_8BIT, 0x0a, 0x00}, //
 260         {GC0310_8BIT, 0x0b, 0x00}, //col start
 261         {GC0310_8BIT, 0x0c, 0x00},
 262         {GC0310_8BIT, 0x0d, 0x01}, //height
 263         {GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height
 264         {GC0310_8BIT, 0x0f, 0x02}, //width
 265         {GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height
 266         {GC0310_8BIT, 0x17, 0x14},
 267         {GC0310_8BIT, 0x18, 0x1a}, //0a//[4]double reset
 268         {GC0310_8BIT, 0x19, 0x14}, //AD pipeline
 269         {GC0310_8BIT, 0x1b, 0x48},
 270         {GC0310_8BIT, 0x1e, 0x6b}, //3b//col bias
 271         {GC0310_8BIT, 0x1f, 0x28}, //20//00//08//txlow
 272         {GC0310_8BIT, 0x20, 0x89}, //88//0c//[3:2]DA15
 273         {GC0310_8BIT, 0x21, 0x49}, //48//[3] txhigh
 274         {GC0310_8BIT, 0x22, 0xb0},
 275         {GC0310_8BIT, 0x23, 0x04}, //[1:0]vcm_r
 276         {GC0310_8BIT, 0x24, 0x16}, //15
 277         {GC0310_8BIT, 0x34, 0x20}, //[6:4] rsg high//range
 278
 279 /////////////////////////////////////////////////
 280 ////////////////////   BLK       ////////////////////
 281 /////////////////////////////////////////////////
 282         {GC0310_8BIT, 0x26, 0x23}, //[1]dark_current_en [0]offset_en
 283         {GC0310_8BIT, 0x28, 0xff}, //BLK_limie_value
 284         {GC0310_8BIT, 0x29, 0x00}, //global offset
 285         {GC0310_8BIT, 0x33, 0x18}, //offset_ratio
 286         {GC0310_8BIT, 0x37, 0x20}, //dark_current_ratio
 287         {GC0310_8BIT, 0x2a, 0x00},
 288         {GC0310_8BIT, 0x2b, 0x00},
 289         {GC0310_8BIT, 0x2c, 0x00},
 290         {GC0310_8BIT, 0x2d, 0x00},
 291         {GC0310_8BIT, 0x2e, 0x00},
 292         {GC0310_8BIT, 0x2f, 0x00},
 293         {GC0310_8BIT, 0x30, 0x00},
 294         {GC0310_8BIT, 0x31, 0x00},
 295         {GC0310_8BIT, 0x47, 0x80}, //a7
 296         {GC0310_8BIT, 0x4e, 0x66}, //select_row
 297         {GC0310_8BIT, 0xa8, 0x02}, //win_width_dark, same with crop_win_width
 298         {GC0310_8BIT, 0xa9, 0x80},
 299
 300 /////////////////////////////////////////////////
 301 //////////////////       ISP reg  ///////////////////
 302 /////////////////////////////////////////////////
 303         {GC0310_8BIT, 0x40, 0x06}, // 0xff //ff //48
 304         {GC0310_8BIT, 0x41, 0x00}, // 0x21 //00//[0]curve_en
 305         {GC0310_8BIT, 0x42, 0x04}, // 0xcf //0a//[1]awn_en
 306         {GC0310_8BIT, 0x44, 0x18}, // 0x18 //02
 307         {GC0310_8BIT, 0x46, 0x02}, // 0x03 //sync
 308         {GC0310_8BIT, 0x49, 0x03},
 309         {GC0310_8BIT, 0x4c, 0x20}, //00[5]pretect exp
 310         {GC0310_8BIT, 0x50, 0x01}, //crop enable
 311         {GC0310_8BIT, 0x51, 0x00},
 312         {GC0310_8BIT, 0x52, 0x00},
 313         {GC0310_8BIT, 0x53, 0x00},
 314         {GC0310_8BIT, 0x54, 0x01},
 315         {GC0310_8BIT, 0x55, 0x01}, //crop window height
 316         {GC0310_8BIT, 0x56, 0xf0},
 317         {GC0310_8BIT, 0x57, 0x02}, //crop window width
 318         {GC0310_8BIT, 0x58, 0x90},
 319
 320 /////////////////////////////////////////////////
 321 ///////////////////   GAIN       ////////////////////
 322 /////////////////////////////////////////////////
 323         {GC0310_8BIT, 0x70, 0x70}, //70 //80//global gain
 324         {GC0310_8BIT, 0x71, 0x20}, // pregain gain
 325         {GC0310_8BIT, 0x72, 0x40}, // post gain
 326         {GC0310_8BIT, 0x5a, 0x84}, //84//analog gain 0
 327         {GC0310_8BIT, 0x5b, 0xc9}, //c9
 328         {GC0310_8BIT, 0x5c, 0xed}, //ed//not use pga gain highest level
 329         {GC0310_8BIT, 0x77, 0x40}, // R gain 0x74 //awb gain
 330         {GC0310_8BIT, 0x78, 0x40}, // G gain
 331         {GC0310_8BIT, 0x79, 0x40}, // B gain 0x5f
 332
 333         {GC0310_8BIT, 0x48, 0x00},
 334         {GC0310_8BIT, 0xfe, 0x01},
 335         {GC0310_8BIT, 0x0a, 0x45}, //[7]col gain mode
 336
 337         {GC0310_8BIT, 0x3e, 0x40},
 338         {GC0310_8BIT, 0x3f, 0x5c},
 339         {GC0310_8BIT, 0x40, 0x7b},
 340         {GC0310_8BIT, 0x41, 0xbd},
 341         {GC0310_8BIT, 0x42, 0xf6},
 342         {GC0310_8BIT, 0x43, 0x63},
 343         {GC0310_8BIT, 0x03, 0x60},
 344         {GC0310_8BIT, 0x44, 0x03},
 345
 346 /////////////////////////////////////////////////
 347 /////////////////       dark sun   //////////////////
 348 /////////////////////////////////////////////////
 349         {GC0310_8BIT, 0xfe, 0x01},
 350         {GC0310_8BIT, 0x45, 0xa4}, // 0xf7
 351         {GC0310_8BIT, 0x46, 0xf0}, // 0xff //f0//sun vaule th
 352         {GC0310_8BIT, 0x48, 0x03}, //sun mode
 353         {GC0310_8BIT, 0x4f, 0x60}, //sun_clamp
 354         {GC0310_8BIT, 0xfe, 0x00},
 355
 356         {GC0310_TOK_TERM, 0, 0},
 357 };
 358
 359 static struct gc0310_reg const gc0310_VGA_30fps[] = {
 360         {GC0310_8BIT, 0xfe, 0x00},
 361         {GC0310_8BIT, 0x0d, 0x01}, //height
 362         {GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height
 363         {GC0310_8BIT, 0x0f, 0x02}, //width
 364         {GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height
 365
 366         {GC0310_8BIT, 0x50, 0x01}, //crop enable
 367         {GC0310_8BIT, 0x51, 0x00},
 368         {GC0310_8BIT, 0x52, 0x00},
 369         {GC0310_8BIT, 0x53, 0x00},
 370         {GC0310_8BIT, 0x54, 0x01},
 371         {GC0310_8BIT, 0x55, 0x01}, //crop window height
 372         {GC0310_8BIT, 0x56, 0xf0},
 373         {GC0310_8BIT, 0x57, 0x02}, //crop window width
 374         {GC0310_8BIT, 0x58, 0x90},
 375
 376         {GC0310_8BIT, 0xfe, 0x03},
 377         {GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0]  //
 378         {GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8]
 379
 380         {GC0310_8BIT, 0xfe, 0x00},
 381
 382         {GC0310_TOK_TERM, 0, 0},
 383 };
 384
 385
 386 struct gc0310_resolution gc0310_res_preview[] = {
 387         {
 388                 .desc = "gc0310_VGA_30fps",
 389                 .width = 656, // 648,
 390                 .height = 496, // 488,
 391                 .fps = 30,
 392                 //.pix_clk_freq = 73,
 393                 .used = 0,
 394 #if 0
 395                 .pixels_per_line = 0x0314,
 396                 .lines_per_frame = 0x0213,
 397 #endif
 398                 .bin_factor_x = 1,
 399                 .bin_factor_y = 1,
 400                 .bin_mode = 0,
 401                 .skip_frames = 2,
 402                 .regs = gc0310_VGA_30fps,
 403         },
 404 };
 405 #define N_RES_PREVIEW (ARRAY_SIZE(gc0310_res_preview))
 406
 407 struct gc0310_resolution gc0310_res_still[] = {
 408         {
 409                 .desc = "gc0310_VGA_30fps",
 410                 .width = 656, // 648,
 411                 .height = 496, // 488,
 412                 .fps = 30,
 413                 //.pix_clk_freq = 73,
 414                 .used = 0,
 415 #if 0
 416                 .pixels_per_line = 0x0314,
 417                 .lines_per_frame = 0x0213,
 418 #endif
 419                 .bin_factor_x = 1,
 420                 .bin_factor_y = 1,
 421                 .bin_mode = 0,
 422                 .skip_frames = 2,
 423                 .regs = gc0310_VGA_30fps,
 424         },
 425 };
 426 #define N_RES_STILL (ARRAY_SIZE(gc0310_res_still))
 427
 428 struct gc0310_resolution gc0310_res_video[] = {
 429         {
 430                 .desc = "gc0310_VGA_30fps",
 431                 .width = 656, // 648,
 432                 .height = 496, // 488,
 433                 .fps = 30,
 434                 //.pix_clk_freq = 73,
 435                 .used = 0,
 436 #if 0
 437                 .pixels_per_line = 0x0314,
 438                 .lines_per_frame = 0x0213,
 439 #endif
 440                 .bin_factor_x = 1,
 441                 .bin_factor_y = 1,
 442                 .bin_mode = 0,
 443                 .skip_frames = 2,
 444                 .regs = gc0310_VGA_30fps,
 445         },
 446 };
 447 #define N_RES_VIDEO (ARRAY_SIZE(gc0310_res_video))
 448
 449 static struct gc0310_resolution *gc0310_res = gc0310_res_preview;
 450 static unsigned long N_RES = N_RES_PREVIEW;
 451 #endif
 452