drivers/staging/media/atomisp/include/asm/intel_mid_pcihelpers.h

   1 /*
   2  * Access to message bus through three registers
   3  * in CUNIT(0:0:0) PCI configuration space.
   4  * MSGBUS_CTRL_REG(0xD0):
   5  *   31:24      = message bus opcode
   6  *   23:16      = message bus port
   7  *   15:8       = message bus address, low 8 bits.
   8  *   7:4        = message bus byte enables
   9  * MSGBUS_CTRL_EXT_REG(0xD8):
  10  *   31:8       = message bus address, high 24 bits.
  11  * MSGBUS_DATA_REG(0xD4):
  12  *   hold the data for write or read
  13  */
  14 #define PCI_ROOT_MSGBUS_CTRL_REG        0xD0
  15 #define PCI_ROOT_MSGBUS_DATA_REG        0xD4
  16 #define PCI_ROOT_MSGBUS_CTRL_EXT_REG    0xD8
  17 #define PCI_ROOT_MSGBUS_READ            0x10
  18 #define PCI_ROOT_MSGBUS_WRITE           0x11
  19 #define PCI_ROOT_MSGBUS_DWORD_ENABLE    0xf0
  20
  21 /* In BYT platform for all internal PCI devices d3 delay
  22  * of 3 ms is sufficient. Default value of 10 ms is overkill.
  23  */
  24 #define INTERNAL_PCI_PM_D3_WAIT         3
  25
  26 #define ISP_SUB_CLASS                   0x80
  27 #define SUB_CLASS_MASK                  0xFF00
  28
  29 u32 intel_mid_msgbus_read32_raw(u32 cmd);
  30 u32 intel_mid_msgbus_read32(u8 port, u32 addr);
  31 void intel_mid_msgbus_write32_raw(u32 cmd, u32 data);
  32 void intel_mid_msgbus_write32(u8 port, u32 addr, u32 data);
  33 u32 intel_mid_msgbus_read32_raw_ext(u32 cmd, u32 cmd_ext);
  34 void intel_mid_msgbus_write32_raw_ext(u32 cmd, u32 cmd_ext, u32 data);
  35 u32 intel_mid_soc_stepping(void);