drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_formatter_subsystem_defs.h

   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef _if_subsystem_defs_h
  16 #define _if_subsystem_defs_h__
  17
  18 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0            0
  19 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_1            1
  20 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_2            2
  21 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_3            3
  22 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4            4
  23 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5            5
  24 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6            6
  25 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7            7
  26 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG        8
  27 #define HIVE_IFMT_GP_REGS_SRST_IDX                          9
  28 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX                 10
  29
  30 #define HIVE_IFMT_GP_REGS_CH_ID_FMT_TYPE_IDX               11
  31
  32 #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_BASE         HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0
  33
  34 /* order of the input bits for the ifmt irq controller */
  35 #define HIVE_IFMT_IRQ_IFT_PRIM_BIT_ID                       0
  36 #define HIVE_IFMT_IRQ_IFT_PRIM_B_BIT_ID                     1
  37 #define HIVE_IFMT_IRQ_IFT_SEC_BIT_ID                        2
  38 #define HIVE_IFMT_IRQ_MEM_CPY_BIT_ID                        3
  39 #define HIVE_IFMT_IRQ_SIDEBAND_CHANGED_BIT_ID               4
  40
  41 /* order of the input bits for the ifmt Soft reset register */
  42 #define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_BIT_IDX             0
  43 #define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_B_BIT_IDX           1
  44 #define HIVE_IFMT_GP_REGS_SRST_IFT_SEC_BIT_IDX              2
  45 #define HIVE_IFMT_GP_REGS_SRST_MEM_CPY_BIT_IDX              3
  46
  47 /* order of the input bits for the ifmt Soft reset register */
  48 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_BIT_IDX     0
  49 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_B_BIT_IDX   1
  50 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_SEC_BIT_IDX      2
  51 #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_MEM_CPY_BIT_IDX      3
  52
  53 #endif /* _if_subsystem_defs_h__ */