drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_private.h

   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef __CSI_RX_PRIVATE_H_INCLUDED__
  16 #define __CSI_RX_PRIVATE_H_INCLUDED__
  17
  18 #include "rx_csi_defs.h"
  19 #include "mipi_backend_defs.h"
  20 #include "csi_rx_public.h"
  21
  22 #include "device_access.h"      /* ia_css_device_load_uint32 */
  23
  24 #include "assert_support.h" /* assert */
  25 #include "print_support.h" /* print */
  26
  27
  28 /*****************************************************
  29  *
  30  * Native command interface (NCI).
  31  *
  32  *****************************************************/
  33 /**
  34  * @brief Get the csi rx fe state.
  35  * Refer to "csi_rx_public.h" for details.
  36  */
  37 static inline void csi_rx_fe_ctrl_get_state(
  38                 const csi_rx_frontend_ID_t ID,
  39                 csi_rx_fe_ctrl_state_t *state)
  40 {
  41         uint32_t i;
  42
  43         state->enable =
  44                 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ENABLE_REG_IDX);
  45         state->nof_enable_lanes =
  46                 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX);
  47         state->error_handling =
  48                 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ERROR_HANDLING_REG_IDX);
  49         state->status =
  50                 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_REG_IDX);
  51         state->status_dlane_hs =
  52                 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX);
  53         state->status_dlane_lp =
  54                 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX);
  55         state->clane.termen =
  56                 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX);
  57         state->clane.settle =
  58                 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX);
  59
  60         /*
  61          * Get the values of the register-set per
  62          * dlane.
  63          */
  64         for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) {
  65                 csi_rx_fe_ctrl_get_dlane_state(
  66                                 ID,
  67                                 i,
  68                                 &(state->dlane[i]));
  69         }
  70 }
  71
  72 /**
  73  * @brief Get the state of the csi rx fe dlane process.
  74  * Refer to "csi_rx_public.h" for details.
  75  */
  76 static inline void csi_rx_fe_ctrl_get_dlane_state(
  77                 const csi_rx_frontend_ID_t ID,
  78                 const uint32_t lane,
  79                 csi_rx_fe_ctrl_lane_t *dlane_state)
  80 {
  81
  82         dlane_state->termen =
  83                 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane));
  84         dlane_state->settle =
  85                 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane));
  86
  87 }
  88 /**
  89  * @brief dump the csi rx fe state.
  90  * Refer to "csi_rx_public.h" for details.
  91  */
  92 static inline void csi_rx_fe_ctrl_dump_state(
  93                 const csi_rx_frontend_ID_t ID,
  94                 csi_rx_fe_ctrl_state_t *state)
  95 {
  96         uint32_t i;
  97
  98         ia_css_print("CSI RX FE STATE Controller %d Enable state 0x%x \n", ID, state->enable);
  99         ia_css_print("CSI RX FE STATE Controller %d No Of enable lanes 0x%x \n", ID, state->nof_enable_lanes);
 100         ia_css_print("CSI RX FE STATE Controller %d Error handling 0x%x \n", ID, state->error_handling);
 101         ia_css_print("CSI RX FE STATE Controller %d Status 0x%x \n", ID, state->status);
 102         ia_css_print("CSI RX FE STATE Controller %d Status Dlane HS 0x%x \n", ID, state->status_dlane_hs);
 103         ia_css_print("CSI RX FE STATE Controller %d Status Dlane LP 0x%x \n", ID, state->status_dlane_lp);
 104         ia_css_print("CSI RX FE STATE Controller %d Status term enable LP 0x%x \n", ID, state->clane.termen);
 105         ia_css_print("CSI RX FE STATE Controller %d Status term settle LP 0x%x \n", ID, state->clane.settle);
 106
 107         /*
 108          * Get the values of the register-set per
 109          * dlane.
 110          */
 111         for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) {
 112                 ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d termen 0x%x \n", ID, i, state->dlane[i].termen);
 113                 ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d settle 0x%x \n", ID, i, state->dlane[i].settle);
 114         }
 115 }
 116
 117 /**
 118  * @brief Get the csi rx be state.
 119  * Refer to "csi_rx_public.h" for details.
 120  */
 121 static inline void csi_rx_be_ctrl_get_state(
 122                 const csi_rx_backend_ID_t ID,
 123                 csi_rx_be_ctrl_state_t *state)
 124 {
 125         uint32_t i;
 126
 127         state->enable =
 128                 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_ENABLE_REG_IDX);
 129
 130         state->status =
 131                 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_STATUS_REG_IDX);
 132
 133         for(i = 0; i <N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
 134                 state->comp_format_reg[i] =
 135                         csi_rx_be_ctrl_reg_load(ID,
 136                                                 _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX+i);
 137         }
 138
 139         state->raw16 =
 140                 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX);
 141
 142         state->raw18 =
 143                 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX);
 144         state->force_raw8 =
 145                 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX);
 146         state->irq_status =
 147                 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX);
 148 #if 0 /* device access error for these registers */
 149         /* ToDo: rootcause this failure */
 150         state->custom_mode_enable =
 151                 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_EN_REG_IDX);
 152
 153         state->custom_mode_data_state =
 154                 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX);
 155         for(i = 0; i <N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
 156                 state->pec[i] =
 157                         csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX + i);
 158         }
 159         state->custom_mode_valid_eop_config =
 160                 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX);
 161 #endif
 162         state->global_lut_disregard_reg =
 163                 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX);
 164         state->packet_status_stall =
 165                 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX);
 166         /*
 167          * Get the values of the register-set per
 168          * lut.
 169          */
 170         for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) {
 171                 state->short_packet_lut_entry[i] =
 172                         csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX + i);
 173         }
 174         for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) {
 175                 state->long_packet_lut_entry[i] =
 176                         csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX + i);
 177         }
 178 }
 179
 180 /**
 181  * @brief Dump the csi rx be state.
 182  * Refer to "csi_rx_public.h" for details.
 183  */
 184 static inline void csi_rx_be_ctrl_dump_state(
 185                 const csi_rx_backend_ID_t ID,
 186                 csi_rx_be_ctrl_state_t *state)
 187 {
 188         uint32_t i;
 189
 190         ia_css_print("CSI RX BE STATE Controller %d Enable 0x%x \n", ID, state->enable);
 191         ia_css_print("CSI RX BE STATE Controller %d Status 0x%x \n", ID, state->status);
 192
 193         for(i = 0; i <N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
 194                 ia_css_print("CSI RX BE STATE Controller %d comp format reg vc%d value 0x%x \n", ID, i, state->status);
 195         }
 196         ia_css_print("CSI RX BE STATE Controller %d RAW16 0x%x \n", ID, state->raw16);
 197         ia_css_print("CSI RX BE STATE Controller %d RAW18 0x%x \n", ID, state->raw18);
 198         ia_css_print("CSI RX BE STATE Controller %d Force RAW8 0x%x \n", ID, state->force_raw8);
 199         ia_css_print("CSI RX BE STATE Controller %d IRQ state 0x%x \n", ID, state->irq_status);
 200 #if 0   /* ToDo:Getting device access error for this register */
 201         for(i = 0; i <N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
 202                 ia_css_print("CSI RX BE STATE Controller %d PEC ID %d custom pec 0x%x \n", ID, i, state->pec[i]);
 203         }
 204 #endif
 205         ia_css_print("CSI RX BE STATE Controller %d Global LUT diregard reg 0x%x \n", ID, state->global_lut_disregard_reg);
 206         ia_css_print("CSI RX BE STATE Controller %d packet stall reg 0x%x \n", ID, state->packet_status_stall);
 207         /*
 208          * Get the values of the register-set per
 209          * lut.
 210          */
 211         for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) {
 212                 ia_css_print("CSI RX BE STATE Controller ID %d Short packat entry %d shart packet lut id 0x%x \n", ID, i, state->short_packet_lut_entry[i]);
 213         }
 214         for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) {
 215                 ia_css_print("CSI RX BE STATE Controller ID %d Long packat entry %d Long packet lut id 0x%x \n", ID, i, state->long_packet_lut_entry[i]);
 216         }
 217 }
 218 /* end of NCI */
 219 /*****************************************************
 220  *
 221  * Device level interface (DLI).
 222  *
 223  *****************************************************/
 224 /**
 225  * @brief Load the register value.
 226  * Refer to "csi_rx_public.h" for details.
 227  */
 228 static inline hrt_data csi_rx_fe_ctrl_reg_load(
 229         const csi_rx_frontend_ID_t ID,
 230         const hrt_address reg)
 231 {
 232         assert(ID < N_CSI_RX_FRONTEND_ID);
 233         assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1);
 234         return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg*sizeof(hrt_data));
 235 }
 236
 237
 238 /**
 239  * @brief Store a value to the register.
 240  * Refer to "ibuf_ctrl_public.h" for details.
 241  */
 242 static inline void csi_rx_fe_ctrl_reg_store(
 243         const csi_rx_frontend_ID_t ID,
 244         const hrt_address reg,
 245         const hrt_data value)
 246 {
 247         assert(ID < N_CSI_RX_FRONTEND_ID);
 248         assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1);
 249
 250         ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
 251 }
 252 /**
 253  * @brief Load the register value.
 254  * Refer to "csi_rx_public.h" for details.
 255  */
 256 static inline hrt_data csi_rx_be_ctrl_reg_load(
 257         const csi_rx_backend_ID_t ID,
 258         const hrt_address reg)
 259 {
 260         assert(ID < N_CSI_RX_BACKEND_ID);
 261         assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1);
 262         return ia_css_device_load_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg*sizeof(hrt_data));
 263 }
 264
 265
 266 /**
 267  * @brief Store a value to the register.
 268  * Refer to "ibuf_ctrl_public.h" for details.
 269  */
 270 static inline void csi_rx_be_ctrl_reg_store(
 271         const csi_rx_backend_ID_t ID,
 272         const hrt_address reg,
 273         const hrt_data value)
 274 {
 275         assert(ID < N_CSI_RX_BACKEND_ID);
 276         assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1);
 277
 278         ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg*sizeof(hrt_data), value);
 279 }
 280 /** end of DLI */
 281
 282 #endif /* __CSI_RX_PRIVATE_H_INCLUDED__ */