2 * Support for Intel Camera Imaging ISP subsystem.
3 * Copyright (c) 2015, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #ifndef _HIVE_ISP_CSS_2401_IRQ_TYPES_HRT_H_
16 #define _HIVE_ISP_CSS_2401_IRQ_TYPES_HRT_H_
19 * These are the indices of each interrupt in the interrupt
20 * controller's registers. these can be used as the irq_id
21 * argument to the hrt functions irq_controller.h.
23 * The definitions are taken from <system>_defs.h
25 typedef enum hrt_isp_css_irq
{
26 hrt_isp_css_irq_gpio_pin_0
= HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID
,
27 hrt_isp_css_irq_gpio_pin_1
= HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID
,
28 hrt_isp_css_irq_gpio_pin_2
= HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID
,
29 hrt_isp_css_irq_gpio_pin_3
= HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID
,
30 hrt_isp_css_irq_gpio_pin_4
= HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID
,
31 hrt_isp_css_irq_gpio_pin_5
= HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID
,
32 hrt_isp_css_irq_gpio_pin_6
= HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID
,
33 hrt_isp_css_irq_gpio_pin_7
= HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID
,
34 hrt_isp_css_irq_gpio_pin_8
= HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID
,
35 hrt_isp_css_irq_gpio_pin_9
= HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID
,
36 hrt_isp_css_irq_gpio_pin_10
= HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID
,
37 hrt_isp_css_irq_gpio_pin_11
= HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID
,
38 hrt_isp_css_irq_sp
= HIVE_GP_DEV_IRQ_SP_BIT_ID
,
39 hrt_isp_css_irq_isp
= HIVE_GP_DEV_IRQ_ISP_BIT_ID
,
40 hrt_isp_css_irq_isys
= HIVE_GP_DEV_IRQ_ISYS_BIT_ID
,
41 hrt_isp_css_irq_isel
= HIVE_GP_DEV_IRQ_ISEL_BIT_ID
,
42 hrt_isp_css_irq_ifmt
= HIVE_GP_DEV_IRQ_IFMT_BIT_ID
,
43 hrt_isp_css_irq_sp_stream_mon
= HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID
,
44 hrt_isp_css_irq_isp_stream_mon
= HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID
,
45 hrt_isp_css_irq_mod_stream_mon
= HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID
,
46 hrt_isp_css_irq_is2401
= HIVE_GP_DEV_IRQ_IS2401_BIT_ID
,
47 hrt_isp_css_irq_isp_bamem_error
= HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID
,
48 hrt_isp_css_irq_isp_dmem_error
= HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID
,
49 hrt_isp_css_irq_sp_icache_mem_error
= HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID
,
50 hrt_isp_css_irq_sp_dmem_error
= HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID
,
51 hrt_isp_css_irq_mmu_cache_mem_error
= HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID
,
52 hrt_isp_css_irq_gp_timer_0
= HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID
,
53 hrt_isp_css_irq_gp_timer_1
= HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID
,
54 hrt_isp_css_irq_sw_pin_0
= HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID
,
55 hrt_isp_css_irq_sw_pin_1
= HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID
,
56 hrt_isp_css_irq_dma
= HIVE_GP_DEV_IRQ_DMA_BIT_ID
,
57 hrt_isp_css_irq_sp_stream_mon_b
= HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID
,
58 /* this must (obviously) be the last on in the enum */
59 hrt_isp_css_irq_num_irqs
62 typedef enum hrt_isp_css_irq_status
{
63 hrt_isp_css_irq_status_error
,
64 hrt_isp_css_irq_status_more_irqs
,
65 hrt_isp_css_irq_status_success
66 } hrt_isp_css_irq_status_t
;
68 #endif /* _HIVE_ISP_CSS_2401_IRQ_TYPES_HRT_H_ */