drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gdc_v2_defs.h

   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef HRT_GDC_v2_defs_h_
  16 #define HRT_GDC_v2_defs_h_
  17
  18 #define HRT_GDC_IS_V2
  19
  20 #define HRT_GDC_N                     1024 /* Top-level design constant, equal to the number of entries in the LUT      */
  21 #define HRT_GDC_FRAC_BITS               10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */
  22
  23 #define HRT_GDC_BLI_FRAC_BITS            4 /* Number of fractional bits for the bi-linear interpolation type            */
  24 #define HRT_GDC_BLI_COEF_ONE             (1 << HRT_GDC_BLI_FRAC_BITS)
  25
  26 #define HRT_GDC_BCI_COEF_BITS           14 /* 14 bits per coefficient                                                   */
  27 #define HRT_GDC_BCI_COEF_ONE             (1 << (HRT_GDC_BCI_COEF_BITS-2))  /* We represent signed 10 bit coefficients.  */
  28                                                                         /* The supported range is [-256, .., +256]      */
  29                                                                         /* in 14-bit signed notation,                   */
  30                                                                         /* We need all ten bits (MSB must be zero).     */
  31                                                                         /* -s is inserted to solve this issue, and      */
  32                                                                         /* therefore "1" is equal to +256.              */
  33 #define HRT_GDC_BCI_COEF_MASK            ((1 << HRT_GDC_BCI_COEF_BITS) - 1)
  34
  35 #define HRT_GDC_LUT_BYTES                (HRT_GDC_N*4*2)                /* 1024 addresses, 4 coefficients per address,  */
  36                                                                         /* 2 bytes per coefficient                      */
  37
  38 #define _HRT_GDC_REG_ALIGN               4
  39
  40   //     31  30  29    25 24                     0
  41   //  |-----|---|--------|------------------------|
  42   //  | CMD | C | Reg_ID |        Value           |
  43
  44
  45   // There are just two commands possible for the GDC block:
  46   // 1 - Configure reg
  47   // 0 - Data token
  48
  49   // C      - Reserved bit
  50   //          Used in protocol to indicate whether it is C-run or other type of runs
  51   //          In case of C-run, this bit has a value of 1, for all the other runs, it is 0.
  52
  53   // Reg_ID - Address of the register to be configured
  54
  55   // Value  - Value to store to the addressed register, maximum of 24 bits
  56
  57   // Configure reg command is not followed by any other token.
  58   // The address of the register and the data to be filled in is contained in the same token
  59
  60   // When the first data token is received, it must be:
  61   //   1. FRX and FRY (device configured in one of the  scaling modes) ***DEFAULT MODE***, or,
  62   //   2. P0'X        (device configured in one of the tetragon modes)
  63   // After the first data token is received, pre-defined number of tokens with the following meaning follow:
  64   //   1. two  tokens: SRC address ; DST address
  65   //   2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address
  66
  67 #define HRT_GDC_CONFIG_CMD             1
  68 #define HRT_GDC_DATA_CMD               0
  69
  70
  71 #define HRT_GDC_CMD_POS               31
  72 #define HRT_GDC_CMD_BITS               1
  73 #define HRT_GDC_CRUN_POS              30
  74 #define HRT_GDC_REG_ID_POS            25
  75 #define HRT_GDC_REG_ID_BITS            5
  76 #define HRT_GDC_DATA_POS               0
  77 #define HRT_GDC_DATA_BITS             25
  78
  79 #define HRT_GDC_FRYIPXFRX_BITS        26
  80 #define HRT_GDC_P0X_BITS              23
  81
  82
  83 #define HRT_GDC_MAX_OXDIM           (8192-64)
  84 #define HRT_GDC_MAX_OYDIM           4095
  85 #define HRT_GDC_MAX_IXDIM           (8192-64)
  86 #define HRT_GDC_MAX_IYDIM           4095
  87 #define HRT_GDC_MAX_DS_FAC            16
  88 #define HRT_GDC_MAX_DX                 (HRT_GDC_MAX_DS_FAC*HRT_GDC_N - 1)
  89 #define HRT_GDC_MAX_DY                 HRT_GDC_MAX_DX
  90
  91
  92 /* GDC lookup tables entries are 10 bits values, but they're
  93    stored 2 by 2 as 32 bit values, yielding 16 bits per entry.
  94    A GDC lookup table contains 64 * 4 elements */
  95
  96 #define HRT_GDC_PERF_1_1_pix          0
  97 #define HRT_GDC_PERF_2_1_pix          1
  98 #define HRT_GDC_PERF_1_2_pix          2
  99 #define HRT_GDC_PERF_2_2_pix          3
 100
 101 #define HRT_GDC_NND_MODE              0
 102 #define HRT_GDC_BLI_MODE              1
 103 #define HRT_GDC_BCI_MODE              2
 104 #define HRT_GDC_LUT_MODE              3
 105
 106 #define HRT_GDC_SCAN_STB              0
 107 #define HRT_GDC_SCAN_STR              1
 108
 109 #define HRT_GDC_MODE_SCALING          0
 110 #define HRT_GDC_MODE_TETRAGON         1
 111
 112 #define HRT_GDC_LUT_COEFF_OFFSET     16
 113 #define HRT_GDC_FRY_BIT_OFFSET       16
 114 // FRYIPXFRX is the only register where we store two values in one field,
 115 // to save one token in the scaling protocol.
 116 // Like this, we have three tokens in the scaling protocol,
 117 // Otherwise, we would have had four.
 118 // The register bit-map is:
 119 //   31  26 25      16 15  10 9        0
 120 //  |------|----------|------|----------|
 121 //  | XXXX |   FRY    |  IPX |   FRX    |
 122
 123
 124 #define HRT_GDC_CE_FSM0_POS           0
 125 #define HRT_GDC_CE_FSM0_LEN           2
 126 #define HRT_GDC_CE_OPY_POS            2
 127 #define HRT_GDC_CE_OPY_LEN           14
 128 #define HRT_GDC_CE_OPX_POS           16
 129 #define HRT_GDC_CE_OPX_LEN           16
 130 // CHK_ENGINE register bit-map:
 131 //   31            16 15        2 1  0
 132 //  |----------------|-----------|----|
 133 //  |      OPX       |    OPY    |FSM0|
 134 // However, for the time being at least,
 135 // this implementation is meaningless in hss model,
 136 // So, we just return 0
 137
 138
 139 #define HRT_GDC_CHK_ENGINE_IDX        0
 140 #define HRT_GDC_WOIX_IDX              1
 141 #define HRT_GDC_WOIY_IDX              2
 142 #define HRT_GDC_BPP_IDX               3
 143 #define HRT_GDC_FRYIPXFRX_IDX         4
 144 #define HRT_GDC_OXDIM_IDX             5
 145 #define HRT_GDC_OYDIM_IDX             6
 146 #define HRT_GDC_SRC_ADDR_IDX          7
 147 #define HRT_GDC_SRC_END_ADDR_IDX      8
 148 #define HRT_GDC_SRC_WRAP_ADDR_IDX     9
 149 #define HRT_GDC_SRC_STRIDE_IDX       10
 150 #define HRT_GDC_DST_ADDR_IDX         11
 151 #define HRT_GDC_DST_STRIDE_IDX       12
 152 #define HRT_GDC_DX_IDX               13
 153 #define HRT_GDC_DY_IDX               14
 154 #define HRT_GDC_P0X_IDX              15
 155 #define HRT_GDC_P0Y_IDX              16
 156 #define HRT_GDC_P1X_IDX              17
 157 #define HRT_GDC_P1Y_IDX              18
 158 #define HRT_GDC_P2X_IDX              19
 159 #define HRT_GDC_P2Y_IDX              20
 160 #define HRT_GDC_P3X_IDX              21
 161 #define HRT_GDC_P3Y_IDX              22
 162 #define HRT_GDC_PERF_POINT_IDX       23  // 1x1 ; 1x2 ; 2x1 ; 2x2 pixels per cc
 163 #define HRT_GDC_INTERP_TYPE_IDX      24  // NND ; BLI ; BCI ; LUT
 164 #define HRT_GDC_SCAN_IDX             25  // 0 = STB (Slide To Bottom) ; 1 = STR (Slide To Right)
 165 #define HRT_GDC_PROC_MODE_IDX        26  // 0 = Scaling ; 1 = Tetragon
 166
 167 #define HRT_GDC_LUT_IDX              32
 168
 169
 170 #endif /* HRT_GDC_v2_defs_h_ */