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git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_system_defs.h
2 * Support for Intel Camera Imaging ISP subsystem.
3 * Copyright (c) 2015, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #ifndef _input_system_defs_h
16 #define _input_system_defs_h
18 /* csi controller modes */
19 #define HIVE_CSI_CONFIG_MAIN 0
20 #define HIVE_CSI_CONFIG_STEREO1 4
21 #define HIVE_CSI_CONFIG_STEREO2 8
23 /* general purpose register IDs */
25 /* Stream Multicast select modes */
26 #define HIVE_ISYS_GPREG_MULTICAST_A_IDX 0
27 #define HIVE_ISYS_GPREG_MULTICAST_B_IDX 1
28 #define HIVE_ISYS_GPREG_MULTICAST_C_IDX 2
30 /* Stream Mux select modes */
31 #define HIVE_ISYS_GPREG_MUX_IDX 3
33 /* streaming monitor status and control */
34 #define HIVE_ISYS_GPREG_STRMON_STAT_IDX 4
35 #define HIVE_ISYS_GPREG_STRMON_COND_IDX 5
36 #define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX 6
37 #define HIVE_ISYS_GPREG_SRST_IDX 7
38 #define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX 8
39 #define HIVE_ISYS_GPREG_REG_PORT_A_IDX 9
40 #define HIVE_ISYS_GPREG_REG_PORT_B_IDX 10
42 /* Bit numbers of the soft reset register */
43 #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT 0
44 #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT 1
45 #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT 2
46 #define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT 3
47 #define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT 4
48 #define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT 5
49 #define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT 6
50 #define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT 7
51 #define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT 8
52 #define HIVE_ISYS_GPREG_SRST_ACQ_BIT 9
53 /* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */
54 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT 10 /*LSB for 5bit vector */
55 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT 10
56 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT 11
57 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT 12
58 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT 13
59 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT 14
61 #define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT 15
62 #define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT 16
63 #define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT 17
64 #define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT 18 // includes CIO conv
65 #define HIVE_ISYS_GPREG_SRST_DMA_BIT 19
66 #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT 20
67 #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT 21
68 #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT 22
69 #define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT 23
70 #define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT 24
72 #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT 0
73 #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT 1
74 #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT 2
75 #define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT 3
76 #define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT 4
77 #define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT 5
79 /* streaming monitor port id's */
80 #define HIVE_ISYS_STR_MON_PORT_CAPA 0
81 #define HIVE_ISYS_STR_MON_PORT_CAPB 1
82 #define HIVE_ISYS_STR_MON_PORT_CAPC 2
83 #define HIVE_ISYS_STR_MON_PORT_ACQ 3
84 #define HIVE_ISYS_STR_MON_PORT_CSS_GENSH 4
85 #define HIVE_ISYS_STR_MON_PORT_SF_GENSH 5
86 #define HIVE_ISYS_STR_MON_PORT_SP2ISYS 6
87 #define HIVE_ISYS_STR_MON_PORT_ISYS2SP 7
88 #define HIVE_ISYS_STR_MON_PORT_PIXA 8
89 #define HIVE_ISYS_STR_MON_PORT_PIXB 9
91 /* interrupt bit ID's */
92 #define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID 0
93 #define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID 1
94 #define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID 2
95 #define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID 3
96 #define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID 4
97 #define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID 5
98 #define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP 6
99 #define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP 7
100 /*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/
101 #define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP 8
102 #define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP 9
103 /*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/
104 #define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP 10
105 #define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP 11
106 /*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/
107 #define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH 12
108 /*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/
109 #define HIVE_ISYS_IRQ_INP_CTRL_CAPA 13
110 #define HIVE_ISYS_IRQ_INP_CTRL_CAPB 14
111 #define HIVE_ISYS_IRQ_INP_CTRL_CAPC 15
112 #define HIVE_ISYS_IRQ_CIO2AHB 16
113 #define HIVE_ISYS_IRQ_DMA_BIT_ID 17
114 #define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID 18
115 #define HIVE_ISYS_IRQ_NUM_BITS 19
118 #define HIVE_ISYS_DMA_CHANNEL 0
119 #define HIVE_ISYS_DMA_IBUF_DDR_CONN 0
120 #define HIVE_ISYS_DMA_HEIGHT 1
121 #define HIVE_ISYS_DMA_ELEMS 1 /* both master buses of same width */
122 #define HIVE_ISYS_DMA_STRIDE 0 /* no stride required as height is fixed to 1 */
123 #define HIVE_ISYS_DMA_CROP 0 /* no cropping */
124 #define HIVE_ISYS_DMA_EXTENSION 0 /* no extension as elem width is same on both side */
126 #endif /* _input_system_defs_h */