drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/sp.c

   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2010-2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include "sp.h"
  16
  17 #ifndef __INLINE_SP__
  18 #include "sp_private.h"
  19 #endif /* __INLINE_SP__ */
  20
  21 #include "assert_support.h"
  22
  23 void cnd_sp_irq_enable(
  24         const sp_ID_t           ID,
  25         const bool              cnd)
  26 {
  27         if (cnd) {
  28                 sp_ctrl_setbit(ID, SP_IRQ_READY_REG, SP_IRQ_READY_BIT);
  29 /* Enabling the IRQ immediately triggers an interrupt, clear it */
  30                 sp_ctrl_setbit(ID, SP_IRQ_CLEAR_REG, SP_IRQ_CLEAR_BIT);
  31         } else {
  32                 sp_ctrl_clearbit(ID, SP_IRQ_READY_REG, SP_IRQ_READY_BIT);
  33         }
  34 }
  35
  36 void sp_get_state(
  37         const sp_ID_t                   ID,
  38         sp_state_t                              *state,
  39         sp_stall_t                              *stall)
  40 {
  41         hrt_data sc = sp_ctrl_load(ID, SP_SC_REG);
  42
  43         assert(state != NULL);
  44         assert(stall != NULL);
  45
  46         state->pc = sp_ctrl_load(ID, SP_PC_REG);
  47         state->status_register = sc;
  48         state->is_broken   = (sc & (1U << SP_BROKEN_BIT)) != 0;
  49         state->is_idle     = (sc & (1U << SP_IDLE_BIT)) != 0;
  50         state->is_sleeping = (sc & (1U << SP_SLEEPING_BIT)) != 0;
  51         state->is_stalling = (sc & (1U << SP_STALLING_BIT)) != 0;
  52         stall->fifo0 =
  53                 !sp_ctrl_getbit(ID, SP_FIFO0_SINK_REG, SP_FIFO0_SINK_BIT);
  54         stall->fifo1 =
  55                 !sp_ctrl_getbit(ID, SP_FIFO1_SINK_REG, SP_FIFO1_SINK_BIT);
  56         stall->fifo2 =
  57                 !sp_ctrl_getbit(ID, SP_FIFO2_SINK_REG, SP_FIFO2_SINK_BIT);
  58         stall->fifo3 =
  59                 !sp_ctrl_getbit(ID, SP_FIFO3_SINK_REG, SP_FIFO3_SINK_BIT);
  60         stall->fifo4 =
  61                 !sp_ctrl_getbit(ID, SP_FIFO4_SINK_REG, SP_FIFO4_SINK_BIT);
  62         stall->fifo5 =
  63                 !sp_ctrl_getbit(ID, SP_FIFO5_SINK_REG, SP_FIFO5_SINK_BIT);
  64         stall->fifo6 =
  65                 !sp_ctrl_getbit(ID, SP_FIFO6_SINK_REG, SP_FIFO6_SINK_BIT);
  66         stall->fifo7 =
  67                 !sp_ctrl_getbit(ID, SP_FIFO7_SINK_REG, SP_FIFO7_SINK_BIT);
  68         stall->fifo8 =
  69                 !sp_ctrl_getbit(ID, SP_FIFO8_SINK_REG, SP_FIFO8_SINK_BIT);
  70         stall->fifo9 =
  71                 !sp_ctrl_getbit(ID, SP_FIFO9_SINK_REG, SP_FIFO9_SINK_BIT);
  72         stall->fifoa =
  73                 !sp_ctrl_getbit(ID, SP_FIFOA_SINK_REG, SP_FIFOA_SINK_BIT);
  74         stall->dmem =
  75                 !sp_ctrl_getbit(ID, SP_DMEM_SINK_REG, SP_DMEM_SINK_BIT);
  76         stall->control_master =
  77                 !sp_ctrl_getbit(ID, SP_CTRL_MT_SINK_REG, SP_CTRL_MT_SINK_BIT);
  78         stall->icache_master =
  79                 !sp_ctrl_getbit(ID, SP_ICACHE_MT_SINK_REG,
  80                         SP_ICACHE_MT_SINK_BIT);
  81 }