2 * Support for Intel Camera Imaging ISP subsystem.
3 * Copyright (c) 2015, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #ifndef __INPUT_SYSTEM_PUBLIC_H_INCLUDED__
16 #define __INPUT_SYSTEM_PUBLIC_H_INCLUDED__
18 #include <type_support.h>
19 #ifdef USE_INPUT_SYSTEM_VERSION_2401
20 #include "isys_public.h"
23 typedef struct input_system_state_s input_system_state_t
;
24 typedef struct receiver_state_s receiver_state_t
;
26 /*! Read the state of INPUT_SYSTEM[ID]
28 \param ID[in] INPUT_SYSTEM identifier
29 \param state[out] input system state structure
31 \return none, state = INPUT_SYSTEM[ID].state
33 extern void input_system_get_state(
34 const input_system_ID_t ID
,
35 input_system_state_t
*state
);
37 /*! Read the state of RECEIVER[ID]
39 \param ID[in] RECEIVER identifier
40 \param state[out] receiver state structure
42 \return none, state = RECEIVER[ID].state
44 extern void receiver_get_state(
46 receiver_state_t
*state
);
48 /*! Flag whether a MIPI format is YUV420
50 \param mipi_format[in] MIPI format
52 \return mipi_format == YUV420
54 extern bool is_mipi_format_yuv420(
55 const mipi_format_t mipi_format
);
57 /*! Set compression parameters for cfg[cfg_ID] of RECEIVER[ID]
59 \param ID[in] RECEIVER identifier
60 \param cfg_ID[in] Configuration identifier
61 \param comp[in] Compression method
62 \param pred[in] Predictor method
64 \NOTE: the storage of compression configuration is
65 implementation specific. The config can be
66 carried either on MIPI ports or on MIPI channels
68 \return none, RECEIVER[ID].cfg[cfg_ID] = {comp, pred}
70 extern void receiver_set_compression(
72 const unsigned int cfg_ID
,
73 const mipi_compressor_t comp
,
74 const mipi_predictor_t pred
);
76 /*! Enable PORT[port_ID] of RECEIVER[ID]
78 \param ID[in] RECEIVER identifier
79 \param port_ID[in] mipi PORT identifier
80 \param cnd[in] irq predicate
82 \return None, enable(RECEIVER[ID].PORT[port_ID])
84 extern void receiver_port_enable(
86 const mipi_port_ID_t port_ID
,
89 /*! Flag if PORT[port_ID] of RECEIVER[ID] is enabled
91 \param ID[in] RECEIVER identifier
92 \param port_ID[in] mipi PORT identifier
94 \return enable(RECEIVER[ID].PORT[port_ID]) == true
96 extern bool is_receiver_port_enabled(
98 const mipi_port_ID_t port_ID
);
100 /*! Enable the IRQ channels of PORT[port_ID] of RECEIVER[ID]
102 \param ID[in] RECEIVER identifier
103 \param port_ID[in] mipi PORT identifier
104 \param irq_info[in] irq channels
106 \return None, enable(RECEIVER[ID].PORT[port_ID].irq_info)
108 extern void receiver_irq_enable(
110 const mipi_port_ID_t port_ID
,
111 const rx_irq_info_t irq_info
);
113 /*! Return the IRQ status of PORT[port_ID] of RECEIVER[ID]
115 \param ID[in] RECEIVER identifier
116 \param port_ID[in] mipi PORT identifier
118 \return RECEIVER[ID].PORT[port_ID].irq_info
120 extern rx_irq_info_t
receiver_get_irq_info(
122 const mipi_port_ID_t port_ID
);
124 /*! Clear the IRQ status of PORT[port_ID] of RECEIVER[ID]
126 \param ID[in] RECEIVER identifier
127 \param port_ID[in] mipi PORT identifier
128 \param irq_info[in] irq status
130 \return None, clear(RECEIVER[ID].PORT[port_ID].irq_info)
132 extern void receiver_irq_clear(
134 const mipi_port_ID_t port_ID
,
135 const rx_irq_info_t irq_info
);
137 /*! Write to a control register of INPUT_SYSTEM[ID]
139 \param ID[in] INPUT_SYSTEM identifier
140 \param reg[in] register index
141 \param value[in] The data to be written
143 \return none, INPUT_SYSTEM[ID].ctrl[reg] = value
145 STORAGE_CLASS_INPUT_SYSTEM_H
void input_system_reg_store(
146 const input_system_ID_t ID
,
147 const hrt_address reg
,
148 const hrt_data value
);
150 /*! Read from a control register of INPUT_SYSTEM[ID]
152 \param ID[in] INPUT_SYSTEM identifier
153 \param reg[in] register index
154 \param value[in] The data to be written
156 \return INPUT_SYSTEM[ID].ctrl[reg]
158 STORAGE_CLASS_INPUT_SYSTEM_H hrt_data
input_system_reg_load(
159 const input_system_ID_t ID
,
160 const hrt_address reg
);
162 /*! Write to a control register of RECEIVER[ID]
164 \param ID[in] RECEIVER identifier
165 \param reg[in] register index
166 \param value[in] The data to be written
168 \return none, RECEIVER[ID].ctrl[reg] = value
170 STORAGE_CLASS_INPUT_SYSTEM_H
void receiver_reg_store(
172 const hrt_address reg
,
173 const hrt_data value
);
175 /*! Read from a control register of RECEIVER[ID]
177 \param ID[in] RECEIVER identifier
178 \param reg[in] register index
179 \param value[in] The data to be written
181 \return RECEIVER[ID].ctrl[reg]
183 STORAGE_CLASS_INPUT_SYSTEM_H hrt_data
receiver_reg_load(
185 const hrt_address reg
);
187 /*! Write to a control register of PORT[port_ID] of RECEIVER[ID]
189 \param ID[in] RECEIVER identifier
190 \param port_ID[in] mipi PORT identifier
191 \param reg[in] register index
192 \param value[in] The data to be written
194 \return none, RECEIVER[ID].PORT[port_ID].ctrl[reg] = value
196 STORAGE_CLASS_INPUT_SYSTEM_H
void receiver_port_reg_store(
198 const mipi_port_ID_t port_ID
,
199 const hrt_address reg
,
200 const hrt_data value
);
202 /*! Read from a control register PORT[port_ID] of of RECEIVER[ID]
204 \param ID[in] RECEIVER identifier
205 \param port_ID[in] mipi PORT identifier
206 \param reg[in] register index
207 \param value[in] The data to be written
209 \return RECEIVER[ID].PORT[port_ID].ctrl[reg]
211 STORAGE_CLASS_INPUT_SYSTEM_H hrt_data
receiver_port_reg_load(
213 const mipi_port_ID_t port_ID
,
214 const hrt_address reg
);
216 /*! Write to a control register of SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID]
218 \param ID[in] INPUT_SYSTEM identifier
219 \param port_ID[in] sub system identifier
220 \param reg[in] register index
221 \param value[in] The data to be written
223 \return none, INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg] = value
225 STORAGE_CLASS_INPUT_SYSTEM_H
void input_system_sub_system_reg_store(
226 const input_system_ID_t ID
,
227 const sub_system_ID_t sub_ID
,
228 const hrt_address reg
,
229 const hrt_data value
);
231 /*! Read from a control register SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID]
233 \param ID[in] INPUT_SYSTEM identifier
234 \param port_ID[in] sub system identifier
235 \param reg[in] register index
236 \param value[in] The data to be written
238 \return INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg]
240 STORAGE_CLASS_INPUT_SYSTEM_H hrt_data
input_system_sub_system_reg_load(
241 const input_system_ID_t ID
,
242 const sub_system_ID_t sub_ID
,
243 const hrt_address reg
);
247 ///////////////////////////////////////////////////////////////////////////
249 // Functions for configuration phase on input system.
251 ///////////////////////////////////////////////////////////////////////////
253 // Function that resets current configuration.
254 // remove the argument since it should be private.
255 input_system_error_t
input_system_configuration_reset(void);
257 // Function that commits current configuration.
258 // remove the argument since it should be private.
259 input_system_error_t
input_system_configuration_commit(void);
261 ///////////////////////////////////////////////////////////////////////////
264 // (encoded generic function)
266 // - decoding name and agruments into the generic (channel) configuration
269 ///////////////////////////////////////////////////////////////////////////
272 // FIFO channel config function user
274 input_system_error_t
input_system_csi_fifo_channel_cfg(
276 input_system_csi_port_t port
,
277 backend_channel_cfg_t backend_ch
,
278 target_cfg2400_t target
281 input_system_error_t
input_system_csi_fifo_channel_with_counting_cfg(
284 input_system_csi_port_t port
,
285 backend_channel_cfg_t backend_ch
,
286 uint32_t mem_region_size
,
287 uint32_t nof_mem_regions
,
288 target_cfg2400_t target
292 // SRAM channel config function user
294 input_system_error_t
input_system_csi_sram_channel_cfg(
296 input_system_csi_port_t port
,
297 backend_channel_cfg_t backend_ch
,
298 uint32_t csi_mem_region_size
,
299 uint32_t csi_nof_mem_regions
,
300 target_cfg2400_t target
304 //XMEM channel config function user
306 input_system_error_t
input_system_csi_xmem_channel_cfg(
308 input_system_csi_port_t port
,
309 backend_channel_cfg_t backend_ch
,
310 uint32_t mem_region_size
,
311 uint32_t nof_mem_regions
,
312 uint32_t acq_mem_region_size
,
313 uint32_t acq_nof_mem_regions
,
314 target_cfg2400_t target
,
315 uint32_t nof_xmem_buffers
318 input_system_error_t
input_system_csi_xmem_capture_only_channel_cfg(
321 input_system_csi_port_t port
,
322 uint32_t csi_mem_region_size
,
323 uint32_t csi_nof_mem_regions
,
324 uint32_t acq_mem_region_size
,
325 uint32_t acq_nof_mem_regions
,
326 target_cfg2400_t target
329 input_system_error_t
input_system_csi_xmem_acquire_only_channel_cfg(
332 input_system_csi_port_t port
,
333 backend_channel_cfg_t backend_ch
,
334 uint32_t acq_mem_region_size
,
335 uint32_t acq_nof_mem_regions
,
336 target_cfg2400_t target
339 // Non - CSI channel config function user
341 input_system_error_t
input_system_prbs_channel_cfg(
345 uint32_t sync_gen_width
,
346 uint32_t sync_gen_height
,
347 uint32_t sync_gen_hblank_cycles
,
348 uint32_t sync_gen_vblank_cycles
,
349 target_cfg2400_t target
353 input_system_error_t
input_system_tpg_channel_cfg(
355 uint32_t nof_frames
,//not used yet
361 uint32_t sync_gen_width
,
362 uint32_t sync_gen_height
,
363 uint32_t sync_gen_hblank_cycles
,
364 uint32_t sync_gen_vblank_cycles
,
365 target_cfg2400_t target
369 input_system_error_t
input_system_gpfifo_channel_cfg(
372 target_cfg2400_t target
374 #endif /* #ifdef USE_INPUT_SYSTEM_VERSION_2401 */
376 #endif /* __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ */