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spi: Fix double "when"
[mirror_ubuntu-hirsute-kernel.git] / drivers / staging / media / atomisp / pci / atomisp2 / css2400 / runtime / debug / src / ia_css_debug.c
1 /*
2 * Support for Intel Camera Imaging ISP subsystem.
3 * Copyright (c) 2015, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #include "debug.h"
16 #include "memory_access.h"
17
18 #ifndef __INLINE_INPUT_SYSTEM__
19 #define __INLINE_INPUT_SYSTEM__
20 #endif
21 #ifndef __INLINE_IBUF_CTRL__
22 #define __INLINE_IBUF_CTRL__
23 #endif
24 #ifndef __INLINE_CSI_RX__
25 #define __INLINE_CSI_RX__
26 #endif
27 #ifndef __INLINE_PIXELGEN__
28 #define __INLINE_PIXELGEN__
29 #endif
30 #ifndef __INLINE_STREAM2MMIO__
31 #define __INLINE_STREAM2MMIO__
32 #endif
33
34 #include "ia_css_debug.h"
35 #include "ia_css_debug_pipe.h"
36 #include "ia_css_irq.h"
37 #include "ia_css_stream.h"
38 #include "ia_css_pipeline.h"
39 #include "ia_css_isp_param.h"
40 #include "sh_css_params.h"
41 #include "ia_css_bufq.h"
42 #ifdef ISP2401
43 #include "ia_css_queue.h"
44 #endif
45
46 #include "ia_css_isp_params.h"
47
48 #include "system_local.h"
49 #include "assert_support.h"
50 #include "print_support.h"
51 #include "string_support.h"
52 #ifdef ISP2401
53 #include "ia_css_system_ctrl.h"
54 #endif
55
56 #include "fifo_monitor.h"
57
58 #if !defined(HAS_NO_INPUT_FORMATTER)
59 #include "input_formatter.h"
60 #endif
61 #include "dma.h"
62 #include "irq.h"
63 #include "gp_device.h"
64 #include "sp.h"
65 #include "isp.h"
66 #include "type_support.h"
67 #include "math_support.h" /* CEIL_DIV */
68 #if defined(HAS_INPUT_FORMATTER_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401)
69 #include "input_system.h" /* input_formatter_reg_load */
70 #endif
71 #if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401)
72 #include "ia_css_tagger_common.h"
73 #endif
74
75 #include "sh_css_internal.h"
76 #if !defined(HAS_NO_INPUT_SYSTEM)
77 #include "ia_css_isys.h"
78 #endif
79 #include "sh_css_sp.h" /* sh_css_sp_get_debug_state() */
80
81 #include "css_trace.h" /* tracer */
82
83 #include "device_access.h" /* for ia_css_device_load_uint32 */
84
85 /* Include all kernel host interfaces for ISP1 */
86 #include "anr/anr_1.0/ia_css_anr.host.h"
87 #include "cnr/cnr_1.0/ia_css_cnr.host.h"
88 #include "csc/csc_1.0/ia_css_csc.host.h"
89 #include "de/de_1.0/ia_css_de.host.h"
90 #include "dp/dp_1.0/ia_css_dp.host.h"
91 #include "bnr/bnr_1.0/ia_css_bnr.host.h"
92 #include "fpn/fpn_1.0/ia_css_fpn.host.h"
93 #include "gc/gc_1.0/ia_css_gc.host.h"
94 #include "ob/ob_1.0/ia_css_ob.host.h"
95 #include "s3a/s3a_1.0/ia_css_s3a.host.h"
96 #include "sc/sc_1.0/ia_css_sc.host.h"
97 #include "tnr/tnr_1.0/ia_css_tnr.host.h"
98 #include "uds/uds_1.0/ia_css_uds_param.h"
99 #include "wb/wb_1.0/ia_css_wb.host.h"
100 #include "ynr/ynr_1.0/ia_css_ynr.host.h"
101
102 /* Include additional kernel host interfaces for ISP2 */
103 #include "aa/aa_2/ia_css_aa2.host.h"
104 #include "anr/anr_2/ia_css_anr2.host.h"
105 #include "cnr/cnr_2/ia_css_cnr2.host.h"
106 #include "de/de_2/ia_css_de2.host.h"
107 #include "gc/gc_2/ia_css_gc2.host.h"
108 #include "ynr/ynr_2/ia_css_ynr2.host.h"
109
110 /* Global variable to store the dtrace verbosity level */
111 unsigned int ia_css_debug_trace_level = IA_CSS_DEBUG_WARNING;
112
113 /* Assumes that IA_CSS_STREAM_FORMAT_BINARY_8 is last */
114 #define N_IA_CSS_STREAM_FORMAT (IA_CSS_STREAM_FORMAT_BINARY_8+1)
115
116 #define DPG_START "ia_css_debug_pipe_graph_dump_start "
117 #define DPG_END " ia_css_debug_pipe_graph_dump_end\n"
118
119 #define ENABLE_LINE_MAX_LENGTH (25)
120
121 #ifdef ISP2401
122 #define DBG_EXT_CMD_TRACE_PNTS_DUMP (1 << 8)
123 #define DBG_EXT_CMD_PUB_CFG_DUMP (1 << 9)
124 #define DBG_EXT_CMD_GAC_REG_DUMP (1 << 10)
125 #define DBG_EXT_CMD_GAC_ACB_REG_DUMP (1 << 11)
126 #define DBG_EXT_CMD_FIFO_DUMP (1 << 12)
127 #define DBG_EXT_CMD_QUEUE_DUMP (1 << 13)
128 #define DBG_EXT_CMD_DMA_DUMP (1 << 14)
129 #define DBG_EXT_CMD_MASK 0xAB0000CD
130
131 #endif
132 /*
133 * TODO:SH_CSS_MAX_SP_THREADS is not the max number of sp threads
134 * future rework should fix this and remove the define MAX_THREAD_NUM
135 */
136 #define MAX_THREAD_NUM (SH_CSS_MAX_SP_THREADS + SH_CSS_MAX_SP_INTERNAL_THREADS)
137
138 static struct pipe_graph_class {
139 bool do_init;
140 int height;
141 int width;
142 int eff_height;
143 int eff_width;
144 enum ia_css_stream_format stream_format;
145 } pg_inst = {true, 0, 0, 0, 0, N_IA_CSS_STREAM_FORMAT};
146
147 static const char * const queue_id_to_str[] = {
148 /* [SH_CSS_QUEUE_A_ID] =*/ "queue_A",
149 /* [SH_CSS_QUEUE_B_ID] =*/ "queue_B",
150 /* [SH_CSS_QUEUE_C_ID] =*/ "queue_C",
151 /* [SH_CSS_QUEUE_D_ID] =*/ "queue_D",
152 /* [SH_CSS_QUEUE_E_ID] =*/ "queue_E",
153 /* [SH_CSS_QUEUE_F_ID] =*/ "queue_F",
154 /* [SH_CSS_QUEUE_G_ID] =*/ "queue_G",
155 /* [SH_CSS_QUEUE_H_ID] =*/ "queue_H"
156 };
157
158 static const char * const pipe_id_to_str[] = {
159 /* [IA_CSS_PIPE_ID_PREVIEW] =*/ "preview",
160 /* [IA_CSS_PIPE_ID_COPY] =*/ "copy",
161 /* [IA_CSS_PIPE_ID_VIDEO] =*/ "video",
162 /* [IA_CSS_PIPE_ID_CAPTURE] =*/ "capture",
163 /* [IA_CSS_PIPE_ID_YUVPP] =*/ "yuvpp",
164 /* [IA_CSS_PIPE_ID_ACC] =*/ "accelerator"
165 };
166
167 static char dot_id_input_bin[SH_CSS_MAX_BINARY_NAME+10];
168 static char ring_buffer[200];
169
170 void ia_css_debug_dtrace(unsigned int level, const char *fmt, ...)
171 {
172 va_list ap;
173
174 va_start(ap, fmt);
175 ia_css_debug_vdtrace(level, fmt, ap);
176 va_end(ap);
177 }
178
179 static void debug_dump_long_array_formatted(
180 const sp_ID_t sp_id,
181 hrt_address stack_sp_addr,
182 unsigned stack_size)
183 {
184 unsigned int i;
185 uint32_t val;
186 uint32_t addr = (uint32_t) stack_sp_addr;
187 uint32_t stack_size_words = CEIL_DIV(stack_size, sizeof(uint32_t));
188
189 /* When size is not multiple of four, last word is only relevant for
190 * remaining bytes */
191 for (i = 0; i < stack_size_words; i++) {
192 val = sp_dmem_load_uint32(sp_id, (hrt_address)addr);
193 if ((i%8) == 0)
194 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n");
195
196 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "0x%08x ", val);
197 addr += sizeof(uint32_t);
198 }
199
200 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n");
201 }
202
203 static void debug_dump_sp_stack_info(
204 const sp_ID_t sp_id)
205 {
206 const struct ia_css_fw_info *fw;
207 unsigned int HIVE_ADDR_sp_threads_stack;
208 unsigned int HIVE_ADDR_sp_threads_stack_size;
209 uint32_t stack_sizes[MAX_THREAD_NUM];
210 uint32_t stack_sp_addr[MAX_THREAD_NUM];
211 unsigned int i;
212
213 fw = &sh_css_sp_fw;
214
215 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "sp_id(%u) stack info\n", sp_id);
216 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
217 "from objects stack_addr_offset:0x%x stack_size_offset:0x%x\n",
218 fw->info.sp.threads_stack,
219 fw->info.sp.threads_stack_size);
220
221 HIVE_ADDR_sp_threads_stack = fw->info.sp.threads_stack;
222 HIVE_ADDR_sp_threads_stack_size = fw->info.sp.threads_stack_size;
223
224 if (fw->info.sp.threads_stack == 0 ||
225 fw->info.sp.threads_stack_size == 0)
226 return;
227
228 (void) HIVE_ADDR_sp_threads_stack;
229 (void) HIVE_ADDR_sp_threads_stack_size;
230
231 sp_dmem_load(sp_id,
232 (unsigned int)sp_address_of(sp_threads_stack),
233 &stack_sp_addr, sizeof(stack_sp_addr));
234 sp_dmem_load(sp_id,
235 (unsigned int)sp_address_of(sp_threads_stack_size),
236 &stack_sizes, sizeof(stack_sizes));
237
238 for (i = 0 ; i < MAX_THREAD_NUM; i++) {
239 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
240 "thread: %u stack_addr: 0x%08x stack_size: %u\n",
241 i, stack_sp_addr[i], stack_sizes[i]);
242 debug_dump_long_array_formatted(sp_id, (hrt_address)stack_sp_addr[i],
243 stack_sizes[i]);
244 }
245 }
246
247 void ia_css_debug_dump_sp_stack_info(void)
248 {
249 debug_dump_sp_stack_info(SP0_ID);
250 }
251
252
253 void ia_css_debug_set_dtrace_level(const unsigned int trace_level)
254 {
255 ia_css_debug_trace_level = trace_level;
256 return;
257 }
258
259 unsigned int ia_css_debug_get_dtrace_level(void)
260 {
261 return ia_css_debug_trace_level;
262 }
263
264 static const char *debug_stream_format2str(const enum ia_css_stream_format stream_format)
265 {
266 switch (stream_format) {
267 case IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY:
268 return "yuv420-8-legacy";
269 case IA_CSS_STREAM_FORMAT_YUV420_8:
270 return "yuv420-8";
271 case IA_CSS_STREAM_FORMAT_YUV420_10:
272 return "yuv420-10";
273 case IA_CSS_STREAM_FORMAT_YUV420_16:
274 return "yuv420-16";
275 case IA_CSS_STREAM_FORMAT_YUV422_8:
276 return "yuv422-8";
277 case IA_CSS_STREAM_FORMAT_YUV422_10:
278 return "yuv422-10";
279 case IA_CSS_STREAM_FORMAT_YUV422_16:
280 return "yuv422-16";
281 case IA_CSS_STREAM_FORMAT_RGB_444:
282 return "rgb444";
283 case IA_CSS_STREAM_FORMAT_RGB_555:
284 return "rgb555";
285 case IA_CSS_STREAM_FORMAT_RGB_565:
286 return "rgb565";
287 case IA_CSS_STREAM_FORMAT_RGB_666:
288 return "rgb666";
289 case IA_CSS_STREAM_FORMAT_RGB_888:
290 return "rgb888";
291 case IA_CSS_STREAM_FORMAT_RAW_6:
292 return "raw6";
293 case IA_CSS_STREAM_FORMAT_RAW_7:
294 return "raw7";
295 case IA_CSS_STREAM_FORMAT_RAW_8:
296 return "raw8";
297 case IA_CSS_STREAM_FORMAT_RAW_10:
298 return "raw10";
299 case IA_CSS_STREAM_FORMAT_RAW_12:
300 return "raw12";
301 case IA_CSS_STREAM_FORMAT_RAW_14:
302 return "raw14";
303 case IA_CSS_STREAM_FORMAT_RAW_16:
304 return "raw16";
305 case IA_CSS_STREAM_FORMAT_BINARY_8:
306 return "binary8";
307 case IA_CSS_STREAM_FORMAT_GENERIC_SHORT1:
308 return "generic-short1";
309 case IA_CSS_STREAM_FORMAT_GENERIC_SHORT2:
310 return "generic-short2";
311 case IA_CSS_STREAM_FORMAT_GENERIC_SHORT3:
312 return "generic-short3";
313 case IA_CSS_STREAM_FORMAT_GENERIC_SHORT4:
314 return "generic-short4";
315 case IA_CSS_STREAM_FORMAT_GENERIC_SHORT5:
316 return "generic-short5";
317 case IA_CSS_STREAM_FORMAT_GENERIC_SHORT6:
318 return "generic-short6";
319 case IA_CSS_STREAM_FORMAT_GENERIC_SHORT7:
320 return "generic-short7";
321 case IA_CSS_STREAM_FORMAT_GENERIC_SHORT8:
322 return "generic-short8";
323 case IA_CSS_STREAM_FORMAT_YUV420_8_SHIFT:
324 return "yuv420-8-shift";
325 case IA_CSS_STREAM_FORMAT_YUV420_10_SHIFT:
326 return "yuv420-10-shift";
327 case IA_CSS_STREAM_FORMAT_EMBEDDED:
328 return "embedded-8";
329 case IA_CSS_STREAM_FORMAT_USER_DEF1:
330 return "user-def-8-type-1";
331 case IA_CSS_STREAM_FORMAT_USER_DEF2:
332 return "user-def-8-type-2";
333 case IA_CSS_STREAM_FORMAT_USER_DEF3:
334 return "user-def-8-type-3";
335 case IA_CSS_STREAM_FORMAT_USER_DEF4:
336 return "user-def-8-type-4";
337 case IA_CSS_STREAM_FORMAT_USER_DEF5:
338 return "user-def-8-type-5";
339 case IA_CSS_STREAM_FORMAT_USER_DEF6:
340 return "user-def-8-type-6";
341 case IA_CSS_STREAM_FORMAT_USER_DEF7:
342 return "user-def-8-type-7";
343 case IA_CSS_STREAM_FORMAT_USER_DEF8:
344 return "user-def-8-type-8";
345
346 default:
347 assert(!"Unknown stream format");
348 return "unknown-stream-format";
349 }
350 };
351
352 static const char *debug_frame_format2str(const enum ia_css_frame_format frame_format)
353 {
354 switch (frame_format) {
355
356 case IA_CSS_FRAME_FORMAT_NV11:
357 return "NV11";
358 case IA_CSS_FRAME_FORMAT_NV12:
359 return "NV12";
360 case IA_CSS_FRAME_FORMAT_NV12_16:
361 return "NV12_16";
362 case IA_CSS_FRAME_FORMAT_NV12_TILEY:
363 return "NV12_TILEY";
364 case IA_CSS_FRAME_FORMAT_NV16:
365 return "NV16";
366 case IA_CSS_FRAME_FORMAT_NV21:
367 return "NV21";
368 case IA_CSS_FRAME_FORMAT_NV61:
369 return "NV61";
370 case IA_CSS_FRAME_FORMAT_YV12:
371 return "YV12";
372 case IA_CSS_FRAME_FORMAT_YV16:
373 return "YV16";
374 case IA_CSS_FRAME_FORMAT_YUV420:
375 return "YUV420";
376 case IA_CSS_FRAME_FORMAT_YUV420_16:
377 return "YUV420_16";
378 case IA_CSS_FRAME_FORMAT_YUV422:
379 return "YUV422";
380 case IA_CSS_FRAME_FORMAT_YUV422_16:
381 return "YUV422_16";
382 case IA_CSS_FRAME_FORMAT_UYVY:
383 return "UYVY";
384 case IA_CSS_FRAME_FORMAT_YUYV:
385 return "YUYV";
386 case IA_CSS_FRAME_FORMAT_YUV444:
387 return "YUV444";
388 case IA_CSS_FRAME_FORMAT_YUV_LINE:
389 return "YUV_LINE";
390 case IA_CSS_FRAME_FORMAT_RAW:
391 return "RAW";
392 case IA_CSS_FRAME_FORMAT_RGB565:
393 return "RGB565";
394 case IA_CSS_FRAME_FORMAT_PLANAR_RGB888:
395 return "PLANAR_RGB888";
396 case IA_CSS_FRAME_FORMAT_RGBA888:
397 return "RGBA888";
398 case IA_CSS_FRAME_FORMAT_QPLANE6:
399 return "QPLANE6";
400 case IA_CSS_FRAME_FORMAT_BINARY_8:
401 return "BINARY_8";
402 case IA_CSS_FRAME_FORMAT_MIPI:
403 return "MIPI";
404 case IA_CSS_FRAME_FORMAT_RAW_PACKED:
405 return "RAW_PACKED";
406 case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8:
407 return "CSI_MIPI_YUV420_8";
408 case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8:
409 return "CSI_MIPI_LEGACY_YUV420_8";
410 case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10:
411 return "CSI_MIPI_YUV420_10";
412
413 default:
414 assert(!"Unknown frame format");
415 return "unknown-frame-format";
416 }
417 }
418
419 static void debug_print_sp_state(const sp_state_t *state, const char *cell)
420 {
421 assert(cell != NULL);
422 assert(state != NULL);
423
424 ia_css_debug_dtrace(2, "%s state:\n", cell);
425 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc);
426 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register",
427 state->status_register);
428 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken);
429 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle);
430 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping",
431 state->is_sleeping);
432 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling",
433 state->is_stalling);
434 return;
435 }
436
437 static void debug_print_isp_state(const isp_state_t *state, const char *cell)
438 {
439 assert(state != NULL);
440 assert(cell != NULL);
441
442 ia_css_debug_dtrace(2, "%s state:\n", cell);
443 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc);
444 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register",
445 state->status_register);
446 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken);
447 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle);
448 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping",
449 state->is_sleeping);
450 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling",
451 state->is_stalling);
452 return;
453 }
454
455 void ia_css_debug_dump_isp_state(void)
456 {
457 isp_state_t state;
458 isp_stall_t stall;
459
460 isp_get_state(ISP0_ID, &state, &stall);
461
462 debug_print_isp_state(&state, "ISP");
463
464 if (state.is_stalling) {
465 #if !defined(HAS_NO_INPUT_FORMATTER)
466 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
467 "[0] if_prim_a_FIFO stalled", stall.fifo0);
468 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
469 "[1] if_prim_b_FIFO stalled", stall.fifo1);
470 #endif
471 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[2] dma_FIFO stalled",
472 stall.fifo2);
473 #if defined(HAS_ISP_2400_MAMOIADA) || defined(HAS_ISP_2401_MAMOIADA) || defined(IS_ISP_2500_SYSTEM)
474
475 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[3] gdc0_FIFO stalled",
476 stall.fifo3);
477 #if !defined(IS_ISP_2500_SYSTEM)
478 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[4] gdc1_FIFO stalled",
479 stall.fifo4);
480 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[5] gpio_FIFO stalled",
481 stall.fifo5);
482 #endif
483 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[6] sp_FIFO stalled",
484 stall.fifo6);
485 #else
486 #error "ia_css_debug: ISP cell must be one of {2400_MAMOIADA,, 2401_MAMOIADA, 2500_SKYCAM}"
487 #endif
488 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
489 "status & control stalled",
490 stall.stat_ctrl);
491 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled",
492 stall.dmem);
493 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vmem stalled",
494 stall.vmem);
495 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem1 stalled",
496 stall.vamem1);
497 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem2 stalled",
498 stall.vamem2);
499 #if defined(HAS_ISP_2400_MAMOIADA) || defined(HAS_ISP_2401_MAMOIADA)
500 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem3 stalled",
501 stall.vamem3);
502 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "hmem stalled",
503 stall.hmem);
504 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "pmem stalled",
505 stall.pmem);
506 #endif
507 }
508 return;
509 }
510
511 void ia_css_debug_dump_sp_state(void)
512 {
513 sp_state_t state;
514 sp_stall_t stall;
515 sp_get_state(SP0_ID, &state, &stall);
516 debug_print_sp_state(&state, "SP");
517 if (state.is_stalling) {
518 #if defined(HAS_SP_2400) || defined(IS_ISP_2500_SYSTEM)
519 #if !defined(HAS_NO_INPUT_SYSTEM)
520 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isys_FIFO stalled",
521 stall.fifo0);
522 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "if_sec_FIFO stalled",
523 stall.fifo1);
524 #endif
525 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
526 "str_to_mem_FIFO stalled", stall.fifo2);
527 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dma_FIFO stalled",
528 stall.fifo3);
529 #if !defined(HAS_NO_INPUT_FORMATTER)
530 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
531 "if_prim_a_FIFO stalled", stall.fifo4);
532 #endif
533 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isp_FIFO stalled",
534 stall.fifo5);
535 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gp_FIFO stalled",
536 stall.fifo6);
537 #if !defined(HAS_NO_INPUT_FORMATTER)
538 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
539 "if_prim_b_FIFO stalled", stall.fifo7);
540 #endif
541 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc0_FIFO stalled",
542 stall.fifo8);
543 #if !defined(IS_ISP_2500_SYSTEM)
544 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc1_FIFO stalled",
545 stall.fifo9);
546 #endif
547 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "irq FIFO stalled",
548 stall.fifoa);
549 #else
550 #error "ia_css_debug: SP cell must be one of {SP2400, SP2500}"
551 #endif
552 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled",
553 stall.dmem);
554 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
555 "control master stalled",
556 stall.control_master);
557 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
558 "i-cache master stalled",
559 stall.icache_master);
560 }
561 ia_css_debug_dump_trace();
562 return;
563 }
564
565 static void debug_print_fifo_channel_state(const fifo_channel_state_t *state,
566 const char *descr)
567 {
568 assert(state != NULL);
569 assert(descr != NULL);
570
571 ia_css_debug_dtrace(2, "FIFO channel: %s\n", descr);
572 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "source valid",
573 state->src_valid);
574 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "fifo accept",
575 state->fifo_accept);
576 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "fifo valid",
577 state->fifo_valid);
578 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "sink accept",
579 state->sink_accept);
580 return;
581 }
582
583 #if !defined(HAS_NO_INPUT_FORMATTER) && defined(USE_INPUT_SYSTEM_VERSION_2)
584 void ia_css_debug_dump_pif_a_isp_fifo_state(void)
585 {
586 fifo_channel_state_t pif_to_isp, isp_to_pif;
587 fifo_channel_get_state(FIFO_MONITOR0_ID,
588 FIFO_CHANNEL_IF0_TO_ISP0, &pif_to_isp);
589 fifo_channel_get_state(FIFO_MONITOR0_ID,
590 FIFO_CHANNEL_ISP0_TO_IF0, &isp_to_pif);
591 debug_print_fifo_channel_state(&pif_to_isp, "Primary IF A to ISP");
592 debug_print_fifo_channel_state(&isp_to_pif, "ISP to Primary IF A");
593 }
594
595 void ia_css_debug_dump_pif_b_isp_fifo_state(void)
596 {
597 fifo_channel_state_t pif_to_isp, isp_to_pif;
598 fifo_channel_get_state(FIFO_MONITOR0_ID,
599 FIFO_CHANNEL_IF1_TO_ISP0, &pif_to_isp);
600 fifo_channel_get_state(FIFO_MONITOR0_ID,
601 FIFO_CHANNEL_ISP0_TO_IF1, &isp_to_pif);
602 debug_print_fifo_channel_state(&pif_to_isp, "Primary IF B to ISP");
603 debug_print_fifo_channel_state(&isp_to_pif, "ISP to Primary IF B");
604 }
605
606 void ia_css_debug_dump_str2mem_sp_fifo_state(void)
607 {
608 fifo_channel_state_t s2m_to_sp, sp_to_s2m;
609 fifo_channel_get_state(FIFO_MONITOR0_ID,
610 FIFO_CHANNEL_STREAM2MEM0_TO_SP0, &s2m_to_sp);
611 fifo_channel_get_state(FIFO_MONITOR0_ID,
612 FIFO_CHANNEL_SP0_TO_STREAM2MEM0, &sp_to_s2m);
613 debug_print_fifo_channel_state(&s2m_to_sp, "Stream-to-memory to SP");
614 debug_print_fifo_channel_state(&sp_to_s2m, "SP to stream-to-memory");
615 }
616
617 static void debug_print_if_state(input_formatter_state_t *state, const char *id)
618 {
619 unsigned int val;
620
621 #if defined(HAS_INPUT_FORMATTER_VERSION_1)
622 const char *st_reset = (state->reset ? "Active" : "Not active");
623 #endif
624 const char *st_vsync_active_low =
625 (state->vsync_active_low ? "low" : "high");
626 const char *st_hsync_active_low =
627 (state->hsync_active_low ? "low" : "high");
628
629 const char *fsm_sync_status_str = "unknown";
630 const char *fsm_crop_status_str = "unknown";
631 const char *fsm_padding_status_str = "unknown";
632
633 int st_stline = state->start_line;
634 int st_stcol = state->start_column;
635 int st_crpht = state->cropped_height;
636 int st_crpwd = state->cropped_width;
637 int st_verdcm = state->ver_decimation;
638 int st_hordcm = state->hor_decimation;
639 int st_ver_deinterleaving = state->ver_deinterleaving;
640 int st_hor_deinterleaving = state->hor_deinterleaving;
641 int st_leftpd = state->left_padding;
642 int st_eoloff = state->eol_offset;
643 int st_vmstartaddr = state->vmem_start_address;
644 int st_vmendaddr = state->vmem_end_address;
645 int st_vmincr = state->vmem_increment;
646 int st_yuv420 = state->is_yuv420;
647 int st_allow_fifo_overflow = state->allow_fifo_overflow;
648 int st_block_fifo_when_no_req = state->block_fifo_when_no_req;
649
650 assert(state != NULL);
651 ia_css_debug_dtrace(2, "InputFormatter State (%s):\n", id);
652
653 ia_css_debug_dtrace(2, "\tConfiguration:\n");
654
655 #if defined(HAS_INPUT_FORMATTER_VERSION_1)
656 ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "Software reset", st_reset);
657 #endif
658 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start line", st_stline);
659 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start column", st_stcol);
660 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped height", st_crpht);
661 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped width", st_crpwd);
662 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Ver decimation", st_verdcm);
663 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Hor decimation", st_hordcm);
664 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
665 "Ver deinterleaving", st_ver_deinterleaving);
666 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
667 "Hor deinterleaving", st_hor_deinterleaving);
668 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Left padding", st_leftpd);
669 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
670 "EOL offset (bytes)", st_eoloff);
671 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n",
672 "VMEM start address", st_vmstartaddr);
673 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n",
674 "VMEM end address", st_vmendaddr);
675 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n",
676 "VMEM increment", st_vmincr);
677 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "YUV 420 format", st_yuv420);
678 ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n",
679 "Vsync", st_vsync_active_low);
680 ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n",
681 "Hsync", st_hsync_active_low);
682 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
683 "Allow FIFO overflow", st_allow_fifo_overflow);
684 /* Flag that tells whether the IF gives backpressure on frames */
685 /*
686 * FYI, this is only on the frame request (indicate), when the IF has
687 * synch'd on a frame it will always give back pressure
688 */
689 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
690 "Block when no request", st_block_fifo_when_no_req);
691
692 #if defined(HAS_INPUT_FORMATTER_VERSION_2)
693 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
694 "IF_BLOCKED_FIFO_NO_REQ_ADDRESS",
695 input_formatter_reg_load(INPUT_FORMATTER0_ID,
696 HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS)
697 );
698
699 ia_css_debug_dtrace(2, "\t%-32s:\n", "InputSwitch State");
700
701 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
702 "_REG_GP_IFMT_input_switch_lut_reg0",
703 gp_device_reg_load(GP_DEVICE0_ID,
704 _REG_GP_IFMT_input_switch_lut_reg0));
705
706 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
707 "_REG_GP_IFMT_input_switch_lut_reg1",
708 gp_device_reg_load(GP_DEVICE0_ID,
709 _REG_GP_IFMT_input_switch_lut_reg1));
710
711 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
712 "_REG_GP_IFMT_input_switch_lut_reg2",
713 gp_device_reg_load(GP_DEVICE0_ID,
714 _REG_GP_IFMT_input_switch_lut_reg2));
715
716 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
717 "_REG_GP_IFMT_input_switch_lut_reg3",
718 gp_device_reg_load(GP_DEVICE0_ID,
719 _REG_GP_IFMT_input_switch_lut_reg3));
720
721 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
722 "_REG_GP_IFMT_input_switch_lut_reg4",
723 gp_device_reg_load(GP_DEVICE0_ID,
724 _REG_GP_IFMT_input_switch_lut_reg4));
725
726 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
727 "_REG_GP_IFMT_input_switch_lut_reg5",
728 gp_device_reg_load(GP_DEVICE0_ID,
729 _REG_GP_IFMT_input_switch_lut_reg5));
730
731 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
732 "_REG_GP_IFMT_input_switch_lut_reg6",
733 gp_device_reg_load(GP_DEVICE0_ID,
734 _REG_GP_IFMT_input_switch_lut_reg6));
735
736 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
737 "_REG_GP_IFMT_input_switch_lut_reg7",
738 gp_device_reg_load(GP_DEVICE0_ID,
739 _REG_GP_IFMT_input_switch_lut_reg7));
740
741 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
742 "_REG_GP_IFMT_input_switch_fsync_lut",
743 gp_device_reg_load(GP_DEVICE0_ID,
744 _REG_GP_IFMT_input_switch_fsync_lut));
745
746 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
747 "_REG_GP_IFMT_srst",
748 gp_device_reg_load(GP_DEVICE0_ID,
749 _REG_GP_IFMT_srst));
750
751 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
752 "_REG_GP_IFMT_slv_reg_srst",
753 gp_device_reg_load(GP_DEVICE0_ID,
754 _REG_GP_IFMT_slv_reg_srst));
755 #endif
756
757 ia_css_debug_dtrace(2, "\tFSM Status:\n");
758
759 val = state->fsm_sync_status;
760
761 if (val > 7)
762 fsm_sync_status_str = "ERROR";
763
764 switch (val & 0x7) {
765 case 0:
766 fsm_sync_status_str = "idle";
767 break;
768 case 1:
769 fsm_sync_status_str = "request frame";
770 break;
771 case 2:
772 fsm_sync_status_str = "request lines";
773 break;
774 case 3:
775 fsm_sync_status_str = "request vectors";
776 break;
777 case 4:
778 fsm_sync_status_str = "send acknowledge";
779 break;
780 default:
781 fsm_sync_status_str = "unknown";
782 break;
783 }
784
785 ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n",
786 "FSM Synchronization Status", val,
787 fsm_sync_status_str);
788
789 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
790 "FSM Synchronization Counter",
791 state->fsm_sync_counter);
792
793 val = state->fsm_crop_status;
794
795 if (val > 7)
796 fsm_crop_status_str = "ERROR";
797
798 switch (val & 0x7) {
799 case 0:
800 fsm_crop_status_str = "idle";
801 break;
802 case 1:
803 fsm_crop_status_str = "wait line";
804 break;
805 case 2:
806 fsm_crop_status_str = "crop line";
807 break;
808 case 3:
809 fsm_crop_status_str = "crop pixel";
810 break;
811 case 4:
812 fsm_crop_status_str = "pass pixel";
813 break;
814 case 5:
815 fsm_crop_status_str = "pass line";
816 break;
817 case 6:
818 fsm_crop_status_str = "lost line";
819 break;
820 default:
821 fsm_crop_status_str = "unknown";
822 break;
823 }
824 ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n",
825 "FSM Crop Status", val, fsm_crop_status_str);
826
827 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
828 "FSM Crop Line Counter",
829 state->fsm_crop_line_counter);
830 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
831 "FSM Crop Pixel Counter",
832 state->fsm_crop_pixel_counter);
833 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
834 "FSM Deinterleaving idx buffer",
835 state->fsm_deinterleaving_index);
836 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
837 "FSM H decimation counter",
838 state->fsm_dec_h_counter);
839 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
840 "FSM V decimation counter",
841 state->fsm_dec_v_counter);
842 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
843 "FSM block V decimation counter",
844 state->fsm_dec_block_v_counter);
845
846 val = state->fsm_padding_status;
847
848 if (val > 7)
849 fsm_padding_status_str = "ERROR";
850
851 switch (val & 0x7) {
852 case 0:
853 fsm_padding_status_str = "idle";
854 break;
855 case 1:
856 fsm_padding_status_str = "left pad";
857 break;
858 case 2:
859 fsm_padding_status_str = "write";
860 break;
861 case 3:
862 fsm_padding_status_str = "right pad";
863 break;
864 case 4:
865 fsm_padding_status_str = "send end of line";
866 break;
867 default:
868 fsm_padding_status_str = "unknown";
869 break;
870 }
871
872 ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", "FSM Padding Status",
873 val, fsm_padding_status_str);
874
875 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
876 "FSM Padding element idx counter",
877 state->fsm_padding_elem_counter);
878 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support error",
879 state->fsm_vector_support_error);
880 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support buf full",
881 state->fsm_vector_buffer_full);
882 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support",
883 state->vector_support);
884 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Fifo sensor data lost",
885 state->sensor_data_lost);
886 return;
887 }
888
889 static void debug_print_if_bin_state(input_formatter_bin_state_t *state)
890 {
891 ia_css_debug_dtrace(2, "Stream-to-memory state:\n");
892 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "reset", state->reset);
893 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "input endianness",
894 state->input_endianness);
895 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "output endianness",
896 state->output_endianness);
897 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "bitswap", state->bitswap);
898 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "block_synch",
899 state->block_synch);
900 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "packet_synch",
901 state->packet_synch);
902 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "readpostwrite_sync",
903 state->readpostwrite_synch);
904 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "is_2ppc", state->is_2ppc);
905 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "en_status_update",
906 state->en_status_update);
907 }
908
909 void ia_css_debug_dump_if_state(void)
910 {
911 input_formatter_state_t if_state;
912 input_formatter_bin_state_t if_bin_state;
913
914 input_formatter_get_state(INPUT_FORMATTER0_ID, &if_state);
915 debug_print_if_state(&if_state, "Primary IF A");
916 ia_css_debug_dump_pif_a_isp_fifo_state();
917
918 input_formatter_get_state(INPUT_FORMATTER1_ID, &if_state);
919 debug_print_if_state(&if_state, "Primary IF B");
920 ia_css_debug_dump_pif_b_isp_fifo_state();
921
922 input_formatter_bin_get_state(INPUT_FORMATTER3_ID, &if_bin_state);
923 debug_print_if_bin_state(&if_bin_state);
924 ia_css_debug_dump_str2mem_sp_fifo_state();
925 }
926 #endif
927
928 void ia_css_debug_dump_dma_state(void)
929 {
930 /* note: the var below is made static as it is quite large;
931 if it is not static it ends up on the stack which could
932 cause issues for drivers
933 */
934 static dma_state_t state;
935 int i, ch_id;
936
937 const char *fsm_cmd_st_lbl = "FSM Command flag state";
938 const char *fsm_ctl_st_lbl = "FSM Control flag state";
939 const char *fsm_ctl_state = NULL;
940 const char *fsm_ctl_flag = NULL;
941 const char *fsm_pack_st = NULL;
942 const char *fsm_read_st = NULL;
943 const char *fsm_write_st = NULL;
944 char last_cmd_str[64];
945
946 dma_get_state(DMA0_ID, &state);
947 /* Print header for DMA dump status */
948 ia_css_debug_dtrace(2, "DMA dump status:\n");
949
950 /* Print FSM command flag state */
951 if (state.fsm_command_idle)
952 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "IDLE");
953 if (state.fsm_command_run)
954 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "RUN");
955 if (state.fsm_command_stalling)
956 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl,
957 "STALL");
958 if (state.fsm_command_error)
959 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl,
960 "ERROR");
961
962 /* Print last command along with the channel */
963 ch_id = state.last_command_channel;
964
965 switch (state.last_command) {
966 case DMA_COMMAND_READ:
967 snprintf(last_cmd_str, 64,
968 "Read 2D Block [Channel: %d]", ch_id);
969 break;
970 case DMA_COMMAND_WRITE:
971 snprintf(last_cmd_str, 64,
972 "Write 2D Block [Channel: %d]", ch_id);
973 break;
974 case DMA_COMMAND_SET_CHANNEL:
975 snprintf(last_cmd_str, 64, "Set Channel [Channel: %d]", ch_id);
976 break;
977 case DMA_COMMAND_SET_PARAM:
978 snprintf(last_cmd_str, 64,
979 "Set Param: %d [Channel: %d]",
980 state.last_command_param, ch_id);
981 break;
982 case DMA_COMMAND_READ_SPECIFIC:
983 snprintf(last_cmd_str, 64,
984 "Read Specific 2D Block [Channel: %d]", ch_id);
985 break;
986 case DMA_COMMAND_WRITE_SPECIFIC:
987 snprintf(last_cmd_str, 64,
988 "Write Specific 2D Block [Channel: %d]", ch_id);
989 break;
990 case DMA_COMMAND_INIT:
991 snprintf(last_cmd_str, 64,
992 "Init 2D Block on Device A [Channel: %d]", ch_id);
993 break;
994 case DMA_COMMAND_INIT_SPECIFIC:
995 snprintf(last_cmd_str, 64,
996 "Init Specific 2D Block [Channel: %d]", ch_id);
997 break;
998 case DMA_COMMAND_RST:
999 snprintf(last_cmd_str, 64, "DMA SW Reset");
1000 break;
1001 case N_DMA_COMMANDS:
1002 snprintf(last_cmd_str, 64, "UNKNOWN");
1003 break;
1004 default:
1005 snprintf(last_cmd_str, 64,
1006 "unknown [Channel: %d]", ch_id);
1007 break;
1008 }
1009 ia_css_debug_dtrace(2, "\t%-32s: (0x%X : %s)\n",
1010 "last command received", state.last_command,
1011 last_cmd_str);
1012
1013 /* Print DMA registers */
1014 ia_css_debug_dtrace(2, "\t%-32s\n",
1015 "DMA registers, connection group 0");
1016 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Command",
1017 state.current_command);
1018 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address A",
1019 state.current_addr_a);
1020 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address B",
1021 state.current_addr_b);
1022
1023 if (state.fsm_ctrl_idle)
1024 fsm_ctl_flag = "IDLE";
1025 else if (state.fsm_ctrl_run)
1026 fsm_ctl_flag = "RUN";
1027 else if (state.fsm_ctrl_stalling)
1028 fsm_ctl_flag = "STAL";
1029 else if (state.fsm_ctrl_error)
1030 fsm_ctl_flag = "ERROR";
1031 else
1032 fsm_ctl_flag = "UNKNOWN";
1033
1034 switch (state.fsm_ctrl_state) {
1035 case DMA_CTRL_STATE_IDLE:
1036 fsm_ctl_state = "Idle state";
1037 break;
1038 case DMA_CTRL_STATE_REQ_RCV:
1039 fsm_ctl_state = "Req Rcv state";
1040 break;
1041 case DMA_CTRL_STATE_RCV:
1042 fsm_ctl_state = "Rcv state";
1043 break;
1044 case DMA_CTRL_STATE_RCV_REQ:
1045 fsm_ctl_state = "Rcv Req state";
1046 break;
1047 case DMA_CTRL_STATE_INIT:
1048 fsm_ctl_state = "Init state";
1049 break;
1050 case N_DMA_CTRL_STATES:
1051 fsm_ctl_state = "Unknown";
1052 break;
1053 }
1054
1055 ia_css_debug_dtrace(2, "\t\t%-32s: %s -> %s\n", fsm_ctl_st_lbl,
1056 fsm_ctl_flag, fsm_ctl_state);
1057
1058 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source dev",
1059 state.fsm_ctrl_source_dev);
1060 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source addr",
1061 state.fsm_ctrl_source_addr);
1062 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source stride",
1063 state.fsm_ctrl_source_stride);
1064 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source width",
1065 state.fsm_ctrl_source_width);
1066 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source height",
1067 state.fsm_ctrl_source_height);
1068 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source dev",
1069 state.fsm_ctrl_pack_source_dev);
1070 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest dev",
1071 state.fsm_ctrl_pack_dest_dev);
1072 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest addr",
1073 state.fsm_ctrl_dest_addr);
1074 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest stride",
1075 state.fsm_ctrl_dest_stride);
1076 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source width",
1077 state.fsm_ctrl_pack_source_width);
1078 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest height",
1079 state.fsm_ctrl_pack_dest_height);
1080 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest width",
1081 state.fsm_ctrl_pack_dest_width);
1082 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source elems",
1083 state.fsm_ctrl_pack_source_elems);
1084 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest elems",
1085 state.fsm_ctrl_pack_dest_elems);
1086 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack extension",
1087 state.fsm_ctrl_pack_extension);
1088
1089 if (state.pack_idle)
1090 fsm_pack_st = "IDLE";
1091 if (state.pack_run)
1092 fsm_pack_st = "RUN";
1093 if (state.pack_stalling)
1094 fsm_pack_st = "STALL";
1095 if (state.pack_error)
1096 fsm_pack_st = "ERROR";
1097
1098 ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Pack flag state",
1099 fsm_pack_st);
1100
1101 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack cnt height",
1102 state.pack_cnt_height);
1103 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack src cnt width",
1104 state.pack_src_cnt_width);
1105 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack dest cnt width",
1106 state.pack_dest_cnt_width);
1107
1108 if (state.read_state == DMA_RW_STATE_IDLE)
1109 fsm_read_st = "Idle state";
1110 if (state.read_state == DMA_RW_STATE_REQ)
1111 fsm_read_st = "Req state";
1112 if (state.read_state == DMA_RW_STATE_NEXT_LINE)
1113 fsm_read_st = "Next line";
1114 if (state.read_state == DMA_RW_STATE_UNLOCK_CHANNEL)
1115 fsm_read_st = "Unlock channel";
1116
1117 ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Read state",
1118 fsm_read_st);
1119
1120 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt height",
1121 state.read_cnt_height);
1122 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt width",
1123 state.read_cnt_width);
1124
1125 if (state.write_state == DMA_RW_STATE_IDLE)
1126 fsm_write_st = "Idle state";
1127 if (state.write_state == DMA_RW_STATE_REQ)
1128 fsm_write_st = "Req state";
1129 if (state.write_state == DMA_RW_STATE_NEXT_LINE)
1130 fsm_write_st = "Next line";
1131 if (state.write_state == DMA_RW_STATE_UNLOCK_CHANNEL)
1132 fsm_write_st = "Unlock channel";
1133
1134 ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Write state",
1135 fsm_write_st);
1136
1137 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write height",
1138 state.write_height);
1139 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write width",
1140 state.write_width);
1141
1142 for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) {
1143 dma_port_state_t *port = &(state.port_states[i]);
1144 ia_css_debug_dtrace(2, "\tDMA device interface %d\n", i);
1145 ia_css_debug_dtrace(2, "\t\tDMA internal side state\n");
1146 ia_css_debug_dtrace(2,
1147 "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n",
1148 port->req_cs, port->req_we_n, port->req_run,
1149 port->req_ack);
1150 ia_css_debug_dtrace(2, "\t\tMaster Output side state\n");
1151 ia_css_debug_dtrace(2,
1152 "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n",
1153 port->send_cs, port->send_we_n,
1154 port->send_run, port->send_ack);
1155 ia_css_debug_dtrace(2, "\t\tFifo state\n");
1156 if (port->fifo_state == DMA_FIFO_STATE_WILL_BE_FULL)
1157 ia_css_debug_dtrace(2, "\t\t\tFiFo will be full\n");
1158 else if (port->fifo_state == DMA_FIFO_STATE_FULL)
1159 ia_css_debug_dtrace(2, "\t\t\tFifo Full\n");
1160 else if (port->fifo_state == DMA_FIFO_STATE_EMPTY)
1161 ia_css_debug_dtrace(2, "\t\t\tFifo Empty\n");
1162 else
1163 ia_css_debug_dtrace(2, "\t\t\tFifo state unknown\n");
1164
1165 ia_css_debug_dtrace(2, "\t\tFifo counter %d\n\n",
1166 port->fifo_counter);
1167 }
1168
1169 for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) {
1170 dma_channel_state_t *ch = &(state.channel_states[i]);
1171 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "DMA channel register",
1172 i);
1173 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Connection",
1174 ch->connection);
1175 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Sign extend",
1176 ch->sign_extend);
1177 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev A",
1178 ch->stride_a);
1179 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev A",
1180 ch->elems_a);
1181 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev A",
1182 ch->cropping_a);
1183 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev A",
1184 ch->width_a);
1185 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev B",
1186 ch->stride_b);
1187 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev B",
1188 ch->elems_b);
1189 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev B",
1190 ch->cropping_b);
1191 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev B",
1192 ch->width_b);
1193 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Height", ch->height);
1194 }
1195 ia_css_debug_dtrace(2, "\n");
1196 return;
1197 }
1198
1199 void ia_css_debug_dump_dma_sp_fifo_state(void)
1200 {
1201 fifo_channel_state_t dma_to_sp, sp_to_dma;
1202 fifo_channel_get_state(FIFO_MONITOR0_ID,
1203 FIFO_CHANNEL_DMA0_TO_SP0, &dma_to_sp);
1204 fifo_channel_get_state(FIFO_MONITOR0_ID,
1205 FIFO_CHANNEL_SP0_TO_DMA0, &sp_to_dma);
1206 debug_print_fifo_channel_state(&dma_to_sp, "DMA to SP");
1207 debug_print_fifo_channel_state(&sp_to_dma, "SP to DMA");
1208 return;
1209 }
1210
1211 void ia_css_debug_dump_dma_isp_fifo_state(void)
1212 {
1213 fifo_channel_state_t dma_to_isp, isp_to_dma;
1214 fifo_channel_get_state(FIFO_MONITOR0_ID,
1215 FIFO_CHANNEL_DMA0_TO_ISP0, &dma_to_isp);
1216 fifo_channel_get_state(FIFO_MONITOR0_ID,
1217 FIFO_CHANNEL_ISP0_TO_DMA0, &isp_to_dma);
1218 debug_print_fifo_channel_state(&dma_to_isp, "DMA to ISP");
1219 debug_print_fifo_channel_state(&isp_to_dma, "ISP to DMA");
1220 return;
1221 }
1222
1223 void ia_css_debug_dump_isp_sp_fifo_state(void)
1224 {
1225 fifo_channel_state_t sp_to_isp, isp_to_sp;
1226 fifo_channel_get_state(FIFO_MONITOR0_ID,
1227 FIFO_CHANNEL_SP0_TO_ISP0, &sp_to_isp);
1228 fifo_channel_get_state(FIFO_MONITOR0_ID,
1229 FIFO_CHANNEL_ISP0_TO_SP0, &isp_to_sp);
1230 debug_print_fifo_channel_state(&sp_to_isp, "SP to ISP");
1231 debug_print_fifo_channel_state(&isp_to_sp, "ISP to SP");
1232 return;
1233 }
1234
1235 void ia_css_debug_dump_isp_gdc_fifo_state(void)
1236 {
1237 fifo_channel_state_t gdc_to_isp, isp_to_gdc;
1238
1239 fifo_channel_get_state(FIFO_MONITOR0_ID,
1240 FIFO_CHANNEL_GDC0_TO_ISP0, &gdc_to_isp);
1241 fifo_channel_get_state(FIFO_MONITOR0_ID,
1242 FIFO_CHANNEL_ISP0_TO_GDC0, &isp_to_gdc);
1243 debug_print_fifo_channel_state(&gdc_to_isp, "GDC to ISP");
1244 debug_print_fifo_channel_state(&isp_to_gdc, "ISP to GDC");
1245 return;
1246 }
1247
1248 void ia_css_debug_dump_all_fifo_state(void)
1249 {
1250 int i;
1251 fifo_monitor_state_t state;
1252 fifo_monitor_get_state(FIFO_MONITOR0_ID, &state);
1253
1254 for (i = 0; i < N_FIFO_CHANNEL; i++)
1255 debug_print_fifo_channel_state(&(state.fifo_channels[i]),
1256 "squepfstqkt");
1257 return;
1258 }
1259
1260 static void debug_binary_info_print(const struct ia_css_binary_xinfo *info)
1261 {
1262 assert(info != NULL);
1263 ia_css_debug_dtrace(2, "id = %d\n", info->sp.id);
1264 ia_css_debug_dtrace(2, "mode = %d\n", info->sp.pipeline.mode);
1265 ia_css_debug_dtrace(2, "max_input_width = %d\n", info->sp.input.max_width);
1266 ia_css_debug_dtrace(2, "min_output_width = %d\n",
1267 info->sp.output.min_width);
1268 ia_css_debug_dtrace(2, "max_output_width = %d\n",
1269 info->sp.output.max_width);
1270 ia_css_debug_dtrace(2, "top_cropping = %d\n", info->sp.pipeline.top_cropping);
1271 ia_css_debug_dtrace(2, "left_cropping = %d\n", info->sp.pipeline.left_cropping);
1272 ia_css_debug_dtrace(2, "xmem_addr = %d\n", info->xmem_addr);
1273 ia_css_debug_dtrace(2, "enable_vf_veceven = %d\n",
1274 info->sp.enable.vf_veceven);
1275 ia_css_debug_dtrace(2, "enable_dis = %d\n", info->sp.enable.dis);
1276 ia_css_debug_dtrace(2, "enable_uds = %d\n", info->sp.enable.uds);
1277 ia_css_debug_dtrace(2, "enable ds = %d\n", info->sp.enable.ds);
1278 ia_css_debug_dtrace(2, "s3atbl_use_dmem = %d\n", info->sp.s3a.s3atbl_use_dmem);
1279 return;
1280 }
1281
1282 void ia_css_debug_binary_print(const struct ia_css_binary *bi)
1283 {
1284 unsigned int i;
1285 debug_binary_info_print(bi->info);
1286 ia_css_debug_dtrace(2,
1287 "input: %dx%d, format = %d, padded width = %d\n",
1288 bi->in_frame_info.res.width,
1289 bi->in_frame_info.res.height,
1290 bi->in_frame_info.format,
1291 bi->in_frame_info.padded_width);
1292 ia_css_debug_dtrace(2,
1293 "internal :%dx%d, format = %d, padded width = %d\n",
1294 bi->internal_frame_info.res.width,
1295 bi->internal_frame_info.res.height,
1296 bi->internal_frame_info.format,
1297 bi->internal_frame_info.padded_width);
1298 for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
1299 if (bi->out_frame_info[i].res.width != 0) {
1300 ia_css_debug_dtrace(2,
1301 "out%d: %dx%d, format = %d, padded width = %d\n",
1302 i,
1303 bi->out_frame_info[i].res.width,
1304 bi->out_frame_info[i].res.height,
1305 bi->out_frame_info[i].format,
1306 bi->out_frame_info[i].padded_width);
1307 }
1308 }
1309 ia_css_debug_dtrace(2,
1310 "vf out: %dx%d, format = %d, padded width = %d\n",
1311 bi->vf_frame_info.res.width,
1312 bi->vf_frame_info.res.height,
1313 bi->vf_frame_info.format,
1314 bi->vf_frame_info.padded_width);
1315 ia_css_debug_dtrace(2, "online = %d\n", bi->online);
1316 ia_css_debug_dtrace(2, "input_buf_vectors = %d\n",
1317 bi->input_buf_vectors);
1318 ia_css_debug_dtrace(2, "deci_factor_log2 = %d\n", bi->deci_factor_log2);
1319 ia_css_debug_dtrace(2, "vf_downscale_log2 = %d\n",
1320 bi->vf_downscale_log2);
1321 ia_css_debug_dtrace(2, "dis_deci_factor_log2 = %d\n",
1322 bi->dis.deci_factor_log2);
1323 ia_css_debug_dtrace(2, "dis hor coef num = %d\n",
1324 bi->dis.coef.pad.width);
1325 ia_css_debug_dtrace(2, "dis ver coef num = %d\n",
1326 bi->dis.coef.pad.height);
1327 ia_css_debug_dtrace(2, "dis hor proj num = %d\n",
1328 bi->dis.proj.pad.height);
1329 ia_css_debug_dtrace(2, "sctbl_width_per_color = %d\n",
1330 bi->sctbl_width_per_color);
1331 ia_css_debug_dtrace(2, "s3atbl_width = %d\n", bi->s3atbl_width);
1332 ia_css_debug_dtrace(2, "s3atbl_height = %d\n", bi->s3atbl_height);
1333 return;
1334 }
1335
1336 void ia_css_debug_frame_print(const struct ia_css_frame *frame,
1337 const char *descr)
1338 {
1339 char *data = NULL;
1340
1341 assert(frame != NULL);
1342 assert(descr != NULL);
1343
1344 data = (char *)HOST_ADDRESS(frame->data);
1345 ia_css_debug_dtrace(2, "frame %s (%p):\n", descr, frame);
1346 ia_css_debug_dtrace(2, " resolution = %dx%d\n",
1347 frame->info.res.width, frame->info.res.height);
1348 ia_css_debug_dtrace(2, " padded width = %d\n",
1349 frame->info.padded_width);
1350 ia_css_debug_dtrace(2, " format = %d\n", frame->info.format);
1351 ia_css_debug_dtrace(2, " is contiguous = %s\n",
1352 frame->contiguous ? "yes" : "no");
1353 switch (frame->info.format) {
1354 case IA_CSS_FRAME_FORMAT_NV12:
1355 case IA_CSS_FRAME_FORMAT_NV16:
1356 case IA_CSS_FRAME_FORMAT_NV21:
1357 case IA_CSS_FRAME_FORMAT_NV61:
1358 ia_css_debug_dtrace(2, " Y = %p\n",
1359 data + frame->planes.nv.y.offset);
1360 ia_css_debug_dtrace(2, " UV = %p\n",
1361 data + frame->planes.nv.uv.offset);
1362 break;
1363 case IA_CSS_FRAME_FORMAT_YUYV:
1364 case IA_CSS_FRAME_FORMAT_UYVY:
1365 case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8:
1366 case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8:
1367 case IA_CSS_FRAME_FORMAT_YUV_LINE:
1368 ia_css_debug_dtrace(2, " YUYV = %p\n",
1369 data + frame->planes.yuyv.offset);
1370 break;
1371 case IA_CSS_FRAME_FORMAT_YUV420:
1372 case IA_CSS_FRAME_FORMAT_YUV422:
1373 case IA_CSS_FRAME_FORMAT_YUV444:
1374 case IA_CSS_FRAME_FORMAT_YV12:
1375 case IA_CSS_FRAME_FORMAT_YV16:
1376 case IA_CSS_FRAME_FORMAT_YUV420_16:
1377 case IA_CSS_FRAME_FORMAT_YUV422_16:
1378 ia_css_debug_dtrace(2, " Y = %p\n",
1379 data + frame->planes.yuv.y.offset);
1380 ia_css_debug_dtrace(2, " U = %p\n",
1381 data + frame->planes.yuv.u.offset);
1382 ia_css_debug_dtrace(2, " V = %p\n",
1383 data + frame->planes.yuv.v.offset);
1384 break;
1385 case IA_CSS_FRAME_FORMAT_RAW_PACKED:
1386 ia_css_debug_dtrace(2, " RAW PACKED = %p\n",
1387 data + frame->planes.raw.offset);
1388 break;
1389 case IA_CSS_FRAME_FORMAT_RAW:
1390 ia_css_debug_dtrace(2, " RAW = %p\n",
1391 data + frame->planes.raw.offset);
1392 break;
1393 case IA_CSS_FRAME_FORMAT_RGBA888:
1394 case IA_CSS_FRAME_FORMAT_RGB565:
1395 ia_css_debug_dtrace(2, " RGB = %p\n",
1396 data + frame->planes.rgb.offset);
1397 break;
1398 case IA_CSS_FRAME_FORMAT_QPLANE6:
1399 ia_css_debug_dtrace(2, " R = %p\n",
1400 data + frame->planes.plane6.r.offset);
1401 ia_css_debug_dtrace(2, " RatB = %p\n",
1402 data + frame->planes.plane6.r_at_b.offset);
1403 ia_css_debug_dtrace(2, " Gr = %p\n",
1404 data + frame->planes.plane6.gr.offset);
1405 ia_css_debug_dtrace(2, " Gb = %p\n",
1406 data + frame->planes.plane6.gb.offset);
1407 ia_css_debug_dtrace(2, " B = %p\n",
1408 data + frame->planes.plane6.b.offset);
1409 ia_css_debug_dtrace(2, " BatR = %p\n",
1410 data + frame->planes.plane6.b_at_r.offset);
1411 break;
1412 case IA_CSS_FRAME_FORMAT_BINARY_8:
1413 ia_css_debug_dtrace(2, " Binary data = %p\n",
1414 data + frame->planes.binary.data.offset);
1415 break;
1416 default:
1417 ia_css_debug_dtrace(2, " unknown frame type\n");
1418 break;
1419 }
1420 return;
1421 }
1422
1423 #if SP_DEBUG != SP_DEBUG_NONE
1424
1425 void ia_css_debug_print_sp_debug_state(const struct sh_css_sp_debug_state
1426 *state)
1427 {
1428
1429 #endif
1430
1431 #if SP_DEBUG == SP_DEBUG_DUMP
1432
1433 assert(state != NULL);
1434 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1435 "current SP software counter: %d\n",
1436 state->debug[0]);
1437 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1438 "empty output buffer queue head: 0x%x\n",
1439 state->debug[1]);
1440 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1441 "empty output buffer queue tail: 0x%x\n",
1442 state->debug[2]);
1443 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1444 "empty s3a buffer queue head: 0x%x\n",
1445 state->debug[3]);
1446 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1447 "empty s3a buffer queue tail: 0x%x\n",
1448 state->debug[4]);
1449 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1450 "full output buffer queue head: 0x%x\n",
1451 state->debug[5]);
1452 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1453 "full output buffer queue tail: 0x%x\n",
1454 state->debug[6]);
1455 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1456 "full s3a buffer queue head: 0x%x\n",
1457 state->debug[7]);
1458 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1459 "full s3a buffer queue tail: 0x%x\n",
1460 state->debug[8]);
1461 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "event queue head: 0x%x\n",
1462 state->debug[9]);
1463 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "event queue tail: 0x%x\n",
1464 state->debug[10]);
1465 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1466 "num of stages of current pipeline: 0x%x\n",
1467 state->debug[11]);
1468 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "DDR address of stage 1: 0x%x\n",
1469 state->debug[12]);
1470 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "DDR address of stage 2: 0x%x\n",
1471 state->debug[13]);
1472 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1473 "current stage out_vf buffer idx: 0x%x\n",
1474 state->debug[14]);
1475 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1476 "current stage output buffer idx: 0x%x\n",
1477 state->debug[15]);
1478 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1479 "current stage s3a buffer idx: 0x%x\n",
1480 state->debug[16]);
1481 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1482 "first char of current stage name: 0x%x\n",
1483 state->debug[17]);
1484 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "current SP thread id: 0x%x\n",
1485 state->debug[18]);
1486 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1487 "empty output buffer address 1: 0x%x\n",
1488 state->debug[19]);
1489 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1490 "empty output buffer address 2: 0x%x\n",
1491 state->debug[20]);
1492 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1493 "empty out_vf buffer address 1: 0x%x\n",
1494 state->debug[21]);
1495 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1496 "empty out_vf buffer address 2: 0x%x\n",
1497 state->debug[22]);
1498 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1499 "empty s3a_hi buffer address 1: 0x%x\n",
1500 state->debug[23]);
1501 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1502 "empty s3a_hi buffer address 2: 0x%x\n",
1503 state->debug[24]);
1504 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1505 "empty s3a_lo buffer address 1: 0x%x\n",
1506 state->debug[25]);
1507 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1508 "empty s3a_lo buffer address 2: 0x%x\n",
1509 state->debug[26]);
1510 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1511 "empty dis_hor buffer address 1: 0x%x\n",
1512 state->debug[27]);
1513 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1514 "empty dis_hor buffer address 2: 0x%x\n",
1515 state->debug[28]);
1516 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1517 "empty dis_ver buffer address 1: 0x%x\n",
1518 state->debug[29]);
1519 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1520 "empty dis_ver buffer address 2: 0x%x\n",
1521 state->debug[30]);
1522 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1523 "empty param buffer address: 0x%x\n",
1524 state->debug[31]);
1525 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1526 "first incorrect frame address: 0x%x\n",
1527 state->debug[32]);
1528 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1529 "first incorrect frame container address: 0x%x\n",
1530 state->debug[33]);
1531 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1532 "first incorrect frame container payload: 0x%x\n",
1533 state->debug[34]);
1534 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1535 "first incorrect s3a_hi address: 0x%x\n",
1536 state->debug[35]);
1537 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1538 "first incorrect s3a_hi container address: 0x%x\n",
1539 state->debug[36]);
1540 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1541 "first incorrect s3a_hi container payload: 0x%x\n",
1542 state->debug[37]);
1543 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1544 "first incorrect s3a_lo address: 0x%x\n",
1545 state->debug[38]);
1546 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1547 "first incorrect s3a_lo container address: 0x%x\n",
1548 state->debug[39]);
1549 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1550 "first incorrect s3a_lo container payload: 0x%x\n",
1551 state->debug[40]);
1552 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1553 "number of calling flash start function: 0x%x\n",
1554 state->debug[41]);
1555 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1556 "number of calling flash close function: 0x%x\n",
1557 state->debug[42]);
1558 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "number of flashed frame: 0x%x\n",
1559 state->debug[43]);
1560 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "flash in use flag: 0x%x\n",
1561 state->debug[44]);
1562 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1563 "number of update frame flashed flag: 0x%x\n",
1564 state->debug[46]);
1565 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1566 "number of active threads: 0x%x\n",
1567 state->debug[45]);
1568
1569 #elif SP_DEBUG == SP_DEBUG_COPY
1570
1571 /* Remember last_index because we only want to print new entries */
1572 static int last_index;
1573 int sp_index = state->index;
1574 int n;
1575
1576 assert(state != NULL);
1577 if (sp_index < last_index) {
1578 /* SP has been reset */
1579 last_index = 0;
1580 }
1581
1582 if (last_index == 0) {
1583 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1584 "copy-trace init: sp_dbg_if_start_line=%d, "
1585 "sp_dbg_if_start_column=%d, "
1586 "sp_dbg_if_cropped_height=%d, "
1587 "sp_debg_if_cropped_width=%d\n",
1588 state->if_start_line,
1589 state->if_start_column,
1590 state->if_cropped_height,
1591 state->if_cropped_width);
1592 }
1593
1594 if ((last_index + SH_CSS_SP_DBG_TRACE_DEPTH) < sp_index) {
1595 /* last index can be multiple rounds behind */
1596 /* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */
1597 last_index = sp_index - SH_CSS_SP_DBG_TRACE_DEPTH;
1598 }
1599
1600 for (n = last_index; n < sp_index; n++) {
1601 int i = n % SH_CSS_SP_DBG_TRACE_DEPTH;
1602 if (state->trace[i].frame != 0) {
1603 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1604 "copy-trace: frame=%d, line=%d, "
1605 "pixel_distance=%d, "
1606 "mipi_used_dword=%d, "
1607 "sp_index=%d\n",
1608 state->trace[i].frame,
1609 state->trace[i].line,
1610 state->trace[i].pixel_distance,
1611 state->trace[i].mipi_used_dword,
1612 state->trace[i].sp_index);
1613 }
1614 }
1615
1616 last_index = sp_index;
1617
1618 #elif SP_DEBUG == SP_DEBUG_TRACE
1619
1620 /**
1621 * This is just an example how TRACE_FILE_ID (see ia_css_debug.sp.h) will
1622 * me mapped on the file name string.
1623 *
1624 * Adjust this to your trace case!
1625 */
1626 static char const * const id2filename[8] = {
1627 "param_buffer.sp.c | tagger.sp.c | pipe_data.sp.c",
1628 "isp_init.sp.c",
1629 "sp_raw_copy.hive.c",
1630 "dma_configure.sp.c",
1631 "sp.hive.c",
1632 "event_proxy_sp.hive.c",
1633 "circular_buffer.sp.c",
1634 "frame_buffer.sp.c"
1635 };
1636
1637 #if 1
1638 /* Example SH_CSS_SP_DBG_NR_OF_TRACES==1 */
1639 /* Adjust this to your trace case */
1640 static char const *trace_name[SH_CSS_SP_DBG_NR_OF_TRACES] = {
1641 "default"
1642 };
1643 #else
1644 /* Example SH_CSS_SP_DBG_NR_OF_TRACES==4 */
1645 /* Adjust this to your trace case */
1646 static char const *trace_name[SH_CSS_SP_DBG_NR_OF_TRACES] = {
1647 "copy", "preview/video", "capture", "acceleration"
1648 };
1649 #endif
1650
1651 /* Remember host_index_last because we only want to print new entries */
1652 static int host_index_last[SH_CSS_SP_DBG_NR_OF_TRACES] = { 0 };
1653 int t, n;
1654
1655 assert(state != NULL);
1656
1657 for (t = 0; t < SH_CSS_SP_DBG_NR_OF_TRACES; t++) {
1658 int sp_index_last = state->index_last[t];
1659
1660 if (sp_index_last < host_index_last[t]) {
1661 /* SP has been reset */
1662 host_index_last[t] = 0;
1663 }
1664
1665 if ((host_index_last[t] + SH_CSS_SP_DBG_TRACE_DEPTH) <
1666 sp_index_last) {
1667 /* last index can be multiple rounds behind */
1668 /* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */
1669 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1670 "Warning: trace %s has gap of %d "
1671 "traces\n",
1672 trace_name[t],
1673 (sp_index_last -
1674 (host_index_last[t] +
1675 SH_CSS_SP_DBG_TRACE_DEPTH)));
1676
1677 host_index_last[t] =
1678 sp_index_last - SH_CSS_SP_DBG_TRACE_DEPTH;
1679 }
1680
1681 for (n = host_index_last[t]; n < sp_index_last; n++) {
1682 int i = n % SH_CSS_SP_DBG_TRACE_DEPTH;
1683 int l = state->trace[t][i].location &
1684 ((1 << SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS) - 1);
1685 int fid = state->trace[t][i].location >>
1686 SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS;
1687 int ts = state->trace[t][i].time_stamp;
1688
1689 if (ts) {
1690 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1691 "%05d trace=%s, file=%s:%d, "
1692 "data=0x%08x\n",
1693 ts,
1694 trace_name[t],
1695 id2filename[fid], l,
1696 state->trace[t][i].data);
1697 }
1698 }
1699 host_index_last[t] = sp_index_last;
1700 }
1701
1702 #elif SP_DEBUG == SP_DEBUG_MINIMAL
1703 int i;
1704 int base = 0;
1705 int limit = SH_CSS_NUM_SP_DEBUG;
1706 int step = 1;
1707
1708 assert(state != NULL);
1709
1710 for (i = base; i < limit; i += step) {
1711 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1712 "sp_dbg_trace[%d] = %d\n",
1713 i, state->debug[i]);
1714 }
1715 #endif
1716
1717 #if SP_DEBUG != SP_DEBUG_NONE
1718
1719 return;
1720 }
1721 #endif
1722
1723 #if defined(HAS_INPUT_FORMATTER_VERSION_2) && !defined(HAS_NO_INPUT_FORMATTER)
1724 static void debug_print_rx_mipi_port_state(mipi_port_state_t *state)
1725 {
1726 int i;
1727 unsigned int bits, infos;
1728
1729 assert(state != NULL);
1730
1731 bits = state->irq_status;
1732 infos = ia_css_isys_rx_translate_irq_infos(bits);
1733
1734 ia_css_debug_dtrace(2, "\t\t%-32s: (irq reg = 0x%X)\n",
1735 "receiver errors", bits);
1736
1737 if (infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN)
1738 ia_css_debug_dtrace(2, "\t\t\tbuffer overrun\n");
1739 if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT)
1740 ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission error\n");
1741 if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC)
1742 ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission sync error\n");
1743 if (infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL)
1744 ia_css_debug_dtrace(2, "\t\t\tcontrol error\n");
1745 if (infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE)
1746 ia_css_debug_dtrace(2, "\t\t\t2 or more ECC errors\n");
1747 if (infos & IA_CSS_RX_IRQ_INFO_ERR_CRC)
1748 ia_css_debug_dtrace(2, "\t\t\tCRC mismatch\n");
1749 if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID)
1750 ia_css_debug_dtrace(2, "\t\t\tunknown error\n");
1751 if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC)
1752 ia_css_debug_dtrace(2, "\t\t\tframe sync error\n");
1753 if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA)
1754 ia_css_debug_dtrace(2, "\t\t\tframe data error\n");
1755 if (infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT)
1756 ia_css_debug_dtrace(2, "\t\t\tdata timeout\n");
1757 if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC)
1758 ia_css_debug_dtrace(2, "\t\t\tunknown escape command entry\n");
1759 if (infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC)
1760 ia_css_debug_dtrace(2, "\t\t\tline sync error\n");
1761
1762 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1763 "device_ready", state->device_ready);
1764
1765 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1766 "irq_status", state->irq_status);
1767
1768 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1769 "irq_enable", state->irq_enable);
1770
1771 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1772 "timeout_count", state->timeout_count);
1773
1774 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1775 "init_count", state->init_count);
1776
1777 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16_18", state->raw16_18);
1778
1779 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1780 "sync_count", state->sync_count);
1781
1782 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "rx_count", state->rx_count);
1783
1784 for (i = 0; i < MIPI_4LANE_CFG; i++) {
1785 ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n",
1786 "lane_sync_count[", i, "]",
1787 state->lane_sync_count[i]);
1788 }
1789
1790 for (i = 0; i < MIPI_4LANE_CFG; i++) {
1791 ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n",
1792 "lane_rx_count[", i, "]",
1793 state->lane_rx_count[i]);
1794 }
1795
1796 return;
1797 }
1798
1799 static void debug_print_rx_channel_state(rx_channel_state_t *state)
1800 {
1801 int i;
1802
1803 assert(state != NULL);
1804 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1805 "compression_scheme0", state->comp_scheme0);
1806
1807 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1808 "compression_scheme1", state->comp_scheme1);
1809
1810 for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) {
1811 ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n",
1812 "MIPI Predictor ", i, state->pred[i]);
1813 }
1814
1815 for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) {
1816 ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n",
1817 "MIPI Compressor ", i, state->comp[i]);
1818 }
1819
1820 return;
1821 }
1822
1823 static void debug_print_rx_state(receiver_state_t *state)
1824 {
1825 int i;
1826
1827 assert(state != NULL);
1828 ia_css_debug_dtrace(2, "CSI Receiver State:\n");
1829
1830 ia_css_debug_dtrace(2, "\tConfiguration:\n");
1831
1832 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1833 "fs_to_ls_delay", state->fs_to_ls_delay);
1834
1835 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1836 "ls_to_data_delay", state->ls_to_data_delay);
1837
1838 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1839 "data_to_le_delay", state->data_to_le_delay);
1840
1841 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1842 "le_to_fe_delay", state->le_to_fe_delay);
1843
1844 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1845 "fe_to_fs_delay", state->fe_to_fs_delay);
1846
1847 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1848 "le_to_fs_delay", state->le_to_fs_delay);
1849
1850 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1851 "is_two_ppc", state->is_two_ppc);
1852
1853 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1854 "backend_rst", state->backend_rst);
1855
1856 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw18", state->raw18);
1857
1858 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1859 "force_raw8", state->force_raw8);
1860
1861 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16", state->raw16);
1862
1863 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1864 "be_gsp_acc_ovl", state->be_gsp_acc_ovl);
1865
1866 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_srst", state->be_srst);
1867
1868 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1869 "be_is_two_ppc", state->be_is_two_ppc);
1870
1871 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1872 "be_comp_format0", state->be_comp_format0);
1873
1874 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1875 "be_comp_format1", state->be_comp_format1);
1876
1877 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1878 "be_comp_format2", state->be_comp_format2);
1879
1880 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1881 "be_comp_format3", state->be_comp_format3);
1882
1883 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_sel", state->be_sel);
1884
1885 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1886 "be_raw16_config", state->be_raw16_config);
1887
1888 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1889 "be_raw18_config", state->be_raw18_config);
1890
1891 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1892 "be_force_raw8", state->be_force_raw8);
1893
1894 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1895 "be_irq_status", state->be_irq_status);
1896
1897 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1898 "be_irq_clear", state->be_irq_clear);
1899
1900 /* mipi port state */
1901 for (i = 0; i < N_MIPI_PORT_ID; i++) {
1902 ia_css_debug_dtrace(2, "\tMIPI Port %d State:\n", i);
1903
1904 debug_print_rx_mipi_port_state(&state->mipi_port_state[i]);
1905 }
1906 /* end of mipi port state */
1907
1908 /* rx channel state */
1909 for (i = 0; i < N_RX_CHANNEL_ID; i++) {
1910 ia_css_debug_dtrace(2, "\tRX Channel %d State:\n", i);
1911
1912 debug_print_rx_channel_state(&state->rx_channel_state[i]);
1913 }
1914 /* end of rx channel state */
1915
1916 return;
1917 }
1918 #endif
1919
1920 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2)
1921 void ia_css_debug_dump_rx_state(void)
1922 {
1923 #if defined(HAS_INPUT_FORMATTER_VERSION_2) && !defined(HAS_NO_INPUT_FORMATTER)
1924 receiver_state_t state;
1925
1926 receiver_get_state(RX0_ID, &state);
1927 debug_print_rx_state(&state);
1928 #endif
1929 }
1930 #endif
1931
1932 void ia_css_debug_dump_sp_sw_debug_info(void)
1933 {
1934 #if SP_DEBUG != SP_DEBUG_NONE
1935 struct sh_css_sp_debug_state state;
1936
1937 sh_css_sp_get_debug_state(&state);
1938 ia_css_debug_print_sp_debug_state(&state);
1939 #endif
1940 ia_css_bufq_dump_queue_info();
1941 ia_css_pipeline_dump_thread_map_info();
1942 return;
1943 }
1944
1945 #if defined(USE_INPUT_SYSTEM_VERSION_2)
1946 static void debug_print_isys_capture_unit_state(capture_unit_state_t *state)
1947 {
1948 assert(state != NULL);
1949 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1950 "Packet_Length", state->Packet_Length);
1951
1952 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1953 "Received_Length", state->Received_Length);
1954
1955 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1956 "Received_Short_Packets",
1957 state->Received_Short_Packets);
1958
1959 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1960 "Received_Long_Packets",
1961 state->Received_Long_Packets);
1962
1963 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1964 "Last_Command", state->Last_Command);
1965
1966 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1967 "Next_Command", state->Next_Command);
1968
1969 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1970 "Last_Acknowledge", state->Last_Acknowledge);
1971
1972 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1973 "Next_Acknowledge", state->Next_Acknowledge);
1974
1975 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1976 "FSM_State_Info", state->FSM_State_Info);
1977
1978 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1979 "StartMode", state->StartMode);
1980
1981 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1982 "Start_Addr", state->Start_Addr);
1983
1984 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1985 "Mem_Region_Size", state->Mem_Region_Size);
1986
1987 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1988 "Num_Mem_Regions", state->Num_Mem_Regions);
1989 return;
1990 }
1991
1992 static void debug_print_isys_acquisition_unit_state(
1993 acquisition_unit_state_t *state)
1994 {
1995 assert(state != NULL);
1996
1997 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1998 "Received_Short_Packets",
1999 state->Received_Short_Packets);
2000
2001 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2002 "Received_Long_Packets",
2003 state->Received_Long_Packets);
2004
2005 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2006 "Last_Command", state->Last_Command);
2007
2008 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2009 "Next_Command", state->Next_Command);
2010
2011 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2012 "Last_Acknowledge", state->Last_Acknowledge);
2013
2014 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2015 "Next_Acknowledge", state->Next_Acknowledge);
2016
2017 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2018 "FSM_State_Info", state->FSM_State_Info);
2019
2020 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2021 "Int_Cntr_Info", state->Int_Cntr_Info);
2022
2023 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2024 "Start_Addr", state->Start_Addr);
2025
2026 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2027 "Mem_Region_Size", state->Mem_Region_Size);
2028
2029 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2030 "Num_Mem_Regions", state->Num_Mem_Regions);
2031 }
2032
2033 static void debug_print_isys_ctrl_unit_state(ctrl_unit_state_t *state)
2034 {
2035 assert(state != NULL);
2036 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_cmd", state->last_cmd);
2037
2038 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_cmd", state->next_cmd);
2039
2040 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_ack", state->last_ack);
2041
2042 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_ack", state->next_ack);
2043
2044 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2045 "top_fsm_state", state->top_fsm_state);
2046
2047 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2048 "captA_fsm_state", state->captA_fsm_state);
2049
2050 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2051 "captB_fsm_state", state->captB_fsm_state);
2052
2053 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2054 "captC_fsm_state", state->captC_fsm_state);
2055
2056 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2057 "acq_fsm_state", state->acq_fsm_state);
2058
2059 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2060 "captA_start_addr", state->captA_start_addr);
2061
2062 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2063 "captB_start_addr", state->captB_start_addr);
2064
2065 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2066 "captC_start_addr", state->captC_start_addr);
2067
2068 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2069 "captA_mem_region_size",
2070 state->captA_mem_region_size);
2071
2072 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2073 "captB_mem_region_size",
2074 state->captB_mem_region_size);
2075
2076 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2077 "captC_mem_region_size",
2078 state->captC_mem_region_size);
2079
2080 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2081 "captA_num_mem_regions",
2082 state->captA_num_mem_regions);
2083
2084 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2085 "captB_num_mem_regions",
2086 state->captB_num_mem_regions);
2087
2088 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2089 "captC_num_mem_regions",
2090 state->captC_num_mem_regions);
2091
2092 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2093 "acq_start_addr", state->acq_start_addr);
2094
2095 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2096 "acq_mem_region_size", state->acq_mem_region_size);
2097
2098 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2099 "acq_num_mem_regions", state->acq_num_mem_regions);
2100
2101 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2102 "capt_reserve_one_mem_region",
2103 state->capt_reserve_one_mem_region);
2104
2105 return;
2106 }
2107
2108 static void debug_print_isys_state(input_system_state_t *state)
2109 {
2110 int i;
2111
2112 assert(state != NULL);
2113 ia_css_debug_dtrace(2, "InputSystem State:\n");
2114
2115 /* configuration */
2116 ia_css_debug_dtrace(2, "\tConfiguration:\n");
2117
2118 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2119 "str_multiCastA_sel", state->str_multicastA_sel);
2120
2121 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2122 "str_multicastB_sel", state->str_multicastB_sel);
2123
2124 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2125 "str_multicastC_sel", state->str_multicastC_sel);
2126
2127 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2128 "str_mux_sel", state->str_mux_sel);
2129
2130 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2131 "str_mon_status", state->str_mon_status);
2132
2133 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2134 "str_mon_irq_cond", state->str_mon_irq_cond);
2135
2136 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2137 "str_mon_irq_en", state->str_mon_irq_en);
2138
2139 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2140 "isys_srst", state->isys_srst);
2141
2142 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2143 "isys_slv_reg_srst", state->isys_slv_reg_srst);
2144
2145 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2146 "str_deint_portA_cnt", state->str_deint_portA_cnt);
2147
2148 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2149 "str_deint_portB_cnd", state->str_deint_portB_cnt);
2150 /* end of configuration */
2151
2152 /* capture unit state */
2153 for (i = 0; i < N_CAPTURE_UNIT_ID; i++) {
2154 capture_unit_state_t *capture_unit_state;
2155
2156 ia_css_debug_dtrace(2, "\tCaptureUnit %d State:\n", i);
2157
2158 capture_unit_state = &state->capture_unit[i];
2159 debug_print_isys_capture_unit_state(capture_unit_state);
2160 }
2161 /* end of capture unit state */
2162
2163 /* acquisition unit state */
2164 for (i = 0; i < N_ACQUISITION_UNIT_ID; i++) {
2165 acquisition_unit_state_t *acquisition_unit_state;
2166
2167 ia_css_debug_dtrace(2, "\tAcquisitionUnit %d State:\n", i);
2168
2169 acquisition_unit_state = &state->acquisition_unit[i];
2170 debug_print_isys_acquisition_unit_state(acquisition_unit_state);
2171 }
2172 /* end of acquisition unit state */
2173
2174 /* control unit state */
2175 for (i = 0; i < N_CTRL_UNIT_ID; i++) {
2176 ia_css_debug_dtrace(2, "\tControlUnit %d State:\n", i);
2177
2178 debug_print_isys_ctrl_unit_state(&state->ctrl_unit_state[i]);
2179 }
2180 /* end of control unit state */
2181 }
2182
2183 void ia_css_debug_dump_isys_state(void)
2184 {
2185 input_system_state_t state;
2186
2187 input_system_get_state(INPUT_SYSTEM0_ID, &state);
2188 debug_print_isys_state(&state);
2189
2190 return;
2191 }
2192 #endif
2193 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401)
2194 void ia_css_debug_dump_isys_state(void)
2195 {
2196 /* Android compilation fails if made a local variable
2197 stack size on android is limited to 2k and this structure
2198 is around 3.5K, in place of static malloc can be done but
2199 if this call is made too often it will lead to fragment memory
2200 versus a fixed allocation */
2201 static input_system_state_t state;
2202
2203 input_system_get_state(INPUT_SYSTEM0_ID, &state);
2204 input_system_dump_state(INPUT_SYSTEM0_ID, &state);
2205 }
2206 #endif
2207
2208 void ia_css_debug_dump_debug_info(const char *context)
2209 {
2210 if (context == NULL)
2211 context = "No Context provided";
2212
2213 ia_css_debug_dtrace(2, "CSS Debug Info dump [Context = %s]\n", context);
2214 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2)
2215 ia_css_debug_dump_rx_state();
2216 #endif
2217 #if !defined(HAS_NO_INPUT_FORMATTER) && defined(USE_INPUT_SYSTEM_VERSION_2)
2218 ia_css_debug_dump_if_state();
2219 #endif
2220 ia_css_debug_dump_isp_state();
2221 ia_css_debug_dump_isp_sp_fifo_state();
2222 ia_css_debug_dump_isp_gdc_fifo_state();
2223 ia_css_debug_dump_sp_state();
2224 ia_css_debug_dump_perf_counters();
2225
2226 #ifdef HAS_WATCHDOG_SP_THREAD_DEBUG
2227 sh_css_dump_thread_wait_info();
2228 sh_css_dump_pipe_stage_info();
2229 sh_css_dump_pipe_stripe_info();
2230 #endif
2231 ia_css_debug_dump_dma_isp_fifo_state();
2232 ia_css_debug_dump_dma_sp_fifo_state();
2233 ia_css_debug_dump_dma_state();
2234 #if defined(USE_INPUT_SYSTEM_VERSION_2)
2235 ia_css_debug_dump_isys_state();
2236
2237 {
2238 irq_controller_state_t state;
2239 irq_controller_get_state(IRQ2_ID, &state);
2240
2241 ia_css_debug_dtrace(2, "\t%-32s:\n",
2242 "Input System IRQ Controller State");
2243
2244 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2245 "irq_edge", state.irq_edge);
2246
2247 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2248 "irq_mask", state.irq_mask);
2249
2250 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2251 "irq_status", state.irq_status);
2252
2253 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2254 "irq_enable", state.irq_enable);
2255
2256 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2257 "irq_level_not_pulse",
2258 state.irq_level_not_pulse);
2259 }
2260 #endif
2261 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401)
2262 ia_css_debug_dump_isys_state();
2263 #endif
2264 #if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401)
2265 ia_css_debug_tagger_state();
2266 #endif
2267 return;
2268 }
2269
2270 /** this function is for debug use, it can make SP go to sleep
2271 state after each frame, then user can dump the stable SP dmem.
2272 this function can be called after ia_css_start_sp()
2273 and before sh_css_init_buffer_queues()
2274 */
2275 void ia_css_debug_enable_sp_sleep_mode(enum ia_css_sp_sleep_mode mode)
2276 {
2277 const struct ia_css_fw_info *fw;
2278 unsigned int HIVE_ADDR_sp_sleep_mode;
2279
2280 fw = &sh_css_sp_fw;
2281 HIVE_ADDR_sp_sleep_mode = fw->info.sp.sleep_mode;
2282
2283 (void)HIVE_ADDR_sp_sleep_mode; /* Suppres warnings in CRUN */
2284
2285 sp_dmem_store_uint32(SP0_ID,
2286 (unsigned int)sp_address_of(sp_sleep_mode),
2287 (uint32_t) mode);
2288 }
2289
2290 void ia_css_debug_wake_up_sp(void)
2291 {
2292 /*hrt_ctl_start(SP); */
2293 sp_ctrl_setbit(SP0_ID, SP_SC_REG, SP_START_BIT);
2294 }
2295
2296 #if !defined(IS_ISP_2500_SYSTEM)
2297 #define FIND_DMEM_PARAMS_TYPE(stream, kernel, type) \
2298 (struct HRTCAT(HRTCAT(sh_css_isp_, type), _params) *) \
2299 findf_dmem_params(stream, offsetof(struct ia_css_memory_offsets, dmem.kernel))
2300
2301 #define FIND_DMEM_PARAMS(stream, kernel) FIND_DMEM_PARAMS_TYPE(stream, kernel, kernel)
2302
2303 /* Find a stage that support the kernel and return the parameters for that kernel */
2304 static char *
2305 findf_dmem_params(struct ia_css_stream *stream, short idx)
2306 {
2307 int i;
2308 for (i = 0; i < stream->num_pipes; i++) {
2309 struct ia_css_pipe *pipe = stream->pipes[i];
2310 struct ia_css_pipeline *pipeline = ia_css_pipe_get_pipeline(pipe);
2311 struct ia_css_pipeline_stage *stage;
2312 for (stage = pipeline->stages; stage; stage = stage->next) {
2313 struct ia_css_binary *binary = stage->binary;
2314 short *offsets = (short *)&binary->info->mem_offsets.offsets.param->dmem;
2315 short dmem_offset = offsets[idx];
2316 const struct ia_css_host_data *isp_data =
2317 ia_css_isp_param_get_mem_init(&binary->mem_params,
2318 IA_CSS_PARAM_CLASS_PARAM, IA_CSS_ISP_DMEM0);
2319 if (dmem_offset < 0)
2320 continue;
2321 return &isp_data->address[dmem_offset];
2322 }
2323 }
2324 return NULL;
2325 }
2326 #endif
2327
2328 void ia_css_debug_dump_isp_params(struct ia_css_stream *stream,
2329 unsigned int enable)
2330 {
2331 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "ISP PARAMETERS:\n");
2332 #if defined(IS_ISP_2500_SYSTEM)
2333 (void)enable;
2334 (void)stream;
2335 #else
2336
2337 assert(stream != NULL);
2338 if ((enable & IA_CSS_DEBUG_DUMP_FPN)
2339 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2340 ia_css_fpn_dump(FIND_DMEM_PARAMS(stream, fpn), IA_CSS_DEBUG_VERBOSE);
2341 }
2342 if ((enable & IA_CSS_DEBUG_DUMP_OB)
2343 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2344 ia_css_ob_dump(FIND_DMEM_PARAMS(stream, ob), IA_CSS_DEBUG_VERBOSE);
2345 }
2346 if ((enable & IA_CSS_DEBUG_DUMP_SC)
2347 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2348 ia_css_sc_dump(FIND_DMEM_PARAMS(stream, sc), IA_CSS_DEBUG_VERBOSE);
2349 }
2350 if ((enable & IA_CSS_DEBUG_DUMP_WB)
2351 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2352 ia_css_wb_dump(FIND_DMEM_PARAMS(stream, wb), IA_CSS_DEBUG_VERBOSE);
2353 }
2354 if ((enable & IA_CSS_DEBUG_DUMP_DP)
2355 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2356 ia_css_dp_dump(FIND_DMEM_PARAMS(stream, dp), IA_CSS_DEBUG_VERBOSE);
2357 }
2358 if ((enable & IA_CSS_DEBUG_DUMP_BNR)
2359 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2360 ia_css_bnr_dump(FIND_DMEM_PARAMS(stream, bnr), IA_CSS_DEBUG_VERBOSE);
2361 }
2362 if ((enable & IA_CSS_DEBUG_DUMP_S3A)
2363 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2364 ia_css_s3a_dump(FIND_DMEM_PARAMS(stream, s3a), IA_CSS_DEBUG_VERBOSE);
2365 }
2366 if ((enable & IA_CSS_DEBUG_DUMP_DE)
2367 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2368 ia_css_de_dump(FIND_DMEM_PARAMS(stream, de), IA_CSS_DEBUG_VERBOSE);
2369 }
2370 if ((enable & IA_CSS_DEBUG_DUMP_YNR)
2371 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2372 ia_css_nr_dump(FIND_DMEM_PARAMS_TYPE(stream, nr, ynr), IA_CSS_DEBUG_VERBOSE);
2373 ia_css_yee_dump(FIND_DMEM_PARAMS(stream, yee), IA_CSS_DEBUG_VERBOSE);
2374 }
2375 if ((enable & IA_CSS_DEBUG_DUMP_CSC)
2376 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2377 ia_css_csc_dump(FIND_DMEM_PARAMS(stream, csc), IA_CSS_DEBUG_VERBOSE);
2378 ia_css_yuv2rgb_dump(FIND_DMEM_PARAMS_TYPE(stream, yuv2rgb, csc), IA_CSS_DEBUG_VERBOSE);
2379 ia_css_rgb2yuv_dump(FIND_DMEM_PARAMS_TYPE(stream, rgb2yuv, csc), IA_CSS_DEBUG_VERBOSE);
2380 }
2381 if ((enable & IA_CSS_DEBUG_DUMP_GC)
2382 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2383 ia_css_gc_dump(FIND_DMEM_PARAMS(stream, gc), IA_CSS_DEBUG_VERBOSE);
2384 }
2385 if ((enable & IA_CSS_DEBUG_DUMP_TNR)
2386 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2387 ia_css_tnr_dump(FIND_DMEM_PARAMS(stream, tnr), IA_CSS_DEBUG_VERBOSE);
2388 }
2389 if ((enable & IA_CSS_DEBUG_DUMP_ANR)
2390 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2391 ia_css_anr_dump(FIND_DMEM_PARAMS(stream, anr), IA_CSS_DEBUG_VERBOSE);
2392 }
2393 if ((enable & IA_CSS_DEBUG_DUMP_CE)
2394 || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2395 ia_css_ce_dump(FIND_DMEM_PARAMS(stream, ce), IA_CSS_DEBUG_VERBOSE);
2396 }
2397 #endif
2398 }
2399
2400 void sh_css_dump_sp_raw_copy_linecount(bool reduced)
2401 {
2402 const struct ia_css_fw_info *fw;
2403 unsigned int HIVE_ADDR_raw_copy_line_count;
2404 int32_t raw_copy_line_count;
2405 static int32_t prev_raw_copy_line_count = -1;
2406
2407 fw = &sh_css_sp_fw;
2408 HIVE_ADDR_raw_copy_line_count =
2409 fw->info.sp.raw_copy_line_count;
2410
2411 (void)HIVE_ADDR_raw_copy_line_count;
2412
2413 sp_dmem_load(SP0_ID,
2414 (unsigned int)sp_address_of(raw_copy_line_count),
2415 &raw_copy_line_count,
2416 sizeof(raw_copy_line_count));
2417
2418 /* only indicate if copy loop is active */
2419 if (reduced)
2420 raw_copy_line_count = (raw_copy_line_count < 0)?raw_copy_line_count:1;
2421 /* do the handling */
2422 if (prev_raw_copy_line_count != raw_copy_line_count) {
2423 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2424 "sh_css_dump_sp_raw_copy_linecount() "
2425 "line_count=%d\n",
2426 raw_copy_line_count);
2427 prev_raw_copy_line_count = raw_copy_line_count;
2428 }
2429 }
2430
2431 void ia_css_debug_dump_isp_binary(void)
2432 {
2433 const struct ia_css_fw_info *fw;
2434 unsigned int HIVE_ADDR_pipeline_sp_curr_binary_id;
2435 uint32_t curr_binary_id;
2436 static uint32_t prev_binary_id = 0xFFFFFFFF;
2437 static uint32_t sample_count;
2438
2439 fw = &sh_css_sp_fw;
2440 HIVE_ADDR_pipeline_sp_curr_binary_id = fw->info.sp.curr_binary_id;
2441
2442 (void)HIVE_ADDR_pipeline_sp_curr_binary_id;
2443
2444 sp_dmem_load(SP0_ID,
2445 (unsigned int)sp_address_of(pipeline_sp_curr_binary_id),
2446 &curr_binary_id,
2447 sizeof(curr_binary_id));
2448
2449 /* do the handling */
2450 sample_count++;
2451 if (prev_binary_id != curr_binary_id) {
2452 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2453 "sh_css_dump_isp_binary() "
2454 "pipe_id=%d, binary_id=%d, sample_count=%d\n",
2455 (curr_binary_id >> 16),
2456 (curr_binary_id & 0x0ffff),
2457 sample_count);
2458 sample_count = 0;
2459 prev_binary_id = curr_binary_id;
2460 }
2461 }
2462
2463 void ia_css_debug_dump_perf_counters(void)
2464 {
2465 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2)
2466 const struct ia_css_fw_info *fw;
2467 int i;
2468 unsigned int HIVE_ADDR_ia_css_isys_sp_error_cnt;
2469 int32_t ia_css_sp_input_system_error_cnt[N_MIPI_PORT_ID + 1]; /* 3 Capture Units and 1 Acquire Unit. */
2470
2471 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "Input System Error Counters:\n");
2472
2473 fw = &sh_css_sp_fw;
2474 HIVE_ADDR_ia_css_isys_sp_error_cnt = fw->info.sp.perf_counter_input_system_error;
2475
2476 (void)HIVE_ADDR_ia_css_isys_sp_error_cnt;
2477
2478 sp_dmem_load(SP0_ID,
2479 (unsigned int)sp_address_of(ia_css_isys_sp_error_cnt),
2480 &ia_css_sp_input_system_error_cnt,
2481 sizeof(ia_css_sp_input_system_error_cnt));
2482
2483 for (i = 0; i < N_MIPI_PORT_ID + 1; i++) {
2484 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\tport[%d] = %d\n",
2485 i, ia_css_sp_input_system_error_cnt[i]);
2486 }
2487 #endif
2488 }
2489
2490 /*
2491
2492 void sh_css_init_ddr_debug_queue(void)
2493 {
2494 hrt_vaddress ddr_debug_queue_addr =
2495 mmgr_malloc(sizeof(debug_data_ddr_t));
2496 const struct ia_css_fw_info *fw;
2497 unsigned int HIVE_ADDR_debug_buffer_ddr_address;
2498
2499 fw = &sh_css_sp_fw;
2500 HIVE_ADDR_debug_buffer_ddr_address =
2501 fw->info.sp.debug_buffer_ddr_address;
2502
2503 (void)HIVE_ADDR_debug_buffer_ddr_address;
2504
2505 debug_buffer_ddr_init(ddr_debug_queue_addr);
2506
2507 sp_dmem_store_uint32(SP0_ID,
2508 (unsigned int)sp_address_of(debug_buffer_ddr_address),
2509 (uint32_t)(ddr_debug_queue_addr));
2510 }
2511
2512 void sh_css_load_ddr_debug_queue(void)
2513 {
2514 debug_synch_queue_ddr();
2515 }
2516
2517 void ia_css_debug_dump_ddr_debug_queue(void)
2518 {
2519 int i;
2520 sh_css_load_ddr_debug_queue();
2521 for (i = 0; i < DEBUG_BUF_SIZE; i++) {
2522 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2523 "ddr_debug_queue[%d] = 0x%x\n",
2524 i, debug_data_ptr->buf[i]);
2525 }
2526 }
2527 */
2528
2529 /**
2530 * @brief Initialize the debug mode.
2531 * Refer to "ia_css_debug.h" for more details.
2532 */
2533 bool ia_css_debug_mode_init(void)
2534 {
2535 bool rc;
2536 rc = sh_css_sp_init_dma_sw_reg(0);
2537 return rc;
2538 }
2539
2540 /**
2541 * @brief Disable the DMA channel.
2542 * Refer to "ia_css_debug.h" for more details.
2543 */
2544 bool
2545 ia_css_debug_mode_disable_dma_channel(int dma_id,
2546 int channel_id, int request_type)
2547 {
2548 bool rc;
2549
2550 rc = sh_css_sp_set_dma_sw_reg(dma_id, channel_id, request_type, false);
2551
2552 return rc;
2553 }
2554
2555 /**
2556 * @brief Enable the DMA channel.
2557 * Refer to "ia_css_debug.h" for more details.
2558 */
2559 bool
2560 ia_css_debug_mode_enable_dma_channel(int dma_id,
2561 int channel_id, int request_type)
2562 {
2563 bool rc;
2564
2565 rc = sh_css_sp_set_dma_sw_reg(dma_id, channel_id, request_type, true);
2566
2567 return rc;
2568 }
2569
2570 void dtrace_dot(const char *fmt, ...)
2571 {
2572 va_list ap;
2573
2574 assert(fmt != NULL);
2575 va_start(ap, fmt);
2576
2577 ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_START);
2578 ia_css_debug_vdtrace(IA_CSS_DEBUG_INFO, fmt, ap);
2579 ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_END);
2580 va_end(ap);
2581 }
2582 #ifdef HAS_WATCHDOG_SP_THREAD_DEBUG
2583 void sh_css_dump_thread_wait_info(void)
2584 {
2585 const struct ia_css_fw_info *fw;
2586 int i;
2587 unsigned int HIVE_ADDR_sp_thread_wait;
2588 int32_t sp_thread_wait[MAX_THREAD_NUM];
2589 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "SEM WAITS:\n");
2590
2591 fw = &sh_css_sp_fw;
2592 HIVE_ADDR_sp_thread_wait =
2593 fw->info.sp.debug_wait;
2594
2595 (void)HIVE_ADDR_sp_thread_wait;
2596
2597 sp_dmem_load(SP0_ID,
2598 (unsigned int)sp_address_of(sp_thread_wait),
2599 &sp_thread_wait,
2600 sizeof(sp_thread_wait));
2601 for (i = 0; i < MAX_THREAD_NUM; i++) {
2602 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2603 "\twait[%d] = 0x%X\n",
2604 i, sp_thread_wait[i]);
2605 }
2606
2607 }
2608
2609 void sh_css_dump_pipe_stage_info(void)
2610 {
2611 const struct ia_css_fw_info *fw;
2612 int i;
2613 unsigned int HIVE_ADDR_sp_pipe_stage;
2614 int32_t sp_pipe_stage[MAX_THREAD_NUM];
2615 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STAGE:\n");
2616
2617 fw = &sh_css_sp_fw;
2618 HIVE_ADDR_sp_pipe_stage =
2619 fw->info.sp.debug_stage;
2620
2621 (void)HIVE_ADDR_sp_pipe_stage;
2622
2623 sp_dmem_load(SP0_ID,
2624 (unsigned int)sp_address_of(sp_pipe_stage),
2625 &sp_pipe_stage,
2626 sizeof(sp_pipe_stage));
2627 for (i = 0; i < MAX_THREAD_NUM; i++) {
2628 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2629 "\tstage[%d] = %d\n",
2630 i, sp_pipe_stage[i]);
2631 }
2632
2633 }
2634
2635 void sh_css_dump_pipe_stripe_info(void)
2636 {
2637 const struct ia_css_fw_info *fw;
2638 int i;
2639 unsigned int HIVE_ADDR_sp_pipe_stripe;
2640 int32_t sp_pipe_stripe[MAX_THREAD_NUM];
2641 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STRIPE:\n");
2642
2643 fw = &sh_css_sp_fw;
2644 HIVE_ADDR_sp_pipe_stripe =
2645 fw->info.sp.debug_stripe;
2646
2647 (void)HIVE_ADDR_sp_pipe_stripe;
2648
2649 sp_dmem_load(SP0_ID,
2650 (unsigned int)sp_address_of(sp_pipe_stripe),
2651 &sp_pipe_stripe,
2652 sizeof(sp_pipe_stripe));
2653 for (i = 0; i < MAX_THREAD_NUM; i++) {
2654 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2655 "\tstripe[%d] = %d\n",
2656 i, sp_pipe_stripe[i]);
2657 }
2658
2659 }
2660 #endif
2661
2662 static void
2663 ia_css_debug_pipe_graph_dump_frame(
2664 struct ia_css_frame *frame,
2665 enum ia_css_pipe_id id,
2666 char const *blob_name,
2667 char const *frame_name,
2668 bool in_frame)
2669 {
2670 char bufinfo[100];
2671
2672 if (frame->dynamic_queue_id == SH_CSS_INVALID_QUEUE_ID) {
2673 snprintf(bufinfo, sizeof(bufinfo), "Internal");
2674 } else {
2675 snprintf(bufinfo, sizeof(bufinfo), "Queue: %s %s",
2676 pipe_id_to_str[id],
2677 queue_id_to_str[frame->dynamic_queue_id]);
2678 }
2679 dtrace_dot(
2680 "node [shape = box, "
2681 "fixedsize=true, width=2, height=0.7]; \"0x%08lx\" "
2682 "[label = \"%s\\n%d(%d) x %d, %dbpp\\n%s\"];",
2683 HOST_ADDRESS(frame),
2684 debug_frame_format2str(frame->info.format),
2685 frame->info.res.width,
2686 frame->info.padded_width,
2687 frame->info.res.height,
2688 frame->info.raw_bit_depth,
2689 bufinfo);
2690
2691 if (in_frame) {
2692 dtrace_dot(
2693 "\"0x%08lx\"->\"%s(pipe%d)\" "
2694 "[label = %s_frame];",
2695 HOST_ADDRESS(frame),
2696 blob_name, id, frame_name);
2697 } else {
2698 dtrace_dot(
2699 "\"%s(pipe%d)\"->\"0x%08lx\" "
2700 "[label = %s_frame];",
2701 blob_name, id,
2702 HOST_ADDRESS(frame),
2703 frame_name);
2704 }
2705 }
2706
2707 void
2708 ia_css_debug_pipe_graph_dump_prologue(void)
2709 {
2710 dtrace_dot("digraph sh_css_pipe_graph {");
2711 dtrace_dot("rankdir=LR;");
2712
2713 dtrace_dot("fontsize=9;");
2714 dtrace_dot("label = \"\\nEnable options: rp=reduced pipe, vfve=vf_veceven, "
2715 "dvse=dvs_envelope, dvs6=dvs_6axis, bo=block_out, "
2716 "fbds=fixed_bayer_ds, bf6=bayer_fir_6db, "
2717 "rawb=raw_binning, cont=continuous, disc=dis_crop\\n"
2718 "dp2a=dp_2adjacent, outp=output, outt=out_table, "
2719 "reff=ref_frame, par=params, gam=gamma, "
2720 "cagdc=ca_gdc, ispa=isp_addresses, inf=in_frame, "
2721 "outf=out_frame, hs=high_speed, inpc=input_chunking\"");
2722 }
2723
2724 void ia_css_debug_pipe_graph_dump_epilogue(void)
2725 {
2726
2727 if (strlen(ring_buffer) > 0) {
2728 dtrace_dot(ring_buffer);
2729 }
2730
2731
2732 if (pg_inst.stream_format != N_IA_CSS_STREAM_FORMAT) {
2733 /* An input stream format has been set so assume we have
2734 * an input system and sensor
2735 */
2736
2737
2738 dtrace_dot(
2739 "node [shape = doublecircle, "
2740 "fixedsize=true, width=2.5]; \"input_system\" "
2741 "[label = \"Input system\"];");
2742
2743 dtrace_dot(
2744 "\"input_system\"->\"%s\" "
2745 "[label = \"%s\"];",
2746 dot_id_input_bin, debug_stream_format2str(pg_inst.stream_format));
2747
2748 dtrace_dot(
2749 "node [shape = doublecircle, "
2750 "fixedsize=true, width=2.5]; \"sensor\" "
2751 "[label = \"Sensor\"];");
2752
2753 dtrace_dot(
2754 "\"sensor\"->\"input_system\" "
2755 "[label = \"%s\\n%d x %d\\n(%d x %d)\"];",
2756 debug_stream_format2str(pg_inst.stream_format),
2757 pg_inst.width, pg_inst.height,
2758 pg_inst.eff_width, pg_inst.eff_height);
2759 }
2760
2761 dtrace_dot("}");
2762
2763 /* Reset temp strings */
2764 memset(dot_id_input_bin, 0, sizeof(dot_id_input_bin));
2765 memset(ring_buffer, 0, sizeof(ring_buffer));
2766
2767 pg_inst.do_init = true;
2768 pg_inst.width = 0;
2769 pg_inst.height = 0;
2770 pg_inst.eff_width = 0;
2771 pg_inst.eff_height = 0;
2772 pg_inst.stream_format = N_IA_CSS_STREAM_FORMAT;
2773 }
2774
2775 void
2776 ia_css_debug_pipe_graph_dump_stage(
2777 struct ia_css_pipeline_stage *stage,
2778 enum ia_css_pipe_id id)
2779 {
2780 char blob_name[SH_CSS_MAX_BINARY_NAME+10] = "<unknown type>";
2781 char const *bin_type = "<unknown type>";
2782 int i;
2783
2784 assert(stage != NULL);
2785 if (stage->sp_func != IA_CSS_PIPELINE_NO_FUNC)
2786 return;
2787
2788 if (pg_inst.do_init) {
2789 ia_css_debug_pipe_graph_dump_prologue();
2790 pg_inst.do_init = false;
2791 }
2792
2793 if (stage->binary) {
2794 bin_type = "binary";
2795 if (stage->binary->info->blob)
2796 snprintf(blob_name, sizeof(blob_name), "%s_stage%d",
2797 stage->binary->info->blob->name, stage->stage_num);
2798 } else if (stage->firmware) {
2799 bin_type = "firmware";
2800 strncpy_s(blob_name, sizeof(blob_name), IA_CSS_EXT_ISP_PROG_NAME(stage->firmware), sizeof(blob_name));
2801 }
2802
2803 /* Guard in case of binaries that don't have any binary_info */
2804 if (stage->binary_info != NULL) {
2805 char enable_info1[100];
2806 char enable_info2[100];
2807 char enable_info3[100];
2808 char enable_info[200];
2809 struct ia_css_binary_info *bi = stage->binary_info;
2810
2811 /* Split it in 2 function-calls to keep the amount of
2812 * parameters per call "reasonable"
2813 */
2814 snprintf(enable_info1, sizeof(enable_info1),
2815 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
2816 bi->enable.reduced_pipe ? "rp," : "",
2817 bi->enable.vf_veceven ? "vfve," : "",
2818 bi->enable.dis ? "dis," : "",
2819 bi->enable.dvs_envelope ? "dvse," : "",
2820 bi->enable.uds ? "uds," : "",
2821 bi->enable.dvs_6axis ? "dvs6," : "",
2822 bi->enable.block_output ? "bo," : "",
2823 bi->enable.ds ? "ds," : "",
2824 bi->enable.bayer_fir_6db ? "bf6," : "",
2825 bi->enable.raw_binning ? "rawb," : "",
2826 bi->enable.continuous ? "cont," : "",
2827 bi->enable.s3a ? "s3a," : "",
2828 bi->enable.fpnr ? "fpnr," : "",
2829 bi->enable.sc ? "sc," : ""
2830 );
2831
2832 snprintf(enable_info2, sizeof(enable_info2),
2833 "%s%s%s%s%s%s%s%s%s%s%s",
2834 bi->enable.macc ? "macc," : "",
2835 bi->enable.output ? "outp," : "",
2836 bi->enable.ref_frame ? "reff," : "",
2837 bi->enable.tnr ? "tnr," : "",
2838 bi->enable.xnr ? "xnr," : "",
2839 bi->enable.params ? "par," : "",
2840 bi->enable.ca_gdc ? "cagdc," : "",
2841 bi->enable.isp_addresses ? "ispa," : "",
2842 bi->enable.in_frame ? "inf," : "",
2843 bi->enable.out_frame ? "outf," : "",
2844 bi->enable.high_speed ? "hs," : ""
2845 );
2846
2847 /* And merge them into one string */
2848 snprintf(enable_info, sizeof(enable_info), "%s%s",
2849 enable_info1, enable_info2);
2850 {
2851 int l, p;
2852 char *ei = enable_info;
2853
2854 l = strlen(ei);
2855
2856 /* Replace last ',' with \0 if present */
2857 if (l && enable_info[l-1] == ',')
2858 enable_info[--l] = '\0';
2859
2860 if (l <= ENABLE_LINE_MAX_LENGTH) {
2861 /* It fits on one line, copy string and init */
2862 /* other helper strings with empty string */
2863 strcpy_s(enable_info,
2864 sizeof(enable_info),
2865 ei);
2866 } else {
2867 /* Too big for one line, find last comma */
2868 p = ENABLE_LINE_MAX_LENGTH;
2869 while (ei[p] != ',')
2870 p--;
2871 /* Last comma found, copy till that comma */
2872 strncpy_s(enable_info1,
2873 sizeof(enable_info1),
2874 ei, p);
2875 enable_info1[p] = '\0';
2876
2877 ei += p+1;
2878 l = strlen(ei);
2879
2880 if (l <= ENABLE_LINE_MAX_LENGTH) {
2881 /* The 2nd line fits */
2882 /* we cannot use ei as argument because
2883 * it is not guarenteed dword aligned
2884 */
2885 strncpy_s(enable_info2,
2886 sizeof(enable_info2),
2887 ei, l);
2888 enable_info2[l] = '\0';
2889 snprintf(enable_info, sizeof(enable_info), "%s\\n%s",
2890 enable_info1, enable_info2);
2891
2892 } else {
2893 /* 2nd line is still too long */
2894 p = ENABLE_LINE_MAX_LENGTH;
2895 while (ei[p] != ',')
2896 p--;
2897 strncpy_s(enable_info2,
2898 sizeof(enable_info2),
2899 ei, p);
2900 enable_info2[p] = '\0';
2901 ei += p+1;
2902 l = strlen(ei);
2903
2904 if (l <= ENABLE_LINE_MAX_LENGTH) {
2905 /* The 3rd line fits */
2906 /* we cannot use ei as argument because
2907 * it is not guarenteed dword aligned
2908 */
2909 strcpy_s(enable_info3,
2910 sizeof(enable_info3), ei);
2911 enable_info3[l] = '\0';
2912 snprintf(enable_info, sizeof(enable_info),
2913 "%s\\n%s\\n%s",
2914 enable_info1, enable_info2,
2915 enable_info3);
2916 } else {
2917 /* 3rd line is still too long */
2918 p = ENABLE_LINE_MAX_LENGTH;
2919 while (ei[p] != ',')
2920 p--;
2921 strncpy_s(enable_info3,
2922 sizeof(enable_info3),
2923 ei, p);
2924 enable_info3[p] = '\0';
2925 ei += p+1;
2926 strcpy_s(enable_info3,
2927 sizeof(enable_info3), ei);
2928 snprintf(enable_info, sizeof(enable_info),
2929 "%s\\n%s\\n%s",
2930 enable_info1, enable_info2,
2931 enable_info3);
2932 }
2933 }
2934 }
2935 }
2936
2937 dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, "
2938 "label=\"%s\\n%s\\n\\n%s\"]; \"%s(pipe%d)\"",
2939 bin_type, blob_name, enable_info, blob_name, id);
2940
2941 }
2942 else {
2943 dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, "
2944 "label=\"%s\\n%s\\n\"]; \"%s(pipe%d)\"",
2945 bin_type, blob_name, blob_name, id);
2946 }
2947
2948 if (stage->stage_num == 0) {
2949 /*
2950 * There are some implicite assumptions about which bin is the
2951 * input binary e.g. which one is connected to the input system
2952 * Priority:
2953 * 1) sp_raw_copy bin has highest priority
2954 * 2) First stage==0 binary of preview, video or capture
2955 */
2956 if (strlen(dot_id_input_bin) == 0) {
2957 snprintf(dot_id_input_bin, sizeof(dot_id_input_bin),
2958 "%s(pipe%d)", blob_name, id);
2959 }
2960 }
2961
2962 if (stage->args.in_frame) {
2963 ia_css_debug_pipe_graph_dump_frame(
2964 stage->args.in_frame, id, blob_name,
2965 "in", true);
2966 }
2967
2968 #ifndef ISP2401
2969 for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) {
2970 #else
2971 for (i = 0; i < NUM_TNR_FRAMES; i++) {
2972 #endif
2973 if (stage->args.tnr_frames[i]) {
2974 ia_css_debug_pipe_graph_dump_frame(
2975 stage->args.tnr_frames[i], id,
2976 blob_name, "tnr_frame", true);
2977 }
2978 }
2979
2980 for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++) {
2981 if (stage->args.delay_frames[i]) {
2982 ia_css_debug_pipe_graph_dump_frame(
2983 stage->args.delay_frames[i], id,
2984 blob_name, "delay_frame", true);
2985 }
2986 }
2987
2988 for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
2989 if (stage->args.out_frame[i]) {
2990 ia_css_debug_pipe_graph_dump_frame(
2991 stage->args.out_frame[i], id, blob_name,
2992 "out", false);
2993 }
2994 }
2995
2996 if (stage->args.out_vf_frame) {
2997 ia_css_debug_pipe_graph_dump_frame(
2998 stage->args.out_vf_frame, id, blob_name,
2999 "out_vf", false);
3000 }
3001 }
3002
3003 void
3004 ia_css_debug_pipe_graph_dump_sp_raw_copy(
3005 struct ia_css_frame *out_frame)
3006 {
3007 assert(out_frame != NULL);
3008 if (pg_inst.do_init) {
3009 ia_css_debug_pipe_graph_dump_prologue();
3010 pg_inst.do_init = false;
3011 }
3012
3013 dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, "
3014 "label=\"%s\\n%s\"]; \"%s(pipe%d)\"",
3015 "sp-binary", "sp_raw_copy", "sp_raw_copy", 1);
3016
3017 snprintf(ring_buffer, sizeof(ring_buffer),
3018 "node [shape = box, "
3019 "fixedsize=true, width=2, height=0.7]; \"0x%08lx\" "
3020 "[label = \"%s\\n%d(%d) x %d\\nRingbuffer\"];",
3021 HOST_ADDRESS(out_frame),
3022 debug_frame_format2str(out_frame->info.format),
3023 out_frame->info.res.width,
3024 out_frame->info.padded_width,
3025 out_frame->info.res.height);
3026
3027 dtrace_dot(ring_buffer);
3028
3029 dtrace_dot(
3030 "\"%s(pipe%d)\"->\"0x%08lx\" "
3031 "[label = out_frame];",
3032 "sp_raw_copy", 1, HOST_ADDRESS(out_frame));
3033
3034 snprintf(dot_id_input_bin, sizeof(dot_id_input_bin), "%s(pipe%d)", "sp_raw_copy", 1);
3035 }
3036
3037 void
3038 ia_css_debug_pipe_graph_dump_stream_config(
3039 const struct ia_css_stream_config *stream_config)
3040 {
3041 pg_inst.width = stream_config->input_config.input_res.width;
3042 pg_inst.height = stream_config->input_config.input_res.height;
3043 pg_inst.eff_width = stream_config->input_config.effective_res.width;
3044 pg_inst.eff_height = stream_config->input_config.effective_res.height;
3045 pg_inst.stream_format = stream_config->input_config.format;
3046 }
3047
3048 void
3049 ia_css_debug_dump_resolution(
3050 const struct ia_css_resolution *res,
3051 const char *label)
3052 {
3053 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s: =%d x =%d\n",
3054 label, res->width, res->height);
3055 }
3056
3057 void
3058 ia_css_debug_dump_frame_info(
3059 const struct ia_css_frame_info *info,
3060 const char *label)
3061 {
3062 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", label);
3063 ia_css_debug_dump_resolution(&info->res, "res");
3064 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "padded_width: %d\n",
3065 info->padded_width);
3066 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "format: %d\n", info->format);
3067 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "raw_bit_depth: %d\n",
3068 info->raw_bit_depth);
3069 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "raw_bayer_order: %d\n",
3070 info->raw_bayer_order);
3071 }
3072
3073 void
3074 ia_css_debug_dump_capture_config(
3075 const struct ia_css_capture_config *config)
3076 {
3077 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__);
3078 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode);
3079 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_xnr: %d\n",
3080 config->enable_xnr);
3081 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_raw_output: %d\n",
3082 config->enable_raw_output);
3083 }
3084
3085 void
3086 ia_css_debug_dump_pipe_extra_config(
3087 const struct ia_css_pipe_extra_config *extra_config)
3088 {
3089 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__);
3090 if (extra_config) {
3091 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3092 "enable_raw_binning: %d\n",
3093 extra_config->enable_raw_binning);
3094 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_yuv_ds: %d\n",
3095 extra_config->enable_yuv_ds);
3096 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3097 "enable_high_speed: %d\n",
3098 extra_config->enable_high_speed);
3099 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3100 "enable_dvs_6axis: %d\n",
3101 extra_config->enable_dvs_6axis);
3102 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3103 "enable_reduced_pipe: %d\n",
3104 extra_config->enable_reduced_pipe);
3105 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3106 "enable_fractional_ds: %d\n",
3107 extra_config->enable_fractional_ds);
3108 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "disable_vf_pp: %d\n",
3109 extra_config->disable_vf_pp);
3110 }
3111 }
3112
3113 void
3114 ia_css_debug_dump_pipe_config(
3115 const struct ia_css_pipe_config *config)
3116 {
3117 unsigned int i;
3118
3119 IA_CSS_ENTER_PRIVATE("config = %p", config);
3120 if (!config) {
3121 IA_CSS_ERROR("NULL input parameter");
3122 IA_CSS_LEAVE_PRIVATE("");
3123 return;
3124 }
3125 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode);
3126 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "isp_pipe_version: %d\n",
3127 config->isp_pipe_version);
3128 ia_css_debug_dump_resolution(&config->bayer_ds_out_res,
3129 "bayer_ds_out_res");
3130 ia_css_debug_dump_resolution(&config->capt_pp_in_res,
3131 "capt_pp_in_res");
3132 ia_css_debug_dump_resolution(&config->vf_pp_in_res, "vf_pp_in_res");
3133 #ifdef ISP2401
3134 ia_css_debug_dump_resolution(&config->output_system_in_res,
3135 "output_system_in_res");
3136 #endif
3137 ia_css_debug_dump_resolution(&config->dvs_crop_out_res,
3138 "dvs_crop_out_res");
3139 for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) {
3140 ia_css_debug_dump_frame_info(&config->output_info[i], "output_info");
3141 ia_css_debug_dump_frame_info(&config->vf_output_info[i],
3142 "vf_output_info");
3143 }
3144 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "acc_extension: %p\n",
3145 config->acc_extension);
3146 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_acc_stages: %d\n",
3147 config->num_acc_stages);
3148 ia_css_debug_dump_capture_config(&config->default_capture_config);
3149 ia_css_debug_dump_resolution(&config->dvs_envelope, "dvs_envelope");
3150 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "dvs_frame_delay: %d\n",
3151 config->dvs_frame_delay);
3152 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "acc_num_execs: %d\n",
3153 config->acc_num_execs);
3154 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_dz: %d\n",
3155 config->enable_dz);
3156 IA_CSS_LEAVE_PRIVATE("");
3157 }
3158
3159 void
3160 ia_css_debug_dump_stream_config_source(
3161 const struct ia_css_stream_config *config)
3162 {
3163 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__);
3164 switch (config->mode) {
3165 case IA_CSS_INPUT_MODE_SENSOR:
3166 case IA_CSS_INPUT_MODE_BUFFERED_SENSOR:
3167 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.port\n");
3168 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "port: %d\n",
3169 config->source.port.port);
3170 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_lanes: %d\n",
3171 config->source.port.num_lanes);
3172 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "timeout: %d\n",
3173 config->source.port.timeout);
3174 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "compression: %d\n",
3175 config->source.port.compression.type);
3176 break;
3177 case IA_CSS_INPUT_MODE_TPG:
3178 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.tpg\n");
3179 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "id: %d\n",
3180 config->source.tpg.id);
3181 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n",
3182 config->source.tpg.mode);
3183 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x_mask: 0x%x\n",
3184 config->source.tpg.x_mask);
3185 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x_delta: %d\n",
3186 config->source.tpg.x_delta);
3187 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "y_mask: 0x%x\n",
3188 config->source.tpg.y_mask);
3189 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "y_delta: %d\n",
3190 config->source.tpg.y_delta);
3191 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "xy_mask: 0x%x\n",
3192 config->source.tpg.xy_mask);
3193 break;
3194 case IA_CSS_INPUT_MODE_PRBS:
3195 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.prbs\n");
3196 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "id: %d\n",
3197 config->source.prbs.id);
3198 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "h_blank: %d\n",
3199 config->source.prbs.h_blank);
3200 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "v_blank: %d\n",
3201 config->source.prbs.v_blank);
3202 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "seed: 0x%x\n",
3203 config->source.prbs.seed);
3204 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "seed1: 0x%x\n",
3205 config->source.prbs.seed1);
3206 break;
3207 default:
3208 case IA_CSS_INPUT_MODE_FIFO:
3209 case IA_CSS_INPUT_MODE_MEMORY:
3210 break;
3211 }
3212 }
3213
3214 void
3215 ia_css_debug_dump_mipi_buffer_config(
3216 const struct ia_css_mipi_buffer_config *config)
3217 {
3218 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__);
3219 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "size_mem_words: %d\n",
3220 config->size_mem_words);
3221 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "nof_mipi_buffers: %d\n",
3222 config->nof_mipi_buffers);
3223 }
3224
3225 void
3226 ia_css_debug_dump_metadata_config(
3227 const struct ia_css_metadata_config *config)
3228 {
3229 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__);
3230 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "data_type: %d\n",
3231 config->data_type);
3232 ia_css_debug_dump_resolution(&config->resolution, "resolution");
3233 }
3234
3235 void
3236 ia_css_debug_dump_stream_config(
3237 const struct ia_css_stream_config *config,
3238 int num_pipes)
3239 {
3240 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__);
3241 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_pipes: %d\n", num_pipes);
3242 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode);
3243 ia_css_debug_dump_stream_config_source(config);
3244 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "channel_id: %d\n",
3245 config->channel_id);
3246 ia_css_debug_dump_resolution(&config->input_config.input_res, "input_res");
3247 ia_css_debug_dump_resolution(&config->input_config.effective_res, "effective_res");
3248 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "format: %d\n",
3249 config->input_config.format);
3250 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "bayer_order: %d\n",
3251 config->input_config.bayer_order);
3252 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sensor_binning_factor: %d\n",
3253 config->sensor_binning_factor);
3254 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "pixels_per_clock: %d\n",
3255 config->pixels_per_clock);
3256 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "online: %d\n",
3257 config->online);
3258 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "init_num_cont_raw_buf: %d\n",
3259 config->init_num_cont_raw_buf);
3260 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3261 "target_num_cont_raw_buf: %d\n",
3262 config->target_num_cont_raw_buf);
3263 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "pack_raw_pixels: %d\n",
3264 config->pack_raw_pixels);
3265 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "continuous: %d\n",
3266 config->continuous);
3267 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "flash_gpio_pin: %d\n",
3268 config->flash_gpio_pin);
3269 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "left_padding: %d\n",
3270 config->left_padding);
3271 ia_css_debug_dump_mipi_buffer_config(&config->mipi_buffer_config);
3272 ia_css_debug_dump_metadata_config(&config->metadata_config);
3273 }
3274
3275 /*
3276 Trace support.
3277
3278 This tracer is using a buffer to trace the flow of the FW and dump misc values (see below for details).
3279 Currently, support is only for SKC.
3280 To enable support for other platforms:
3281 - Allocate a buffer for tracing in DMEM. The longer the better.
3282 - Use the DBG_init routine in sp.hive.c to initiatilize the tracer with the address and size selected.
3283 - Add trace points in the SP code wherever needed.
3284 - Enable the dump below with the required address and required adjustments.
3285 Dump is called at the end of ia_css_debug_dump_sp_state().
3286 */
3287
3288 /*
3289 dump_trace() : dump the trace points from DMEM2.
3290 for every trace point, the following are printed: index, major:minor and the 16-bit attached value.
3291 The routine looks for the first 0, and then prints from it cyclically.
3292 Data forma in DMEM2:
3293 first 4 DWORDS: header
3294 DWORD 0: data description
3295 byte 0: version
3296 byte 1: number of threads (for future use)
3297 byte 2+3: number ot TPs
3298 DWORD 1: command byte + data (for future use)
3299 byte 0: command
3300 byte 1-3: command signature
3301 DWORD 2-3: additional data (for future use)
3302 Following data is 4-byte oriented:
3303 byte 0: major
3304 byte 1: minor
3305 byte 2-3: data
3306 */
3307 #if TRACE_ENABLE_SP0 || TRACE_ENABLE_SP1 || TRACE_ENABLE_ISP
3308 #ifndef ISP2401
3309 static void debug_dump_one_trace(TRACE_CORE_ID proc_id)
3310 #else
3311 static void debug_dump_one_trace(enum TRACE_CORE_ID proc_id)
3312 #endif
3313 {
3314 #if defined(HAS_TRACER_V2)
3315 uint32_t start_addr;
3316 uint32_t start_addr_data;
3317 uint32_t item_size;
3318 #ifndef ISP2401
3319 uint32_t tmp;
3320 #else
3321 uint8_t tid_val;
3322 enum TRACE_DUMP_FORMAT dump_format;
3323 #endif
3324 int i, j, max_trace_points, point_num, limit = -1;
3325 /* using a static buffer here as the driver has issues allocating memory */
3326 static uint32_t trace_read_buf[TRACE_BUFF_SIZE] = {0};
3327 #ifdef ISP2401
3328 static struct trace_header_t header;
3329 uint8_t *header_arr;
3330 #endif
3331
3332 /* read the header and parse it */
3333 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "~~~ Tracer ");
3334 switch (proc_id)
3335 {
3336 case TRACE_SP0_ID:
3337 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP0");
3338 start_addr = TRACE_SP0_ADDR;
3339 start_addr_data = TRACE_SP0_DATA_ADDR;
3340 item_size = TRACE_SP0_ITEM_SIZE;
3341 max_trace_points = TRACE_SP0_MAX_POINTS;
3342 break;
3343 case TRACE_SP1_ID:
3344 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP1");
3345 start_addr = TRACE_SP1_ADDR;
3346 start_addr_data = TRACE_SP1_DATA_ADDR;
3347 item_size = TRACE_SP1_ITEM_SIZE;
3348 max_trace_points = TRACE_SP1_MAX_POINTS;
3349 break;
3350 case TRACE_ISP_ID:
3351 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ISP");
3352 start_addr = TRACE_ISP_ADDR;
3353 start_addr_data = TRACE_ISP_DATA_ADDR;
3354 item_size = TRACE_ISP_ITEM_SIZE;
3355 max_trace_points = TRACE_ISP_MAX_POINTS;
3356 break;
3357 default:
3358 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\ttraces are not supported for this processor ID - exiting\n");
3359 return;
3360 }
3361 #ifndef ISP2401
3362 tmp = ia_css_device_load_uint32(start_addr);
3363 point_num = (tmp >> 16) & 0xFFFF;
3364 #endif
3365
3366 #ifndef ISP2401
3367 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " ver %d %d points\n", tmp & 0xFF, point_num);
3368 if ((tmp & 0xFF) != TRACER_VER) {
3369 #else
3370 /* Loading byte-by-byte as using the master routine had issues */
3371 header_arr = (uint8_t *)&header;
3372 for (i = 0; i < (int)sizeof(struct trace_header_t); i++)
3373 header_arr[i] = ia_css_device_load_uint8(start_addr + (i));
3374
3375 point_num = header.max_tracer_points;
3376
3377 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " ver %d %d points\n", header.version, point_num);
3378 if ((header.version & 0xFF) != TRACER_VER) {
3379 #endif
3380 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tUnknown version - exiting\n");
3381 return;
3382 }
3383 if (point_num > max_trace_points) {
3384 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tToo many points - exiting\n");
3385 return;
3386 }
3387 /* copy the TPs and find the first 0 */
3388 for (i = 0; i < point_num; i++) {
3389 trace_read_buf[i] = ia_css_device_load_uint32(start_addr_data + (i * item_size));
3390 if ((limit == (-1)) && (trace_read_buf[i] == 0))
3391 limit = i;
3392 }
3393 #ifdef ISP2401
3394 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Status:\n");
3395 for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++)
3396 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\tT%d: %3d (%02x) %6d (%04x) %10d (%08x)\n", i,
3397 header.thr_status_byte[i], header.thr_status_byte[i],
3398 header.thr_status_word[i], header.thr_status_word[i],
3399 header.thr_status_dword[i], header.thr_status_dword[i]);
3400 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Scratch:\n");
3401 for (i = 0; i < MAX_SCRATCH_DATA; i++)
3402 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%10d (%08x) ",
3403 header.scratch_debug[i], header.scratch_debug[i]);
3404 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\n");
3405
3406 #endif
3407 /* two 0s in the beginning: empty buffer */
3408 if ((trace_read_buf[0] == 0) && (trace_read_buf[1] == 0)) {
3409 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tEmpty tracer - exiting\n");
3410 return;
3411 }
3412 /* no overrun: start from 0 */
3413 if ((limit == point_num-1) || /* first 0 is at the end - border case */
3414 (trace_read_buf[limit+1] == 0)) /* did not make a full cycle after the memset */
3415 limit = 0;
3416 /* overrun: limit is the first non-zero after the first zero */
3417 else
3418 limit++;
3419
3420 /* print the TPs */
3421 for (i = 0; i < point_num; i++) {
3422 j = (limit + i) % point_num;
3423 if (trace_read_buf[j])
3424 {
3425 #ifndef ISP2401
3426 TRACE_DUMP_FORMAT dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]);
3427 #else
3428
3429 tid_val = FIELD_TID_UNPACK(trace_read_buf[j]);
3430 dump_format = TRACE_DUMP_FORMAT_POINT;
3431
3432 /*
3433 * When tid value is 111b, the data will be interpreted differently:
3434 * tid val is ignored, major field contains 2 bits (msb) for format type
3435 */
3436 if (tid_val == FIELD_TID_SEL_FORMAT_PAT) {
3437 dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]);
3438 }
3439 #endif
3440 switch (dump_format)
3441 {
3442 case TRACE_DUMP_FORMAT_POINT:
3443 ia_css_debug_dtrace(
3444 #ifndef ISP2401
3445 IA_CSS_DEBUG_TRACE, "\t\t%d %d:%d value - %d\n",
3446 j, FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3447 #else
3448 IA_CSS_DEBUG_TRACE, "\t\t%d T%d %d:%d value - %x (%d)\n",
3449 j,
3450 tid_val,
3451 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3452 #endif
3453 FIELD_MINOR_UNPACK(trace_read_buf[j]),
3454 #ifdef ISP2401
3455 FIELD_VALUE_UNPACK(trace_read_buf[j]),
3456 #endif
3457 FIELD_VALUE_UNPACK(trace_read_buf[j]));
3458 break;
3459 #ifndef ISP2401
3460 case TRACE_DUMP_FORMAT_VALUE24_HEX:
3461 #else
3462 case TRACE_DUMP_FORMAT_POINT_NO_TID:
3463 #endif
3464 ia_css_debug_dtrace(
3465 #ifndef ISP2401
3466 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %x H\n",
3467 #else
3468 IA_CSS_DEBUG_TRACE, "\t\t%d %d:%d value - %x (%d)\n",
3469 #endif
3470 j,
3471 #ifndef ISP2401
3472 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3473 FIELD_VALUE_24_UNPACK(trace_read_buf[j]));
3474 #else
3475 FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]),
3476 FIELD_MINOR_UNPACK(trace_read_buf[j]),
3477 FIELD_VALUE_UNPACK(trace_read_buf[j]),
3478 FIELD_VALUE_UNPACK(trace_read_buf[j]));
3479 #endif
3480 break;
3481 #ifndef ISP2401
3482 case TRACE_DUMP_FORMAT_VALUE24_DEC:
3483 #else
3484 case TRACE_DUMP_FORMAT_VALUE24:
3485 #endif
3486 ia_css_debug_dtrace(
3487 #ifndef ISP2401
3488 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %d D\n",
3489 #else
3490 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %x (%d)\n",
3491 #endif
3492 j,
3493 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3494 #ifdef ISP2401
3495 FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]),
3496 FIELD_VALUE_24_UNPACK(trace_read_buf[j]),
3497 #endif
3498 FIELD_VALUE_24_UNPACK(trace_read_buf[j]));
3499 break;
3500 #ifdef ISP2401
3501
3502 #endif
3503 case TRACE_DUMP_FORMAT_VALUE24_TIMING:
3504 ia_css_debug_dtrace(
3505 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, timing %x\n",
3506 j,
3507 #ifndef ISP2401
3508 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3509 #else
3510 FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]),
3511 #endif
3512 FIELD_VALUE_24_UNPACK(trace_read_buf[j]));
3513 break;
3514 case TRACE_DUMP_FORMAT_VALUE24_TIMING_DELTA:
3515 ia_css_debug_dtrace(
3516 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, timing delta %x\n",
3517 j,
3518 #ifndef ISP2401
3519 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3520 #else
3521 FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]),
3522 #endif
3523 FIELD_VALUE_24_UNPACK(trace_read_buf[j]));
3524 break;
3525 default:
3526 ia_css_debug_dtrace(
3527 IA_CSS_DEBUG_TRACE,
3528 "no such trace dump format %d",
3529 #ifndef ISP2401
3530 FIELD_FORMAT_UNPACK(trace_read_buf[j]));
3531 #else
3532 dump_format);
3533 #endif
3534 break;
3535 }
3536 }
3537 }
3538 #else
3539 (void)proc_id;
3540 #endif /* HAS_TRACER_V2 */
3541 }
3542 #endif /* TRACE_ENABLE_SP0 || TRACE_ENABLE_SP1 || TRACE_ENABLE_ISP */
3543
3544 void ia_css_debug_dump_trace(void)
3545 {
3546 #if TRACE_ENABLE_SP0
3547 debug_dump_one_trace(TRACE_SP0_ID);
3548 #endif
3549 #if TRACE_ENABLE_SP1
3550 debug_dump_one_trace(TRACE_SP1_ID);
3551 #endif
3552 #if TRACE_ENABLE_ISP
3553 debug_dump_one_trace(TRACE_ISP_ID);
3554 #endif
3555 }
3556
3557 #if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401)
3558 /* Tagger state dump function. The tagger is only available when the CSS
3559 * contains an input system (2400 or 2401). */
3560 void ia_css_debug_tagger_state(void)
3561 {
3562 unsigned int i;
3563 unsigned int HIVE_ADDR_tagger_frames;
3564 ia_css_tagger_buf_sp_elem_t tbuf_frames[MAX_CB_ELEMS_FOR_TAGGER];
3565
3566 HIVE_ADDR_tagger_frames = sh_css_sp_fw.info.sp.tagger_frames_addr;
3567
3568 /* This variable is not used in crun */
3569 (void)HIVE_ADDR_tagger_frames;
3570
3571 /* 2400 and 2401 only have 1 SP, so the tagger lives on SP0 */
3572 sp_dmem_load(SP0_ID,
3573 (unsigned int)sp_address_of(tagger_frames),
3574 tbuf_frames,
3575 sizeof(tbuf_frames));
3576
3577 ia_css_debug_dtrace(2, "Tagger Info:\n");
3578 for (i = 0; i < MAX_CB_ELEMS_FOR_TAGGER; i++) {
3579 ia_css_debug_dtrace(2, "\t tagger frame[%d]: exp_id=%d, marked=%d, locked=%d\n",
3580 i, tbuf_frames[i].exp_id, tbuf_frames[i].mark, tbuf_frames[i].lock);
3581 }
3582
3583 }
3584 #endif /* defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) */
3585
3586 #ifdef ISP2401
3587 void ia_css_debug_pc_dump(sp_ID_t id, unsigned int num_of_dumps)
3588 {
3589 unsigned int pc;
3590 unsigned int i;
3591 hrt_data sc = sp_ctrl_load(id, SP_SC_REG);
3592 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Status reg: 0x%X\n", id, sc);
3593 sc = sp_ctrl_load(id, SP_CTRL_SINK_REG);
3594 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Stall reg: 0x%X\n", id, sc);
3595 for (i = 0; i < num_of_dumps; i++) {
3596 pc = sp_ctrl_load(id, SP_PC_REG);
3597 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d PC: 0x%X\n", id, pc);
3598 }
3599 }
3600 #endif
3601
3602 #if defined(HRT_SCHED) || defined(SH_CSS_DEBUG_SPMEM_DUMP_SUPPORT)
3603 #include "spmem_dump.c"
3604 #endif