drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/spctrl/src/spctrl.c

   1 #ifndef ISP2401
   2 /*
   3  * Support for Intel Camera Imaging ISP subsystem.
   4  * Copyright (c) 2015, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15 #else
  16 /*
  17 Support for Intel Camera Imaging ISP subsystem.
  18 Copyright (c) 2010 - 2015, Intel Corporation.
  19
  20 This program is free software; you can redistribute it and/or modify it
  21 under the terms and conditions of the GNU General Public License,
  22 version 2, as published by the Free Software Foundation.
  23
  24 This program is distributed in the hope it will be useful, but WITHOUT
  25 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  26 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  27 more details.
  28 */
  29 #endif
  30
  31 #include "ia_css_types.h"
  32 #define __INLINE_SP__
  33 #include "sp.h"
  34
  35 #include "memory_access.h"
  36 #include "assert_support.h"
  37 #include "ia_css_spctrl.h"
  38 #include "ia_css_debug.h"
  39
  40 struct spctrl_context_info {
  41         struct ia_css_sp_init_dmem_cfg dmem_config;
  42         uint32_t        spctrl_config_dmem_addr; /* location of dmem_cfg  in SP dmem */
  43         uint32_t        spctrl_state_dmem_addr;
  44         unsigned int    sp_entry;           /* entry function ptr on SP */
  45         hrt_vaddress    code_addr;          /* sp firmware location in host mem-DDR*/
  46         uint32_t        code_size;
  47         char           *program_name;       /* used in case of PLATFORM_SIM */
  48 };
  49
  50 static struct spctrl_context_info spctrl_cofig_info[N_SP_ID];
  51 static bool spctrl_loaded[N_SP_ID] = {0};
  52
  53 /* Load firmware */
  54 enum ia_css_err ia_css_spctrl_load_fw(sp_ID_t sp_id,
  55                                 ia_css_spctrl_cfg *spctrl_cfg)
  56 {
  57         hrt_vaddress code_addr = mmgr_NULL;
  58         struct ia_css_sp_init_dmem_cfg *init_dmem_cfg;
  59
  60         if ((sp_id >= N_SP_ID) || (spctrl_cfg == NULL))
  61                 return IA_CSS_ERR_INVALID_ARGUMENTS;
  62
  63         spctrl_cofig_info[sp_id].code_addr = mmgr_NULL;
  64
  65         init_dmem_cfg = &spctrl_cofig_info[sp_id].dmem_config;
  66         init_dmem_cfg->dmem_data_addr = spctrl_cfg->dmem_data_addr;
  67         init_dmem_cfg->dmem_bss_addr  = spctrl_cfg->dmem_bss_addr;
  68         init_dmem_cfg->data_size      = spctrl_cfg->data_size;
  69         init_dmem_cfg->bss_size       = spctrl_cfg->bss_size;
  70         init_dmem_cfg->sp_id          = sp_id;
  71
  72         spctrl_cofig_info[sp_id].spctrl_config_dmem_addr = spctrl_cfg->spctrl_config_dmem_addr;
  73         spctrl_cofig_info[sp_id].spctrl_state_dmem_addr = spctrl_cfg->spctrl_state_dmem_addr;
  74
  75         /* store code (text + icache) and data to DDR
  76          *
  77          * Data used to be stored separately, because of access alignment constraints,
  78          * fix the FW generation instead
  79          */
  80         code_addr = mmgr_malloc(spctrl_cfg->code_size);
  81         if (code_addr == mmgr_NULL)
  82                 return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY;
  83         mmgr_store(code_addr, spctrl_cfg->code, spctrl_cfg->code_size);
  84
  85         if (sizeof(hrt_vaddress) > sizeof(hrt_data)) {
  86                 ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
  87                                     "size of hrt_vaddress can not be greater than hrt_data\n");
  88                 hmm_free(code_addr);
  89                 code_addr = mmgr_NULL;
  90                 return IA_CSS_ERR_INTERNAL_ERROR;
  91         }
  92
  93         init_dmem_cfg->ddr_data_addr  = code_addr + spctrl_cfg->ddr_data_offset;
  94         if ((init_dmem_cfg->ddr_data_addr % HIVE_ISP_DDR_WORD_BYTES) != 0) {
  95                 ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
  96                                     "DDR address pointer is not properly aligned for DMA transfer\n");
  97                 hmm_free(code_addr);
  98                 code_addr = mmgr_NULL;
  99                 return IA_CSS_ERR_INTERNAL_ERROR;
 100         }
 101
 102         spctrl_cofig_info[sp_id].sp_entry = spctrl_cfg->sp_entry;
 103         spctrl_cofig_info[sp_id].code_addr = code_addr;
 104         spctrl_cofig_info[sp_id].program_name = spctrl_cfg->program_name;
 105
 106         /* now we program the base address into the icache and
 107          * invalidate the cache.
 108          */
 109         sp_ctrl_store(sp_id, SP_ICACHE_ADDR_REG, (hrt_data)spctrl_cofig_info[sp_id].code_addr);
 110         sp_ctrl_setbit(sp_id, SP_ICACHE_INV_REG, SP_ICACHE_INV_BIT);
 111         spctrl_loaded[sp_id] = true;
 112         return IA_CSS_SUCCESS;
 113 }
 114
 115 #ifdef ISP2401
 116 /* reload pre-loaded FW */
 117 void sh_css_spctrl_reload_fw(sp_ID_t sp_id)
 118 {
 119         /* now we program the base address into the icache and
 120         * invalidate the cache.
 121         */
 122         sp_ctrl_store(sp_id, SP_ICACHE_ADDR_REG, (hrt_data)spctrl_cofig_info[sp_id].code_addr);
 123         sp_ctrl_setbit(sp_id, SP_ICACHE_INV_REG, SP_ICACHE_INV_BIT);
 124         spctrl_loaded[sp_id] = true;
 125 }
 126 #endif
 127
 128 hrt_vaddress get_sp_code_addr(sp_ID_t  sp_id)
 129 {
 130         return spctrl_cofig_info[sp_id].code_addr;
 131 }
 132
 133 enum ia_css_err ia_css_spctrl_unload_fw(sp_ID_t sp_id)
 134 {
 135         if ((sp_id >= N_SP_ID) || ((sp_id < N_SP_ID) && (!spctrl_loaded[sp_id])))
 136                 return IA_CSS_ERR_INVALID_ARGUMENTS;
 137
 138         /*  freeup the resource */
 139         if (spctrl_cofig_info[sp_id].code_addr)
 140                 hmm_free(spctrl_cofig_info[sp_id].code_addr);
 141         spctrl_loaded[sp_id] = false;
 142         return IA_CSS_SUCCESS;
 143 }
 144
 145 /* Initialize dmem_cfg in SP dmem  and  start SP program*/
 146 enum ia_css_err ia_css_spctrl_start(sp_ID_t sp_id)
 147 {
 148         if ((sp_id >= N_SP_ID) || ((sp_id < N_SP_ID) && (!spctrl_loaded[sp_id])))
 149                 return IA_CSS_ERR_INVALID_ARGUMENTS;
 150
 151         /* Set descr in the SP to initialize the SP DMEM */
 152         /*
 153          * The FW stores user-space pointers to the FW, the ISP pointer
 154          * is only available here
 155          *
 156          */
 157         assert(sizeof(unsigned int) <= sizeof(hrt_data));
 158
 159         sp_dmem_store(sp_id,
 160                 spctrl_cofig_info[sp_id].spctrl_config_dmem_addr,
 161                 &spctrl_cofig_info[sp_id].dmem_config,
 162                 sizeof(spctrl_cofig_info[sp_id].dmem_config));
 163         /* set the start address */
 164         sp_ctrl_store(sp_id, SP_START_ADDR_REG, (hrt_data)spctrl_cofig_info[sp_id].sp_entry);
 165         sp_ctrl_setbit(sp_id, SP_SC_REG, SP_RUN_BIT);
 166         sp_ctrl_setbit(sp_id, SP_SC_REG, SP_START_BIT);
 167         return IA_CSS_SUCCESS;
 168 }
 169
 170 /* Query the state of SP1 */
 171 ia_css_spctrl_sp_sw_state ia_css_spctrl_get_state(sp_ID_t sp_id)
 172 {
 173         ia_css_spctrl_sp_sw_state state = 0;
 174         unsigned int HIVE_ADDR_sp_sw_state;
 175         if (sp_id >= N_SP_ID)
 176                 return IA_CSS_SP_SW_TERMINATED;
 177
 178         HIVE_ADDR_sp_sw_state = spctrl_cofig_info[sp_id].spctrl_state_dmem_addr;
 179         (void)HIVE_ADDR_sp_sw_state; /* Suppres warnings in CRUN */
 180         if (sp_id == SP0_ID)
 181                 state = sp_dmem_load_uint32(sp_id, (unsigned)sp_address_of(sp_sw_state));
 182         return state;
 183 }
 184
 185 int ia_css_spctrl_is_idle(sp_ID_t sp_id)
 186 {
 187         int state = 0;
 188         assert (sp_id < N_SP_ID);
 189
 190         state = sp_ctrl_getbit(sp_id, SP_SC_REG, SP_IDLE_BIT);
 191         return state;
 192 }
 193