1 /***************************************************************************
2 * Copyright (C) 2006-2010 by Marin Mitov *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
21 #include <linux/module.h>
22 #include <linux/version.h>
23 #include <linux/stringify.h>
24 #include <linux/delay.h>
25 #include <linux/kthread.h>
26 #include <linux/slab.h>
27 #include <media/v4l2-dev.h>
28 #include <media/v4l2-ioctl.h>
29 #include <media/videobuf2-dma-contig.h>
31 #include "dt3155v4l.h"
33 #define DT3155_VENDOR_ID 0x8086
34 #define DT3155_DEVICE_ID 0x1223
36 /* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */
37 #define DT3155_CHUNK_SIZE (1U << 22)
39 #define DT3155_COH_FLAGS (GFP_KERNEL | GFP_DMA32 | __GFP_COLD | __GFP_NOWARN)
41 #define DT3155_BUF_SIZE (768 * 576)
43 #ifdef CONFIG_DT3155_STREAMING
44 #define DT3155_CAPTURE_METHOD V4L2_CAP_STREAMING
46 #define DT3155_CAPTURE_METHOD V4L2_CAP_READWRITE
49 /* global initializers (for all boards) */
50 #ifdef CONFIG_DT3155_CCIR
51 static const u8 csr2_init
= VT_50HZ
;
52 #define DT3155_CURRENT_NORM V4L2_STD_625_50
53 static const unsigned int img_width
= 768;
54 static const unsigned int img_height
= 576;
55 static const unsigned int frames_per_sec
= 25;
56 static const struct v4l2_fmtdesc frame_std
[] = {
59 .type
= V4L2_BUF_TYPE_VIDEO_CAPTURE
,
61 .description
= "CCIR/50Hz 8 bits gray",
62 .pixelformat
= V4L2_PIX_FMT_GREY
,
66 static const u8 csr2_init
= VT_60HZ
;
67 #define DT3155_CURRENT_NORM V4L2_STD_525_60
68 static const unsigned int img_width
= 640;
69 static const unsigned int img_height
= 480;
70 static const unsigned int frames_per_sec
= 30;
71 static const struct v4l2_fmtdesc frame_std
[] = {
74 .type
= V4L2_BUF_TYPE_VIDEO_CAPTURE
,
76 .description
= "RS-170/60Hz 8 bits gray",
77 .pixelformat
= V4L2_PIX_FMT_GREY
,
82 #define NUM_OF_FORMATS ARRAY_SIZE(frame_std)
84 static u8 config_init
= ACQ_MODE_EVEN
;
87 * read_i2c_reg - reads an internal i2c register
89 * @addr: dt3155 mmio base address
90 * @index: index (internal address) of register to read
91 * @data: pointer to byte the read data will be placed in
93 * returns: zero on success or error code
95 * This function starts reading the specified (by index) register
96 * and busy waits for the process to finish. The result is placed
97 * in a byte pointed by data.
100 read_i2c_reg(void __iomem
*addr
, u8 index
, u8
*data
)
104 iowrite32((tmp
<<17) | IIC_READ
, addr
+ IIC_CSR2
);
106 udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
107 if (ioread32(addr
+ IIC_CSR2
) & NEW_CYCLE
)
108 return -EIO
; /* error: NEW_CYCLE not cleared */
109 tmp
= ioread32(addr
+ IIC_CSR1
);
110 if (tmp
& DIRECT_ABORT
) {
111 /* reset DIRECT_ABORT bit */
112 iowrite32(DIRECT_ABORT
, addr
+ IIC_CSR1
);
113 return -EIO
; /* error: DIRECT_ABORT set */
120 * write_i2c_reg - writes to an internal i2c register
122 * @addr: dt3155 mmio base address
123 * @index: index (internal address) of register to read
124 * @data: data to be written
126 * returns: zero on success or error code
128 * This function starts writting the specified (by index) register
129 * and busy waits for the process to finish.
132 write_i2c_reg(void __iomem
*addr
, u8 index
, u8 data
)
136 iowrite32((tmp
<<17) | IIC_WRITE
| data
, addr
+ IIC_CSR2
);
138 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
139 if (ioread32(addr
+ IIC_CSR2
) & NEW_CYCLE
)
140 return -EIO
; /* error: NEW_CYCLE not cleared */
141 if (ioread32(addr
+ IIC_CSR1
) & DIRECT_ABORT
) {
142 /* reset DIRECT_ABORT bit */
143 iowrite32(DIRECT_ABORT
, addr
+ IIC_CSR1
);
144 return -EIO
; /* error: DIRECT_ABORT set */
150 * write_i2c_reg_nowait - writes to an internal i2c register
152 * @addr: dt3155 mmio base address
153 * @index: index (internal address) of register to read
154 * @data: data to be written
156 * This function starts writting the specified (by index) register
159 static void write_i2c_reg_nowait(void __iomem
*addr
, u8 index
, u8 data
)
163 iowrite32((tmp
<<17) | IIC_WRITE
| data
, addr
+ IIC_CSR2
);
168 * wait_i2c_reg - waits the read/write to finish
170 * @addr: dt3155 mmio base address
172 * returns: zero on success or error code
174 * This function waits reading/writting to finish.
176 static int wait_i2c_reg(void __iomem
*addr
)
178 if (ioread32(addr
+ IIC_CSR2
) & NEW_CYCLE
)
179 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
180 if (ioread32(addr
+ IIC_CSR2
) & NEW_CYCLE
)
181 return -EIO
; /* error: NEW_CYCLE not cleared */
182 if (ioread32(addr
+ IIC_CSR1
) & DIRECT_ABORT
) {
183 /* reset DIRECT_ABORT bit */
184 iowrite32(DIRECT_ABORT
, addr
+ IIC_CSR1
);
185 return -EIO
; /* error: DIRECT_ABORT set */
191 dt3155_start_acq(struct dt3155_priv
*pd
)
193 struct vb2_buffer
*vb
= pd
->curr_buf
;
196 dma_addr
= vb2_dma_contig_plane_dma_addr(vb
, 0);
197 iowrite32(dma_addr
, pd
->regs
+ EVEN_DMA_START
);
198 iowrite32(dma_addr
+ img_width
, pd
->regs
+ ODD_DMA_START
);
199 iowrite32(img_width
, pd
->regs
+ EVEN_DMA_STRIDE
);
200 iowrite32(img_width
, pd
->regs
+ ODD_DMA_STRIDE
);
201 /* enable interrupts, clear all irq flags */
202 iowrite32(FLD_START_EN
| FLD_END_ODD_EN
| FLD_START
|
203 FLD_END_EVEN
| FLD_END_ODD
, pd
->regs
+ INT_CSR
);
204 iowrite32(FIFO_EN
| SRST
| FLD_CRPT_ODD
| FLD_CRPT_EVEN
|
205 FLD_DN_ODD
| FLD_DN_EVEN
| CAP_CONT_EVEN
| CAP_CONT_ODD
,
207 wait_i2c_reg(pd
->regs
);
208 write_i2c_reg(pd
->regs
, CONFIG
, pd
->config
);
209 write_i2c_reg(pd
->regs
, EVEN_CSR
, CSR_ERROR
| CSR_DONE
);
210 write_i2c_reg(pd
->regs
, ODD_CSR
, CSR_ERROR
| CSR_DONE
);
212 /* start the board */
213 write_i2c_reg(pd
->regs
, CSR2
, pd
->csr2
| BUSY_EVEN
| BUSY_ODD
);
214 return 0; /* success */
218 * driver-specific callbacks (vb2_ops)
221 dt3155_queue_setup(struct vb2_queue
*q
, const struct v4l2_format
*fmt
,
222 unsigned int *num_buffers
, unsigned int *num_planes
,
223 unsigned int sizes
[], void *alloc_ctxs
[])
226 struct dt3155_priv
*pd
= vb2_get_drv_priv(q
);
229 if (*num_buffers
== 0)
232 sizes
[0] = img_width
* img_height
;
233 if (pd
->q
->alloc_ctx
[0])
235 ret
= vb2_dma_contig_init_ctx(&pd
->pdev
->dev
);
238 pd
->q
->alloc_ctx
[0] = ret
;
243 dt3155_wait_prepare(struct vb2_queue
*q
)
245 struct dt3155_priv
*pd
= vb2_get_drv_priv(q
);
247 mutex_unlock(pd
->vdev
->lock
);
251 dt3155_wait_finish(struct vb2_queue
*q
)
253 struct dt3155_priv
*pd
= vb2_get_drv_priv(q
);
255 mutex_lock(pd
->vdev
->lock
);
259 dt3155_buf_prepare(struct vb2_buffer
*vb
)
261 vb2_set_plane_payload(vb
, 0, img_width
* img_height
);
266 dt3155_stop_streaming(struct vb2_queue
*q
)
268 struct dt3155_priv
*pd
= vb2_get_drv_priv(q
);
269 struct vb2_buffer
*vb
;
271 spin_lock_irq(&pd
->lock
);
272 while (!list_empty(&pd
->dmaq
)) {
273 vb
= list_first_entry(&pd
->dmaq
, typeof(*vb
), done_entry
);
274 list_del(&vb
->done_entry
);
275 vb2_buffer_done(vb
, VB2_BUF_STATE_ERROR
);
277 spin_unlock_irq(&pd
->lock
);
278 msleep(45); /* irq hendler will stop the hardware */
283 dt3155_buf_queue(struct vb2_buffer
*vb
)
285 struct dt3155_priv
*pd
= vb2_get_drv_priv(vb
->vb2_queue
);
287 /* pd->q->streaming = 1 when dt3155_buf_queue() is invoked */
288 spin_lock_irq(&pd
->lock
);
290 list_add_tail(&vb
->done_entry
, &pd
->dmaq
);
293 dt3155_start_acq(pd
);
295 spin_unlock_irq(&pd
->lock
);
298 * end driver-specific callbacks
301 const struct vb2_ops q_ops
= {
302 .queue_setup
= dt3155_queue_setup
,
303 .wait_prepare
= dt3155_wait_prepare
,
304 .wait_finish
= dt3155_wait_finish
,
305 .buf_prepare
= dt3155_buf_prepare
,
306 .stop_streaming
= dt3155_stop_streaming
,
307 .buf_queue
= dt3155_buf_queue
,
311 dt3155_irq_handler_even(int irq
, void *dev_id
)
313 struct dt3155_priv
*ipd
= dev_id
;
314 struct vb2_buffer
*ivb
;
318 tmp
= ioread32(ipd
->regs
+ INT_CSR
) & (FLD_START
| FLD_END_ODD
);
320 return IRQ_NONE
; /* not our irq */
321 if ((tmp
& FLD_START
) && !(tmp
& FLD_END_ODD
)) {
322 iowrite32(FLD_START_EN
| FLD_END_ODD_EN
| FLD_START
,
323 ipd
->regs
+ INT_CSR
);
325 return IRQ_HANDLED
; /* start of field irq */
327 if ((tmp
& FLD_START
) && (tmp
& FLD_END_ODD
))
328 ipd
->stats
.start_before_end
++;
329 /* check for corrupted fields */
330 /* write_i2c_reg(ipd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); */
331 /* write_i2c_reg(ipd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); */
332 tmp
= ioread32(ipd
->regs
+ CSR1
) & (FLD_CRPT_EVEN
| FLD_CRPT_ODD
);
334 ipd
->stats
.corrupted_fields
++;
335 iowrite32(FIFO_EN
| SRST
| FLD_CRPT_ODD
| FLD_CRPT_EVEN
|
336 FLD_DN_ODD
| FLD_DN_EVEN
|
337 CAP_CONT_EVEN
| CAP_CONT_ODD
,
342 spin_lock(&ipd
->lock
);
344 do_gettimeofday(&ipd
->curr_buf
->v4l2_buf
.timestamp
);
345 ipd
->curr_buf
->v4l2_buf
.sequence
= (ipd
->field_count
) >> 1;
346 vb2_buffer_done(ipd
->curr_buf
, VB2_BUF_STATE_DONE
);
349 if (!ipd
->q
->streaming
|| list_empty(&ipd
->dmaq
))
351 ivb
= list_first_entry(&ipd
->dmaq
, typeof(*ivb
), done_entry
);
352 list_del(&ivb
->done_entry
);
354 dma_addr
= vb2_dma_contig_plane_dma_addr(ivb
, 0);
355 iowrite32(dma_addr
, ipd
->regs
+ EVEN_DMA_START
);
356 iowrite32(dma_addr
+ img_width
, ipd
->regs
+ ODD_DMA_START
);
357 iowrite32(img_width
, ipd
->regs
+ EVEN_DMA_STRIDE
);
358 iowrite32(img_width
, ipd
->regs
+ ODD_DMA_STRIDE
);
360 /* enable interrupts, clear all irq flags */
361 iowrite32(FLD_START_EN
| FLD_END_ODD_EN
| FLD_START
|
362 FLD_END_EVEN
| FLD_END_ODD
, ipd
->regs
+ INT_CSR
);
363 spin_unlock(&ipd
->lock
);
367 ipd
->curr_buf
= NULL
;
369 write_i2c_reg_nowait(ipd
->regs
, CSR2
, ipd
->csr2
);
370 iowrite32(FIFO_EN
| SRST
| FLD_CRPT_ODD
| FLD_CRPT_EVEN
|
371 FLD_DN_ODD
| FLD_DN_EVEN
, ipd
->regs
+ CSR1
);
372 /* disable interrupts, clear all irq flags */
373 iowrite32(FLD_START
| FLD_END_EVEN
| FLD_END_ODD
, ipd
->regs
+ INT_CSR
);
374 spin_unlock(&ipd
->lock
);
379 dt3155_open(struct file
*filp
)
382 struct dt3155_priv
*pd
= video_drvdata(filp
);
384 if (mutex_lock_interruptible(&pd
->mux
))
387 pd
->q
= kzalloc(sizeof(*pd
->q
), GFP_KERNEL
);
390 goto err_alloc_queue
;
392 pd
->q
->type
= V4L2_BUF_TYPE_VIDEO_CAPTURE
;
393 pd
->q
->io_modes
= VB2_READ
| VB2_MMAP
;
395 pd
->q
->mem_ops
= &vb2_dma_contig_memops
;
396 pd
->q
->drv_priv
= pd
;
399 vb2_queue_init(pd
->q
); /* cannot fail */
400 INIT_LIST_HEAD(&pd
->dmaq
);
401 spin_lock_init(&pd
->lock
);
402 /* disable all irqs, clear all irq flags */
403 iowrite32(FLD_START
| FLD_END_EVEN
| FLD_END_ODD
,
405 ret
= request_irq(pd
->pdev
->irq
, dt3155_irq_handler_even
,
406 IRQF_SHARED
, DT3155_NAME
, pd
);
408 goto err_request_irq
;
411 return 0; /* success */
416 mutex_unlock(&pd
->mux
);
421 dt3155_release(struct file
*filp
)
423 struct dt3155_priv
*pd
= video_drvdata(filp
);
425 mutex_lock(&pd
->mux
);
427 BUG_ON(pd
->users
< 0);
429 vb2_queue_release(pd
->q
);
430 free_irq(pd
->pdev
->irq
, pd
);
431 if (pd
->q
->alloc_ctx
[0])
432 vb2_dma_contig_cleanup_ctx(pd
->q
->alloc_ctx
[0]);
436 mutex_unlock(&pd
->mux
);
441 dt3155_read(struct file
*filp
, char __user
*user
, size_t size
, loff_t
*loff
)
443 struct dt3155_priv
*pd
= video_drvdata(filp
);
446 if (mutex_lock_interruptible(&pd
->mux
))
448 res
= vb2_read(pd
->q
, user
, size
, loff
, filp
->f_flags
& O_NONBLOCK
);
449 mutex_unlock(&pd
->mux
);
454 dt3155_poll(struct file
*filp
, struct poll_table_struct
*polltbl
)
456 struct dt3155_priv
*pd
= video_drvdata(filp
);
459 mutex_lock(&pd
->mux
);
460 res
= vb2_poll(pd
->q
, filp
, polltbl
);
461 mutex_unlock(&pd
->mux
);
466 dt3155_mmap(struct file
*filp
, struct vm_area_struct
*vma
)
468 struct dt3155_priv
*pd
= video_drvdata(filp
);
471 if (mutex_lock_interruptible(&pd
->mux
))
473 res
= vb2_mmap(pd
->q
, vma
);
474 mutex_unlock(&pd
->mux
);
478 static const struct v4l2_file_operations dt3155_fops
= {
479 .owner
= THIS_MODULE
,
481 .release
= dt3155_release
,
484 .unlocked_ioctl
= video_ioctl2
, /* V4L2 ioctl handler */
489 dt3155_ioc_streamon(struct file
*filp
, void *p
, enum v4l2_buf_type type
)
491 struct dt3155_priv
*pd
= video_drvdata(filp
);
493 return vb2_streamon(pd
->q
, type
);
497 dt3155_ioc_streamoff(struct file
*filp
, void *p
, enum v4l2_buf_type type
)
499 struct dt3155_priv
*pd
= video_drvdata(filp
);
501 return vb2_streamoff(pd
->q
, type
);
505 dt3155_ioc_querycap(struct file
*filp
, void *p
, struct v4l2_capability
*cap
)
507 struct dt3155_priv
*pd
= video_drvdata(filp
);
509 strcpy(cap
->driver
, DT3155_NAME
);
510 strcpy(cap
->card
, DT3155_NAME
" frame grabber");
511 sprintf(cap
->bus_info
, "PCI:%s", pci_name(pd
->pdev
));
513 KERNEL_VERSION(DT3155_VER_MAJ
, DT3155_VER_MIN
, DT3155_VER_EXT
);
514 cap
->capabilities
= V4L2_CAP_VIDEO_CAPTURE
|
515 DT3155_CAPTURE_METHOD
;
520 dt3155_ioc_enum_fmt_vid_cap(struct file
*filp
, void *p
, struct v4l2_fmtdesc
*f
)
522 if (f
->index
>= NUM_OF_FORMATS
)
524 *f
= frame_std
[f
->index
];
529 dt3155_ioc_g_fmt_vid_cap(struct file
*filp
, void *p
, struct v4l2_format
*f
)
531 if (f
->type
!= V4L2_BUF_TYPE_VIDEO_CAPTURE
)
533 f
->fmt
.pix
.width
= img_width
;
534 f
->fmt
.pix
.height
= img_height
;
535 f
->fmt
.pix
.pixelformat
= V4L2_PIX_FMT_GREY
;
536 f
->fmt
.pix
.field
= V4L2_FIELD_NONE
;
537 f
->fmt
.pix
.bytesperline
= f
->fmt
.pix
.width
;
538 f
->fmt
.pix
.sizeimage
= f
->fmt
.pix
.width
* f
->fmt
.pix
.height
;
539 f
->fmt
.pix
.colorspace
= 0;
545 dt3155_ioc_try_fmt_vid_cap(struct file
*filp
, void *p
, struct v4l2_format
*f
)
547 if (f
->type
!= V4L2_BUF_TYPE_VIDEO_CAPTURE
)
549 if (f
->fmt
.pix
.width
== img_width
&&
550 f
->fmt
.pix
.height
== img_height
&&
551 f
->fmt
.pix
.pixelformat
== V4L2_PIX_FMT_GREY
&&
552 f
->fmt
.pix
.field
== V4L2_FIELD_NONE
&&
553 f
->fmt
.pix
.bytesperline
== f
->fmt
.pix
.width
&&
554 f
->fmt
.pix
.sizeimage
== f
->fmt
.pix
.width
* f
->fmt
.pix
.height
)
561 dt3155_ioc_s_fmt_vid_cap(struct file
*filp
, void *p
, struct v4l2_format
*f
)
563 return dt3155_ioc_g_fmt_vid_cap(filp
, p
, f
);
567 dt3155_ioc_reqbufs(struct file
*filp
, void *p
, struct v4l2_requestbuffers
*b
)
569 struct dt3155_priv
*pd
= video_drvdata(filp
);
571 return vb2_reqbufs(pd
->q
, b
);
575 dt3155_ioc_querybuf(struct file
*filp
, void *p
, struct v4l2_buffer
*b
)
577 struct dt3155_priv
*pd
= video_drvdata(filp
);
579 return vb2_querybuf(pd
->q
, b
);
583 dt3155_ioc_qbuf(struct file
*filp
, void *p
, struct v4l2_buffer
*b
)
585 struct dt3155_priv
*pd
= video_drvdata(filp
);
587 return vb2_qbuf(pd
->q
, b
);
591 dt3155_ioc_dqbuf(struct file
*filp
, void *p
, struct v4l2_buffer
*b
)
593 struct dt3155_priv
*pd
= video_drvdata(filp
);
595 return vb2_dqbuf(pd
->q
, b
, filp
->f_flags
& O_NONBLOCK
);
599 dt3155_ioc_querystd(struct file
*filp
, void *p
, v4l2_std_id
*norm
)
601 *norm
= DT3155_CURRENT_NORM
;
606 dt3155_ioc_g_std(struct file
*filp
, void *p
, v4l2_std_id
*norm
)
608 *norm
= DT3155_CURRENT_NORM
;
613 dt3155_ioc_s_std(struct file
*filp
, void *p
, v4l2_std_id
*norm
)
615 if (*norm
& DT3155_CURRENT_NORM
)
621 dt3155_ioc_enum_input(struct file
*filp
, void *p
, struct v4l2_input
*input
)
625 strcpy(input
->name
, "Coax in");
626 input
->type
= V4L2_INPUT_TYPE_CAMERA
;
628 * FIXME: input->std = 0 according to v4l2 API
629 * VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD
630 * should return -EINVAL
632 input
->std
= DT3155_CURRENT_NORM
;
633 input
->status
= 0;/* FIXME: add sync detection & V4L2_IN_ST_NO_H_LOCK */
638 dt3155_ioc_g_input(struct file
*filp
, void *p
, unsigned int *i
)
645 dt3155_ioc_s_input(struct file
*filp
, void *p
, unsigned int i
)
653 dt3155_ioc_g_parm(struct file
*filp
, void *p
, struct v4l2_streamparm
*parms
)
655 if (parms
->type
!= V4L2_BUF_TYPE_VIDEO_CAPTURE
)
657 parms
->parm
.capture
.capability
= V4L2_CAP_TIMEPERFRAME
;
658 parms
->parm
.capture
.capturemode
= 0;
659 parms
->parm
.capture
.timeperframe
.numerator
= 1001;
660 parms
->parm
.capture
.timeperframe
.denominator
= frames_per_sec
* 1000;
661 parms
->parm
.capture
.extendedmode
= 0;
662 parms
->parm
.capture
.readbuffers
= 1; /* FIXME: 2 buffers? */
667 dt3155_ioc_s_parm(struct file
*filp
, void *p
, struct v4l2_streamparm
*parms
)
669 if (parms
->type
!= V4L2_BUF_TYPE_VIDEO_CAPTURE
)
671 parms
->parm
.capture
.capability
= V4L2_CAP_TIMEPERFRAME
;
672 parms
->parm
.capture
.capturemode
= 0;
673 parms
->parm
.capture
.timeperframe
.numerator
= 1001;
674 parms
->parm
.capture
.timeperframe
.denominator
= frames_per_sec
* 1000;
675 parms
->parm
.capture
.extendedmode
= 0;
676 parms
->parm
.capture
.readbuffers
= 1; /* FIXME: 2 buffers? */
680 static const struct v4l2_ioctl_ops dt3155_ioctl_ops
= {
681 .vidioc_streamon
= dt3155_ioc_streamon
,
682 .vidioc_streamoff
= dt3155_ioc_streamoff
,
683 .vidioc_querycap
= dt3155_ioc_querycap
,
685 .vidioc_g_priority = dt3155_ioc_g_priority,
686 .vidioc_s_priority = dt3155_ioc_s_priority,
688 .vidioc_enum_fmt_vid_cap
= dt3155_ioc_enum_fmt_vid_cap
,
689 .vidioc_try_fmt_vid_cap
= dt3155_ioc_try_fmt_vid_cap
,
690 .vidioc_g_fmt_vid_cap
= dt3155_ioc_g_fmt_vid_cap
,
691 .vidioc_s_fmt_vid_cap
= dt3155_ioc_s_fmt_vid_cap
,
692 .vidioc_reqbufs
= dt3155_ioc_reqbufs
,
693 .vidioc_querybuf
= dt3155_ioc_querybuf
,
694 .vidioc_qbuf
= dt3155_ioc_qbuf
,
695 .vidioc_dqbuf
= dt3155_ioc_dqbuf
,
696 .vidioc_querystd
= dt3155_ioc_querystd
,
697 .vidioc_g_std
= dt3155_ioc_g_std
,
698 .vidioc_s_std
= dt3155_ioc_s_std
,
699 .vidioc_enum_input
= dt3155_ioc_enum_input
,
700 .vidioc_g_input
= dt3155_ioc_g_input
,
701 .vidioc_s_input
= dt3155_ioc_s_input
,
703 .vidioc_queryctrl = dt3155_ioc_queryctrl,
704 .vidioc_g_ctrl = dt3155_ioc_g_ctrl,
705 .vidioc_s_ctrl = dt3155_ioc_s_ctrl,
706 .vidioc_querymenu = dt3155_ioc_querymenu,
707 .vidioc_g_ext_ctrls = dt3155_ioc_g_ext_ctrls,
708 .vidioc_s_ext_ctrls = dt3155_ioc_s_ext_ctrls,
710 .vidioc_g_parm
= dt3155_ioc_g_parm
,
711 .vidioc_s_parm
= dt3155_ioc_s_parm
,
713 .vidioc_cropcap = dt3155_ioc_cropcap,
714 .vidioc_g_crop = dt3155_ioc_g_crop,
715 .vidioc_s_crop = dt3155_ioc_s_crop,
716 .vidioc_enum_framesizes = dt3155_ioc_enum_framesizes,
717 .vidioc_enum_frameintervals = dt3155_ioc_enum_frameintervals,
722 dt3155_init_board(struct pci_dev
*pdev
)
724 struct dt3155_priv
*pd
= pci_get_drvdata(pdev
);
730 pci_set_master(pdev
); /* dt3155 needs it */
732 /* resetting the adapter */
733 iowrite32(FLD_CRPT_ODD
| FLD_CRPT_EVEN
| FLD_DN_ODD
| FLD_DN_EVEN
,
738 /* initializing adaper registers */
739 iowrite32(FIFO_EN
| SRST
, pd
->regs
+ CSR1
);
741 iowrite32(0xEEEEEE01, pd
->regs
+ EVEN_PIXEL_FMT
);
742 iowrite32(0xEEEEEE01, pd
->regs
+ ODD_PIXEL_FMT
);
743 iowrite32(0x00000020, pd
->regs
+ FIFO_TRIGER
);
744 iowrite32(0x00000103, pd
->regs
+ XFER_MODE
);
745 iowrite32(0, pd
->regs
+ RETRY_WAIT_CNT
);
746 iowrite32(0, pd
->regs
+ INT_CSR
);
747 iowrite32(1, pd
->regs
+ EVEN_FLD_MASK
);
748 iowrite32(1, pd
->regs
+ ODD_FLD_MASK
);
749 iowrite32(0, pd
->regs
+ MASK_LENGTH
);
750 iowrite32(0x0005007C, pd
->regs
+ FIFO_FLAG_CNT
);
751 iowrite32(0x01010101, pd
->regs
+ IIC_CLK_DUR
);
754 /* verifying that we have a DT3155 board (not just a SAA7116 chip) */
755 read_i2c_reg(pd
->regs
, DT_ID
, &tmp
);
756 if (tmp
!= DT3155_ID
)
759 /* initialize AD LUT */
760 write_i2c_reg(pd
->regs
, AD_ADDR
, 0);
761 for (i
= 0; i
< 256; i
++)
762 write_i2c_reg(pd
->regs
, AD_LUT
, i
);
764 /* initialize ADC references */
765 /* FIXME: pos_ref & neg_ref depend on VT_50HZ */
766 write_i2c_reg(pd
->regs
, AD_ADDR
, AD_CMD_REG
);
767 write_i2c_reg(pd
->regs
, AD_CMD
, VIDEO_CNL_1
| SYNC_CNL_1
| SYNC_LVL_3
);
768 write_i2c_reg(pd
->regs
, AD_ADDR
, AD_POS_REF
);
769 write_i2c_reg(pd
->regs
, AD_CMD
, 34);
770 write_i2c_reg(pd
->regs
, AD_ADDR
, AD_NEG_REF
);
771 write_i2c_reg(pd
->regs
, AD_CMD
, 0);
773 /* initialize PM LUT */
774 write_i2c_reg(pd
->regs
, CONFIG
, pd
->config
| PM_LUT_PGM
);
775 for (i
= 0; i
< 256; i
++) {
776 write_i2c_reg(pd
->regs
, PM_LUT_ADDR
, i
);
777 write_i2c_reg(pd
->regs
, PM_LUT_DATA
, i
);
779 write_i2c_reg(pd
->regs
, CONFIG
, pd
->config
| PM_LUT_PGM
| PM_LUT_SEL
);
780 for (i
= 0; i
< 256; i
++) {
781 write_i2c_reg(pd
->regs
, PM_LUT_ADDR
, i
);
782 write_i2c_reg(pd
->regs
, PM_LUT_DATA
, i
);
784 write_i2c_reg(pd
->regs
, CONFIG
, pd
->config
); /* ACQ_MODE_EVEN */
786 /* select chanel 1 for input and set sync level */
787 write_i2c_reg(pd
->regs
, AD_ADDR
, AD_CMD_REG
);
788 write_i2c_reg(pd
->regs
, AD_CMD
, VIDEO_CNL_1
| SYNC_CNL_1
| SYNC_LVL_3
);
790 /* allocate memory, and initialize the DMA machine */
791 buf_cpu
= dma_alloc_coherent(&pdev
->dev
, DT3155_BUF_SIZE
, &buf_dma
,
795 iowrite32(buf_dma
, pd
->regs
+ EVEN_DMA_START
);
796 iowrite32(buf_dma
, pd
->regs
+ ODD_DMA_START
);
797 iowrite32(0, pd
->regs
+ EVEN_DMA_STRIDE
);
798 iowrite32(0, pd
->regs
+ ODD_DMA_STRIDE
);
800 /* Perform a pseudo even field acquire */
801 iowrite32(FIFO_EN
| SRST
| CAP_CONT_ODD
, pd
->regs
+ CSR1
);
802 write_i2c_reg(pd
->regs
, CSR2
, pd
->csr2
| SYNC_SNTL
);
803 write_i2c_reg(pd
->regs
, CONFIG
, pd
->config
);
804 write_i2c_reg(pd
->regs
, EVEN_CSR
, CSR_SNGL
);
805 write_i2c_reg(pd
->regs
, CSR2
, pd
->csr2
| BUSY_EVEN
| SYNC_SNTL
);
807 read_i2c_reg(pd
->regs
, CSR2
, &tmp
);
808 write_i2c_reg(pd
->regs
, EVEN_CSR
, CSR_ERROR
| CSR_SNGL
| CSR_DONE
);
809 write_i2c_reg(pd
->regs
, ODD_CSR
, CSR_ERROR
| CSR_SNGL
| CSR_DONE
);
810 write_i2c_reg(pd
->regs
, CSR2
, pd
->csr2
);
811 iowrite32(FIFO_EN
| SRST
| FLD_DN_EVEN
| FLD_DN_ODD
, pd
->regs
+ CSR1
);
813 /* deallocate memory */
814 dma_free_coherent(&pdev
->dev
, DT3155_BUF_SIZE
, buf_cpu
, buf_dma
);
820 static struct video_device dt3155_vdev
= {
822 .fops
= &dt3155_fops
,
823 .ioctl_ops
= &dt3155_ioctl_ops
,
825 .release
= video_device_release
,
826 .tvnorms
= DT3155_CURRENT_NORM
,
827 .current_norm
= DT3155_CURRENT_NORM
,
830 /* same as in drivers/base/dma-coherent.c */
831 struct dma_coherent_mem
{
833 dma_addr_t device_base
;
836 unsigned long *bitmap
;
840 dt3155_alloc_coherent(struct device
*dev
, size_t size
, int flags
)
842 struct dma_coherent_mem
*mem
;
844 int pages
= size
>> PAGE_SHIFT
;
845 int bitmap_size
= BITS_TO_LONGS(pages
) * sizeof(long);
847 if ((flags
& DMA_MEMORY_MAP
) == 0)
854 mem
= kzalloc(sizeof(*mem
), GFP_KERNEL
);
857 mem
->virt_base
= dma_alloc_coherent(dev
, size
, &dev_base
,
860 goto err_alloc_coherent
;
861 mem
->bitmap
= kzalloc(bitmap_size
, GFP_KERNEL
);
865 /* coherent_dma_mask is already set to 32 bits */
866 mem
->device_base
= dev_base
;
870 return DMA_MEMORY_MAP
;
873 dma_free_coherent(dev
, size
, mem
->virt_base
, dev_base
);
881 dt3155_free_coherent(struct device
*dev
)
883 struct dma_coherent_mem
*mem
= dev
->dma_mem
;
888 dma_free_coherent(dev
, mem
->size
<< PAGE_SHIFT
,
889 mem
->virt_base
, mem
->device_base
);
895 dt3155_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
898 struct dt3155_priv
*pd
;
900 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
903 err
= dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(32));
906 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
909 pd
->vdev
= video_device_alloc();
911 goto err_video_device_alloc
;
912 *pd
->vdev
= dt3155_vdev
;
913 pci_set_drvdata(pdev
, pd
); /* for use in dt3155_remove() */
914 video_set_drvdata(pd
->vdev
, pd
); /* for use in video_fops */
917 INIT_LIST_HEAD(&pd
->dmaq
);
918 mutex_init(&pd
->mux
);
919 pd
->vdev
->lock
= &pd
->mux
; /* for locking v4l2_file_operations */
920 spin_lock_init(&pd
->lock
);
921 pd
->csr2
= csr2_init
;
922 pd
->config
= config_init
;
923 err
= pci_enable_device(pdev
);
926 err
= pci_request_region(pdev
, 0, pci_name(pdev
));
929 pd
->regs
= pci_iomap(pdev
, 0, pci_resource_len(pd
->pdev
, 0));
934 err
= dt3155_init_board(pdev
);
937 err
= video_register_device(pd
->vdev
, VFL_TYPE_GRABBER
, -1);
940 if (dt3155_alloc_coherent(&pdev
->dev
, DT3155_CHUNK_SIZE
,
942 dev_info(&pdev
->dev
, "preallocated 8 buffers\n");
943 dev_info(&pdev
->dev
, "/dev/video%i is ready\n", pd
->vdev
->minor
);
944 return 0; /* success */
947 pci_iounmap(pdev
, pd
->regs
);
949 pci_release_region(pdev
, 0);
951 pci_disable_device(pdev
);
953 video_device_release(pd
->vdev
);
954 err_video_device_alloc
:
960 dt3155_remove(struct pci_dev
*pdev
)
962 struct dt3155_priv
*pd
= pci_get_drvdata(pdev
);
964 dt3155_free_coherent(&pdev
->dev
);
965 video_unregister_device(pd
->vdev
);
966 pci_iounmap(pdev
, pd
->regs
);
967 pci_release_region(pdev
, 0);
968 pci_disable_device(pdev
);
970 * video_device_release() is invoked automatically
971 * see: struct video_device dt3155_vdev
976 static DEFINE_PCI_DEVICE_TABLE(pci_ids
) = {
977 { PCI_DEVICE(DT3155_VENDOR_ID
, DT3155_DEVICE_ID
) },
978 { 0, /* zero marks the end */ },
980 MODULE_DEVICE_TABLE(pci
, pci_ids
);
982 static struct pci_driver pci_driver
= {
985 .probe
= dt3155_probe
,
986 .remove
= dt3155_remove
,
989 module_pci_driver(pci_driver
);
991 MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
992 MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
993 MODULE_VERSION(DT3155_VERSION
);
994 MODULE_LICENSE("GPL");