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Merge tag 'v3.8-rc1' into staging/for_v3.9
[mirror_ubuntu-artful-kernel.git] / drivers / staging / media / lirc / lirc_sir.c
1 /*
2 * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk>
3 *
4 * lirc_sir - Device driver for use with SIR (serial infra red)
5 * mode of IrDA on many notebooks.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 *
22 * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> :
23 * added timeout and relaxed pulse detection, removed gap bug
24 *
25 * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> :
26 * added support for Tekram Irmate 210 (sending does not work yet,
27 * kind of disappointing that nobody was able to implement that
28 * before),
29 * major clean-up
30 *
31 * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> :
32 * added support for StrongARM SA1100 embedded microprocessor
33 * parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King
34 */
35
36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37
38 #include <linux/module.h>
39 #include <linux/sched.h>
40 #include <linux/errno.h>
41 #include <linux/signal.h>
42 #include <linux/fs.h>
43 #include <linux/interrupt.h>
44 #include <linux/ioport.h>
45 #include <linux/kernel.h>
46 #include <linux/serial_reg.h>
47 #include <linux/time.h>
48 #include <linux/string.h>
49 #include <linux/types.h>
50 #include <linux/wait.h>
51 #include <linux/mm.h>
52 #include <linux/delay.h>
53 #include <linux/poll.h>
54 #include <linux/io.h>
55 #include <asm/irq.h>
56 #include <linux/fcntl.h>
57 #include <linux/platform_device.h>
58 #ifdef LIRC_ON_SA1100
59 #include <asm/hardware.h>
60 #ifdef CONFIG_SA1100_COLLIE
61 #include <asm/arch/tc35143.h>
62 #include <asm/ucb1200.h>
63 #endif
64 #endif
65
66 #include <linux/timer.h>
67
68 #include <media/lirc.h>
69 #include <media/lirc_dev.h>
70
71 /* SECTION: Definitions */
72
73 /*** Tekram dongle ***/
74 #ifdef LIRC_SIR_TEKRAM
75 /* stolen from kernel source */
76 /* definitions for Tekram dongle */
77 #define TEKRAM_115200 0x00
78 #define TEKRAM_57600 0x01
79 #define TEKRAM_38400 0x02
80 #define TEKRAM_19200 0x03
81 #define TEKRAM_9600 0x04
82 #define TEKRAM_2400 0x08
83
84 #define TEKRAM_PW 0x10 /* Pulse select bit */
85
86 /* 10bit * 1s/115200bit in milliseconds = 87ms*/
87 #define TIME_CONST (10000000ul/115200ul)
88
89 #endif
90
91 #ifdef LIRC_SIR_ACTISYS_ACT200L
92 static void init_act200(void);
93 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
94 static void init_act220(void);
95 #endif
96
97 /*** SA1100 ***/
98 #ifdef LIRC_ON_SA1100
99 struct sa1100_ser2_registers {
100 /* HSSP control register */
101 unsigned char hscr0;
102 /* UART registers */
103 unsigned char utcr0;
104 unsigned char utcr1;
105 unsigned char utcr2;
106 unsigned char utcr3;
107 unsigned char utcr4;
108 unsigned char utdr;
109 unsigned char utsr0;
110 unsigned char utsr1;
111 } sr;
112
113 static int irq = IRQ_Ser2ICP;
114
115 #define LIRC_ON_SA1100_TRANSMITTER_LATENCY 0
116
117 /* pulse/space ratio of 50/50 */
118 static unsigned long pulse_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY);
119 /* 1000000/freq-pulse_width */
120 static unsigned long space_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY);
121 static unsigned int freq = 38000; /* modulation frequency */
122 static unsigned int duty_cycle = 50; /* duty cycle of 50% */
123
124 #endif
125
126 #define RBUF_LEN 1024
127 #define WBUF_LEN 1024
128
129 #define LIRC_DRIVER_NAME "lirc_sir"
130
131 #define PULSE '['
132
133 #ifndef LIRC_SIR_TEKRAM
134 /* 9bit * 1s/115200bit in milli seconds = 78.125ms*/
135 #define TIME_CONST (9000000ul/115200ul)
136 #endif
137
138
139 /* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */
140 #define SIR_TIMEOUT (HZ*5/100)
141
142 #ifndef LIRC_ON_SA1100
143 #ifndef LIRC_IRQ
144 #define LIRC_IRQ 4
145 #endif
146 #ifndef LIRC_PORT
147 /* for external dongles, default to com1 */
148 #if defined(LIRC_SIR_ACTISYS_ACT200L) || \
149 defined(LIRC_SIR_ACTISYS_ACT220L) || \
150 defined(LIRC_SIR_TEKRAM)
151 #define LIRC_PORT 0x3f8
152 #else
153 /* onboard sir ports are typically com3 */
154 #define LIRC_PORT 0x3e8
155 #endif
156 #endif
157
158 static int io = LIRC_PORT;
159 static int irq = LIRC_IRQ;
160 static int threshold = 3;
161 #endif
162
163 static DEFINE_SPINLOCK(timer_lock);
164 static struct timer_list timerlist;
165 /* time of last signal change detected */
166 static struct timeval last_tv = {0, 0};
167 /* time of last UART data ready interrupt */
168 static struct timeval last_intr_tv = {0, 0};
169 static int last_value;
170
171 static DECLARE_WAIT_QUEUE_HEAD(lirc_read_queue);
172
173 static DEFINE_SPINLOCK(hardware_lock);
174
175 static int rx_buf[RBUF_LEN];
176 static unsigned int rx_tail, rx_head;
177
178 static bool debug;
179 #define dprintk(fmt, args...) \
180 do { \
181 if (debug) \
182 printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \
183 fmt, ## args); \
184 } while (0)
185
186 /* SECTION: Prototypes */
187
188 /* Communication with user-space */
189 static unsigned int lirc_poll(struct file *file, poll_table *wait);
190 static ssize_t lirc_read(struct file *file, char *buf, size_t count,
191 loff_t *ppos);
192 static ssize_t lirc_write(struct file *file, const char *buf, size_t n,
193 loff_t *pos);
194 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
195 static void add_read_queue(int flag, unsigned long val);
196 static int init_chrdev(void);
197 static void drop_chrdev(void);
198 /* Hardware */
199 static irqreturn_t sir_interrupt(int irq, void *dev_id);
200 static void send_space(unsigned long len);
201 static void send_pulse(unsigned long len);
202 static int init_hardware(void);
203 static void drop_hardware(void);
204 /* Initialisation */
205 static int init_port(void);
206 static void drop_port(void);
207
208 #ifdef LIRC_ON_SA1100
209 static void on(void)
210 {
211 PPSR |= PPC_TXD2;
212 }
213
214 static void off(void)
215 {
216 PPSR &= ~PPC_TXD2;
217 }
218 #else
219 static inline unsigned int sinp(int offset)
220 {
221 return inb(io + offset);
222 }
223
224 static inline void soutp(int offset, int value)
225 {
226 outb(value, io + offset);
227 }
228 #endif
229
230 #ifndef MAX_UDELAY_MS
231 #define MAX_UDELAY_US 5000
232 #else
233 #define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
234 #endif
235
236 static void safe_udelay(unsigned long usecs)
237 {
238 while (usecs > MAX_UDELAY_US) {
239 udelay(MAX_UDELAY_US);
240 usecs -= MAX_UDELAY_US;
241 }
242 udelay(usecs);
243 }
244
245 /* SECTION: Communication with user-space */
246
247 static unsigned int lirc_poll(struct file *file, poll_table *wait)
248 {
249 poll_wait(file, &lirc_read_queue, wait);
250 if (rx_head != rx_tail)
251 return POLLIN | POLLRDNORM;
252 return 0;
253 }
254
255 static ssize_t lirc_read(struct file *file, char *buf, size_t count,
256 loff_t *ppos)
257 {
258 int n = 0;
259 int retval = 0;
260 DECLARE_WAITQUEUE(wait, current);
261
262 if (count % sizeof(int))
263 return -EINVAL;
264
265 add_wait_queue(&lirc_read_queue, &wait);
266 set_current_state(TASK_INTERRUPTIBLE);
267 while (n < count) {
268 if (rx_head != rx_tail) {
269 if (copy_to_user((void *) buf + n,
270 (void *) (rx_buf + rx_head),
271 sizeof(int))) {
272 retval = -EFAULT;
273 break;
274 }
275 rx_head = (rx_head + 1) & (RBUF_LEN - 1);
276 n += sizeof(int);
277 } else {
278 if (file->f_flags & O_NONBLOCK) {
279 retval = -EAGAIN;
280 break;
281 }
282 if (signal_pending(current)) {
283 retval = -ERESTARTSYS;
284 break;
285 }
286 schedule();
287 set_current_state(TASK_INTERRUPTIBLE);
288 }
289 }
290 remove_wait_queue(&lirc_read_queue, &wait);
291 set_current_state(TASK_RUNNING);
292 return n ? n : retval;
293 }
294 static ssize_t lirc_write(struct file *file, const char *buf, size_t n,
295 loff_t *pos)
296 {
297 unsigned long flags;
298 int i, count;
299 int *tx_buf;
300
301 count = n / sizeof(int);
302 if (n % sizeof(int) || count % 2 == 0)
303 return -EINVAL;
304 tx_buf = memdup_user(buf, n);
305 if (IS_ERR(tx_buf))
306 return PTR_ERR(tx_buf);
307 i = 0;
308 #ifdef LIRC_ON_SA1100
309 /* disable receiver */
310 Ser2UTCR3 = 0;
311 #endif
312 local_irq_save(flags);
313 while (1) {
314 if (i >= count)
315 break;
316 if (tx_buf[i])
317 send_pulse(tx_buf[i]);
318 i++;
319 if (i >= count)
320 break;
321 if (tx_buf[i])
322 send_space(tx_buf[i]);
323 i++;
324 }
325 local_irq_restore(flags);
326 #ifdef LIRC_ON_SA1100
327 off();
328 udelay(1000); /* wait 1ms for IR diode to recover */
329 Ser2UTCR3 = 0;
330 /* clear status register to prevent unwanted interrupts */
331 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
332 /* enable receiver */
333 Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE;
334 #endif
335 kfree(tx_buf);
336 return count;
337 }
338
339 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
340 {
341 int retval = 0;
342 __u32 value = 0;
343 #ifdef LIRC_ON_SA1100
344
345 if (cmd == LIRC_GET_FEATURES)
346 value = LIRC_CAN_SEND_PULSE |
347 LIRC_CAN_SET_SEND_DUTY_CYCLE |
348 LIRC_CAN_SET_SEND_CARRIER |
349 LIRC_CAN_REC_MODE2;
350 else if (cmd == LIRC_GET_SEND_MODE)
351 value = LIRC_MODE_PULSE;
352 else if (cmd == LIRC_GET_REC_MODE)
353 value = LIRC_MODE_MODE2;
354 #else
355 if (cmd == LIRC_GET_FEATURES)
356 value = LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2;
357 else if (cmd == LIRC_GET_SEND_MODE)
358 value = LIRC_MODE_PULSE;
359 else if (cmd == LIRC_GET_REC_MODE)
360 value = LIRC_MODE_MODE2;
361 #endif
362
363 switch (cmd) {
364 case LIRC_GET_FEATURES:
365 case LIRC_GET_SEND_MODE:
366 case LIRC_GET_REC_MODE:
367 retval = put_user(value, (__u32 *) arg);
368 break;
369
370 case LIRC_SET_SEND_MODE:
371 case LIRC_SET_REC_MODE:
372 retval = get_user(value, (__u32 *) arg);
373 break;
374 #ifdef LIRC_ON_SA1100
375 case LIRC_SET_SEND_DUTY_CYCLE:
376 retval = get_user(value, (__u32 *) arg);
377 if (retval)
378 return retval;
379 if (value <= 0 || value > 100)
380 return -EINVAL;
381 /* (value/100)*(1000000/freq) */
382 duty_cycle = value;
383 pulse_width = (unsigned long) duty_cycle*10000/freq;
384 space_width = (unsigned long) 1000000L/freq-pulse_width;
385 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
386 pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
387 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
388 space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
389 break;
390 case LIRC_SET_SEND_CARRIER:
391 retval = get_user(value, (__u32 *) arg);
392 if (retval)
393 return retval;
394 if (value > 500000 || value < 20000)
395 return -EINVAL;
396 freq = value;
397 pulse_width = (unsigned long) duty_cycle*10000/freq;
398 space_width = (unsigned long) 1000000L/freq-pulse_width;
399 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
400 pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
401 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
402 space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
403 break;
404 #endif
405 default:
406 retval = -ENOIOCTLCMD;
407
408 }
409
410 if (retval)
411 return retval;
412 if (cmd == LIRC_SET_REC_MODE) {
413 if (value != LIRC_MODE_MODE2)
414 retval = -ENOSYS;
415 } else if (cmd == LIRC_SET_SEND_MODE) {
416 if (value != LIRC_MODE_PULSE)
417 retval = -ENOSYS;
418 }
419
420 return retval;
421 }
422
423 static void add_read_queue(int flag, unsigned long val)
424 {
425 unsigned int new_rx_tail;
426 int newval;
427
428 dprintk("add flag %d with val %lu\n", flag, val);
429
430 newval = val & PULSE_MASK;
431
432 /*
433 * statistically, pulses are ~TIME_CONST/2 too long. we could
434 * maybe make this more exact, but this is good enough
435 */
436 if (flag) {
437 /* pulse */
438 if (newval > TIME_CONST/2)
439 newval -= TIME_CONST/2;
440 else /* should not ever happen */
441 newval = 1;
442 newval |= PULSE_BIT;
443 } else {
444 newval += TIME_CONST/2;
445 }
446 new_rx_tail = (rx_tail + 1) & (RBUF_LEN - 1);
447 if (new_rx_tail == rx_head) {
448 dprintk("Buffer overrun.\n");
449 return;
450 }
451 rx_buf[rx_tail] = newval;
452 rx_tail = new_rx_tail;
453 wake_up_interruptible(&lirc_read_queue);
454 }
455
456 static const struct file_operations lirc_fops = {
457 .owner = THIS_MODULE,
458 .read = lirc_read,
459 .write = lirc_write,
460 .poll = lirc_poll,
461 .unlocked_ioctl = lirc_ioctl,
462 #ifdef CONFIG_COMPAT
463 .compat_ioctl = lirc_ioctl,
464 #endif
465 .open = lirc_dev_fop_open,
466 .release = lirc_dev_fop_close,
467 .llseek = no_llseek,
468 };
469
470 static int set_use_inc(void *data)
471 {
472 return 0;
473 }
474
475 static void set_use_dec(void *data)
476 {
477 }
478
479 static struct lirc_driver driver = {
480 .name = LIRC_DRIVER_NAME,
481 .minor = -1,
482 .code_length = 1,
483 .sample_rate = 0,
484 .data = NULL,
485 .add_to_buf = NULL,
486 .set_use_inc = set_use_inc,
487 .set_use_dec = set_use_dec,
488 .fops = &lirc_fops,
489 .dev = NULL,
490 .owner = THIS_MODULE,
491 };
492
493 static struct platform_device *lirc_sir_dev;
494
495 static int init_chrdev(void)
496 {
497 driver.dev = &lirc_sir_dev->dev;
498 driver.minor = lirc_register_driver(&driver);
499 if (driver.minor < 0) {
500 pr_err("init_chrdev() failed.\n");
501 return -EIO;
502 }
503 return 0;
504 }
505
506 static void drop_chrdev(void)
507 {
508 lirc_unregister_driver(driver.minor);
509 }
510
511 /* SECTION: Hardware */
512 static long delta(struct timeval *tv1, struct timeval *tv2)
513 {
514 unsigned long deltv;
515
516 deltv = tv2->tv_sec - tv1->tv_sec;
517 if (deltv > 15)
518 deltv = 0xFFFFFF;
519 else
520 deltv = deltv*1000000 +
521 tv2->tv_usec -
522 tv1->tv_usec;
523 return deltv;
524 }
525
526 static void sir_timeout(unsigned long data)
527 {
528 /*
529 * if last received signal was a pulse, but receiving stopped
530 * within the 9 bit frame, we need to finish this pulse and
531 * simulate a signal change to from pulse to space. Otherwise
532 * upper layers will receive two sequences next time.
533 */
534
535 unsigned long flags;
536 unsigned long pulse_end;
537
538 /* avoid interference with interrupt */
539 spin_lock_irqsave(&timer_lock, flags);
540 if (last_value) {
541 #ifndef LIRC_ON_SA1100
542 /* clear unread bits in UART and restart */
543 outb(UART_FCR_CLEAR_RCVR, io + UART_FCR);
544 #endif
545 /* determine 'virtual' pulse end: */
546 pulse_end = delta(&last_tv, &last_intr_tv);
547 dprintk("timeout add %d for %lu usec\n", last_value, pulse_end);
548 add_read_queue(last_value, pulse_end);
549 last_value = 0;
550 last_tv = last_intr_tv;
551 }
552 spin_unlock_irqrestore(&timer_lock, flags);
553 }
554
555 static irqreturn_t sir_interrupt(int irq, void *dev_id)
556 {
557 unsigned char data;
558 struct timeval curr_tv;
559 static unsigned long deltv;
560 #ifdef LIRC_ON_SA1100
561 int status;
562 static int n;
563
564 status = Ser2UTSR0;
565 /*
566 * Deal with any receive errors first. The bytes in error may be
567 * the only bytes in the receive FIFO, so we do this first.
568 */
569 while (status & UTSR0_EIF) {
570 int bstat;
571
572 if (debug) {
573 dprintk("EIF\n");
574 bstat = Ser2UTSR1;
575
576 if (bstat & UTSR1_FRE)
577 dprintk("frame error\n");
578 if (bstat & UTSR1_ROR)
579 dprintk("receive fifo overrun\n");
580 if (bstat & UTSR1_PRE)
581 dprintk("parity error\n");
582 }
583
584 bstat = Ser2UTDR;
585 n++;
586 status = Ser2UTSR0;
587 }
588
589 if (status & (UTSR0_RFS | UTSR0_RID)) {
590 do_gettimeofday(&curr_tv);
591 deltv = delta(&last_tv, &curr_tv);
592 do {
593 data = Ser2UTDR;
594 dprintk("%d data: %u\n", n, (unsigned int) data);
595 n++;
596 } while (status & UTSR0_RID && /* do not empty fifo in order to
597 * get UTSR0_RID in any case */
598 Ser2UTSR1 & UTSR1_RNE); /* data ready */
599
600 if (status&UTSR0_RID) {
601 add_read_queue(0 , deltv - n * TIME_CONST); /*space*/
602 add_read_queue(1, n * TIME_CONST); /*pulse*/
603 n = 0;
604 last_tv = curr_tv;
605 }
606 }
607
608 if (status & UTSR0_TFS)
609 pr_err("transmit fifo not full, shouldn't happen\n");
610
611 /* We must clear certain bits. */
612 status &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
613 if (status)
614 Ser2UTSR0 = status;
615 #else
616 unsigned long deltintrtv;
617 unsigned long flags;
618 int iir, lsr;
619
620 while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) {
621 switch (iir&UART_IIR_ID) { /* FIXME toto treba preriedit */
622 case UART_IIR_MSI:
623 (void) inb(io + UART_MSR);
624 break;
625 case UART_IIR_RLSI:
626 (void) inb(io + UART_LSR);
627 break;
628 case UART_IIR_THRI:
629 #if 0
630 if (lsr & UART_LSR_THRE) /* FIFO is empty */
631 outb(data, io + UART_TX)
632 #endif
633 break;
634 case UART_IIR_RDI:
635 /* avoid interference with timer */
636 spin_lock_irqsave(&timer_lock, flags);
637 do {
638 del_timer(&timerlist);
639 data = inb(io + UART_RX);
640 do_gettimeofday(&curr_tv);
641 deltv = delta(&last_tv, &curr_tv);
642 deltintrtv = delta(&last_intr_tv, &curr_tv);
643 dprintk("t %lu, d %d\n", deltintrtv, (int)data);
644 /*
645 * if nothing came in last X cycles,
646 * it was gap
647 */
648 if (deltintrtv > TIME_CONST * threshold) {
649 if (last_value) {
650 dprintk("GAP\n");
651 /* simulate signal change */
652 add_read_queue(last_value,
653 deltv -
654 deltintrtv);
655 last_value = 0;
656 last_tv.tv_sec =
657 last_intr_tv.tv_sec;
658 last_tv.tv_usec =
659 last_intr_tv.tv_usec;
660 deltv = deltintrtv;
661 }
662 }
663 data = 1;
664 if (data ^ last_value) {
665 /*
666 * deltintrtv > 2*TIME_CONST, remember?
667 * the other case is timeout
668 */
669 add_read_queue(last_value,
670 deltv-TIME_CONST);
671 last_value = data;
672 last_tv = curr_tv;
673 if (last_tv.tv_usec >= TIME_CONST) {
674 last_tv.tv_usec -= TIME_CONST;
675 } else {
676 last_tv.tv_sec--;
677 last_tv.tv_usec += 1000000 -
678 TIME_CONST;
679 }
680 }
681 last_intr_tv = curr_tv;
682 if (data) {
683 /*
684 * start timer for end of
685 * sequence detection
686 */
687 timerlist.expires = jiffies +
688 SIR_TIMEOUT;
689 add_timer(&timerlist);
690 }
691
692 lsr = inb(io + UART_LSR);
693 } while (lsr & UART_LSR_DR); /* data ready */
694 spin_unlock_irqrestore(&timer_lock, flags);
695 break;
696 default:
697 break;
698 }
699 }
700 #endif
701 return IRQ_RETVAL(IRQ_HANDLED);
702 }
703
704 #ifdef LIRC_ON_SA1100
705 static void send_pulse(unsigned long length)
706 {
707 unsigned long k, delay;
708 int flag;
709
710 if (length == 0)
711 return;
712 /*
713 * this won't give us the carrier frequency we really want
714 * due to integer arithmetic, but we can accept this inaccuracy
715 */
716
717 for (k = flag = 0; k < length; k += delay, flag = !flag) {
718 if (flag) {
719 off();
720 delay = space_width;
721 } else {
722 on();
723 delay = pulse_width;
724 }
725 safe_udelay(delay);
726 }
727 off();
728 }
729
730 static void send_space(unsigned long length)
731 {
732 if (length == 0)
733 return;
734 off();
735 safe_udelay(length);
736 }
737 #else
738 static void send_space(unsigned long len)
739 {
740 safe_udelay(len);
741 }
742
743 static void send_pulse(unsigned long len)
744 {
745 long bytes_out = len / TIME_CONST;
746
747 if (bytes_out == 0)
748 bytes_out++;
749
750 while (bytes_out--) {
751 outb(PULSE, io + UART_TX);
752 /* FIXME treba seriozne cakanie z char/serial.c */
753 while (!(inb(io + UART_LSR) & UART_LSR_THRE))
754 ;
755 }
756 }
757 #endif
758
759 #ifdef CONFIG_SA1100_COLLIE
760 static int sa1100_irda_set_power_collie(int state)
761 {
762 if (state) {
763 /*
764 * 0 - off
765 * 1 - short range, lowest power
766 * 2 - medium range, medium power
767 * 3 - maximum range, high power
768 */
769 ucb1200_set_io_direction(TC35143_GPIO_IR_ON,
770 TC35143_IODIR_OUTPUT);
771 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_LOW);
772 udelay(100);
773 } else {
774 /* OFF */
775 ucb1200_set_io_direction(TC35143_GPIO_IR_ON,
776 TC35143_IODIR_OUTPUT);
777 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_HIGH);
778 }
779 return 0;
780 }
781 #endif
782
783 static int init_hardware(void)
784 {
785 unsigned long flags;
786
787 spin_lock_irqsave(&hardware_lock, flags);
788 /* reset UART */
789 #ifdef LIRC_ON_SA1100
790 #ifdef CONFIG_SA1100_BITSY
791 if (machine_is_bitsy()) {
792 pr_info("Power on IR module\n");
793 set_bitsy_egpio(EGPIO_BITSY_IR_ON);
794 }
795 #endif
796 #ifdef CONFIG_SA1100_COLLIE
797 sa1100_irda_set_power_collie(3); /* power on */
798 #endif
799 sr.hscr0 = Ser2HSCR0;
800
801 sr.utcr0 = Ser2UTCR0;
802 sr.utcr1 = Ser2UTCR1;
803 sr.utcr2 = Ser2UTCR2;
804 sr.utcr3 = Ser2UTCR3;
805 sr.utcr4 = Ser2UTCR4;
806
807 sr.utdr = Ser2UTDR;
808 sr.utsr0 = Ser2UTSR0;
809 sr.utsr1 = Ser2UTSR1;
810
811 /* configure GPIO */
812 /* output */
813 PPDR |= PPC_TXD2;
814 PSDR |= PPC_TXD2;
815 /* set output to 0 */
816 off();
817
818 /* Enable HP-SIR modulation, and ensure that the port is disabled. */
819 Ser2UTCR3 = 0;
820 Ser2HSCR0 = sr.hscr0 & (~HSCR0_HSSP);
821
822 /* clear status register to prevent unwanted interrupts */
823 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
824
825 /* 7N1 */
826 Ser2UTCR0 = UTCR0_1StpBit|UTCR0_7BitData;
827 /* 115200 */
828 Ser2UTCR1 = 0;
829 Ser2UTCR2 = 1;
830 /* use HPSIR, 1.6 usec pulses */
831 Ser2UTCR4 = UTCR4_HPSIR|UTCR4_Z1_6us;
832
833 /* enable receiver, receive fifo interrupt */
834 Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE;
835
836 /* clear status register to prevent unwanted interrupts */
837 Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
838
839 #elif defined(LIRC_SIR_TEKRAM)
840 /* disable FIFO */
841 soutp(UART_FCR,
842 UART_FCR_CLEAR_RCVR|
843 UART_FCR_CLEAR_XMIT|
844 UART_FCR_TRIGGER_1);
845
846 /* Set DLAB 0. */
847 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
848
849 /* First of all, disable all interrupts */
850 soutp(UART_IER, sinp(UART_IER) &
851 (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI)));
852
853 /* Set DLAB 1. */
854 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
855
856 /* Set divisor to 12 => 9600 Baud */
857 soutp(UART_DLM, 0);
858 soutp(UART_DLL, 12);
859
860 /* Set DLAB 0. */
861 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
862
863 /* power supply */
864 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
865 safe_udelay(50*1000);
866
867 /* -DTR low -> reset PIC */
868 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
869 udelay(1*1000);
870
871 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
872 udelay(100);
873
874
875 /* -RTS low -> send control byte */
876 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
877 udelay(7);
878 soutp(UART_TX, TEKRAM_115200|TEKRAM_PW);
879
880 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
881 udelay(1500);
882
883 /* back to normal operation */
884 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
885 udelay(50);
886
887 udelay(1500);
888
889 /* read previous control byte */
890 pr_info("0x%02x\n", sinp(UART_RX));
891
892 /* Set DLAB 1. */
893 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
894
895 /* Set divisor to 1 => 115200 Baud */
896 soutp(UART_DLM, 0);
897 soutp(UART_DLL, 1);
898
899 /* Set DLAB 0, 8 Bit */
900 soutp(UART_LCR, UART_LCR_WLEN8);
901 /* enable interrupts */
902 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
903 #else
904 outb(0, io + UART_MCR);
905 outb(0, io + UART_IER);
906 /* init UART */
907 /* set DLAB, speed = 115200 */
908 outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR);
909 outb(1, io + UART_DLL); outb(0, io + UART_DLM);
910 /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */
911 outb(UART_LCR_WLEN7, io + UART_LCR);
912 /* FIFO operation */
913 outb(UART_FCR_ENABLE_FIFO, io + UART_FCR);
914 /* interrupts */
915 /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */
916 outb(UART_IER_RDI, io + UART_IER);
917 /* turn on UART */
918 outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR);
919 #ifdef LIRC_SIR_ACTISYS_ACT200L
920 init_act200();
921 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
922 init_act220();
923 #endif
924 #endif
925 spin_unlock_irqrestore(&hardware_lock, flags);
926 return 0;
927 }
928
929 static void drop_hardware(void)
930 {
931 unsigned long flags;
932
933 spin_lock_irqsave(&hardware_lock, flags);
934
935 #ifdef LIRC_ON_SA1100
936 Ser2UTCR3 = 0;
937
938 Ser2UTCR0 = sr.utcr0;
939 Ser2UTCR1 = sr.utcr1;
940 Ser2UTCR2 = sr.utcr2;
941 Ser2UTCR4 = sr.utcr4;
942 Ser2UTCR3 = sr.utcr3;
943
944 Ser2HSCR0 = sr.hscr0;
945 #ifdef CONFIG_SA1100_BITSY
946 if (machine_is_bitsy())
947 clr_bitsy_egpio(EGPIO_BITSY_IR_ON);
948 #endif
949 #ifdef CONFIG_SA1100_COLLIE
950 sa1100_irda_set_power_collie(0); /* power off */
951 #endif
952 #else
953 /* turn off interrupts */
954 outb(0, io + UART_IER);
955 #endif
956 spin_unlock_irqrestore(&hardware_lock, flags);
957 }
958
959 /* SECTION: Initialisation */
960
961 static int init_port(void)
962 {
963 int retval;
964
965 /* get I/O port access and IRQ line */
966 #ifndef LIRC_ON_SA1100
967 if (request_region(io, 8, LIRC_DRIVER_NAME) == NULL) {
968 pr_err("i/o port 0x%.4x already in use.\n", io);
969 return -EBUSY;
970 }
971 #endif
972 retval = request_irq(irq, sir_interrupt, 0,
973 LIRC_DRIVER_NAME, NULL);
974 if (retval < 0) {
975 # ifndef LIRC_ON_SA1100
976 release_region(io, 8);
977 # endif
978 pr_err("IRQ %d already in use.\n", irq);
979 return retval;
980 }
981 #ifndef LIRC_ON_SA1100
982 pr_info("I/O port 0x%.4x, IRQ %d.\n", io, irq);
983 #endif
984
985 init_timer(&timerlist);
986 timerlist.function = sir_timeout;
987 timerlist.data = 0xabadcafe;
988
989 return 0;
990 }
991
992 static void drop_port(void)
993 {
994 free_irq(irq, NULL);
995 del_timer_sync(&timerlist);
996 #ifndef LIRC_ON_SA1100
997 release_region(io, 8);
998 #endif
999 }
1000
1001 #ifdef LIRC_SIR_ACTISYS_ACT200L
1002 /* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */
1003 /* some code borrowed from Linux IRDA driver */
1004
1005 /* Register 0: Control register #1 */
1006 #define ACT200L_REG0 0x00
1007 #define ACT200L_TXEN 0x01 /* Enable transmitter */
1008 #define ACT200L_RXEN 0x02 /* Enable receiver */
1009 #define ACT200L_ECHO 0x08 /* Echo control chars */
1010
1011 /* Register 1: Control register #2 */
1012 #define ACT200L_REG1 0x10
1013 #define ACT200L_LODB 0x01 /* Load new baud rate count value */
1014 #define ACT200L_WIDE 0x04 /* Expand the maximum allowable pulse */
1015
1016 /* Register 3: Transmit mode register #2 */
1017 #define ACT200L_REG3 0x30
1018 #define ACT200L_B0 0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
1019 #define ACT200L_B1 0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
1020 #define ACT200L_CHSY 0x04 /* StartBit Synced 0=bittime, 1=startbit */
1021
1022 /* Register 4: Output Power register */
1023 #define ACT200L_REG4 0x40
1024 #define ACT200L_OP0 0x01 /* Enable LED1C output */
1025 #define ACT200L_OP1 0x02 /* Enable LED2C output */
1026 #define ACT200L_BLKR 0x04
1027
1028 /* Register 5: Receive Mode register */
1029 #define ACT200L_REG5 0x50
1030 #define ACT200L_RWIDL 0x01 /* fixed 1.6us pulse mode */
1031 /*.. other various IRDA bit modes, and TV remote modes..*/
1032
1033 /* Register 6: Receive Sensitivity register #1 */
1034 #define ACT200L_REG6 0x60
1035 #define ACT200L_RS0 0x01 /* receive threshold bit 0 */
1036 #define ACT200L_RS1 0x02 /* receive threshold bit 1 */
1037
1038 /* Register 7: Receive Sensitivity register #2 */
1039 #define ACT200L_REG7 0x70
1040 #define ACT200L_ENPOS 0x04 /* Ignore the falling edge */
1041
1042 /* Register 8,9: Baud Rate Divider register #1,#2 */
1043 #define ACT200L_REG8 0x80
1044 #define ACT200L_REG9 0x90
1045
1046 #define ACT200L_2400 0x5f
1047 #define ACT200L_9600 0x17
1048 #define ACT200L_19200 0x0b
1049 #define ACT200L_38400 0x05
1050 #define ACT200L_57600 0x03
1051 #define ACT200L_115200 0x01
1052
1053 /* Register 13: Control register #3 */
1054 #define ACT200L_REG13 0xd0
1055 #define ACT200L_SHDW 0x01 /* Enable access to shadow registers */
1056
1057 /* Register 15: Status register */
1058 #define ACT200L_REG15 0xf0
1059
1060 /* Register 21: Control register #4 */
1061 #define ACT200L_REG21 0x50
1062 #define ACT200L_EXCK 0x02 /* Disable clock output driver */
1063 #define ACT200L_OSCL 0x04 /* oscillator in low power, medium accuracy mode */
1064
1065 static void init_act200(void)
1066 {
1067 int i;
1068 __u8 control[] = {
1069 ACT200L_REG15,
1070 ACT200L_REG13 | ACT200L_SHDW,
1071 ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL,
1072 ACT200L_REG13,
1073 ACT200L_REG7 | ACT200L_ENPOS,
1074 ACT200L_REG6 | ACT200L_RS0 | ACT200L_RS1,
1075 ACT200L_REG5 | ACT200L_RWIDL,
1076 ACT200L_REG4 | ACT200L_OP0 | ACT200L_OP1 | ACT200L_BLKR,
1077 ACT200L_REG3 | ACT200L_B0,
1078 ACT200L_REG0 | ACT200L_TXEN | ACT200L_RXEN,
1079 ACT200L_REG8 | (ACT200L_115200 & 0x0f),
1080 ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f),
1081 ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE
1082 };
1083
1084 /* Set DLAB 1. */
1085 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
1086
1087 /* Set divisor to 12 => 9600 Baud */
1088 soutp(UART_DLM, 0);
1089 soutp(UART_DLL, 12);
1090
1091 /* Set DLAB 0. */
1092 soutp(UART_LCR, UART_LCR_WLEN8);
1093 /* Set divisor to 12 => 9600 Baud */
1094
1095 /* power supply */
1096 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1097 for (i = 0; i < 50; i++)
1098 safe_udelay(1000);
1099
1100 /* Reset the dongle : set RTS low for 25 ms */
1101 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
1102 for (i = 0; i < 25; i++)
1103 udelay(1000);
1104
1105 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1106 udelay(100);
1107
1108 /* Clear DTR and set RTS to enter command mode */
1109 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
1110 udelay(7);
1111
1112 /* send out the control register settings for 115K 7N1 SIR operation */
1113 for (i = 0; i < sizeof(control); i++) {
1114 soutp(UART_TX, control[i]);
1115 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
1116 udelay(1500);
1117 }
1118
1119 /* back to normal operation */
1120 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1121 udelay(50);
1122
1123 udelay(1500);
1124 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
1125
1126 /* Set DLAB 1. */
1127 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
1128
1129 /* Set divisor to 1 => 115200 Baud */
1130 soutp(UART_DLM, 0);
1131 soutp(UART_DLL, 1);
1132
1133 /* Set DLAB 0. */
1134 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
1135
1136 /* Set DLAB 0, 7 Bit */
1137 soutp(UART_LCR, UART_LCR_WLEN7);
1138
1139 /* enable interrupts */
1140 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
1141 }
1142 #endif
1143
1144 #ifdef LIRC_SIR_ACTISYS_ACT220L
1145 /*
1146 * Derived from linux IrDA driver (net/irda/actisys.c)
1147 * Drop me a mail for any kind of comment: maxx@spaceboyz.net
1148 */
1149
1150 void init_act220(void)
1151 {
1152 int i;
1153
1154 /* DLAB 1 */
1155 soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7);
1156
1157 /* 9600 baud */
1158 soutp(UART_DLM, 0);
1159 soutp(UART_DLL, 12);
1160
1161 /* DLAB 0 */
1162 soutp(UART_LCR, UART_LCR_WLEN7);
1163
1164 /* reset the dongle, set DTR low for 10us */
1165 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
1166 udelay(10);
1167
1168 /* back to normal (still 9600) */
1169 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2);
1170
1171 /*
1172 * send RTS pulses until we reach 115200
1173 * i hope this is really the same for act220l/act220l+
1174 */
1175 for (i = 0; i < 3; i++) {
1176 udelay(10);
1177 /* set RTS low for 10 us */
1178 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
1179 udelay(10);
1180 /* set RTS high for 10 us */
1181 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1182 }
1183
1184 /* back to normal operation */
1185 udelay(1500); /* better safe than sorry ;) */
1186
1187 /* Set DLAB 1. */
1188 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
1189
1190 /* Set divisor to 1 => 115200 Baud */
1191 soutp(UART_DLM, 0);
1192 soutp(UART_DLL, 1);
1193
1194 /* Set DLAB 0, 7 Bit */
1195 /* The dongle doesn't seem to have any problems with operation at 7N1 */
1196 soutp(UART_LCR, UART_LCR_WLEN7);
1197
1198 /* enable interrupts */
1199 soutp(UART_IER, UART_IER_RDI);
1200 }
1201 #endif
1202
1203 static int init_lirc_sir(void)
1204 {
1205 int retval;
1206
1207 init_waitqueue_head(&lirc_read_queue);
1208 retval = init_port();
1209 if (retval < 0)
1210 return retval;
1211 init_hardware();
1212 pr_info("Installed.\n");
1213 return 0;
1214 }
1215
1216 static int lirc_sir_probe(struct platform_device *dev)
1217 {
1218 return 0;
1219 }
1220
1221 static int lirc_sir_remove(struct platform_device *dev)
1222 {
1223 return 0;
1224 }
1225
1226 static struct platform_driver lirc_sir_driver = {
1227 .probe = lirc_sir_probe,
1228 .remove = lirc_sir_remove,
1229 .driver = {
1230 .name = "lirc_sir",
1231 .owner = THIS_MODULE,
1232 },
1233 };
1234
1235 static int __init lirc_sir_init(void)
1236 {
1237 int retval;
1238
1239 retval = platform_driver_register(&lirc_sir_driver);
1240 if (retval) {
1241 pr_err("Platform driver register failed!\n");
1242 return -ENODEV;
1243 }
1244
1245 lirc_sir_dev = platform_device_alloc("lirc_dev", 0);
1246 if (!lirc_sir_dev) {
1247 pr_err("Platform device alloc failed!\n");
1248 retval = -ENOMEM;
1249 goto pdev_alloc_fail;
1250 }
1251
1252 retval = platform_device_add(lirc_sir_dev);
1253 if (retval) {
1254 pr_err("Platform device add failed!\n");
1255 retval = -ENODEV;
1256 goto pdev_add_fail;
1257 }
1258
1259 retval = init_chrdev();
1260 if (retval < 0)
1261 goto fail;
1262
1263 retval = init_lirc_sir();
1264 if (retval) {
1265 drop_chrdev();
1266 goto fail;
1267 }
1268
1269 return 0;
1270
1271 fail:
1272 platform_device_del(lirc_sir_dev);
1273 pdev_add_fail:
1274 platform_device_put(lirc_sir_dev);
1275 pdev_alloc_fail:
1276 platform_driver_unregister(&lirc_sir_driver);
1277 return retval;
1278 }
1279
1280 static void __exit lirc_sir_exit(void)
1281 {
1282 drop_hardware();
1283 drop_chrdev();
1284 drop_port();
1285 platform_device_unregister(lirc_sir_dev);
1286 platform_driver_unregister(&lirc_sir_driver);
1287 pr_info("Uninstalled.\n");
1288 }
1289
1290 module_init(lirc_sir_init);
1291 module_exit(lirc_sir_exit);
1292
1293 #ifdef LIRC_SIR_TEKRAM
1294 MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210");
1295 MODULE_AUTHOR("Christoph Bartelmus");
1296 #elif defined(LIRC_ON_SA1100)
1297 MODULE_DESCRIPTION("LIRC driver for StrongARM SA1100 embedded microprocessor");
1298 MODULE_AUTHOR("Christoph Bartelmus");
1299 #elif defined(LIRC_SIR_ACTISYS_ACT200L)
1300 MODULE_DESCRIPTION("LIRC driver for Actisys Act200L");
1301 MODULE_AUTHOR("Karl Bongers");
1302 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
1303 MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)");
1304 MODULE_AUTHOR("Jan Roemisch");
1305 #else
1306 MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports");
1307 MODULE_AUTHOR("Milan Pikula");
1308 #endif
1309 MODULE_LICENSE("GPL");
1310
1311 #ifdef LIRC_ON_SA1100
1312 module_param(irq, int, S_IRUGO);
1313 MODULE_PARM_DESC(irq, "Interrupt (16)");
1314 #else
1315 module_param(io, int, S_IRUGO);
1316 MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)");
1317
1318 module_param(irq, int, S_IRUGO);
1319 MODULE_PARM_DESC(irq, "Interrupt (4 or 3)");
1320
1321 module_param(threshold, int, S_IRUGO);
1322 MODULE_PARM_DESC(threshold, "space detection threshold (3)");
1323 #endif
1324
1325 module_param(debug, bool, S_IRUGO | S_IWUSR);
1326 MODULE_PARM_DESC(debug, "Enable debugging messages");
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