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efi/arm: Fix boot crash with CONFIG_CPUMASK_OFFSTACK=y
[mirror_ubuntu-artful-kernel.git] / drivers / staging / media / lirc / lirc_sir.c
1 /*
2 * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk>
3 *
4 * sir_ir - Device driver for use with SIR (serial infra red)
5 * mode of IrDA on many notebooks.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 *
22 * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> :
23 * added timeout and relaxed pulse detection, removed gap bug
24 *
25 * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> :
26 * added support for Tekram Irmate 210 (sending does not work yet,
27 * kind of disappointing that nobody was able to implement that
28 * before),
29 * major clean-up
30 *
31 * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> :
32 * added support for StrongARM SA1100 embedded microprocessor
33 * parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King
34 */
35
36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37
38 #include <linux/module.h>
39 #include <linux/sched.h>
40 #include <linux/errno.h>
41 #include <linux/signal.h>
42 #include <linux/fs.h>
43 #include <linux/interrupt.h>
44 #include <linux/ioport.h>
45 #include <linux/kernel.h>
46 #include <linux/serial_reg.h>
47 #include <linux/ktime.h>
48 #include <linux/string.h>
49 #include <linux/types.h>
50 #include <linux/wait.h>
51 #include <linux/mm.h>
52 #include <linux/delay.h>
53 #include <linux/poll.h>
54 #include <linux/io.h>
55 #include <asm/irq.h>
56 #include <linux/fcntl.h>
57 #include <linux/platform_device.h>
58
59 #include <linux/timer.h>
60
61 #include <media/rc-core.h>
62
63 /* SECTION: Definitions */
64
65 /*** Tekram dongle ***/
66 #ifdef LIRC_SIR_TEKRAM
67 /* stolen from kernel source */
68 /* definitions for Tekram dongle */
69 #define TEKRAM_115200 0x00
70 #define TEKRAM_57600 0x01
71 #define TEKRAM_38400 0x02
72 #define TEKRAM_19200 0x03
73 #define TEKRAM_9600 0x04
74 #define TEKRAM_2400 0x08
75
76 #define TEKRAM_PW 0x10 /* Pulse select bit */
77
78 /* 10bit * 1s/115200bit in milliseconds = 87ms*/
79 #define TIME_CONST (10000000ul/115200ul)
80
81 #endif
82
83 #ifdef LIRC_SIR_ACTISYS_ACT200L
84 static void init_act200(void);
85 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
86 static void init_act220(void);
87 #endif
88
89 #define PULSE '['
90
91 #ifndef LIRC_SIR_TEKRAM
92 /* 9bit * 1s/115200bit in milli seconds = 78.125ms*/
93 #define TIME_CONST (9000000ul/115200ul)
94 #endif
95
96
97 /* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */
98 #define SIR_TIMEOUT (HZ*5/100)
99
100 #ifndef LIRC_ON_SA1100
101 #ifndef LIRC_IRQ
102 #define LIRC_IRQ 4
103 #endif
104 #ifndef LIRC_PORT
105 /* for external dongles, default to com1 */
106 #if defined(LIRC_SIR_ACTISYS_ACT200L) || \
107 defined(LIRC_SIR_ACTISYS_ACT220L) || \
108 defined(LIRC_SIR_TEKRAM)
109 #define LIRC_PORT 0x3f8
110 #else
111 /* onboard sir ports are typically com3 */
112 #define LIRC_PORT 0x3e8
113 #endif
114 #endif
115
116 static int io = LIRC_PORT;
117 static int irq = LIRC_IRQ;
118 static int threshold = 3;
119 #endif
120
121 static DEFINE_SPINLOCK(timer_lock);
122 static struct timer_list timerlist;
123 /* time of last signal change detected */
124 static ktime_t last;
125 /* time of last UART data ready interrupt */
126 static ktime_t last_intr_time;
127 static int last_value;
128 static struct rc_dev *rcdev;
129
130 static struct platform_device *sir_ir_dev;
131
132 static DEFINE_SPINLOCK(hardware_lock);
133
134 static bool debug;
135
136 /* SECTION: Prototypes */
137
138 /* Communication with user-space */
139 static void add_read_queue(int flag, unsigned long val);
140 static int init_chrdev(void);
141 /* Hardware */
142 static irqreturn_t sir_interrupt(int irq, void *dev_id);
143 static void send_space(unsigned long len);
144 static void send_pulse(unsigned long len);
145 static int init_hardware(void);
146 static void drop_hardware(void);
147 /* Initialisation */
148 static int init_port(void);
149 static void drop_port(void);
150
151 static inline unsigned int sinp(int offset)
152 {
153 return inb(io + offset);
154 }
155
156 static inline void soutp(int offset, int value)
157 {
158 outb(value, io + offset);
159 }
160
161 #ifndef MAX_UDELAY_MS
162 #define MAX_UDELAY_US 5000
163 #else
164 #define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
165 #endif
166
167 static void safe_udelay(unsigned long usecs)
168 {
169 while (usecs > MAX_UDELAY_US) {
170 udelay(MAX_UDELAY_US);
171 usecs -= MAX_UDELAY_US;
172 }
173 udelay(usecs);
174 }
175
176 /* SECTION: Communication with user-space */
177 static int sir_tx_ir(struct rc_dev *dev, unsigned int *tx_buf,
178 unsigned int count)
179 {
180 unsigned long flags;
181 int i;
182
183 local_irq_save(flags);
184 for (i = 0; i < count;) {
185 if (tx_buf[i])
186 send_pulse(tx_buf[i]);
187 i++;
188 if (i >= count)
189 break;
190 if (tx_buf[i])
191 send_space(tx_buf[i]);
192 i++;
193 }
194 local_irq_restore(flags);
195
196 return count;
197 }
198
199 static void add_read_queue(int flag, unsigned long val)
200 {
201 DEFINE_IR_RAW_EVENT(ev);
202
203 pr_debug("add flag %d with val %lu\n", flag, val);
204
205 /*
206 * statistically, pulses are ~TIME_CONST/2 too long. we could
207 * maybe make this more exact, but this is good enough
208 */
209 if (flag) {
210 /* pulse */
211 if (val > TIME_CONST / 2)
212 val -= TIME_CONST / 2;
213 else /* should not ever happen */
214 val = 1;
215 ev.pulse = true;
216 } else {
217 val += TIME_CONST / 2;
218 }
219 ev.duration = US_TO_NS(val);
220
221 ir_raw_event_store_with_filter(rcdev, &ev);
222 }
223
224 static int init_chrdev(void)
225 {
226 rcdev = devm_rc_allocate_device(&sir_ir_dev->dev, RC_DRIVER_IR_RAW);
227 if (!rcdev)
228 return -ENOMEM;
229
230 rcdev->input_phys = KBUILD_MODNAME "/input0";
231 rcdev->input_id.bustype = BUS_HOST;
232 rcdev->input_id.vendor = 0x0001;
233 rcdev->input_id.product = 0x0001;
234 rcdev->input_id.version = 0x0100;
235 rcdev->tx_ir = sir_tx_ir;
236 rcdev->allowed_protocols = RC_BIT_ALL_IR_DECODER;
237 rcdev->map_name = RC_MAP_RC6_MCE;
238 rcdev->timeout = IR_DEFAULT_TIMEOUT;
239 rcdev->dev.parent = &sir_ir_dev->dev;
240
241 return devm_rc_register_device(&sir_ir_dev->dev, rcdev);
242 }
243
244 /* SECTION: Hardware */
245 static void sir_timeout(unsigned long data)
246 {
247 /*
248 * if last received signal was a pulse, but receiving stopped
249 * within the 9 bit frame, we need to finish this pulse and
250 * simulate a signal change to from pulse to space. Otherwise
251 * upper layers will receive two sequences next time.
252 */
253
254 unsigned long flags;
255 unsigned long pulse_end;
256
257 /* avoid interference with interrupt */
258 spin_lock_irqsave(&timer_lock, flags);
259 if (last_value) {
260 /* clear unread bits in UART and restart */
261 outb(UART_FCR_CLEAR_RCVR, io + UART_FCR);
262 /* determine 'virtual' pulse end: */
263 pulse_end = min_t(unsigned long,
264 ktime_us_delta(last, last_intr_time),
265 IR_MAX_DURATION);
266 dev_dbg(&sir_ir_dev->dev, "timeout add %d for %lu usec\n",
267 last_value, pulse_end);
268 add_read_queue(last_value, pulse_end);
269 last_value = 0;
270 last = last_intr_time;
271 }
272 spin_unlock_irqrestore(&timer_lock, flags);
273 ir_raw_event_handle(rcdev);
274 }
275
276 static irqreturn_t sir_interrupt(int irq, void *dev_id)
277 {
278 unsigned char data;
279 ktime_t curr_time;
280 static unsigned long delt;
281 unsigned long deltintr;
282 unsigned long flags;
283 int iir, lsr;
284
285 while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) {
286 switch (iir&UART_IIR_ID) { /* FIXME toto treba preriedit */
287 case UART_IIR_MSI:
288 (void) inb(io + UART_MSR);
289 break;
290 case UART_IIR_RLSI:
291 (void) inb(io + UART_LSR);
292 break;
293 case UART_IIR_THRI:
294 #if 0
295 if (lsr & UART_LSR_THRE) /* FIFO is empty */
296 outb(data, io + UART_TX)
297 #endif
298 break;
299 case UART_IIR_RDI:
300 /* avoid interference with timer */
301 spin_lock_irqsave(&timer_lock, flags);
302 do {
303 del_timer(&timerlist);
304 data = inb(io + UART_RX);
305 curr_time = ktime_get();
306 delt = min_t(unsigned long,
307 ktime_us_delta(last, curr_time),
308 IR_MAX_DURATION);
309 deltintr = min_t(unsigned long,
310 ktime_us_delta(last_intr_time,
311 curr_time),
312 IR_MAX_DURATION);
313 dev_dbg(&sir_ir_dev->dev, "t %lu, d %d\n",
314 deltintr, (int)data);
315 /*
316 * if nothing came in last X cycles,
317 * it was gap
318 */
319 if (deltintr > TIME_CONST * threshold) {
320 if (last_value) {
321 dev_dbg(&sir_ir_dev->dev, "GAP\n");
322 /* simulate signal change */
323 add_read_queue(last_value,
324 delt -
325 deltintr);
326 last_value = 0;
327 last = last_intr_time;
328 delt = deltintr;
329 }
330 }
331 data = 1;
332 if (data ^ last_value) {
333 /*
334 * deltintr > 2*TIME_CONST, remember?
335 * the other case is timeout
336 */
337 add_read_queue(last_value,
338 delt-TIME_CONST);
339 last_value = data;
340 last = curr_time;
341 last = ktime_sub_us(last,
342 TIME_CONST);
343 }
344 last_intr_time = curr_time;
345 if (data) {
346 /*
347 * start timer for end of
348 * sequence detection
349 */
350 timerlist.expires = jiffies +
351 SIR_TIMEOUT;
352 add_timer(&timerlist);
353 }
354
355 lsr = inb(io + UART_LSR);
356 } while (lsr & UART_LSR_DR); /* data ready */
357 spin_unlock_irqrestore(&timer_lock, flags);
358 break;
359 default:
360 break;
361 }
362 }
363 ir_raw_event_handle(rcdev);
364 return IRQ_RETVAL(IRQ_HANDLED);
365 }
366
367 static void send_space(unsigned long len)
368 {
369 safe_udelay(len);
370 }
371
372 static void send_pulse(unsigned long len)
373 {
374 long bytes_out = len / TIME_CONST;
375
376 if (bytes_out == 0)
377 bytes_out++;
378
379 while (bytes_out--) {
380 outb(PULSE, io + UART_TX);
381 /* FIXME treba seriozne cakanie z char/serial.c */
382 while (!(inb(io + UART_LSR) & UART_LSR_THRE))
383 ;
384 }
385 }
386
387 static int init_hardware(void)
388 {
389 unsigned long flags;
390
391 spin_lock_irqsave(&hardware_lock, flags);
392 /* reset UART */
393 #if defined(LIRC_SIR_TEKRAM)
394 /* disable FIFO */
395 soutp(UART_FCR,
396 UART_FCR_CLEAR_RCVR|
397 UART_FCR_CLEAR_XMIT|
398 UART_FCR_TRIGGER_1);
399
400 /* Set DLAB 0. */
401 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
402
403 /* First of all, disable all interrupts */
404 soutp(UART_IER, sinp(UART_IER) &
405 (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI)));
406
407 /* Set DLAB 1. */
408 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
409
410 /* Set divisor to 12 => 9600 Baud */
411 soutp(UART_DLM, 0);
412 soutp(UART_DLL, 12);
413
414 /* Set DLAB 0. */
415 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
416
417 /* power supply */
418 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
419 safe_udelay(50*1000);
420
421 /* -DTR low -> reset PIC */
422 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
423 udelay(1*1000);
424
425 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
426 udelay(100);
427
428
429 /* -RTS low -> send control byte */
430 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
431 udelay(7);
432 soutp(UART_TX, TEKRAM_115200|TEKRAM_PW);
433
434 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
435 udelay(1500);
436
437 /* back to normal operation */
438 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
439 udelay(50);
440
441 udelay(1500);
442
443 /* read previous control byte */
444 pr_info("0x%02x\n", sinp(UART_RX));
445
446 /* Set DLAB 1. */
447 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
448
449 /* Set divisor to 1 => 115200 Baud */
450 soutp(UART_DLM, 0);
451 soutp(UART_DLL, 1);
452
453 /* Set DLAB 0, 8 Bit */
454 soutp(UART_LCR, UART_LCR_WLEN8);
455 /* enable interrupts */
456 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
457 #else
458 outb(0, io + UART_MCR);
459 outb(0, io + UART_IER);
460 /* init UART */
461 /* set DLAB, speed = 115200 */
462 outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR);
463 outb(1, io + UART_DLL); outb(0, io + UART_DLM);
464 /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */
465 outb(UART_LCR_WLEN7, io + UART_LCR);
466 /* FIFO operation */
467 outb(UART_FCR_ENABLE_FIFO, io + UART_FCR);
468 /* interrupts */
469 /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */
470 outb(UART_IER_RDI, io + UART_IER);
471 /* turn on UART */
472 outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR);
473 #ifdef LIRC_SIR_ACTISYS_ACT200L
474 init_act200();
475 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
476 init_act220();
477 #endif
478 #endif
479 spin_unlock_irqrestore(&hardware_lock, flags);
480 return 0;
481 }
482
483 static void drop_hardware(void)
484 {
485 unsigned long flags;
486
487 spin_lock_irqsave(&hardware_lock, flags);
488
489 /* turn off interrupts */
490 outb(0, io + UART_IER);
491
492 spin_unlock_irqrestore(&hardware_lock, flags);
493 }
494
495 /* SECTION: Initialisation */
496
497 static int init_port(void)
498 {
499 int retval;
500
501 /* get I/O port access and IRQ line */
502 if (!request_region(io, 8, KBUILD_MODNAME)) {
503 pr_err("i/o port 0x%.4x already in use.\n", io);
504 return -EBUSY;
505 }
506 retval = request_irq(irq, sir_interrupt, 0,
507 KBUILD_MODNAME, NULL);
508 if (retval < 0) {
509 release_region(io, 8);
510 pr_err("IRQ %d already in use.\n", irq);
511 return retval;
512 }
513 pr_info("I/O port 0x%.4x, IRQ %d.\n", io, irq);
514
515 setup_timer(&timerlist, sir_timeout, 0);
516
517 return 0;
518 }
519
520 static void drop_port(void)
521 {
522 free_irq(irq, NULL);
523 del_timer_sync(&timerlist);
524 release_region(io, 8);
525 }
526
527 #ifdef LIRC_SIR_ACTISYS_ACT200L
528 /* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */
529 /* some code borrowed from Linux IRDA driver */
530
531 /* Register 0: Control register #1 */
532 #define ACT200L_REG0 0x00
533 #define ACT200L_TXEN 0x01 /* Enable transmitter */
534 #define ACT200L_RXEN 0x02 /* Enable receiver */
535 #define ACT200L_ECHO 0x08 /* Echo control chars */
536
537 /* Register 1: Control register #2 */
538 #define ACT200L_REG1 0x10
539 #define ACT200L_LODB 0x01 /* Load new baud rate count value */
540 #define ACT200L_WIDE 0x04 /* Expand the maximum allowable pulse */
541
542 /* Register 3: Transmit mode register #2 */
543 #define ACT200L_REG3 0x30
544 #define ACT200L_B0 0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
545 #define ACT200L_B1 0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
546 #define ACT200L_CHSY 0x04 /* StartBit Synced 0=bittime, 1=startbit */
547
548 /* Register 4: Output Power register */
549 #define ACT200L_REG4 0x40
550 #define ACT200L_OP0 0x01 /* Enable LED1C output */
551 #define ACT200L_OP1 0x02 /* Enable LED2C output */
552 #define ACT200L_BLKR 0x04
553
554 /* Register 5: Receive Mode register */
555 #define ACT200L_REG5 0x50
556 #define ACT200L_RWIDL 0x01 /* fixed 1.6us pulse mode */
557 /*.. other various IRDA bit modes, and TV remote modes..*/
558
559 /* Register 6: Receive Sensitivity register #1 */
560 #define ACT200L_REG6 0x60
561 #define ACT200L_RS0 0x01 /* receive threshold bit 0 */
562 #define ACT200L_RS1 0x02 /* receive threshold bit 1 */
563
564 /* Register 7: Receive Sensitivity register #2 */
565 #define ACT200L_REG7 0x70
566 #define ACT200L_ENPOS 0x04 /* Ignore the falling edge */
567
568 /* Register 8,9: Baud Rate Divider register #1,#2 */
569 #define ACT200L_REG8 0x80
570 #define ACT200L_REG9 0x90
571
572 #define ACT200L_2400 0x5f
573 #define ACT200L_9600 0x17
574 #define ACT200L_19200 0x0b
575 #define ACT200L_38400 0x05
576 #define ACT200L_57600 0x03
577 #define ACT200L_115200 0x01
578
579 /* Register 13: Control register #3 */
580 #define ACT200L_REG13 0xd0
581 #define ACT200L_SHDW 0x01 /* Enable access to shadow registers */
582
583 /* Register 15: Status register */
584 #define ACT200L_REG15 0xf0
585
586 /* Register 21: Control register #4 */
587 #define ACT200L_REG21 0x50
588 #define ACT200L_EXCK 0x02 /* Disable clock output driver */
589 #define ACT200L_OSCL 0x04 /* oscillator in low power, medium accuracy mode */
590
591 static void init_act200(void)
592 {
593 int i;
594 __u8 control[] = {
595 ACT200L_REG15,
596 ACT200L_REG13 | ACT200L_SHDW,
597 ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL,
598 ACT200L_REG13,
599 ACT200L_REG7 | ACT200L_ENPOS,
600 ACT200L_REG6 | ACT200L_RS0 | ACT200L_RS1,
601 ACT200L_REG5 | ACT200L_RWIDL,
602 ACT200L_REG4 | ACT200L_OP0 | ACT200L_OP1 | ACT200L_BLKR,
603 ACT200L_REG3 | ACT200L_B0,
604 ACT200L_REG0 | ACT200L_TXEN | ACT200L_RXEN,
605 ACT200L_REG8 | (ACT200L_115200 & 0x0f),
606 ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f),
607 ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE
608 };
609
610 /* Set DLAB 1. */
611 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
612
613 /* Set divisor to 12 => 9600 Baud */
614 soutp(UART_DLM, 0);
615 soutp(UART_DLL, 12);
616
617 /* Set DLAB 0. */
618 soutp(UART_LCR, UART_LCR_WLEN8);
619 /* Set divisor to 12 => 9600 Baud */
620
621 /* power supply */
622 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
623 for (i = 0; i < 50; i++)
624 safe_udelay(1000);
625
626 /* Reset the dongle : set RTS low for 25 ms */
627 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
628 for (i = 0; i < 25; i++)
629 udelay(1000);
630
631 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
632 udelay(100);
633
634 /* Clear DTR and set RTS to enter command mode */
635 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
636 udelay(7);
637
638 /* send out the control register settings for 115K 7N1 SIR operation */
639 for (i = 0; i < sizeof(control); i++) {
640 soutp(UART_TX, control[i]);
641 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
642 udelay(1500);
643 }
644
645 /* back to normal operation */
646 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
647 udelay(50);
648
649 udelay(1500);
650 soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
651
652 /* Set DLAB 1. */
653 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
654
655 /* Set divisor to 1 => 115200 Baud */
656 soutp(UART_DLM, 0);
657 soutp(UART_DLL, 1);
658
659 /* Set DLAB 0. */
660 soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
661
662 /* Set DLAB 0, 7 Bit */
663 soutp(UART_LCR, UART_LCR_WLEN7);
664
665 /* enable interrupts */
666 soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
667 }
668 #endif
669
670 #ifdef LIRC_SIR_ACTISYS_ACT220L
671 /*
672 * Derived from linux IrDA driver (net/irda/actisys.c)
673 * Drop me a mail for any kind of comment: maxx@spaceboyz.net
674 */
675
676 void init_act220(void)
677 {
678 int i;
679
680 /* DLAB 1 */
681 soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7);
682
683 /* 9600 baud */
684 soutp(UART_DLM, 0);
685 soutp(UART_DLL, 12);
686
687 /* DLAB 0 */
688 soutp(UART_LCR, UART_LCR_WLEN7);
689
690 /* reset the dongle, set DTR low for 10us */
691 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
692 udelay(10);
693
694 /* back to normal (still 9600) */
695 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2);
696
697 /*
698 * send RTS pulses until we reach 115200
699 * i hope this is really the same for act220l/act220l+
700 */
701 for (i = 0; i < 3; i++) {
702 udelay(10);
703 /* set RTS low for 10 us */
704 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
705 udelay(10);
706 /* set RTS high for 10 us */
707 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
708 }
709
710 /* back to normal operation */
711 udelay(1500); /* better safe than sorry ;) */
712
713 /* Set DLAB 1. */
714 soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
715
716 /* Set divisor to 1 => 115200 Baud */
717 soutp(UART_DLM, 0);
718 soutp(UART_DLL, 1);
719
720 /* Set DLAB 0, 7 Bit */
721 /* The dongle doesn't seem to have any problems with operation at 7N1 */
722 soutp(UART_LCR, UART_LCR_WLEN7);
723
724 /* enable interrupts */
725 soutp(UART_IER, UART_IER_RDI);
726 }
727 #endif
728
729 static int init_sir_ir(void)
730 {
731 int retval;
732
733 retval = init_port();
734 if (retval < 0)
735 return retval;
736 init_hardware();
737 pr_info("Installed.\n");
738 return 0;
739 }
740
741 static int sir_ir_probe(struct platform_device *dev)
742 {
743 return 0;
744 }
745
746 static int sir_ir_remove(struct platform_device *dev)
747 {
748 return 0;
749 }
750
751 static struct platform_driver sir_ir_driver = {
752 .probe = sir_ir_probe,
753 .remove = sir_ir_remove,
754 .driver = {
755 .name = "sir_ir",
756 },
757 };
758
759 static int __init sir_ir_init(void)
760 {
761 int retval;
762
763 retval = platform_driver_register(&sir_ir_driver);
764 if (retval) {
765 pr_err("Platform driver register failed!\n");
766 return -ENODEV;
767 }
768
769 sir_ir_dev = platform_device_alloc("sir_ir", 0);
770 if (!sir_ir_dev) {
771 pr_err("Platform device alloc failed!\n");
772 retval = -ENOMEM;
773 goto pdev_alloc_fail;
774 }
775
776 retval = platform_device_add(sir_ir_dev);
777 if (retval) {
778 pr_err("Platform device add failed!\n");
779 retval = -ENODEV;
780 goto pdev_add_fail;
781 }
782
783 retval = init_chrdev();
784 if (retval < 0)
785 goto fail;
786
787 retval = init_sir_ir();
788 if (retval)
789 goto fail;
790
791 return 0;
792
793 fail:
794 platform_device_del(sir_ir_dev);
795 pdev_add_fail:
796 platform_device_put(sir_ir_dev);
797 pdev_alloc_fail:
798 platform_driver_unregister(&sir_ir_driver);
799 return retval;
800 }
801
802 static void __exit sir_ir_exit(void)
803 {
804 drop_hardware();
805 drop_port();
806 platform_device_unregister(sir_ir_dev);
807 platform_driver_unregister(&sir_ir_driver);
808 pr_info("Uninstalled.\n");
809 }
810
811 module_init(sir_ir_init);
812 module_exit(sir_ir_exit);
813
814 #ifdef LIRC_SIR_TEKRAM
815 MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210");
816 MODULE_AUTHOR("Christoph Bartelmus");
817 #elif defined(LIRC_SIR_ACTISYS_ACT200L)
818 MODULE_DESCRIPTION("LIRC driver for Actisys Act200L");
819 MODULE_AUTHOR("Karl Bongers");
820 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
821 MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)");
822 MODULE_AUTHOR("Jan Roemisch");
823 #else
824 MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports");
825 MODULE_AUTHOR("Milan Pikula");
826 #endif
827 MODULE_LICENSE("GPL");
828
829 module_param(io, int, S_IRUGO);
830 MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)");
831
832 module_param(irq, int, S_IRUGO);
833 MODULE_PARM_DESC(irq, "Interrupt (4 or 3)");
834
835 module_param(threshold, int, S_IRUGO);
836 MODULE_PARM_DESC(threshold, "space detection threshold (3)");
837
838 module_param(debug, bool, S_IRUGO | S_IWUSR);
839 MODULE_PARM_DESC(debug, "Enable debugging messages");
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