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39
40
41 /**
42 * @file
43 *
44 * "cvmx-usb.c" defines a set of low level USB functions to help
45 * developers create Octeon USB drivers for various operating
46 * systems. These functions provide a generic API to the Octeon
47 * USB blocks, hiding the internal hardware specific
48 * operations.
49 */
50 #include <linux/delay.h>
51 #include <asm/octeon/cvmx.h>
52 #include <asm/octeon/octeon.h>
53 #include <asm/octeon/cvmx-sysinfo.h>
54 #include "cvmx-usbnx-defs.h"
55 #include "cvmx-usbcx-defs.h"
56 #include "cvmx-usb.h"
57 #include <asm/octeon/cvmx-helper.h>
58 #include <asm/octeon/cvmx-helper-board.h>
59
60 #define CVMX_PREFETCH0(address) CVMX_PREFETCH(address, 0)
61 #define CVMX_PREFETCH128(address) CVMX_PREFETCH(address, 128)
62 // a normal prefetch
63 #define CVMX_PREFETCH(address, offset) CVMX_PREFETCH_PREF0(address, offset)
64 // normal prefetches that use the pref instruction
65 #define CVMX_PREFETCH_PREFX(X, address, offset) asm volatile ("pref %[type], %[off](%[rbase])" : : [rbase] "d" (address), [off] "I" (offset), [type] "n" (X))
66 #define CVMX_PREFETCH_PREF0(address, offset) CVMX_PREFETCH_PREFX(0, address, offset)
67 #define CVMX_CLZ(result, input) asm ("clz %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
68
69 #define MAX_RETRIES 3 /* Maximum number of times to retry failed transactions */
70 #define MAX_PIPES 32 /* Maximum number of pipes that can be open at once */
71 #define MAX_TRANSACTIONS 256 /* Maximum number of outstanding transactions across all pipes */
72 #define MAX_CHANNELS 8 /* Maximum number of hardware channels supported by the USB block */
73 #define MAX_USB_ADDRESS 127 /* The highest valid USB device address */
74 #define MAX_USB_ENDPOINT 15 /* The highest valid USB endpoint number */
75 #define MAX_USB_HUB_PORT 15 /* The highest valid port number on a hub */
76 #define MAX_TRANSFER_BYTES ((1<<19)-1) /* The low level hardware can transfer a maximum of this number of bytes in each transfer. The field is 19 bits wide */
77 #define MAX_TRANSFER_PACKETS ((1<<10)-1) /* The low level hardware can transfer a maximum of this number of packets in each transfer. The field is 10 bits wide */
78
79 /*
80 * These defines disable the normal read and write csr. This is so I can add
81 * extra debug stuff to the usb specific version and I won't use the normal
82 * version by mistake
83 */
84 #define cvmx_read_csr use_cvmx_usb_read_csr64_instead_of_cvmx_read_csr
85 #define cvmx_write_csr use_cvmx_usb_write_csr64_instead_of_cvmx_write_csr
86
87 enum cvmx_usb_transaction_flags {
88 __CVMX_USB_TRANSACTION_FLAGS_IN_USE = 1<<16,
89 };
90
91 enum {
92 USB_CLOCK_TYPE_REF_12,
93 USB_CLOCK_TYPE_REF_24,
94 USB_CLOCK_TYPE_REF_48,
95 USB_CLOCK_TYPE_CRYSTAL_12,
96 };
97
98 /**
99 * Logical transactions may take numerous low level
100 * transactions, especially when splits are concerned. This
101 * enum represents all of the possible stages a transaction can
102 * be in. Note that split completes are always even. This is so
103 * the NAK handler can backup to the previous low level
104 * transaction with a simple clearing of bit 0.
105 */
106 enum cvmx_usb_stage {
107 CVMX_USB_STAGE_NON_CONTROL,
108 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE,
109 CVMX_USB_STAGE_SETUP,
110 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE,
111 CVMX_USB_STAGE_DATA,
112 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE,
113 CVMX_USB_STAGE_STATUS,
114 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE,
115 };
116
117 /**
118 * struct cvmx_usb_transaction - describes each pending USB transaction
119 * regardless of type. These are linked together
120 * to form a list of pending requests for a pipe.
121 *
122 * @prev: Transaction before this one in the pipe.
123 * @next: Transaction after this one in the pipe.
124 * @type: Type of transaction, duplicated of the pipe.
125 * @flags: State flags for this transaction.
126 * @buffer: User's physical buffer address to read/write.
127 * @buffer_length: Size of the user's buffer in bytes.
128 * @control_header: For control transactions, physical address of the 8
129 * byte standard header.
130 * @iso_start_frame: For ISO transactions, the starting frame number.
131 * @iso_number_packets: For ISO transactions, the number of packets in the
132 * request.
133 * @iso_packets: For ISO transactions, the sub packets in the request.
134 * @actual_bytes: Actual bytes transfer for this transaction.
135 * @stage: For control transactions, the current stage.
136 * @callback: User's callback function when complete.
137 * @callback_data: User's data.
138 */
139 struct cvmx_usb_transaction {
140 struct cvmx_usb_transaction *prev;
141 struct cvmx_usb_transaction *next;
142 enum cvmx_usb_transfer type;
143 enum cvmx_usb_transaction_flags flags;
144 uint64_t buffer;
145 int buffer_length;
146 uint64_t control_header;
147 int iso_start_frame;
148 int iso_number_packets;
149 struct cvmx_usb_iso_packet *iso_packets;
150 int xfersize;
151 int pktcnt;
152 int retries;
153 int actual_bytes;
154 enum cvmx_usb_stage stage;
155 cvmx_usb_callback_func_t callback;
156 void *callback_data;
157 };
158
159 /**
160 * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon
161 * and some USB device. It contains a list of pending
162 * request to the device.
163 *
164 * @prev: Pipe before this one in the list
165 * @next: Pipe after this one in the list
166 * @head: The first pending transaction
167 * @tail: The last pending transaction
168 * @interval: For periodic pipes, the interval between packets in
169 * frames
170 * @next_tx_frame: The next frame this pipe is allowed to transmit on
171 * @flags: State flags for this pipe
172 * @device_speed: Speed of device connected to this pipe
173 * @transfer_type: Type of transaction supported by this pipe
174 * @transfer_dir: IN or OUT. Ignored for Control
175 * @multi_count: Max packet in a row for the device
176 * @max_packet: The device's maximum packet size in bytes
177 * @device_addr: USB device address at other end of pipe
178 * @endpoint_num: USB endpoint number at other end of pipe
179 * @hub_device_addr: Hub address this device is connected to
180 * @hub_port: Hub port this device is connected to
181 * @pid_toggle: This toggles between 0/1 on every packet send to track
182 * the data pid needed
183 * @channel: Hardware DMA channel for this pipe
184 * @split_sc_frame: The low order bits of the frame number the split
185 * complete should be sent on
186 */
187 struct cvmx_usb_pipe {
188 struct cvmx_usb_pipe *prev;
189 struct cvmx_usb_pipe *next;
190 struct cvmx_usb_transaction *head;
191 struct cvmx_usb_transaction *tail;
192 uint64_t interval;
193 uint64_t next_tx_frame;
194 enum cvmx_usb_pipe_flags flags;
195 enum cvmx_usb_speed device_speed;
196 enum cvmx_usb_transfer transfer_type;
197 enum cvmx_usb_direction transfer_dir;
198 int multi_count;
199 uint16_t max_packet;
200 uint8_t device_addr;
201 uint8_t endpoint_num;
202 uint8_t hub_device_addr;
203 uint8_t hub_port;
204 uint8_t pid_toggle;
205 uint8_t channel;
206 int8_t split_sc_frame;
207 };
208
209 /**
210 * struct cvmx_usb_pipe_list
211 *
212 * @head: Head of the list, or NULL if empty.
213 * @tail: Tail if the list, or NULL if empty.
214 */
215 struct cvmx_usb_pipe_list {
216 struct cvmx_usb_pipe *head;
217 struct cvmx_usb_pipe *tail;
218 };
219
220 struct cvmx_usb_tx_fifo {
221 struct {
222 int channel;
223 int size;
224 uint64_t address;
225 } entry[MAX_CHANNELS+1];
226 int head;
227 int tail;
228 };
229
230 /**
231 * struct cvmx_usb_internal_state - the state of the USB block
232 *
233 * init_flags: Flags passed to initialize.
234 * index: Which USB block this is for.
235 * idle_hardware_channels: Bit set for every idle hardware channel.
236 * usbcx_hprt: Stored port status so we don't need to read a CSR to
237 * determine splits.
238 * pipe_for_channel: Map channels to pipes.
239 * free_transaction_head: List of free transactions head.
240 * free_transaction_tail: List of free transactions tail.
241 * pipe: Storage for pipes.
242 * transaction: Storage for transactions.
243 * callback: User global callbacks.
244 * callback_data: User data for each callback.
245 * indent: Used by debug output to indent functions.
246 * port_status: Last port status used for change notification.
247 * free_pipes: List of all pipes that are currently closed.
248 * idle_pipes: List of open pipes that have no transactions.
249 * active_pipes: Active pipes indexed by transfer type.
250 * frame_number: Increments every SOF interrupt for time keeping.
251 * active_split: Points to the current active split, or NULL.
252 */
253 struct cvmx_usb_internal_state {
254 int init_flags;
255 int index;
256 int idle_hardware_channels;
257 union cvmx_usbcx_hprt usbcx_hprt;
258 struct cvmx_usb_pipe *pipe_for_channel[MAX_CHANNELS];
259 struct cvmx_usb_transaction *free_transaction_head;
260 struct cvmx_usb_transaction *free_transaction_tail;
261 struct cvmx_usb_pipe pipe[MAX_PIPES];
262 struct cvmx_usb_transaction transaction[MAX_TRANSACTIONS];
263 cvmx_usb_callback_func_t callback[__CVMX_USB_CALLBACK_END];
264 void *callback_data[__CVMX_USB_CALLBACK_END];
265 int indent;
266 struct cvmx_usb_port_status port_status;
267 struct cvmx_usb_pipe_list free_pipes;
268 struct cvmx_usb_pipe_list idle_pipes;
269 struct cvmx_usb_pipe_list active_pipes[4];
270 uint64_t frame_number;
271 struct cvmx_usb_transaction *active_split;
272 struct cvmx_usb_tx_fifo periodic;
273 struct cvmx_usb_tx_fifo nonperiodic;
274 };
275
276 /* This macro spins on a field waiting for it to reach a value */
277 #define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\
278 ({int result; \
279 do { \
280 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
281 octeon_get_clock_rate() / 1000000; \
282 type c; \
283 while (1) { \
284 c.u32 = __cvmx_usb_read_csr32(usb, address); \
285 if (c.s.field op (value)) { \
286 result = 0; \
287 break; \
288 } else if (cvmx_get_cycle() > done) { \
289 result = -1; \
290 break; \
291 } else \
292 cvmx_wait(100); \
293 } \
294 } while (0); \
295 result; })
296
297 /*
298 * This macro logically sets a single field in a CSR. It does the sequence
299 * read, modify, and write
300 */
301 #define USB_SET_FIELD32(address, type, field, value) \
302 do { \
303 type c; \
304 c.u32 = __cvmx_usb_read_csr32(usb, address); \
305 c.s.field = value; \
306 __cvmx_usb_write_csr32(usb, address, c.u32); \
307 } while (0)
308
309 /* Returns the IO address to push/pop stuff data from the FIFOs */
310 #define USB_FIFO_ADDRESS(channel, usb_index) (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
311
312 static int octeon_usb_get_clock_type(void)
313 {
314 switch (cvmx_sysinfo_get()->board_type) {
315 case CVMX_BOARD_TYPE_BBGW_REF:
316 case CVMX_BOARD_TYPE_LANAI2_A:
317 case CVMX_BOARD_TYPE_LANAI2_U:
318 case CVMX_BOARD_TYPE_LANAI2_G:
319 case CVMX_BOARD_TYPE_UBNT_E100:
320 return USB_CLOCK_TYPE_CRYSTAL_12;
321 }
322 return USB_CLOCK_TYPE_REF_48;
323 }
324
325 /**
326 * Read a USB 32bit CSR. It performs the necessary address swizzle
327 * for 32bit CSRs and logs the value in a readable format if
328 * debugging is on.
329 *
330 * @usb: USB block this access is for
331 * @address: 64bit address to read
332 *
333 * Returns: Result of the read
334 */
335 static inline uint32_t __cvmx_usb_read_csr32(struct cvmx_usb_internal_state *usb,
336 uint64_t address)
337 {
338 uint32_t result = cvmx_read64_uint32(address ^ 4);
339 return result;
340 }
341
342
343 /**
344 * Write a USB 32bit CSR. It performs the necessary address
345 * swizzle for 32bit CSRs and logs the value in a readable format
346 * if debugging is on.
347 *
348 * @usb: USB block this access is for
349 * @address: 64bit address to write
350 * @value: Value to write
351 */
352 static inline void __cvmx_usb_write_csr32(struct cvmx_usb_internal_state *usb,
353 uint64_t address, uint32_t value)
354 {
355 cvmx_write64_uint32(address ^ 4, value);
356 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
357 }
358
359
360 /**
361 * Read a USB 64bit CSR. It logs the value in a readable format if
362 * debugging is on.
363 *
364 * @usb: USB block this access is for
365 * @address: 64bit address to read
366 *
367 * Returns: Result of the read
368 */
369 static inline uint64_t __cvmx_usb_read_csr64(struct cvmx_usb_internal_state *usb,
370 uint64_t address)
371 {
372 uint64_t result = cvmx_read64_uint64(address);
373 return result;
374 }
375
376
377 /**
378 * Write a USB 64bit CSR. It logs the value in a readable format
379 * if debugging is on.
380 *
381 * @usb: USB block this access is for
382 * @address: 64bit address to write
383 * @value: Value to write
384 */
385 static inline void __cvmx_usb_write_csr64(struct cvmx_usb_internal_state *usb,
386 uint64_t address, uint64_t value)
387 {
388 cvmx_write64_uint64(address, value);
389 }
390
391 /**
392 * Return non zero if this pipe connects to a non HIGH speed
393 * device through a high speed hub.
394 *
395 * @usb: USB block this access is for
396 * @pipe: Pipe to check
397 *
398 * Returns: Non zero if we need to do split transactions
399 */
400 static inline int __cvmx_usb_pipe_needs_split(struct cvmx_usb_internal_state *usb, struct cvmx_usb_pipe *pipe)
401 {
402 return ((pipe->device_speed != CVMX_USB_SPEED_HIGH) && (usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH));
403 }
404
405
406 /**
407 * Trivial utility function to return the correct PID for a pipe
408 *
409 * @pipe: pipe to check
410 *
411 * Returns: PID for pipe
412 */
413 static inline int __cvmx_usb_get_data_pid(struct cvmx_usb_pipe *pipe)
414 {
415 if (pipe->pid_toggle)
416 return 2; /* Data1 */
417 else
418 return 0; /* Data0 */
419 }
420
421
422 /**
423 * Return the number of USB ports supported by this Octeon
424 * chip. If the chip doesn't support USB, or is not supported
425 * by this API, a zero will be returned. Most Octeon chips
426 * support one usb port, but some support two ports.
427 * cvmx_usb_initialize() must be called on independent
428 * struct cvmx_usb_state.
429 *
430 * Returns: Number of port, zero if usb isn't supported
431 */
432 int cvmx_usb_get_num_ports(void)
433 {
434 int arch_ports = 0;
435
436 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
437 arch_ports = 1;
438 else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
439 arch_ports = 2;
440 else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
441 arch_ports = 1;
442 else if (OCTEON_IS_MODEL(OCTEON_CN31XX))
443 arch_ports = 1;
444 else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
445 arch_ports = 1;
446 else
447 arch_ports = 0;
448
449 return arch_ports;
450 }
451
452
453 /**
454 * Allocate a usb transaction for use
455 *
456 * @usb: USB device state populated by
457 * cvmx_usb_initialize().
458 *
459 * Returns: Transaction or NULL
460 */
461 static inline struct cvmx_usb_transaction *__cvmx_usb_alloc_transaction(struct cvmx_usb_internal_state *usb)
462 {
463 struct cvmx_usb_transaction *t;
464 t = usb->free_transaction_head;
465 if (t) {
466 usb->free_transaction_head = t->next;
467 if (!usb->free_transaction_head)
468 usb->free_transaction_tail = NULL;
469 }
470 if (t) {
471 memset(t, 0, sizeof(*t));
472 t->flags = __CVMX_USB_TRANSACTION_FLAGS_IN_USE;
473 }
474 return t;
475 }
476
477
478 /**
479 * Free a usb transaction
480 *
481 * @usb: USB device state populated by
482 * cvmx_usb_initialize().
483 * @transaction:
484 * Transaction to free
485 */
486 static inline void __cvmx_usb_free_transaction(struct cvmx_usb_internal_state *usb,
487 struct cvmx_usb_transaction *transaction)
488 {
489 transaction->flags = 0;
490 transaction->prev = NULL;
491 transaction->next = NULL;
492 if (usb->free_transaction_tail)
493 usb->free_transaction_tail->next = transaction;
494 else
495 usb->free_transaction_head = transaction;
496 usb->free_transaction_tail = transaction;
497 }
498
499
500 /**
501 * Add a pipe to the tail of a list
502 * @list: List to add pipe to
503 * @pipe: Pipe to add
504 */
505 static inline void __cvmx_usb_append_pipe(struct cvmx_usb_pipe_list *list, struct cvmx_usb_pipe *pipe)
506 {
507 pipe->next = NULL;
508 pipe->prev = list->tail;
509 if (list->tail)
510 list->tail->next = pipe;
511 else
512 list->head = pipe;
513 list->tail = pipe;
514 }
515
516
517 /**
518 * Remove a pipe from a list
519 * @list: List to remove pipe from
520 * @pipe: Pipe to remove
521 */
522 static inline void __cvmx_usb_remove_pipe(struct cvmx_usb_pipe_list *list, struct cvmx_usb_pipe *pipe)
523 {
524 if (list->head == pipe) {
525 list->head = pipe->next;
526 pipe->next = NULL;
527 if (list->head)
528 list->head->prev = NULL;
529 else
530 list->tail = NULL;
531 } else if (list->tail == pipe) {
532 list->tail = pipe->prev;
533 list->tail->next = NULL;
534 pipe->prev = NULL;
535 } else {
536 pipe->prev->next = pipe->next;
537 pipe->next->prev = pipe->prev;
538 pipe->prev = NULL;
539 pipe->next = NULL;
540 }
541 }
542
543
544 /**
545 * Initialize a USB port for use. This must be called before any
546 * other access to the Octeon USB port is made. The port starts
547 * off in the disabled state.
548 *
549 * @state: Pointer to an empty struct cvmx_usb_state
550 * that will be populated by the initialize call.
551 * This structure is then passed to all other USB
552 * functions.
553 * @usb_port_number:
554 * Which Octeon USB port to initialize.
555 * @flags: Flags to control hardware initialization. See
556 * enum cvmx_usb_initialize_flags for the flag
557 * definitions. Some flags are mandatory.
558 *
559 * Returns: 0 or a negative error code.
560 */
561 int cvmx_usb_initialize(struct cvmx_usb_state *state, int usb_port_number,
562 enum cvmx_usb_initialize_flags flags)
563 {
564 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
565 union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status;
566 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
567
568 usb->init_flags = flags;
569
570 /* Make sure that state is large enough to store the internal state */
571 if (sizeof(*state) < sizeof(*usb))
572 return -EINVAL;
573 /* At first allow 0-1 for the usb port number */
574 if ((usb_port_number < 0) || (usb_port_number > 1))
575 return -EINVAL;
576 /* For all chips except 52XX there is only one port */
577 if (!OCTEON_IS_MODEL(OCTEON_CN52XX) && (usb_port_number > 0))
578 return -EINVAL;
579 /* Try to determine clock type automatically */
580 if ((flags & (CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI |
581 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND)) == 0) {
582 if (octeon_usb_get_clock_type() == USB_CLOCK_TYPE_CRYSTAL_12)
583 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI; /* Only 12 MHZ crystals are supported */
584 else
585 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND;
586 }
587
588 if (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) {
589 /* Check for auto ref clock frequency */
590 if (!(flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK))
591 switch (octeon_usb_get_clock_type()) {
592 case USB_CLOCK_TYPE_REF_12:
593 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ;
594 break;
595 case USB_CLOCK_TYPE_REF_24:
596 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ;
597 break;
598 case USB_CLOCK_TYPE_REF_48:
599 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ;
600 break;
601 default:
602 return -EINVAL;
603 break;
604 }
605 }
606
607 memset(usb, 0, sizeof(usb));
608 usb->init_flags = flags;
609
610 /* Initialize the USB state structure */
611 {
612 int i;
613 usb->index = usb_port_number;
614
615 /* Initialize the transaction double linked list */
616 usb->free_transaction_head = NULL;
617 usb->free_transaction_tail = NULL;
618 for (i = 0; i < MAX_TRANSACTIONS; i++)
619 __cvmx_usb_free_transaction(usb, usb->transaction + i);
620 for (i = 0; i < MAX_PIPES; i++)
621 __cvmx_usb_append_pipe(&usb->free_pipes, usb->pipe + i);
622 }
623
624 /*
625 * Power On Reset and PHY Initialization
626 *
627 * 1. Wait for DCOK to assert (nothing to do)
628 *
629 * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
630 * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
631 */
632 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
633 usbn_clk_ctl.s.por = 1;
634 usbn_clk_ctl.s.hrst = 0;
635 usbn_clk_ctl.s.prst = 0;
636 usbn_clk_ctl.s.hclk_rst = 0;
637 usbn_clk_ctl.s.enable = 0;
638 /*
639 * 2b. Select the USB reference clock/crystal parameters by writing
640 * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]
641 */
642 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) {
643 /*
644 * The USB port uses 12/24/48MHz 2.5V board clock
645 * source at USB_XO. USB_XI should be tied to GND.
646 * Most Octeon evaluation boards require this setting
647 */
648 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
649 usbn_clk_ctl.cn31xx.p_rclk = 1; /* From CN31XX,CN30XX manual */
650 usbn_clk_ctl.cn31xx.p_xenbn = 0;
651 } else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
652 usbn_clk_ctl.cn56xx.p_rtype = 2; /* From CN56XX,CN50XX manual */
653 else
654 usbn_clk_ctl.cn52xx.p_rtype = 1; /* From CN52XX manual */
655
656 switch (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK) {
657 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ:
658 usbn_clk_ctl.s.p_c_sel = 0;
659 break;
660 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ:
661 usbn_clk_ctl.s.p_c_sel = 1;
662 break;
663 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ:
664 usbn_clk_ctl.s.p_c_sel = 2;
665 break;
666 }
667 } else {
668 /*
669 * The USB port uses a 12MHz crystal as clock source
670 * at USB_XO and USB_XI
671 */
672 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
673 usbn_clk_ctl.cn31xx.p_rclk = 1; /* From CN31XX,CN30XX manual */
674 usbn_clk_ctl.cn31xx.p_xenbn = 1;
675 } else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
676 usbn_clk_ctl.cn56xx.p_rtype = 0; /* From CN56XX,CN50XX manual */
677 else
678 usbn_clk_ctl.cn52xx.p_rtype = 0; /* From CN52XX manual */
679
680 usbn_clk_ctl.s.p_c_sel = 0;
681 }
682 /*
683 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
684 * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down
685 * such that USB is as close as possible to 125Mhz
686 */
687 {
688 int divisor = (octeon_get_clock_rate()+125000000-1)/125000000;
689 if (divisor < 4) /* Lower than 4 doesn't seem to work properly */
690 divisor = 4;
691 usbn_clk_ctl.s.divide = divisor;
692 usbn_clk_ctl.s.divide2 = 0;
693 }
694 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
695 usbn_clk_ctl.u64);
696 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
697 usbn_clk_ctl.s.hclk_rst = 1;
698 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
699 usbn_clk_ctl.u64);
700 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
701 cvmx_wait(64);
702 /*
703 * 3. Program the power-on reset field in the USBN clock-control
704 * register:
705 * USBN_CLK_CTL[POR] = 0
706 */
707 usbn_clk_ctl.s.por = 0;
708 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
709 usbn_clk_ctl.u64);
710 /* 4. Wait 1 ms for PHY clock to start */
711 mdelay(1);
712 /*
713 * 5. Program the Reset input from automatic test equipment field in the
714 * USBP control and status register:
715 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1
716 */
717 usbn_usbp_ctl_status.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index));
718 usbn_usbp_ctl_status.s.ate_reset = 1;
719 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
720 usbn_usbp_ctl_status.u64);
721 /* 6. Wait 10 cycles */
722 cvmx_wait(10);
723 /*
724 * 7. Clear ATE_RESET field in the USBN clock-control register:
725 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0
726 */
727 usbn_usbp_ctl_status.s.ate_reset = 0;
728 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
729 usbn_usbp_ctl_status.u64);
730 /*
731 * 8. Program the PHY reset field in the USBN clock-control register:
732 * USBN_CLK_CTL[PRST] = 1
733 */
734 usbn_clk_ctl.s.prst = 1;
735 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
736 usbn_clk_ctl.u64);
737 /*
738 * 9. Program the USBP control and status register to select host or
739 * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
740 * device
741 */
742 usbn_usbp_ctl_status.s.hst_mode = 0;
743 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
744 usbn_usbp_ctl_status.u64);
745 /* 10. Wait 1 us */
746 udelay(1);
747 /*
748 * 11. Program the hreset_n field in the USBN clock-control register:
749 * USBN_CLK_CTL[HRST] = 1
750 */
751 usbn_clk_ctl.s.hrst = 1;
752 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
753 usbn_clk_ctl.u64);
754 /* 12. Proceed to USB core initialization */
755 usbn_clk_ctl.s.enable = 1;
756 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
757 usbn_clk_ctl.u64);
758 udelay(1);
759
760 /*
761 * USB Core Initialization
762 *
763 * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
764 * determine USB core configuration parameters.
765 *
766 * Nothing needed
767 *
768 * 2. Program the following fields in the global AHB configuration
769 * register (USBC_GAHBCFG)
770 * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
771 * Burst length, USBC_GAHBCFG[HBSTLEN] = 0
772 * Nonperiodic TxFIFO empty level (slave mode only),
773 * USBC_GAHBCFG[NPTXFEMPLVL]
774 * Periodic TxFIFO empty level (slave mode only),
775 * USBC_GAHBCFG[PTXFEMPLVL]
776 * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1
777 */
778 {
779 union cvmx_usbcx_gahbcfg usbcx_gahbcfg;
780 /* Due to an errata, CN31XX doesn't support DMA */
781 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
782 usb->init_flags |= CVMX_USB_INITIALIZE_FLAGS_NO_DMA;
783 usbcx_gahbcfg.u32 = 0;
784 usbcx_gahbcfg.s.dmaen = !(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA);
785 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
786 usb->idle_hardware_channels = 0x1; /* Only use one channel with non DMA */
787 else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
788 usb->idle_hardware_channels = 0xf7; /* CN5XXX have an errata with channel 3 */
789 else
790 usb->idle_hardware_channels = 0xff;
791 usbcx_gahbcfg.s.hbstlen = 0;
792 usbcx_gahbcfg.s.nptxfemplvl = 1;
793 usbcx_gahbcfg.s.ptxfemplvl = 1;
794 usbcx_gahbcfg.s.glblintrmsk = 1;
795 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index),
796 usbcx_gahbcfg.u32);
797 }
798 /*
799 * 3. Program the following fields in USBC_GUSBCFG register.
800 * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
801 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
802 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
803 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0
804 */
805 {
806 union cvmx_usbcx_gusbcfg usbcx_gusbcfg;
807 usbcx_gusbcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index));
808 usbcx_gusbcfg.s.toutcal = 0;
809 usbcx_gusbcfg.s.ddrsel = 0;
810 usbcx_gusbcfg.s.usbtrdtim = 0x5;
811 usbcx_gusbcfg.s.phylpwrclksel = 0;
812 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index),
813 usbcx_gusbcfg.u32);
814 }
815 /*
816 * 4. The software must unmask the following bits in the USBC_GINTMSK
817 * register.
818 * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
819 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1
820 */
821 {
822 union cvmx_usbcx_gintmsk usbcx_gintmsk;
823 int channel;
824
825 usbcx_gintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTMSK(usb->index));
826 usbcx_gintmsk.s.otgintmsk = 1;
827 usbcx_gintmsk.s.modemismsk = 1;
828 usbcx_gintmsk.s.hchintmsk = 1;
829 usbcx_gintmsk.s.sofmsk = 0;
830 /* We need RX FIFO interrupts if we don't have DMA */
831 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
832 usbcx_gintmsk.s.rxflvlmsk = 1;
833 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index),
834 usbcx_gintmsk.u32);
835
836 /* Disable all channel interrupts. We'll enable them per channel later */
837 for (channel = 0; channel < 8; channel++)
838 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
839 }
840
841 {
842 /*
843 * Host Port Initialization
844 *
845 * 1. Program the host-port interrupt-mask field to unmask,
846 * USBC_GINTMSK[PRTINT] = 1
847 */
848 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk,
849 prtintmsk, 1);
850 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk,
851 disconnintmsk, 1);
852 /*
853 * 2. Program the USBC_HCFG register to select full-speed host
854 * or high-speed host.
855 */
856 {
857 union cvmx_usbcx_hcfg usbcx_hcfg;
858 usbcx_hcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCFG(usb->index));
859 usbcx_hcfg.s.fslssupp = 0;
860 usbcx_hcfg.s.fslspclksel = 0;
861 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCFG(usb->index), usbcx_hcfg.u32);
862 }
863 /*
864 * 3. Program the port power bit to drive VBUS on the USB,
865 * USBC_HPRT[PRTPWR] = 1
866 */
867 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtpwr, 1);
868
869 /*
870 * Steps 4-15 from the manual are done later in the port enable
871 */
872 }
873
874 return 0;
875 }
876
877
878 /**
879 * Shutdown a USB port after a call to cvmx_usb_initialize().
880 * The port should be disabled with all pipes closed when this
881 * function is called.
882 *
883 * @state: USB device state populated by
884 * cvmx_usb_initialize().
885 *
886 * Returns: 0 or a negative error code.
887 */
888 int cvmx_usb_shutdown(struct cvmx_usb_state *state)
889 {
890 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
891 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
892
893 /* Make sure all pipes are closed */
894 if (usb->idle_pipes.head ||
895 usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS].head ||
896 usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT].head ||
897 usb->active_pipes[CVMX_USB_TRANSFER_CONTROL].head ||
898 usb->active_pipes[CVMX_USB_TRANSFER_BULK].head)
899 return -EBUSY;
900
901 /* Disable the clocks and put them in power on reset */
902 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
903 usbn_clk_ctl.s.enable = 1;
904 usbn_clk_ctl.s.por = 1;
905 usbn_clk_ctl.s.hclk_rst = 1;
906 usbn_clk_ctl.s.prst = 0;
907 usbn_clk_ctl.s.hrst = 0;
908 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
909 usbn_clk_ctl.u64);
910 return 0;
911 }
912
913
914 /**
915 * Enable a USB port. After this call succeeds, the USB port is
916 * online and servicing requests.
917 *
918 * @state: USB device state populated by
919 * cvmx_usb_initialize().
920 *
921 * Returns: 0 or a negative error code.
922 */
923 int cvmx_usb_enable(struct cvmx_usb_state *state)
924 {
925 union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3;
926 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
927
928 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
929
930 /*
931 * If the port is already enabled the just return. We don't need to do
932 * anything
933 */
934 if (usb->usbcx_hprt.s.prtena)
935 return 0;
936
937 /* If there is nothing plugged into the port then fail immediately */
938 if (!usb->usbcx_hprt.s.prtconnsts) {
939 return -ETIMEDOUT;
940 }
941
942 /* Program the port reset bit to start the reset process */
943 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtrst, 1);
944
945 /*
946 * Wait at least 50ms (high speed), or 10ms (full speed) for the reset
947 * process to complete.
948 */
949 mdelay(50);
950
951 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
952 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtrst, 0);
953
954 /* Wait for the USBC_HPRT[PRTENA]. */
955 if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt,
956 prtena, ==, 1, 100000))
957 return -ETIMEDOUT;
958
959 /* Read the port speed field to get the enumerated speed, USBC_HPRT[PRTSPD]. */
960 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
961 usbcx_ghwcfg3.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GHWCFG3(usb->index));
962
963 /*
964 * 13. Program the USBC_GRXFSIZ register to select the size of the
965 * receive FIFO (25%).
966 */
967 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index), union cvmx_usbcx_grxfsiz,
968 rxfdep, usbcx_ghwcfg3.s.dfifodepth / 4);
969 /*
970 * 14. Program the USBC_GNPTXFSIZ register to select the size and the
971 * start address of the non- periodic transmit FIFO for nonperiodic
972 * transactions (50%).
973 */
974 {
975 union cvmx_usbcx_gnptxfsiz siz;
976 siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index));
977 siz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2;
978 siz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4;
979 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), siz.u32);
980 }
981 /*
982 * 15. Program the USBC_HPTXFSIZ register to select the size and start
983 * address of the periodic transmit FIFO for periodic transactions
984 * (25%).
985 */
986 {
987 union cvmx_usbcx_hptxfsiz siz;
988 siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index));
989 siz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4;
990 siz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4;
991 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index), siz.u32);
992 }
993 /* Flush all FIFOs */
994 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, txfnum, 0x10);
995 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, txfflsh, 1);
996 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl,
997 txfflsh, ==, 0, 100);
998 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, rxfflsh, 1);
999 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl,
1000 rxfflsh, ==, 0, 100);
1001
1002 return 0;
1003 }
1004
1005
1006 /**
1007 * Disable a USB port. After this call the USB port will not
1008 * generate data transfers and will not generate events.
1009 * Transactions in process will fail and call their
1010 * associated callbacks.
1011 *
1012 * @state: USB device state populated by
1013 * cvmx_usb_initialize().
1014 *
1015 * Returns: 0 or a negative error code.
1016 */
1017 int cvmx_usb_disable(struct cvmx_usb_state *state)
1018 {
1019 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
1020
1021 /* Disable the port */
1022 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtena, 1);
1023 return 0;
1024 }
1025
1026
1027 /**
1028 * Get the current state of the USB port. Use this call to
1029 * determine if the usb port has anything connected, is enabled,
1030 * or has some sort of error condition. The return value of this
1031 * call has "changed" bits to signal of the value of some fields
1032 * have changed between calls. These "changed" fields are based
1033 * on the last call to cvmx_usb_set_status(). In order to clear
1034 * them, you must update the status through cvmx_usb_set_status().
1035 *
1036 * @state: USB device state populated by
1037 * cvmx_usb_initialize().
1038 *
1039 * Returns: Port status information
1040 */
1041 struct cvmx_usb_port_status cvmx_usb_get_status(struct cvmx_usb_state *state)
1042 {
1043 union cvmx_usbcx_hprt usbc_hprt;
1044 struct cvmx_usb_port_status result;
1045 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
1046
1047 memset(&result, 0, sizeof(result));
1048
1049 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
1050 result.port_enabled = usbc_hprt.s.prtena;
1051 result.port_over_current = usbc_hprt.s.prtovrcurract;
1052 result.port_powered = usbc_hprt.s.prtpwr;
1053 result.port_speed = usbc_hprt.s.prtspd;
1054 result.connected = usbc_hprt.s.prtconnsts;
1055 result.connect_change = (result.connected != usb->port_status.connected);
1056
1057 return result;
1058 }
1059
1060
1061 /**
1062 * Set the current state of the USB port. The status is used as
1063 * a reference for the "changed" bits returned by
1064 * cvmx_usb_get_status(). Other than serving as a reference, the
1065 * status passed to this function is not used. No fields can be
1066 * changed through this call.
1067 *
1068 * @state: USB device state populated by
1069 * cvmx_usb_initialize().
1070 * @port_status:
1071 * Port status to set, most like returned by cvmx_usb_get_status()
1072 */
1073 void cvmx_usb_set_status(struct cvmx_usb_state *state, struct cvmx_usb_port_status port_status)
1074 {
1075 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
1076 usb->port_status = port_status;
1077 return;
1078 }
1079
1080
1081 /**
1082 * Convert a USB transaction into a handle
1083 *
1084 * @usb: USB device state populated by
1085 * cvmx_usb_initialize().
1086 * @transaction:
1087 * Transaction to get handle for
1088 *
1089 * Returns: Handle
1090 */
1091 static inline int __cvmx_usb_get_submit_handle(struct cvmx_usb_internal_state *usb,
1092 struct cvmx_usb_transaction *transaction)
1093 {
1094 return ((unsigned long)transaction - (unsigned long)usb->transaction) /
1095 sizeof(*transaction);
1096 }
1097
1098
1099 /**
1100 * Convert a USB pipe into a handle
1101 *
1102 * @usb: USB device state populated by
1103 * cvmx_usb_initialize().
1104 * @pipe: Pipe to get handle for
1105 *
1106 * Returns: Handle
1107 */
1108 static inline int __cvmx_usb_get_pipe_handle(struct cvmx_usb_internal_state *usb,
1109 struct cvmx_usb_pipe *pipe)
1110 {
1111 return ((unsigned long)pipe - (unsigned long)usb->pipe) / sizeof(*pipe);
1112 }
1113
1114
1115 /**
1116 * Open a virtual pipe between the host and a USB device. A pipe
1117 * must be opened before data can be transferred between a device
1118 * and Octeon.
1119 *
1120 * @state: USB device state populated by
1121 * cvmx_usb_initialize().
1122 * @flags: Optional pipe flags defined in
1123 * enum cvmx_usb_pipe_flags.
1124 * @device_addr:
1125 * USB device address to open the pipe to
1126 * (0-127).
1127 * @endpoint_num:
1128 * USB endpoint number to open the pipe to
1129 * (0-15).
1130 * @device_speed:
1131 * The speed of the device the pipe is going
1132 * to. This must match the device's speed,
1133 * which may be different than the port speed.
1134 * @max_packet: The maximum packet length the device can
1135 * transmit/receive (low speed=0-8, full
1136 * speed=0-1023, high speed=0-1024). This value
1137 * comes from the standard endpoint descriptor
1138 * field wMaxPacketSize bits <10:0>.
1139 * @transfer_type:
1140 * The type of transfer this pipe is for.
1141 * @transfer_dir:
1142 * The direction the pipe is in. This is not
1143 * used for control pipes.
1144 * @interval: For ISOCHRONOUS and INTERRUPT transfers,
1145 * this is how often the transfer is scheduled
1146 * for. All other transfers should specify
1147 * zero. The units are in frames (8000/sec at
1148 * high speed, 1000/sec for full speed).
1149 * @multi_count:
1150 * For high speed devices, this is the maximum
1151 * allowed number of packet per microframe.
1152 * Specify zero for non high speed devices. This
1153 * value comes from the standard endpoint descriptor
1154 * field wMaxPacketSize bits <12:11>.
1155 * @hub_device_addr:
1156 * Hub device address this device is connected
1157 * to. Devices connected directly to Octeon
1158 * use zero. This is only used when the device
1159 * is full/low speed behind a high speed hub.
1160 * The address will be of the high speed hub,
1161 * not and full speed hubs after it.
1162 * @hub_port: Which port on the hub the device is
1163 * connected. Use zero for devices connected
1164 * directly to Octeon. Like hub_device_addr,
1165 * this is only used for full/low speed
1166 * devices behind a high speed hub.
1167 *
1168 * Returns: A non negative value is a pipe handle. Negative
1169 * values are error codes.
1170 */
1171 int cvmx_usb_open_pipe(struct cvmx_usb_state *state, enum cvmx_usb_pipe_flags flags,
1172 int device_addr, int endpoint_num,
1173 enum cvmx_usb_speed device_speed, int max_packet,
1174 enum cvmx_usb_transfer transfer_type,
1175 enum cvmx_usb_direction transfer_dir, int interval,
1176 int multi_count, int hub_device_addr, int hub_port)
1177 {
1178 struct cvmx_usb_pipe *pipe;
1179 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
1180
1181 if (unlikely((device_addr < 0) || (device_addr > MAX_USB_ADDRESS)))
1182 return -EINVAL;
1183 if (unlikely((endpoint_num < 0) || (endpoint_num > MAX_USB_ENDPOINT)))
1184 return -EINVAL;
1185 if (unlikely(device_speed > CVMX_USB_SPEED_LOW))
1186 return -EINVAL;
1187 if (unlikely((max_packet <= 0) || (max_packet > 1024)))
1188 return -EINVAL;
1189 if (unlikely(transfer_type > CVMX_USB_TRANSFER_INTERRUPT))
1190 return -EINVAL;
1191 if (unlikely((transfer_dir != CVMX_USB_DIRECTION_OUT) &&
1192 (transfer_dir != CVMX_USB_DIRECTION_IN)))
1193 return -EINVAL;
1194 if (unlikely(interval < 0))
1195 return -EINVAL;
1196 if (unlikely((transfer_type == CVMX_USB_TRANSFER_CONTROL) && interval))
1197 return -EINVAL;
1198 if (unlikely(multi_count < 0))
1199 return -EINVAL;
1200 if (unlikely((device_speed != CVMX_USB_SPEED_HIGH) &&
1201 (multi_count != 0)))
1202 return -EINVAL;
1203 if (unlikely((hub_device_addr < 0) || (hub_device_addr > MAX_USB_ADDRESS)))
1204 return -EINVAL;
1205 if (unlikely((hub_port < 0) || (hub_port > MAX_USB_HUB_PORT)))
1206 return -EINVAL;
1207
1208 /* Find a free pipe */
1209 pipe = usb->free_pipes.head;
1210 if (!pipe)
1211 return -ENOMEM;
1212 __cvmx_usb_remove_pipe(&usb->free_pipes, pipe);
1213 pipe->flags = flags | __CVMX_USB_PIPE_FLAGS_OPEN;
1214 if ((device_speed == CVMX_USB_SPEED_HIGH) &&
1215 (transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1216 (transfer_type == CVMX_USB_TRANSFER_BULK))
1217 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
1218 pipe->device_addr = device_addr;
1219 pipe->endpoint_num = endpoint_num;
1220 pipe->device_speed = device_speed;
1221 pipe->max_packet = max_packet;
1222 pipe->transfer_type = transfer_type;
1223 pipe->transfer_dir = transfer_dir;
1224 /*
1225 * All pipes use interval to rate limit NAK processing. Force an
1226 * interval if one wasn't supplied
1227 */
1228 if (!interval)
1229 interval = 1;
1230 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1231 pipe->interval = interval*8;
1232 /* Force start splits to be schedule on uFrame 0 */
1233 pipe->next_tx_frame = ((usb->frame_number+7)&~7) + pipe->interval;
1234 } else {
1235 pipe->interval = interval;
1236 pipe->next_tx_frame = usb->frame_number + pipe->interval;
1237 }
1238 pipe->multi_count = multi_count;
1239 pipe->hub_device_addr = hub_device_addr;
1240 pipe->hub_port = hub_port;
1241 pipe->pid_toggle = 0;
1242 pipe->split_sc_frame = -1;
1243 __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
1244
1245 /*
1246 * We don't need to tell the hardware about this pipe yet since
1247 * it doesn't have any submitted requests
1248 */
1249
1250 return __cvmx_usb_get_pipe_handle(usb, pipe);
1251 }
1252
1253
1254 /**
1255 * Poll the RX FIFOs and remove data as needed. This function is only used
1256 * in non DMA mode. It is very important that this function be called quickly
1257 * enough to prevent FIFO overflow.
1258 *
1259 * @usb: USB device state populated by
1260 * cvmx_usb_initialize().
1261 */
1262 static void __cvmx_usb_poll_rx_fifo(struct cvmx_usb_internal_state *usb)
1263 {
1264 union cvmx_usbcx_grxstsph rx_status;
1265 int channel;
1266 int bytes;
1267 uint64_t address;
1268 uint32_t *ptr;
1269
1270 rx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GRXSTSPH(usb->index));
1271 /* Only read data if IN data is there */
1272 if (rx_status.s.pktsts != 2)
1273 return;
1274 /* Check if no data is available */
1275 if (!rx_status.s.bcnt)
1276 return;
1277
1278 channel = rx_status.s.chnum;
1279 bytes = rx_status.s.bcnt;
1280 if (!bytes)
1281 return;
1282
1283 /* Get where the DMA engine would have written this data */
1284 address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8);
1285 ptr = cvmx_phys_to_ptr(address);
1286 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, address + bytes);
1287
1288 /* Loop writing the FIFO data for this packet into memory */
1289 while (bytes > 0) {
1290 *ptr++ = __cvmx_usb_read_csr32(usb, USB_FIFO_ADDRESS(channel, usb->index));
1291 bytes -= 4;
1292 }
1293 CVMX_SYNCW;
1294
1295 return;
1296 }
1297
1298
1299 /**
1300 * Fill the TX hardware fifo with data out of the software
1301 * fifos
1302 *
1303 * @usb: USB device state populated by
1304 * cvmx_usb_initialize().
1305 * @fifo: Software fifo to use
1306 * @available: Amount of space in the hardware fifo
1307 *
1308 * Returns: Non zero if the hardware fifo was too small and needs
1309 * to be serviced again.
1310 */
1311 static int __cvmx_usb_fill_tx_hw(struct cvmx_usb_internal_state *usb, struct cvmx_usb_tx_fifo *fifo, int available)
1312 {
1313 /*
1314 * We're done either when there isn't anymore space or the software FIFO
1315 * is empty
1316 */
1317 while (available && (fifo->head != fifo->tail)) {
1318 int i = fifo->tail;
1319 const uint32_t *ptr = cvmx_phys_to_ptr(fifo->entry[i].address);
1320 uint64_t csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel, usb->index) ^ 4;
1321 int words = available;
1322
1323 /* Limit the amount of data to waht the SW fifo has */
1324 if (fifo->entry[i].size <= available) {
1325 words = fifo->entry[i].size;
1326 fifo->tail++;
1327 if (fifo->tail > MAX_CHANNELS)
1328 fifo->tail = 0;
1329 }
1330
1331 /* Update the next locations and counts */
1332 available -= words;
1333 fifo->entry[i].address += words * 4;
1334 fifo->entry[i].size -= words;
1335
1336 /*
1337 * Write the HW fifo data. The read every three writes is due
1338 * to an errata on CN3XXX chips
1339 */
1340 while (words > 3) {
1341 cvmx_write64_uint32(csr_address, *ptr++);
1342 cvmx_write64_uint32(csr_address, *ptr++);
1343 cvmx_write64_uint32(csr_address, *ptr++);
1344 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1345 words -= 3;
1346 }
1347 cvmx_write64_uint32(csr_address, *ptr++);
1348 if (--words) {
1349 cvmx_write64_uint32(csr_address, *ptr++);
1350 if (--words)
1351 cvmx_write64_uint32(csr_address, *ptr++);
1352 }
1353 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1354 }
1355 return fifo->head != fifo->tail;
1356 }
1357
1358
1359 /**
1360 * Check the hardware FIFOs and fill them as needed
1361 *
1362 * @usb: USB device state populated by
1363 * cvmx_usb_initialize().
1364 */
1365 static void __cvmx_usb_poll_tx_fifo(struct cvmx_usb_internal_state *usb)
1366 {
1367 if (usb->periodic.head != usb->periodic.tail) {
1368 union cvmx_usbcx_hptxsts tx_status;
1369 tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXSTS(usb->index));
1370 if (__cvmx_usb_fill_tx_hw(usb, &usb->periodic, tx_status.s.ptxfspcavail))
1371 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, ptxfempmsk, 1);
1372 else
1373 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, ptxfempmsk, 0);
1374 }
1375
1376 if (usb->nonperiodic.head != usb->nonperiodic.tail) {
1377 union cvmx_usbcx_gnptxsts tx_status;
1378 tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXSTS(usb->index));
1379 if (__cvmx_usb_fill_tx_hw(usb, &usb->nonperiodic, tx_status.s.nptxfspcavail))
1380 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, nptxfempmsk, 1);
1381 else
1382 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, nptxfempmsk, 0);
1383 }
1384
1385 return;
1386 }
1387
1388
1389 /**
1390 * Fill the TX FIFO with an outgoing packet
1391 *
1392 * @usb: USB device state populated by
1393 * cvmx_usb_initialize().
1394 * @channel: Channel number to get packet from
1395 */
1396 static void __cvmx_usb_fill_tx_fifo(struct cvmx_usb_internal_state *usb, int channel)
1397 {
1398 union cvmx_usbcx_hccharx hcchar;
1399 union cvmx_usbcx_hcspltx usbc_hcsplt;
1400 union cvmx_usbcx_hctsizx usbc_hctsiz;
1401 struct cvmx_usb_tx_fifo *fifo;
1402
1403 /* We only need to fill data on outbound channels */
1404 hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
1405 if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT)
1406 return;
1407
1408 /* OUT Splits only have data on the start and not the complete */
1409 usbc_hcsplt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index));
1410 if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt)
1411 return;
1412
1413 /* Find out how many bytes we need to fill and convert it into 32bit words */
1414 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
1415 if (!usbc_hctsiz.s.xfersize)
1416 return;
1417
1418 if ((hcchar.s.eptype == CVMX_USB_TRANSFER_INTERRUPT) ||
1419 (hcchar.s.eptype == CVMX_USB_TRANSFER_ISOCHRONOUS))
1420 fifo = &usb->periodic;
1421 else
1422 fifo = &usb->nonperiodic;
1423
1424 fifo->entry[fifo->head].channel = channel;
1425 fifo->entry[fifo->head].address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8);
1426 fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize+3)>>2;
1427 fifo->head++;
1428 if (fifo->head > MAX_CHANNELS)
1429 fifo->head = 0;
1430
1431 __cvmx_usb_poll_tx_fifo(usb);
1432
1433 return;
1434 }
1435
1436 /**
1437 * Perform channel specific setup for Control transactions. All
1438 * the generic stuff will already have been done in
1439 * __cvmx_usb_start_channel()
1440 *
1441 * @usb: USB device state populated by
1442 * cvmx_usb_initialize().
1443 * @channel: Channel to setup
1444 * @pipe: Pipe for control transaction
1445 */
1446 static void __cvmx_usb_start_channel_control(struct cvmx_usb_internal_state *usb,
1447 int channel,
1448 struct cvmx_usb_pipe *pipe)
1449 {
1450 struct cvmx_usb_transaction *transaction = pipe->head;
1451 union cvmx_usb_control_header *header =
1452 cvmx_phys_to_ptr(transaction->control_header);
1453 int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
1454 int packets_to_transfer;
1455 union cvmx_usbcx_hctsizx usbc_hctsiz;
1456
1457 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
1458
1459 switch (transaction->stage) {
1460 case CVMX_USB_STAGE_NON_CONTROL:
1461 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
1462 cvmx_dprintf("%s: ERROR - Non control stage\n", __FUNCTION__);
1463 break;
1464 case CVMX_USB_STAGE_SETUP:
1465 usbc_hctsiz.s.pid = 3; /* Setup */
1466 bytes_to_transfer = sizeof(*header);
1467 /* All Control operations start with a setup going OUT */
1468 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir, CVMX_USB_DIRECTION_OUT);
1469 /*
1470 * Setup send the control header instead of the buffer data. The
1471 * buffer data will be used in the next stage
1472 */
1473 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, transaction->control_header);
1474 break;
1475 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
1476 usbc_hctsiz.s.pid = 3; /* Setup */
1477 bytes_to_transfer = 0;
1478 /* All Control operations start with a setup going OUT */
1479 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir, CVMX_USB_DIRECTION_OUT);
1480 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1481 break;
1482 case CVMX_USB_STAGE_DATA:
1483 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1484 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1485 if (header->s.request_type & 0x80)
1486 bytes_to_transfer = 0;
1487 else if (bytes_to_transfer > pipe->max_packet)
1488 bytes_to_transfer = pipe->max_packet;
1489 }
1490 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1491 union cvmx_usbcx_hccharx, epdir,
1492 ((header->s.request_type & 0x80) ?
1493 CVMX_USB_DIRECTION_IN :
1494 CVMX_USB_DIRECTION_OUT));
1495 break;
1496 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
1497 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1498 if (!(header->s.request_type & 0x80))
1499 bytes_to_transfer = 0;
1500 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1501 union cvmx_usbcx_hccharx, epdir,
1502 ((header->s.request_type & 0x80) ?
1503 CVMX_USB_DIRECTION_IN :
1504 CVMX_USB_DIRECTION_OUT));
1505 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1506 break;
1507 case CVMX_USB_STAGE_STATUS:
1508 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1509 bytes_to_transfer = 0;
1510 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir,
1511 ((header->s.request_type & 0x80) ?
1512 CVMX_USB_DIRECTION_OUT :
1513 CVMX_USB_DIRECTION_IN));
1514 break;
1515 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
1516 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1517 bytes_to_transfer = 0;
1518 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir,
1519 ((header->s.request_type & 0x80) ?
1520 CVMX_USB_DIRECTION_OUT :
1521 CVMX_USB_DIRECTION_IN));
1522 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1523 break;
1524 }
1525
1526 /*
1527 * Make sure the transfer never exceeds the byte limit of the hardware.
1528 * Further bytes will be sent as continued transactions
1529 */
1530 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1531 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1532 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1533 bytes_to_transfer *= pipe->max_packet;
1534 }
1535
1536 /*
1537 * Calculate the number of packets to transfer. If the length is zero
1538 * we still need to transfer one packet
1539 */
1540 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
1541 if (packets_to_transfer == 0)
1542 packets_to_transfer = 1;
1543 else if ((packets_to_transfer > 1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1544 /*
1545 * Limit to one packet when not using DMA. Channels must be
1546 * restarted between every packet for IN transactions, so there
1547 * is no reason to do multiple packets in a row
1548 */
1549 packets_to_transfer = 1;
1550 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1551 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1552 /*
1553 * Limit the number of packet and data transferred to what the
1554 * hardware can handle
1555 */
1556 packets_to_transfer = MAX_TRANSFER_PACKETS;
1557 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1558 }
1559
1560 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1561 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1562
1563 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
1564 return;
1565 }
1566
1567
1568 /**
1569 * Start a channel to perform the pipe's head transaction
1570 *
1571 * @usb: USB device state populated by
1572 * cvmx_usb_initialize().
1573 * @channel: Channel to setup
1574 * @pipe: Pipe to start
1575 */
1576 static void __cvmx_usb_start_channel(struct cvmx_usb_internal_state *usb,
1577 int channel,
1578 struct cvmx_usb_pipe *pipe)
1579 {
1580 struct cvmx_usb_transaction *transaction = pipe->head;
1581
1582 /* Make sure all writes to the DMA region get flushed */
1583 CVMX_SYNCW;
1584
1585 /* Attach the channel to the pipe */
1586 usb->pipe_for_channel[channel] = pipe;
1587 pipe->channel = channel;
1588 pipe->flags |= __CVMX_USB_PIPE_FLAGS_SCHEDULED;
1589
1590 /* Mark this channel as in use */
1591 usb->idle_hardware_channels &= ~(1<<channel);
1592
1593 /* Enable the channel interrupt bits */
1594 {
1595 union cvmx_usbcx_hcintx usbc_hcint;
1596 union cvmx_usbcx_hcintmskx usbc_hcintmsk;
1597 union cvmx_usbcx_haintmsk usbc_haintmsk;
1598
1599 /* Clear all channel status bits */
1600 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
1601 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index), usbc_hcint.u32);
1602
1603 usbc_hcintmsk.u32 = 0;
1604 usbc_hcintmsk.s.chhltdmsk = 1;
1605 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1606 /* Channels need these extra interrupts when we aren't in DMA mode */
1607 usbc_hcintmsk.s.datatglerrmsk = 1;
1608 usbc_hcintmsk.s.frmovrunmsk = 1;
1609 usbc_hcintmsk.s.bblerrmsk = 1;
1610 usbc_hcintmsk.s.xacterrmsk = 1;
1611 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1612 /* Splits don't generate xfercompl, so we need ACK and NYET */
1613 usbc_hcintmsk.s.nyetmsk = 1;
1614 usbc_hcintmsk.s.ackmsk = 1;
1615 }
1616 usbc_hcintmsk.s.nakmsk = 1;
1617 usbc_hcintmsk.s.stallmsk = 1;
1618 usbc_hcintmsk.s.xfercomplmsk = 1;
1619 }
1620 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), usbc_hcintmsk.u32);
1621
1622 /* Enable the channel interrupt to propagate */
1623 usbc_haintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index));
1624 usbc_haintmsk.s.haintmsk |= 1<<channel;
1625 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index), usbc_haintmsk.u32);
1626 }
1627
1628 /* Setup the locations the DMA engines use */
1629 {
1630 uint64_t dma_address = transaction->buffer + transaction->actual_bytes;
1631 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1632 dma_address = transaction->buffer + transaction->iso_packets[0].offset + transaction->actual_bytes;
1633 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, dma_address);
1634 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, dma_address);
1635 }
1636
1637 /* Setup both the size of the transfer and the SPLIT characteristics */
1638 {
1639 union cvmx_usbcx_hcspltx usbc_hcsplt = {.u32 = 0};
1640 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = 0};
1641 int packets_to_transfer;
1642 int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
1643
1644 /*
1645 * ISOCHRONOUS transactions store each individual transfer size
1646 * in the packet structure, not the global buffer_length
1647 */
1648 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1649 bytes_to_transfer = transaction->iso_packets[0].length - transaction->actual_bytes;
1650
1651 /*
1652 * We need to do split transactions when we are talking to non
1653 * high speed devices that are behind a high speed hub
1654 */
1655 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1656 /*
1657 * On the start split phase (stage is even) record the
1658 * frame number we will need to send the split complete.
1659 * We only store the lower two bits since the time ahead
1660 * can only be two frames
1661 */
1662 if ((transaction->stage&1) == 0) {
1663 if (transaction->type == CVMX_USB_TRANSFER_BULK)
1664 pipe->split_sc_frame = (usb->frame_number + 1) & 0x7f;
1665 else
1666 pipe->split_sc_frame = (usb->frame_number + 2) & 0x7f;
1667 } else
1668 pipe->split_sc_frame = -1;
1669
1670 usbc_hcsplt.s.spltena = 1;
1671 usbc_hcsplt.s.hubaddr = pipe->hub_device_addr;
1672 usbc_hcsplt.s.prtaddr = pipe->hub_port;
1673 usbc_hcsplt.s.compsplt = (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE);
1674
1675 /*
1676 * SPLIT transactions can only ever transmit one data
1677 * packet so limit the transfer size to the max packet
1678 * size
1679 */
1680 if (bytes_to_transfer > pipe->max_packet)
1681 bytes_to_transfer = pipe->max_packet;
1682
1683 /*
1684 * ISOCHRONOUS OUT splits are unique in that they limit
1685 * data transfers to 188 byte chunks representing the
1686 * begin/middle/end of the data or all
1687 */
1688 if (!usbc_hcsplt.s.compsplt &&
1689 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1690 (pipe->transfer_type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
1691 /*
1692 * Clear the split complete frame number as
1693 * there isn't going to be a split complete
1694 */
1695 pipe->split_sc_frame = -1;
1696 /*
1697 * See if we've started this transfer and sent
1698 * data
1699 */
1700 if (transaction->actual_bytes == 0) {
1701 /*
1702 * Nothing sent yet, this is either a
1703 * begin or the entire payload
1704 */
1705 if (bytes_to_transfer <= 188)
1706 usbc_hcsplt.s.xactpos = 3; /* Entire payload in one go */
1707 else
1708 usbc_hcsplt.s.xactpos = 2; /* First part of payload */
1709 } else {
1710 /*
1711 * Continuing the previous data, we must
1712 * either be in the middle or at the end
1713 */
1714 if (bytes_to_transfer <= 188)
1715 usbc_hcsplt.s.xactpos = 1; /* End of payload */
1716 else
1717 usbc_hcsplt.s.xactpos = 0; /* Middle of payload */
1718 }
1719 /*
1720 * Again, the transfer size is limited to 188
1721 * bytes
1722 */
1723 if (bytes_to_transfer > 188)
1724 bytes_to_transfer = 188;
1725 }
1726 }
1727
1728 /*
1729 * Make sure the transfer never exceeds the byte limit of the
1730 * hardware. Further bytes will be sent as continued
1731 * transactions
1732 */
1733 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1734 /*
1735 * Round MAX_TRANSFER_BYTES to a multiple of out packet
1736 * size
1737 */
1738 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1739 bytes_to_transfer *= pipe->max_packet;
1740 }
1741
1742 /*
1743 * Calculate the number of packets to transfer. If the length is
1744 * zero we still need to transfer one packet
1745 */
1746 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
1747 if (packets_to_transfer == 0)
1748 packets_to_transfer = 1;
1749 else if ((packets_to_transfer > 1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1750 /*
1751 * Limit to one packet when not using DMA. Channels must
1752 * be restarted between every packet for IN
1753 * transactions, so there is no reason to do multiple
1754 * packets in a row
1755 */
1756 packets_to_transfer = 1;
1757 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1758 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1759 /*
1760 * Limit the number of packet and data transferred to
1761 * what the hardware can handle
1762 */
1763 packets_to_transfer = MAX_TRANSFER_PACKETS;
1764 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1765 }
1766
1767 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1768 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1769
1770 /* Update the DATA0/DATA1 toggle */
1771 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1772 /*
1773 * High speed pipes may need a hardware ping before they start
1774 */
1775 if (pipe->flags & __CVMX_USB_PIPE_FLAGS_NEED_PING)
1776 usbc_hctsiz.s.dopng = 1;
1777
1778 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index), usbc_hcsplt.u32);
1779 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
1780 }
1781
1782 /* Setup the Host Channel Characteristics Register */
1783 {
1784 union cvmx_usbcx_hccharx usbc_hcchar = {.u32 = 0};
1785
1786 /*
1787 * Set the startframe odd/even properly. This is only used for
1788 * periodic
1789 */
1790 usbc_hcchar.s.oddfrm = usb->frame_number&1;
1791
1792 /*
1793 * Set the number of back to back packets allowed by this
1794 * endpoint. Split transactions interpret "ec" as the number of
1795 * immediate retries of failure. These retries happen too
1796 * quickly, so we disable these entirely for splits
1797 */
1798 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1799 usbc_hcchar.s.ec = 1;
1800 else if (pipe->multi_count < 1)
1801 usbc_hcchar.s.ec = 1;
1802 else if (pipe->multi_count > 3)
1803 usbc_hcchar.s.ec = 3;
1804 else
1805 usbc_hcchar.s.ec = pipe->multi_count;
1806
1807 /* Set the rest of the endpoint specific settings */
1808 usbc_hcchar.s.devaddr = pipe->device_addr;
1809 usbc_hcchar.s.eptype = transaction->type;
1810 usbc_hcchar.s.lspddev = (pipe->device_speed == CVMX_USB_SPEED_LOW);
1811 usbc_hcchar.s.epdir = pipe->transfer_dir;
1812 usbc_hcchar.s.epnum = pipe->endpoint_num;
1813 usbc_hcchar.s.mps = pipe->max_packet;
1814 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
1815 }
1816
1817 /* Do transaction type specific fixups as needed */
1818 switch (transaction->type) {
1819 case CVMX_USB_TRANSFER_CONTROL:
1820 __cvmx_usb_start_channel_control(usb, channel, pipe);
1821 break;
1822 case CVMX_USB_TRANSFER_BULK:
1823 case CVMX_USB_TRANSFER_INTERRUPT:
1824 break;
1825 case CVMX_USB_TRANSFER_ISOCHRONOUS:
1826 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
1827 /*
1828 * ISO transactions require different PIDs depending on
1829 * direction and how many packets are needed
1830 */
1831 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
1832 if (pipe->multi_count < 2) /* Need DATA0 */
1833 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), union cvmx_usbcx_hctsizx, pid, 0);
1834 else /* Need MDATA */
1835 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), union cvmx_usbcx_hctsizx, pid, 3);
1836 }
1837 }
1838 break;
1839 }
1840 {
1841 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index))};
1842 transaction->xfersize = usbc_hctsiz.s.xfersize;
1843 transaction->pktcnt = usbc_hctsiz.s.pktcnt;
1844 }
1845 /* Remeber when we start a split transaction */
1846 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1847 usb->active_split = transaction;
1848 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, chena, 1);
1849 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
1850 __cvmx_usb_fill_tx_fifo(usb, channel);
1851 return;
1852 }
1853
1854
1855 /**
1856 * Find a pipe that is ready to be scheduled to hardware.
1857 * @usb: USB device state populated by
1858 * cvmx_usb_initialize().
1859 * @list: Pipe list to search
1860 * @current_frame:
1861 * Frame counter to use as a time reference.
1862 *
1863 * Returns: Pipe or NULL if none are ready
1864 */
1865 static struct cvmx_usb_pipe *__cvmx_usb_find_ready_pipe(struct cvmx_usb_internal_state *usb, struct cvmx_usb_pipe_list *list, uint64_t current_frame)
1866 {
1867 struct cvmx_usb_pipe *pipe = list->head;
1868 while (pipe) {
1869 if (!(pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED) && pipe->head &&
1870 (pipe->next_tx_frame <= current_frame) &&
1871 ((pipe->split_sc_frame == -1) || ((((int)current_frame - (int)pipe->split_sc_frame) & 0x7f) < 0x40)) &&
1872 (!usb->active_split || (usb->active_split == pipe->head))) {
1873 CVMX_PREFETCH(pipe, 128);
1874 CVMX_PREFETCH(pipe->head, 0);
1875 return pipe;
1876 }
1877 pipe = pipe->next;
1878 }
1879 return NULL;
1880 }
1881
1882
1883 /**
1884 * Called whenever a pipe might need to be scheduled to the
1885 * hardware.
1886 *
1887 * @usb: USB device state populated by
1888 * cvmx_usb_initialize().
1889 * @is_sof: True if this schedule was called on a SOF interrupt.
1890 */
1891 static void __cvmx_usb_schedule(struct cvmx_usb_internal_state *usb, int is_sof)
1892 {
1893 int channel;
1894 struct cvmx_usb_pipe *pipe;
1895 int need_sof;
1896 enum cvmx_usb_transfer ttype;
1897
1898 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1899 /* Without DMA we need to be careful to not schedule something at the end of a frame and cause an overrun */
1900 union cvmx_usbcx_hfnum hfnum = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index))};
1901 union cvmx_usbcx_hfir hfir = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFIR(usb->index))};
1902 if (hfnum.s.frrem < hfir.s.frint/4)
1903 goto done;
1904 }
1905
1906 while (usb->idle_hardware_channels) {
1907 /* Find an idle channel */
1908 CVMX_CLZ(channel, usb->idle_hardware_channels);
1909 channel = 31 - channel;
1910 if (unlikely(channel > 7))
1911 break;
1912
1913 /* Find a pipe needing service */
1914 pipe = NULL;
1915 if (is_sof) {
1916 /*
1917 * Only process periodic pipes on SOF interrupts. This
1918 * way we are sure that the periodic data is sent in the
1919 * beginning of the frame
1920 */
1921 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_ISOCHRONOUS, usb->frame_number);
1922 if (likely(!pipe))
1923 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_INTERRUPT, usb->frame_number);
1924 }
1925 if (likely(!pipe)) {
1926 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_CONTROL, usb->frame_number);
1927 if (likely(!pipe))
1928 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_BULK, usb->frame_number);
1929 }
1930 if (!pipe)
1931 break;
1932
1933 __cvmx_usb_start_channel(usb, channel, pipe);
1934 }
1935
1936 done:
1937 /*
1938 * Only enable SOF interrupts when we have transactions pending in the
1939 * future that might need to be scheduled
1940 */
1941 need_sof = 0;
1942 for (ttype = CVMX_USB_TRANSFER_CONTROL; ttype <= CVMX_USB_TRANSFER_INTERRUPT; ttype++) {
1943 pipe = usb->active_pipes[ttype].head;
1944 while (pipe) {
1945 if (pipe->next_tx_frame > usb->frame_number) {
1946 need_sof = 1;
1947 break;
1948 }
1949 pipe = pipe->next;
1950 }
1951 }
1952 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, sofmsk, need_sof);
1953 return;
1954 }
1955
1956
1957 /**
1958 * Call a user's callback for a specific reason.
1959 *
1960 * @usb: USB device state populated by
1961 * cvmx_usb_initialize().
1962 * @pipe: Pipe the callback is for or NULL
1963 * @transaction:
1964 * Transaction the callback is for or NULL
1965 * @reason: Reason this callback is being called
1966 * @complete_code:
1967 * Completion code for the transaction, if any
1968 */
1969 static void __cvmx_usb_perform_callback(struct cvmx_usb_internal_state *usb,
1970 struct cvmx_usb_pipe *pipe,
1971 struct cvmx_usb_transaction *transaction,
1972 enum cvmx_usb_callback reason,
1973 enum cvmx_usb_complete complete_code)
1974 {
1975 cvmx_usb_callback_func_t callback = usb->callback[reason];
1976 void *user_data = usb->callback_data[reason];
1977 int submit_handle = -1;
1978 int pipe_handle = -1;
1979 int bytes_transferred = 0;
1980
1981 if (pipe)
1982 pipe_handle = __cvmx_usb_get_pipe_handle(usb, pipe);
1983
1984 if (transaction) {
1985 submit_handle = __cvmx_usb_get_submit_handle(usb, transaction);
1986 bytes_transferred = transaction->actual_bytes;
1987 /* Transactions are allowed to override the default callback */
1988 if ((reason == CVMX_USB_CALLBACK_TRANSFER_COMPLETE) && transaction->callback) {
1989 callback = transaction->callback;
1990 user_data = transaction->callback_data;
1991 }
1992 }
1993
1994 if (!callback)
1995 return;
1996
1997 callback((struct cvmx_usb_state *)usb, reason, complete_code, pipe_handle, submit_handle,
1998 bytes_transferred, user_data);
1999 }
2000
2001
2002 /**
2003 * Signal the completion of a transaction and free it. The
2004 * transaction will be removed from the pipe transaction list.
2005 *
2006 * @usb: USB device state populated by
2007 * cvmx_usb_initialize().
2008 * @pipe: Pipe the transaction is on
2009 * @transaction:
2010 * Transaction that completed
2011 * @complete_code:
2012 * Completion code
2013 */
2014 static void __cvmx_usb_perform_complete(struct cvmx_usb_internal_state *usb,
2015 struct cvmx_usb_pipe *pipe,
2016 struct cvmx_usb_transaction *transaction,
2017 enum cvmx_usb_complete complete_code)
2018 {
2019 /* If this was a split then clear our split in progress marker */
2020 if (usb->active_split == transaction)
2021 usb->active_split = NULL;
2022
2023 /*
2024 * Isochronous transactions need extra processing as they might not be
2025 * done after a single data transfer
2026 */
2027 if (unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
2028 /* Update the number of bytes transferred in this ISO packet */
2029 transaction->iso_packets[0].length = transaction->actual_bytes;
2030 transaction->iso_packets[0].status = complete_code;
2031
2032 /*
2033 * If there are more ISOs pending and we succeeded, schedule the
2034 * next one
2035 */
2036 if ((transaction->iso_number_packets > 1) && (complete_code == CVMX_USB_COMPLETE_SUCCESS)) {
2037 transaction->actual_bytes = 0; /* No bytes transferred for this packet as of yet */
2038 transaction->iso_number_packets--; /* One less ISO waiting to transfer */
2039 transaction->iso_packets++; /* Increment to the next location in our packet array */
2040 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2041 goto done;
2042 }
2043 }
2044
2045 /* Remove the transaction from the pipe list */
2046 if (transaction->next)
2047 transaction->next->prev = transaction->prev;
2048 else
2049 pipe->tail = transaction->prev;
2050 if (transaction->prev)
2051 transaction->prev->next = transaction->next;
2052 else
2053 pipe->head = transaction->next;
2054 if (!pipe->head) {
2055 __cvmx_usb_remove_pipe(usb->active_pipes + pipe->transfer_type, pipe);
2056 __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
2057
2058 }
2059 __cvmx_usb_perform_callback(usb, pipe, transaction,
2060 CVMX_USB_CALLBACK_TRANSFER_COMPLETE,
2061 complete_code);
2062 __cvmx_usb_free_transaction(usb, transaction);
2063 done:
2064 return;
2065 }
2066
2067
2068 /**
2069 * Submit a usb transaction to a pipe. Called for all types
2070 * of transactions.
2071 *
2072 * @usb:
2073 * @pipe_handle:
2074 * Which pipe to submit to. Will be validated in this function.
2075 * @type: Transaction type
2076 * @flags: Flags for the transaction
2077 * @buffer: User buffer for the transaction
2078 * @buffer_length:
2079 * User buffer's length in bytes
2080 * @control_header:
2081 * For control transactions, the 8 byte standard header
2082 * @iso_start_frame:
2083 * For ISO transactions, the start frame
2084 * @iso_number_packets:
2085 * For ISO, the number of packet in the transaction.
2086 * @iso_packets:
2087 * A description of each ISO packet
2088 * @callback: User callback to call when the transaction completes
2089 * @user_data: User's data for the callback
2090 *
2091 * Returns: Submit handle or negative on failure. Matches the result
2092 * in the external API.
2093 */
2094 static int __cvmx_usb_submit_transaction(struct cvmx_usb_internal_state *usb,
2095 int pipe_handle,
2096 enum cvmx_usb_transfer type,
2097 int flags,
2098 uint64_t buffer,
2099 int buffer_length,
2100 uint64_t control_header,
2101 int iso_start_frame,
2102 int iso_number_packets,
2103 struct cvmx_usb_iso_packet *iso_packets,
2104 cvmx_usb_callback_func_t callback,
2105 void *user_data)
2106 {
2107 int submit_handle;
2108 struct cvmx_usb_transaction *transaction;
2109 struct cvmx_usb_pipe *pipe = usb->pipe + pipe_handle;
2110
2111 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2112 return -EINVAL;
2113 /* Fail if the pipe isn't open */
2114 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2115 return -EINVAL;
2116 if (unlikely(pipe->transfer_type != type))
2117 return -EINVAL;
2118
2119 transaction = __cvmx_usb_alloc_transaction(usb);
2120 if (unlikely(!transaction))
2121 return -ENOMEM;
2122
2123 transaction->type = type;
2124 transaction->flags |= flags;
2125 transaction->buffer = buffer;
2126 transaction->buffer_length = buffer_length;
2127 transaction->control_header = control_header;
2128 transaction->iso_start_frame = iso_start_frame; // FIXME: This is not used, implement it
2129 transaction->iso_number_packets = iso_number_packets;
2130 transaction->iso_packets = iso_packets;
2131 transaction->callback = callback;
2132 transaction->callback_data = user_data;
2133 if (transaction->type == CVMX_USB_TRANSFER_CONTROL)
2134 transaction->stage = CVMX_USB_STAGE_SETUP;
2135 else
2136 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2137
2138 transaction->next = NULL;
2139 if (pipe->tail) {
2140 transaction->prev = pipe->tail;
2141 transaction->prev->next = transaction;
2142 } else {
2143 if (pipe->next_tx_frame < usb->frame_number)
2144 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2145 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2146 transaction->prev = NULL;
2147 pipe->head = transaction;
2148 __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
2149 __cvmx_usb_append_pipe(usb->active_pipes + pipe->transfer_type, pipe);
2150 }
2151 pipe->tail = transaction;
2152
2153 submit_handle = __cvmx_usb_get_submit_handle(usb, transaction);
2154
2155 /* We may need to schedule the pipe if this was the head of the pipe */
2156 if (!transaction->prev)
2157 __cvmx_usb_schedule(usb, 0);
2158
2159 return submit_handle;
2160 }
2161
2162
2163 /**
2164 * Call to submit a USB Bulk transfer to a pipe.
2165 *
2166 * @state: USB device state populated by
2167 * cvmx_usb_initialize().
2168 * @pipe_handle:
2169 * Handle to the pipe for the transfer.
2170 * @buffer: Physical address of the data buffer in
2171 * memory. Note that this is NOT A POINTER, but
2172 * the full 64bit physical address of the
2173 * buffer. This may be zero if buffer_length is
2174 * zero.
2175 * @buffer_length:
2176 * Length of buffer in bytes.
2177 * @callback: Function to call when this transaction
2178 * completes. If the return value of this
2179 * function isn't an error, then this function
2180 * is guaranteed to be called when the
2181 * transaction completes. If this parameter is
2182 * NULL, then the generic callback registered
2183 * through cvmx_usb_register_callback is
2184 * called. If both are NULL, then there is no
2185 * way to know when a transaction completes.
2186 * @user_data: User supplied data returned when the
2187 * callback is called. This is only used if
2188 * callback in not NULL.
2189 *
2190 * Returns: A submitted transaction handle or negative on
2191 * failure. Negative values are error codes.
2192 */
2193 int cvmx_usb_submit_bulk(struct cvmx_usb_state *state, int pipe_handle,
2194 uint64_t buffer, int buffer_length,
2195 cvmx_usb_callback_func_t callback,
2196 void *user_data)
2197 {
2198 int submit_handle;
2199 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2200
2201 /* Pipe handle checking is done later in a common place */
2202 if (unlikely(!buffer))
2203 return -EINVAL;
2204 if (unlikely(buffer_length < 0))
2205 return -EINVAL;
2206
2207 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2208 CVMX_USB_TRANSFER_BULK,
2209 0, /* flags */
2210 buffer,
2211 buffer_length,
2212 0, /* control_header */
2213 0, /* iso_start_frame */
2214 0, /* iso_number_packets */
2215 NULL, /* iso_packets */
2216 callback,
2217 user_data);
2218 return submit_handle;
2219 }
2220
2221
2222 /**
2223 * Call to submit a USB Interrupt transfer to a pipe.
2224 *
2225 * @state: USB device state populated by
2226 * cvmx_usb_initialize().
2227 * @pipe_handle:
2228 * Handle to the pipe for the transfer.
2229 * @buffer: Physical address of the data buffer in
2230 * memory. Note that this is NOT A POINTER, but
2231 * the full 64bit physical address of the
2232 * buffer. This may be zero if buffer_length is
2233 * zero.
2234 * @buffer_length:
2235 * Length of buffer in bytes.
2236 * @callback: Function to call when this transaction
2237 * completes. If the return value of this
2238 * function isn't an error, then this function
2239 * is guaranteed to be called when the
2240 * transaction completes. If this parameter is
2241 * NULL, then the generic callback registered
2242 * through cvmx_usb_register_callback is
2243 * called. If both are NULL, then there is no
2244 * way to know when a transaction completes.
2245 * @user_data: User supplied data returned when the
2246 * callback is called. This is only used if
2247 * callback in not NULL.
2248 *
2249 * Returns: A submitted transaction handle or negative on
2250 * failure. Negative values are error codes.
2251 */
2252 int cvmx_usb_submit_interrupt(struct cvmx_usb_state *state, int pipe_handle,
2253 uint64_t buffer, int buffer_length,
2254 cvmx_usb_callback_func_t callback,
2255 void *user_data)
2256 {
2257 int submit_handle;
2258 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2259
2260 /* Pipe handle checking is done later in a common place */
2261 if (unlikely(!buffer))
2262 return -EINVAL;
2263 if (unlikely(buffer_length < 0))
2264 return -EINVAL;
2265
2266 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2267 CVMX_USB_TRANSFER_INTERRUPT,
2268 0, /* flags */
2269 buffer,
2270 buffer_length,
2271 0, /* control_header */
2272 0, /* iso_start_frame */
2273 0, /* iso_number_packets */
2274 NULL, /* iso_packets */
2275 callback,
2276 user_data);
2277 return submit_handle;
2278 }
2279
2280
2281 /**
2282 * Call to submit a USB Control transfer to a pipe.
2283 *
2284 * @state: USB device state populated by
2285 * cvmx_usb_initialize().
2286 * @pipe_handle:
2287 * Handle to the pipe for the transfer.
2288 * @control_header:
2289 * USB 8 byte control header physical address.
2290 * Note that this is NOT A POINTER, but the
2291 * full 64bit physical address of the buffer.
2292 * @buffer: Physical address of the data buffer in
2293 * memory. Note that this is NOT A POINTER, but
2294 * the full 64bit physical address of the
2295 * buffer. This may be zero if buffer_length is
2296 * zero.
2297 * @buffer_length:
2298 * Length of buffer in bytes.
2299 * @callback: Function to call when this transaction
2300 * completes. If the return value of this
2301 * function isn't an error, then this function
2302 * is guaranteed to be called when the
2303 * transaction completes. If this parameter is
2304 * NULL, then the generic callback registered
2305 * through cvmx_usb_register_callback is
2306 * called. If both are NULL, then there is no
2307 * way to know when a transaction completes.
2308 * @user_data: User supplied data returned when the
2309 * callback is called. This is only used if
2310 * callback in not NULL.
2311 *
2312 * Returns: A submitted transaction handle or negative on
2313 * failure. Negative values are error codes.
2314 */
2315 int cvmx_usb_submit_control(struct cvmx_usb_state *state, int pipe_handle,
2316 uint64_t control_header,
2317 uint64_t buffer, int buffer_length,
2318 cvmx_usb_callback_func_t callback,
2319 void *user_data)
2320 {
2321 int submit_handle;
2322 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2323 union cvmx_usb_control_header *header =
2324 cvmx_phys_to_ptr(control_header);
2325
2326 /* Pipe handle checking is done later in a common place */
2327 if (unlikely(!control_header))
2328 return -EINVAL;
2329 /* Some drivers send a buffer with a zero length. God only knows why */
2330 if (unlikely(buffer && (buffer_length < 0)))
2331 return -EINVAL;
2332 if (unlikely(!buffer && (buffer_length != 0)))
2333 return -EINVAL;
2334 if ((header->s.request_type & 0x80) == 0)
2335 buffer_length = le16_to_cpu(header->s.length);
2336
2337 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2338 CVMX_USB_TRANSFER_CONTROL,
2339 0, /* flags */
2340 buffer,
2341 buffer_length,
2342 control_header,
2343 0, /* iso_start_frame */
2344 0, /* iso_number_packets */
2345 NULL, /* iso_packets */
2346 callback,
2347 user_data);
2348 return submit_handle;
2349 }
2350
2351
2352 /**
2353 * Call to submit a USB Isochronous transfer to a pipe.
2354 *
2355 * @state: USB device state populated by
2356 * cvmx_usb_initialize().
2357 * @pipe_handle:
2358 * Handle to the pipe for the transfer.
2359 * @start_frame:
2360 * Number of frames into the future to schedule
2361 * this transaction.
2362 * @flags: Flags to control the transfer. See
2363 * enum cvmx_usb_isochronous_flags for the flag
2364 * definitions.
2365 * @number_packets:
2366 * Number of sequential packets to transfer.
2367 * "packets" is a pointer to an array of this
2368 * many packet structures.
2369 * @packets: Description of each transfer packet as
2370 * defined by struct cvmx_usb_iso_packet. The array
2371 * pointed to here must stay valid until the
2372 * complete callback is called.
2373 * @buffer: Physical address of the data buffer in
2374 * memory. Note that this is NOT A POINTER, but
2375 * the full 64bit physical address of the
2376 * buffer. This may be zero if buffer_length is
2377 * zero.
2378 * @buffer_length:
2379 * Length of buffer in bytes.
2380 * @callback: Function to call when this transaction
2381 * completes. If the return value of this
2382 * function isn't an error, then this function
2383 * is guaranteed to be called when the
2384 * transaction completes. If this parameter is
2385 * NULL, then the generic callback registered
2386 * through cvmx_usb_register_callback is
2387 * called. If both are NULL, then there is no
2388 * way to know when a transaction completes.
2389 * @user_data: User supplied data returned when the
2390 * callback is called. This is only used if
2391 * callback in not NULL.
2392 *
2393 * Returns: A submitted transaction handle or negative on
2394 * failure. Negative values are error codes.
2395 */
2396 int cvmx_usb_submit_isochronous(struct cvmx_usb_state *state, int pipe_handle,
2397 int start_frame, int flags,
2398 int number_packets,
2399 struct cvmx_usb_iso_packet packets[],
2400 uint64_t buffer, int buffer_length,
2401 cvmx_usb_callback_func_t callback,
2402 void *user_data)
2403 {
2404 int submit_handle;
2405 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2406
2407 /* Pipe handle checking is done later in a common place */
2408 if (unlikely(start_frame < 0))
2409 return -EINVAL;
2410 if (unlikely(flags & ~(CVMX_USB_ISOCHRONOUS_FLAGS_ALLOW_SHORT | CVMX_USB_ISOCHRONOUS_FLAGS_ASAP)))
2411 return -EINVAL;
2412 if (unlikely(number_packets < 1))
2413 return -EINVAL;
2414 if (unlikely(!packets))
2415 return -EINVAL;
2416 if (unlikely(!buffer))
2417 return -EINVAL;
2418 if (unlikely(buffer_length < 0))
2419 return -EINVAL;
2420
2421 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2422 CVMX_USB_TRANSFER_ISOCHRONOUS,
2423 flags,
2424 buffer,
2425 buffer_length,
2426 0, /* control_header */
2427 start_frame,
2428 number_packets,
2429 packets,
2430 callback,
2431 user_data);
2432 return submit_handle;
2433 }
2434
2435
2436 /**
2437 * Cancel one outstanding request in a pipe. Canceling a request
2438 * can fail if the transaction has already completed before cancel
2439 * is called. Even after a successful cancel call, it may take
2440 * a frame or two for the cvmx_usb_poll() function to call the
2441 * associated callback.
2442 *
2443 * @state: USB device state populated by
2444 * cvmx_usb_initialize().
2445 * @pipe_handle:
2446 * Pipe handle to cancel requests in.
2447 * @submit_handle:
2448 * Handle to transaction to cancel, returned by the submit function.
2449 *
2450 * Returns: 0 or a negative error code.
2451 */
2452 int cvmx_usb_cancel(struct cvmx_usb_state *state, int pipe_handle, int submit_handle)
2453 {
2454 struct cvmx_usb_transaction *transaction;
2455 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2456 struct cvmx_usb_pipe *pipe = usb->pipe + pipe_handle;
2457
2458 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2459 return -EINVAL;
2460 if (unlikely((submit_handle < 0) || (submit_handle >= MAX_TRANSACTIONS)))
2461 return -EINVAL;
2462
2463 /* Fail if the pipe isn't open */
2464 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2465 return -EINVAL;
2466
2467 transaction = usb->transaction + submit_handle;
2468
2469 /* Fail if this transaction already completed */
2470 if (unlikely((transaction->flags & __CVMX_USB_TRANSACTION_FLAGS_IN_USE) == 0))
2471 return -EINVAL;
2472
2473 /*
2474 * If the transaction is the HEAD of the queue and scheduled. We need to
2475 * treat it special
2476 */
2477 if ((pipe->head == transaction) &&
2478 (pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED)) {
2479 union cvmx_usbcx_hccharx usbc_hcchar;
2480
2481 usb->pipe_for_channel[pipe->channel] = NULL;
2482 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2483
2484 CVMX_SYNCW;
2485
2486 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index));
2487 /* If the channel isn't enabled then the transaction already completed */
2488 if (usbc_hcchar.s.chena) {
2489 usbc_hcchar.s.chdis = 1;
2490 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index), usbc_hcchar.u32);
2491 }
2492 }
2493 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_CANCEL);
2494 return 0;
2495 }
2496
2497
2498 /**
2499 * Cancel all outstanding requests in a pipe. Logically all this
2500 * does is call cvmx_usb_cancel() in a loop.
2501 *
2502 * @state: USB device state populated by
2503 * cvmx_usb_initialize().
2504 * @pipe_handle:
2505 * Pipe handle to cancel requests in.
2506 *
2507 * Returns: 0 or a negative error code.
2508 */
2509 int cvmx_usb_cancel_all(struct cvmx_usb_state *state, int pipe_handle)
2510 {
2511 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2512 struct cvmx_usb_pipe *pipe = usb->pipe + pipe_handle;
2513
2514 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2515 return -EINVAL;
2516
2517 /* Fail if the pipe isn't open */
2518 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2519 return -EINVAL;
2520
2521 /* Simply loop through and attempt to cancel each transaction */
2522 while (pipe->head) {
2523 int result = cvmx_usb_cancel(state, pipe_handle,
2524 __cvmx_usb_get_submit_handle(usb, pipe->head));
2525 if (unlikely(result != 0))
2526 return result;
2527 }
2528 return 0;
2529 }
2530
2531
2532 /**
2533 * Close a pipe created with cvmx_usb_open_pipe().
2534 *
2535 * @state: USB device state populated by
2536 * cvmx_usb_initialize().
2537 * @pipe_handle:
2538 * Pipe handle to close.
2539 *
2540 * Returns: 0 or a negative error code. EBUSY is returned if the pipe has
2541 * outstanding transfers.
2542 */
2543 int cvmx_usb_close_pipe(struct cvmx_usb_state *state, int pipe_handle)
2544 {
2545 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2546 struct cvmx_usb_pipe *pipe = usb->pipe + pipe_handle;
2547
2548 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2549 return -EINVAL;
2550
2551 /* Fail if the pipe isn't open */
2552 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2553 return -EINVAL;
2554
2555 /* Fail if the pipe has pending transactions */
2556 if (unlikely(pipe->head))
2557 return -EBUSY;
2558
2559 pipe->flags = 0;
2560 __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
2561 __cvmx_usb_append_pipe(&usb->free_pipes, pipe);
2562
2563 return 0;
2564 }
2565
2566
2567 /**
2568 * Register a function to be called when various USB events occur.
2569 *
2570 * @state: USB device state populated by
2571 * cvmx_usb_initialize().
2572 * @reason: Which event to register for.
2573 * @callback: Function to call when the event occurs.
2574 * @user_data: User data parameter to the function.
2575 *
2576 * Returns: 0 or a negative error code.
2577 */
2578 int cvmx_usb_register_callback(struct cvmx_usb_state *state,
2579 enum cvmx_usb_callback reason,
2580 cvmx_usb_callback_func_t callback,
2581 void *user_data)
2582 {
2583 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2584
2585 if (unlikely(reason >= __CVMX_USB_CALLBACK_END))
2586 return -EINVAL;
2587 if (unlikely(!callback))
2588 return -EINVAL;
2589
2590 usb->callback[reason] = callback;
2591 usb->callback_data[reason] = user_data;
2592
2593 return 0;
2594 }
2595
2596
2597 /**
2598 * Get the current USB protocol level frame number. The frame
2599 * number is always in the range of 0-0x7ff.
2600 *
2601 * @state: USB device state populated by
2602 * cvmx_usb_initialize().
2603 *
2604 * Returns: USB frame number
2605 */
2606 int cvmx_usb_get_frame_number(struct cvmx_usb_state *state)
2607 {
2608 int frame_number;
2609 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2610 union cvmx_usbcx_hfnum usbc_hfnum;
2611
2612 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
2613 frame_number = usbc_hfnum.s.frnum;
2614
2615 return frame_number;
2616 }
2617
2618
2619 /**
2620 * Poll a channel for status
2621 *
2622 * @usb: USB device
2623 * @channel: Channel to poll
2624 *
2625 * Returns: Zero on success
2626 */
2627 static int __cvmx_usb_poll_channel(struct cvmx_usb_internal_state *usb, int channel)
2628 {
2629 union cvmx_usbcx_hcintx usbc_hcint;
2630 union cvmx_usbcx_hctsizx usbc_hctsiz;
2631 union cvmx_usbcx_hccharx usbc_hcchar;
2632 struct cvmx_usb_pipe *pipe;
2633 struct cvmx_usb_transaction *transaction;
2634 int bytes_this_transfer;
2635 int bytes_in_last_packet;
2636 int packets_processed;
2637 int buffer_space_left;
2638
2639 /* Read the interrupt status bits for the channel */
2640 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
2641
2642 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
2643 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
2644
2645 if (usbc_hcchar.s.chena && usbc_hcchar.s.chdis) {
2646 /*
2647 * There seems to be a bug in CN31XX which can cause
2648 * interrupt IN transfers to get stuck until we do a
2649 * write of HCCHARX without changing things
2650 */
2651 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
2652 return 0;
2653 }
2654
2655 /*
2656 * In non DMA mode the channels don't halt themselves. We need
2657 * to manually disable channels that are left running
2658 */
2659 if (!usbc_hcint.s.chhltd) {
2660 if (usbc_hcchar.s.chena) {
2661 union cvmx_usbcx_hcintmskx hcintmsk;
2662 /* Disable all interrupts except CHHLTD */
2663 hcintmsk.u32 = 0;
2664 hcintmsk.s.chhltdmsk = 1;
2665 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), hcintmsk.u32);
2666 usbc_hcchar.s.chdis = 1;
2667 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
2668 return 0;
2669 } else if (usbc_hcint.s.xfercompl) {
2670 /* Successful IN/OUT with transfer complete. Channel halt isn't needed */
2671 } else {
2672 cvmx_dprintf("USB%d: Channel %d interrupt without halt\n", usb->index, channel);
2673 return 0;
2674 }
2675 }
2676 } else {
2677 /*
2678 * There is are no interrupts that we need to process when the
2679 * channel is still running
2680 */
2681 if (!usbc_hcint.s.chhltd)
2682 return 0;
2683 }
2684
2685 /* Disable the channel interrupts now that it is done */
2686 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
2687 usb->idle_hardware_channels |= (1<<channel);
2688
2689 /* Make sure this channel is tied to a valid pipe */
2690 pipe = usb->pipe_for_channel[channel];
2691 CVMX_PREFETCH(pipe, 0);
2692 CVMX_PREFETCH(pipe, 128);
2693 if (!pipe)
2694 return 0;
2695 transaction = pipe->head;
2696 CVMX_PREFETCH0(transaction);
2697
2698 /*
2699 * Disconnect this pipe from the HW channel. Later the schedule
2700 * function will figure out which pipe needs to go
2701 */
2702 usb->pipe_for_channel[channel] = NULL;
2703 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2704
2705 /*
2706 * Read the channel config info so we can figure out how much data
2707 * transfered
2708 */
2709 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
2710 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
2711
2712 /*
2713 * Calculating the number of bytes successfully transferred is dependent
2714 * on the transfer direction
2715 */
2716 packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt;
2717 if (usbc_hcchar.s.epdir) {
2718 /*
2719 * IN transactions are easy. For every byte received the
2720 * hardware decrements xfersize. All we need to do is subtract
2721 * the current value of xfersize from its starting value and we
2722 * know how many bytes were written to the buffer
2723 */
2724 bytes_this_transfer = transaction->xfersize - usbc_hctsiz.s.xfersize;
2725 } else {
2726 /*
2727 * OUT transaction don't decrement xfersize. Instead pktcnt is
2728 * decremented on every successful packet send. The hardware
2729 * does this when it receives an ACK, or NYET. If it doesn't
2730 * receive one of these responses pktcnt doesn't change
2731 */
2732 bytes_this_transfer = packets_processed * usbc_hcchar.s.mps;
2733 /*
2734 * The last packet may not be a full transfer if we didn't have
2735 * enough data
2736 */
2737 if (bytes_this_transfer > transaction->xfersize)
2738 bytes_this_transfer = transaction->xfersize;
2739 }
2740 /* Figure out how many bytes were in the last packet of the transfer */
2741 if (packets_processed)
2742 bytes_in_last_packet = bytes_this_transfer - (packets_processed-1) * usbc_hcchar.s.mps;
2743 else
2744 bytes_in_last_packet = bytes_this_transfer;
2745
2746 /*
2747 * As a special case, setup transactions output the setup header, not
2748 * the user's data. For this reason we don't count setup data as bytes
2749 * transferred
2750 */
2751 if ((transaction->stage == CVMX_USB_STAGE_SETUP) ||
2752 (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE))
2753 bytes_this_transfer = 0;
2754
2755 /*
2756 * Add the bytes transferred to the running total. It is important that
2757 * bytes_this_transfer doesn't count any data that needs to be
2758 * retransmitted
2759 */
2760 transaction->actual_bytes += bytes_this_transfer;
2761 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
2762 buffer_space_left = transaction->iso_packets[0].length - transaction->actual_bytes;
2763 else
2764 buffer_space_left = transaction->buffer_length - transaction->actual_bytes;
2765
2766 /*
2767 * We need to remember the PID toggle state for the next transaction.
2768 * The hardware already updated it for the next transaction
2769 */
2770 pipe->pid_toggle = !(usbc_hctsiz.s.pid == 0);
2771
2772 /*
2773 * For high speed bulk out, assume the next transaction will need to do
2774 * a ping before proceeding. If this isn't true the ACK processing below
2775 * will clear this flag
2776 */
2777 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2778 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2779 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT))
2780 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2781
2782 if (usbc_hcint.s.stall) {
2783 /*
2784 * STALL as a response means this transaction cannot be
2785 * completed because the device can't process transactions. Tell
2786 * the user. Any data that was transferred will be counted on
2787 * the actual bytes transferred
2788 */
2789 pipe->pid_toggle = 0;
2790 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_STALL);
2791 } else if (usbc_hcint.s.xacterr) {
2792 /*
2793 * We know at least one packet worked if we get a ACK or NAK.
2794 * Reset the retry counter
2795 */
2796 if (usbc_hcint.s.nak || usbc_hcint.s.ack)
2797 transaction->retries = 0;
2798 transaction->retries++;
2799 if (transaction->retries > MAX_RETRIES) {
2800 /*
2801 * XactErr as a response means the device signaled
2802 * something wrong with the transfer. For example, PID
2803 * toggle errors cause these
2804 */
2805 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_XACTERR);
2806 } else {
2807 /*
2808 * If this was a split then clear our split in progress
2809 * marker
2810 */
2811 if (usb->active_split == transaction)
2812 usb->active_split = NULL;
2813 /*
2814 * Rewind to the beginning of the transaction by anding
2815 * off the split complete bit
2816 */
2817 transaction->stage &= ~1;
2818 pipe->split_sc_frame = -1;
2819 pipe->next_tx_frame += pipe->interval;
2820 if (pipe->next_tx_frame < usb->frame_number)
2821 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2822 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2823 }
2824 } else if (usbc_hcint.s.bblerr) {
2825 /* Babble Error (BblErr) */
2826 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_BABBLEERR);
2827 } else if (usbc_hcint.s.datatglerr) {
2828 /* We'll retry the exact same transaction again */
2829 transaction->retries++;
2830 } else if (usbc_hcint.s.nyet) {
2831 /*
2832 * NYET as a response is only allowed in three cases: as a
2833 * response to a ping, as a response to a split transaction, and
2834 * as a response to a bulk out. The ping case is handled by
2835 * hardware, so we only have splits and bulk out
2836 */
2837 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
2838 transaction->retries = 0;
2839 /*
2840 * If there is more data to go then we need to try
2841 * again. Otherwise this transaction is complete
2842 */
2843 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet))
2844 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2845 } else {
2846 /*
2847 * Split transactions retry the split complete 4 times
2848 * then rewind to the start split and do the entire
2849 * transactions again
2850 */
2851 transaction->retries++;
2852 if ((transaction->retries & 0x3) == 0) {
2853 /*
2854 * Rewind to the beginning of the transaction by
2855 * anding off the split complete bit
2856 */
2857 transaction->stage &= ~1;
2858 pipe->split_sc_frame = -1;
2859 }
2860 }
2861 } else if (usbc_hcint.s.ack) {
2862 transaction->retries = 0;
2863 /*
2864 * The ACK bit can only be checked after the other error bits.
2865 * This is because a multi packet transfer may succeed in a
2866 * number of packets and then get a different response on the
2867 * last packet. In this case both ACK and the last response bit
2868 * will be set. If none of the other response bits is set, then
2869 * the last packet must have been an ACK
2870 *
2871 * Since we got an ACK, we know we don't need to do a ping on
2872 * this pipe
2873 */
2874 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_NEED_PING;
2875
2876 switch (transaction->type) {
2877 case CVMX_USB_TRANSFER_CONTROL:
2878 switch (transaction->stage) {
2879 case CVMX_USB_STAGE_NON_CONTROL:
2880 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
2881 /* This should be impossible */
2882 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
2883 break;
2884 case CVMX_USB_STAGE_SETUP:
2885 pipe->pid_toggle = 1;
2886 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2887 transaction->stage = CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE;
2888 else {
2889 union cvmx_usb_control_header *header =
2890 cvmx_phys_to_ptr(transaction->control_header);
2891 if (header->s.length)
2892 transaction->stage = CVMX_USB_STAGE_DATA;
2893 else
2894 transaction->stage = CVMX_USB_STAGE_STATUS;
2895 }
2896 break;
2897 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
2898 {
2899 union cvmx_usb_control_header *header =
2900 cvmx_phys_to_ptr(transaction->control_header);
2901 if (header->s.length)
2902 transaction->stage = CVMX_USB_STAGE_DATA;
2903 else
2904 transaction->stage = CVMX_USB_STAGE_STATUS;
2905 }
2906 break;
2907 case CVMX_USB_STAGE_DATA:
2908 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2909 transaction->stage = CVMX_USB_STAGE_DATA_SPLIT_COMPLETE;
2910 /*
2911 * For setup OUT data that are splits,
2912 * the hardware doesn't appear to count
2913 * transferred data. Here we manually
2914 * update the data transferred
2915 */
2916 if (!usbc_hcchar.s.epdir) {
2917 if (buffer_space_left < pipe->max_packet)
2918 transaction->actual_bytes += buffer_space_left;
2919 else
2920 transaction->actual_bytes += pipe->max_packet;
2921 }
2922 } else if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2923 pipe->pid_toggle = 1;
2924 transaction->stage = CVMX_USB_STAGE_STATUS;
2925 }
2926 break;
2927 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
2928 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2929 pipe->pid_toggle = 1;
2930 transaction->stage = CVMX_USB_STAGE_STATUS;
2931 } else {
2932 transaction->stage = CVMX_USB_STAGE_DATA;
2933 }
2934 break;
2935 case CVMX_USB_STAGE_STATUS:
2936 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2937 transaction->stage = CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE;
2938 else
2939 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2940 break;
2941 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
2942 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2943 break;
2944 }
2945 break;
2946 case CVMX_USB_TRANSFER_BULK:
2947 case CVMX_USB_TRANSFER_INTERRUPT:
2948 /*
2949 * The only time a bulk transfer isn't complete when it
2950 * finishes with an ACK is during a split transaction.
2951 * For splits we need to continue the transfer if more
2952 * data is needed
2953 */
2954 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2955 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL)
2956 transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2957 else {
2958 if (buffer_space_left && (bytes_in_last_packet == pipe->max_packet))
2959 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2960 else {
2961 if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
2962 pipe->next_tx_frame += pipe->interval;
2963 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2964 }
2965 }
2966 } else {
2967 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2968 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2969 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
2970 (usbc_hcint.s.nak))
2971 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2972 if (!buffer_space_left || (bytes_in_last_packet < pipe->max_packet)) {
2973 if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
2974 pipe->next_tx_frame += pipe->interval;
2975 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2976 }
2977 }
2978 break;
2979 case CVMX_USB_TRANSFER_ISOCHRONOUS:
2980 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2981 /*
2982 * ISOCHRONOUS OUT splits don't require a
2983 * complete split stage. Instead they use a
2984 * sequence of begin OUT splits to transfer the
2985 * data 188 bytes at a time. Once the transfer
2986 * is complete, the pipe sleeps until the next
2987 * schedule interval
2988 */
2989 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
2990 /*
2991 * If no space left or this wasn't a max
2992 * size packet then this transfer is
2993 * complete. Otherwise start it again to
2994 * send the next 188 bytes
2995 */
2996 if (!buffer_space_left || (bytes_this_transfer < 188)) {
2997 pipe->next_tx_frame += pipe->interval;
2998 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2999 }
3000 } else {
3001 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE) {
3002 /*
3003 * We are in the incoming data
3004 * phase. Keep getting data
3005 * until we run out of space or
3006 * get a small packet
3007 */
3008 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
3009 pipe->next_tx_frame += pipe->interval;
3010 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
3011 }
3012 } else
3013 transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
3014 }
3015 } else {
3016 pipe->next_tx_frame += pipe->interval;
3017 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
3018 }
3019 break;
3020 }
3021 } else if (usbc_hcint.s.nak) {
3022 /* If this was a split then clear our split in progress marker */
3023 if (usb->active_split == transaction)
3024 usb->active_split = NULL;
3025 /*
3026 * NAK as a response means the device couldn't accept the
3027 * transaction, but it should be retried in the future. Rewind
3028 * to the beginning of the transaction by anding off the split
3029 * complete bit. Retry in the next interval
3030 */
3031 transaction->retries = 0;
3032 transaction->stage &= ~1;
3033 pipe->next_tx_frame += pipe->interval;
3034 if (pipe->next_tx_frame < usb->frame_number)
3035 pipe->next_tx_frame = usb->frame_number + pipe->interval -
3036 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
3037 } else {
3038 struct cvmx_usb_port_status port;
3039 port = cvmx_usb_get_status((struct cvmx_usb_state *)usb);
3040 if (port.port_enabled) {
3041 /* We'll retry the exact same transaction again */
3042 transaction->retries++;
3043 } else {
3044 /*
3045 * We get channel halted interrupts with no result bits
3046 * sets when the cable is unplugged
3047 */
3048 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
3049 }
3050 }
3051 return 0;
3052 }
3053
3054
3055 /**
3056 * Poll the USB block for status and call all needed callback
3057 * handlers. This function is meant to be called in the interrupt
3058 * handler for the USB controller. It can also be called
3059 * periodically in a loop for non-interrupt based operation.
3060 *
3061 * @state: USB device state populated by
3062 * cvmx_usb_initialize().
3063 *
3064 * Returns: 0 or a negative error code.
3065 */
3066 int cvmx_usb_poll(struct cvmx_usb_state *state)
3067 {
3068 union cvmx_usbcx_hfnum usbc_hfnum;
3069 union cvmx_usbcx_gintsts usbc_gintsts;
3070 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
3071
3072 CVMX_PREFETCH(usb, 0);
3073 CVMX_PREFETCH(usb, 1*128);
3074 CVMX_PREFETCH(usb, 2*128);
3075 CVMX_PREFETCH(usb, 3*128);
3076 CVMX_PREFETCH(usb, 4*128);
3077
3078 /* Update the frame counter */
3079 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
3080 if ((usb->frame_number&0x3fff) > usbc_hfnum.s.frnum)
3081 usb->frame_number += 0x4000;
3082 usb->frame_number &= ~0x3fffull;
3083 usb->frame_number |= usbc_hfnum.s.frnum;
3084
3085 /* Read the pending interrupts */
3086 usbc_gintsts.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTSTS(usb->index));
3087
3088 /* Clear the interrupts now that we know about them */
3089 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), usbc_gintsts.u32);
3090
3091 if (usbc_gintsts.s.rxflvl) {
3092 /*
3093 * RxFIFO Non-Empty (RxFLvl)
3094 * Indicates that there is at least one packet pending to be
3095 * read from the RxFIFO.
3096 *
3097 * In DMA mode this is handled by hardware
3098 */
3099 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
3100 __cvmx_usb_poll_rx_fifo(usb);
3101 }
3102 if (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp) {
3103 /* Fill the Tx FIFOs when not in DMA mode */
3104 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
3105 __cvmx_usb_poll_tx_fifo(usb);
3106 }
3107 if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint) {
3108 union cvmx_usbcx_hprt usbc_hprt;
3109 /*
3110 * Disconnect Detected Interrupt (DisconnInt)
3111 * Asserted when a device disconnect is detected.
3112 *
3113 * Host Port Interrupt (PrtInt)
3114 * The core sets this bit to indicate a change in port status of
3115 * one of the O2P USB core ports in Host mode. The application
3116 * must read the Host Port Control and Status (HPRT) register to
3117 * determine the exact event that caused this interrupt. The
3118 * application must clear the appropriate status bit in the Host
3119 * Port Control and Status register to clear this bit.
3120 *
3121 * Call the user's port callback
3122 */
3123 __cvmx_usb_perform_callback(usb, NULL, NULL,
3124 CVMX_USB_CALLBACK_PORT_CHANGED,
3125 CVMX_USB_COMPLETE_SUCCESS);
3126 /* Clear the port change bits */
3127 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
3128 usbc_hprt.s.prtena = 0;
3129 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index), usbc_hprt.u32);
3130 }
3131 if (usbc_gintsts.s.hchint) {
3132 /*
3133 * Host Channels Interrupt (HChInt)
3134 * The core sets this bit to indicate that an interrupt is
3135 * pending on one of the channels of the core (in Host mode).
3136 * The application must read the Host All Channels Interrupt
3137 * (HAINT) register to determine the exact number of the channel
3138 * on which the interrupt occurred, and then read the
3139 * corresponding Host Channel-n Interrupt (HCINTn) register to
3140 * determine the exact cause of the interrupt. The application
3141 * must clear the appropriate status bit in the HCINTn register
3142 * to clear this bit.
3143 */
3144 union cvmx_usbcx_haint usbc_haint;
3145 usbc_haint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINT(usb->index));
3146 while (usbc_haint.u32) {
3147 int channel;
3148 CVMX_CLZ(channel, usbc_haint.u32);
3149 channel = 31 - channel;
3150 __cvmx_usb_poll_channel(usb, channel);
3151 usbc_haint.u32 ^= 1<<channel;
3152 }
3153 }
3154
3155 __cvmx_usb_schedule(usb, usbc_gintsts.s.sof);
3156
3157 return 0;
3158 }