]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blob - drivers/staging/pi433/rf69.c
projects / mirror_ubuntu-focal-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ASoC: tlv320aic31xx: Reset registers during power up
[mirror_ubuntu-focal-kernel.git] / drivers / staging / pi433 / rf69.c
1 /*
2 * abstraction of the spi interface of HopeRf rf69 radio module
3 *
4 * Copyright (C) 2016 Wolf-Entwicklungen
5 * Marcus Wolf <linux@wolf-entwicklungen.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 /* enable prosa debug info */
19 #undef DEBUG
20 /* enable print of values on reg access */
21 #undef DEBUG_VALUES
22 /* enable print of values on fifo access */
23 #undef DEBUG_FIFO_ACCESS
24
25 #include <linux/types.h>
26 #include <linux/spi/spi.h>
27
28 #include "rf69.h"
29 #include "rf69_registers.h"
30
31 #define F_OSC 32000000 /* in Hz */
32 #define FIFO_SIZE 66 /* in byte */
33
34 /*-------------------------------------------------------------------------*/
35
36 #define READ_REG(x) rf69_read_reg (spi, x)
37 #define WRITE_REG(x, y) rf69_write_reg(spi, x, y)
38
39 /*-------------------------------------------------------------------------*/
40
41 int rf69_set_mode(struct spi_device *spi, enum mode mode)
42 {
43 #ifdef DEBUG
44 dev_dbg(&spi->dev, "set: mode");
45 #endif
46
47 switch (mode) {
48 case transmit: return WRITE_REG(REG_OPMODE, (READ_REG(REG_OPMODE) & ~MASK_OPMODE_MODE) | OPMODE_MODE_TRANSMIT);
49 case receive: return WRITE_REG(REG_OPMODE, (READ_REG(REG_OPMODE) & ~MASK_OPMODE_MODE) | OPMODE_MODE_RECEIVE);
50 case synthesizer: return WRITE_REG(REG_OPMODE, (READ_REG(REG_OPMODE) & ~MASK_OPMODE_MODE) | OPMODE_MODE_SYNTHESIZER);
51 case standby: return WRITE_REG(REG_OPMODE, (READ_REG(REG_OPMODE) & ~MASK_OPMODE_MODE) | OPMODE_MODE_STANDBY);
52 case mode_sleep: return WRITE_REG(REG_OPMODE, (READ_REG(REG_OPMODE) & ~MASK_OPMODE_MODE) | OPMODE_MODE_SLEEP);
53 default:
54 dev_dbg(&spi->dev, "set: illegal input param");
55 return -EINVAL;
56 }
57
58 // we are using packet mode, so this check is not really needed
59 // but waiting for mode ready is necessary when going from sleep because the FIFO may not be immediately available from previous mode
60 //while (_mode == RF69_MODE_SLEEP && (READ_REG(REG_IRQFLAGS1) & RF_IRQFLAGS1_MODEREADY) == 0x00); // Wait for ModeReady
61
62 }
63
64 int rf69_set_data_mode(struct spi_device *spi, enum dataMode dataMode)
65 {
66 #ifdef DEBUG
67 dev_dbg(&spi->dev, "set: data mode");
68 #endif
69
70 switch (dataMode) {
71 case packet: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODE) | DATAMODUL_MODE_PACKET);
72 case continuous: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODE) | DATAMODUL_MODE_CONTINUOUS);
73 case continuousNoSync: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODE) | DATAMODUL_MODE_CONTINUOUS_NOSYNC);
74 default:
75 dev_dbg(&spi->dev, "set: illegal input param");
76 return -EINVAL;
77 }
78 }
79
80 int rf69_set_modulation(struct spi_device *spi, enum modulation modulation)
81 {
82 #ifdef DEBUG
83 dev_dbg(&spi->dev, "set: modulation");
84 #endif
85
86 switch (modulation) {
87 case OOK: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_TYPE) | DATAMODUL_MODULATION_TYPE_OOK);
88 case FSK: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_TYPE) | DATAMODUL_MODULATION_TYPE_FSK);
89 default:
90 dev_dbg(&spi->dev, "set: illegal input param");
91 return -EINVAL;
92 }
93 }
94
95 enum modulation rf69_get_modulation(struct spi_device *spi)
96 {
97 u8 currentValue;
98
99 #ifdef DEBUG
100 dev_dbg(&spi->dev, "get: mode");
101 #endif
102
103 currentValue = READ_REG(REG_DATAMODUL);
104
105 switch (currentValue & MASK_DATAMODUL_MODULATION_TYPE >> 3) { // TODO improvement: change 3 to define
106 case DATAMODUL_MODULATION_TYPE_OOK: return OOK;
107 case DATAMODUL_MODULATION_TYPE_FSK: return FSK;
108 default: return undefined;
109 }
110 }
111
112 int rf69_set_modulation_shaping(struct spi_device *spi, enum modShaping modShaping)
113 {
114 #ifdef DEBUG
115 dev_dbg(&spi->dev, "set: mod shaping");
116 #endif
117
118 if (rf69_get_modulation(spi) == FSK) {
119 switch (modShaping) {
120 case shapingOff: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_SHAPE) | DATAMODUL_MODULATION_SHAPE_NONE);
121 case shaping1_0: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_SHAPE) | DATAMODUL_MODULATION_SHAPE_1_0);
122 case shaping0_5: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_SHAPE) | DATAMODUL_MODULATION_SHAPE_0_3);
123 case shaping0_3: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_SHAPE) | DATAMODUL_MODULATION_SHAPE_0_5);
124 default:
125 dev_dbg(&spi->dev, "set: illegal input param");
126 return -EINVAL;
127 }
128 } else {
129 switch (modShaping) {
130 case shapingOff: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_SHAPE) | DATAMODUL_MODULATION_SHAPE_NONE);
131 case shapingBR: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_SHAPE) | DATAMODUL_MODULATION_SHAPE_BR);
132 case shaping2BR: return WRITE_REG(REG_DATAMODUL, (READ_REG(REG_DATAMODUL) & ~MASK_DATAMODUL_MODULATION_SHAPE) | DATAMODUL_MODULATION_SHAPE_2BR);
133 default:
134 dev_dbg(&spi->dev, "set: illegal input param");
135 return -EINVAL;
136 }
137 }
138 }
139
140 int rf69_set_bit_rate(struct spi_device *spi, u16 bitRate)
141 {
142 int retval;
143 u32 bitRate_min;
144 u32 bitRate_reg;
145 u8 msb;
146 u8 lsb;
147
148 #ifdef DEBUG
149 dev_dbg(&spi->dev, "set: bit rate");
150 #endif
151
152 // check input value
153 bitRate_min = F_OSC / 8388608; // 8388608 = 2^23;
154 if (bitRate < bitRate_min) {
155 dev_dbg(&spi->dev, "setBitRate: illegal input param");
156 return -EINVAL;
157 }
158
159 // calculate reg settings
160 bitRate_reg = (F_OSC / bitRate);
161
162 msb = (bitRate_reg&0xff00) >> 8;
163 lsb = (bitRate_reg&0xff);
164
165 // transmit to RF 69
166 retval = WRITE_REG(REG_BITRATE_MSB, msb);
167 if (retval)
168 return retval;
169
170 retval = WRITE_REG(REG_BITRATE_LSB, lsb);
171 if (retval)
172 return retval;
173
174 return 0;
175 }
176
177 int rf69_set_deviation(struct spi_device *spi, u32 deviation)
178 {
179 int retval;
180 // u32 f_max; TODO: Abhängigkeit von Bitrate beachten!!
181 u64 f_reg;
182 u64 f_step;
183 u8 msb;
184 u8 lsb;
185 u64 factor = 1000000; // to improve precision of calculation
186
187 #ifdef DEBUG
188 dev_dbg(&spi->dev, "set: deviation");
189 #endif
190
191 if (deviation < 600 || deviation > 500000) { //TODO: Abhängigkeit von Bitrate beachten!!
192 dev_dbg(&spi->dev, "set_deviation: illegal input param");
193 return -EINVAL;
194 }
195
196 // calculat f step
197 f_step = F_OSC * factor;
198 do_div(f_step, 524288); // 524288 = 2^19
199
200 // calculate register settings
201 f_reg = deviation * factor;
202 do_div(f_reg, f_step);
203
204 msb = (f_reg&0xff00) >> 8;
205 lsb = (f_reg&0xff);
206
207 // check msb
208 if (msb & ~FDEVMASB_MASK) {
209 dev_dbg(&spi->dev, "set_deviation: err in calc of msb");
210 return -EINVAL;
211 }
212
213 // write to chip
214 retval = WRITE_REG(REG_FDEV_MSB, msb);
215 if (retval)
216 return retval;
217
218 retval = WRITE_REG(REG_FDEV_LSB, lsb);
219 if (retval)
220 return retval;
221
222 return 0;
223 }
224
225 int rf69_set_frequency(struct spi_device *spi, u32 frequency)
226 {
227 int retval;
228 u32 f_max;
229 u64 f_reg;
230 u64 f_step;
231 u8 msb;
232 u8 mid;
233 u8 lsb;
234 u64 factor = 1000000; // to improve precision of calculation
235
236 #ifdef DEBUG
237 dev_dbg(&spi->dev, "set: frequency");
238 #endif
239
240 // calculat f step
241 f_step = F_OSC * factor;
242 do_div(f_step, 524288); // 524288 = 2^19
243
244 // check input value
245 f_max = div_u64(f_step * 8388608, factor);
246 if (frequency > f_max) {
247 dev_dbg(&spi->dev, "setFrequency: illegal input param");
248 return -EINVAL;
249 }
250
251 // calculate reg settings
252 f_reg = frequency * factor;
253 do_div(f_reg, f_step);
254
255 msb = (f_reg&0xff0000) >> 16;
256 mid = (f_reg&0xff00) >> 8;
257 lsb = (f_reg&0xff);
258
259 // write to chip
260 retval = WRITE_REG(REG_FRF_MSB, msb);
261 if (retval)
262 return retval;
263
264 retval = WRITE_REG(REG_FRF_MID, mid);
265 if (retval)
266 return retval;
267
268 retval = WRITE_REG(REG_FRF_LSB, lsb);
269 if (retval)
270 return retval;
271
272 return 0;
273 }
274
275 int rf69_set_amplifier_0(struct spi_device *spi, enum optionOnOff optionOnOff)
276 {
277 #ifdef DEBUG
278 dev_dbg(&spi->dev, "set: amp #0");
279 #endif
280
281 switch (optionOnOff) {
282 case optionOn: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) | MASK_PALEVEL_PA0));
283 case optionOff: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) & ~MASK_PALEVEL_PA0));
284 default:
285 dev_dbg(&spi->dev, "set: illegal input param");
286 return -EINVAL;
287 }
288 }
289
290 int rf69_set_amplifier_1(struct spi_device *spi, enum optionOnOff optionOnOff)
291 {
292 #ifdef DEBUG
293 dev_dbg(&spi->dev, "set: amp #1");
294 #endif
295
296 switch (optionOnOff) {
297 case optionOn: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) | MASK_PALEVEL_PA1));
298 case optionOff: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) & ~MASK_PALEVEL_PA1));
299 default:
300 dev_dbg(&spi->dev, "set: illegal input param");
301 return -EINVAL;
302 }
303 }
304
305 int rf69_set_amplifier_2(struct spi_device *spi, enum optionOnOff optionOnOff)
306 {
307 #ifdef DEBUG
308 dev_dbg(&spi->dev, "set: amp #2");
309 #endif
310
311 switch (optionOnOff) {
312 case optionOn: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) | MASK_PALEVEL_PA2));
313 case optionOff: return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) & ~MASK_PALEVEL_PA2));
314 default:
315 dev_dbg(&spi->dev, "set: illegal input param");
316 return -EINVAL;
317 }
318 }
319
320 int rf69_set_output_power_level(struct spi_device *spi, u8 powerLevel)
321 {
322 #ifdef DEBUG
323 dev_dbg(&spi->dev, "set: power level");
324 #endif
325
326 powerLevel += 18; // TODO Abhängigkeit von PA0,1,2 setting
327
328 // check input value
329 if (powerLevel > 0x1f) {
330 dev_dbg(&spi->dev, "set: illegal input param");
331 return -EINVAL;
332 }
333
334 // write value
335 return WRITE_REG(REG_PALEVEL, (READ_REG(REG_PALEVEL) & ~MASK_PALEVEL_OUTPUT_POWER) | powerLevel);
336 }
337
338 int rf69_set_pa_ramp(struct spi_device *spi, enum paRamp paRamp)
339 {
340 #ifdef DEBUG
341 dev_dbg(&spi->dev, "set: pa ramp");
342 #endif
343
344 switch (paRamp) {
345 case ramp3400: return WRITE_REG(REG_PARAMP, PARAMP_3400);
346 case ramp2000: return WRITE_REG(REG_PARAMP, PARAMP_2000);
347 case ramp1000: return WRITE_REG(REG_PARAMP, PARAMP_1000);
348 case ramp500: return WRITE_REG(REG_PARAMP, PARAMP_500);
349 case ramp250: return WRITE_REG(REG_PARAMP, PARAMP_250);
350 case ramp125: return WRITE_REG(REG_PARAMP, PARAMP_125);
351 case ramp100: return WRITE_REG(REG_PARAMP, PARAMP_100);
352 case ramp62: return WRITE_REG(REG_PARAMP, PARAMP_62);
353 case ramp50: return WRITE_REG(REG_PARAMP, PARAMP_50);
354 case ramp40: return WRITE_REG(REG_PARAMP, PARAMP_40);
355 case ramp31: return WRITE_REG(REG_PARAMP, PARAMP_31);
356 case ramp25: return WRITE_REG(REG_PARAMP, PARAMP_25);
357 case ramp20: return WRITE_REG(REG_PARAMP, PARAMP_20);
358 case ramp15: return WRITE_REG(REG_PARAMP, PARAMP_15);
359 case ramp12: return WRITE_REG(REG_PARAMP, PARAMP_12);
360 case ramp10: return WRITE_REG(REG_PARAMP, PARAMP_10);
361 default:
362 dev_dbg(&spi->dev, "set: illegal input param");
363 return -EINVAL;
364 }
365 }
366
367 int rf69_set_antenna_impedance(struct spi_device *spi, enum antennaImpedance antennaImpedance)
368 {
369 #ifdef DEBUG
370 dev_dbg(&spi->dev, "set: antenna impedance");
371 #endif
372
373 switch (antennaImpedance) {
374 case fiftyOhm: return WRITE_REG(REG_LNA, (READ_REG(REG_LNA) & ~MASK_LNA_ZIN));
375 case twohundretOhm: return WRITE_REG(REG_LNA, (READ_REG(REG_LNA) | MASK_LNA_ZIN));
376 default:
377 dev_dbg(&spi->dev, "set: illegal input param");
378 return -EINVAL;
379 }
380 }
381
382 int rf69_set_lna_gain(struct spi_device *spi, enum lnaGain lnaGain)
383 {
384 #ifdef DEBUG
385 dev_dbg(&spi->dev, "set: lna gain");
386 #endif
387
388 switch (lnaGain) {
389 case automatic: return WRITE_REG(REG_LNA, ((READ_REG(REG_LNA) & ~MASK_LNA_GAIN) & LNA_GAIN_AUTO));
390 case max: return WRITE_REG(REG_LNA, ((READ_REG(REG_LNA) & ~MASK_LNA_GAIN) & LNA_GAIN_MAX));
391 case maxMinus6: return WRITE_REG(REG_LNA, ((READ_REG(REG_LNA) & ~MASK_LNA_GAIN) & LNA_GAIN_MAX_MINUS_6));
392 case maxMinus12: return WRITE_REG(REG_LNA, ((READ_REG(REG_LNA) & ~MASK_LNA_GAIN) & LNA_GAIN_MAX_MINUS_12));
393 case maxMinus24: return WRITE_REG(REG_LNA, ((READ_REG(REG_LNA) & ~MASK_LNA_GAIN) & LNA_GAIN_MAX_MINUS_24));
394 case maxMinus36: return WRITE_REG(REG_LNA, ((READ_REG(REG_LNA) & ~MASK_LNA_GAIN) & LNA_GAIN_MAX_MINUS_36));
395 case maxMinus48: return WRITE_REG(REG_LNA, ((READ_REG(REG_LNA) & ~MASK_LNA_GAIN) & LNA_GAIN_MAX_MINUS_48));
396 default:
397 dev_dbg(&spi->dev, "set: illegal input param");
398 return -EINVAL;
399 }
400 }
401
402 enum lnaGain rf69_get_lna_gain(struct spi_device *spi)
403 {
404 u8 currentValue;
405
406 #ifdef DEBUG
407 dev_dbg(&spi->dev, "get: lna gain");
408 #endif
409
410 currentValue = READ_REG(REG_LNA);
411
412 switch (currentValue & MASK_LNA_CURRENT_GAIN >> 3) { // improvement: change 3 to define
413 case LNA_GAIN_AUTO: return automatic;
414 case LNA_GAIN_MAX: return max;
415 case LNA_GAIN_MAX_MINUS_6: return maxMinus6;
416 case LNA_GAIN_MAX_MINUS_12: return maxMinus12;
417 case LNA_GAIN_MAX_MINUS_24: return maxMinus24;
418 case LNA_GAIN_MAX_MINUS_36: return maxMinus36;
419 case LNA_GAIN_MAX_MINUS_48: return maxMinus48;
420 default: return undefined;
421 }
422 }
423
424 int rf69_set_dc_cut_off_frequency_intern(struct spi_device *spi, u8 reg, enum dccPercent dccPercent)
425 {
426 switch (dccPercent) {
427 case dcc16Percent: return WRITE_REG(reg, ((READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_16_PERCENT));
428 case dcc8Percent: return WRITE_REG(reg, ((READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_8_PERCENT));
429 case dcc4Percent: return WRITE_REG(reg, ((READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_4_PERCENT));
430 case dcc2Percent: return WRITE_REG(reg, ((READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_2_PERCENT));
431 case dcc1Percent: return WRITE_REG(reg, ((READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_1_PERCENT));
432 case dcc0_5Percent: return WRITE_REG(reg, ((READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_0_5_PERCENT));
433 case dcc0_25Percent: return WRITE_REG(reg, ((READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_0_25_PERCENT));
434 case dcc0_125Percent: return WRITE_REG(reg, ((READ_REG(reg) & ~MASK_BW_DCC_FREQ) | BW_DCC_0_125_PERCENT));
435 default:
436 dev_dbg(&spi->dev, "set: illegal input param");
437 return -EINVAL;
438 }
439 }
440
441 int rf69_set_dc_cut_off_frequency(struct spi_device *spi, enum dccPercent dccPercent)
442 {
443 #ifdef DEBUG
444 dev_dbg(&spi->dev, "set: cut off freq");
445 #endif
446
447 return rf69_set_dc_cut_off_frequency_intern(spi, REG_RXBW, dccPercent);
448 }
449
450 int rf69_set_dc_cut_off_frequency_during_afc(struct spi_device *spi, enum dccPercent dccPercent)
451 {
452 #ifdef DEBUG
453 dev_dbg(&spi->dev, "set: cut off freq during afc");
454 #endif
455
456 return rf69_set_dc_cut_off_frequency_intern(spi, REG_AFCBW, dccPercent);
457 }
458
459 static int rf69_set_bandwidth_intern(struct spi_device *spi, u8 reg,
460 enum mantisse mantisse, u8 exponent)
461 {
462 u8 newValue;
463
464 // check value for mantisse and exponent
465 if (exponent > 7) {
466 dev_dbg(&spi->dev, "set: illegal input param");
467 return -EINVAL;
468 }
469
470 if ((mantisse != mantisse16) &&
471 (mantisse != mantisse20) &&
472 (mantisse != mantisse24)) {
473 dev_dbg(&spi->dev, "set: illegal input param");
474 return -EINVAL;
475 }
476
477 // read old value
478 newValue = READ_REG(reg);
479
480 // "delete" mantisse and exponent = just keep the DCC setting
481 newValue = newValue & MASK_BW_DCC_FREQ;
482
483 // add new mantisse
484 switch (mantisse) {
485 case mantisse16:
486 newValue = newValue | BW_MANT_16;
487 break;
488 case mantisse20:
489 newValue = newValue | BW_MANT_20;
490 break;
491 case mantisse24:
492 newValue = newValue | BW_MANT_24;
493 break;
494 }
495
496 // add new exponent
497 newValue = newValue | exponent;
498
499 // write back
500 return WRITE_REG(reg, newValue);
501 }
502
503 int rf69_set_bandwidth(struct spi_device *spi, enum mantisse mantisse, u8 exponent)
504 {
505 #ifdef DEBUG
506 dev_dbg(&spi->dev, "set: band width");
507 #endif
508
509 return rf69_set_bandwidth_intern(spi, REG_RXBW, mantisse, exponent);
510 }
511
512 int rf69_set_bandwidth_during_afc(struct spi_device *spi, enum mantisse mantisse, u8 exponent)
513 {
514 #ifdef DEBUG
515 dev_dbg(&spi->dev, "set: band width during afc");
516 #endif
517
518 return rf69_set_bandwidth_intern(spi, REG_AFCBW, mantisse, exponent);
519 }
520
521 int rf69_set_ook_threshold_type(struct spi_device *spi, enum thresholdType thresholdType)
522 {
523 #ifdef DEBUG
524 dev_dbg(&spi->dev, "set: threshold type");
525 #endif
526
527 switch (thresholdType) {
528 case fixed: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESTYPE) | OOKPEAK_THRESHTYPE_FIXED));
529 case peak: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESTYPE) | OOKPEAK_THRESHTYPE_PEAK));
530 case average: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESTYPE) | OOKPEAK_THRESHTYPE_AVERAGE));
531 default:
532 dev_dbg(&spi->dev, "set: illegal input param");
533 return -EINVAL;
534 }
535 }
536
537 int rf69_set_ook_threshold_step(struct spi_device *spi, enum thresholdStep thresholdStep)
538 {
539 #ifdef DEBUG
540 dev_dbg(&spi->dev, "set: threshold step");
541 #endif
542
543 switch (thresholdStep) {
544 case step_0_5db: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_0_5_DB));
545 case step_1_0db: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_1_0_DB));
546 case step_1_5db: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_1_5_DB));
547 case step_2_0db: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_2_0_DB));
548 case step_3_0db: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_3_0_DB));
549 case step_4_0db: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_4_0_DB));
550 case step_5_0db: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_5_0_DB));
551 case step_6_0db: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESSTEP) | OOKPEAK_THRESHSTEP_6_0_DB));
552 default:
553 dev_dbg(&spi->dev, "set: illegal input param");
554 return -EINVAL;
555 }
556 }
557
558 int rf69_set_ook_threshold_dec(struct spi_device *spi, enum thresholdDecrement thresholdDecrement)
559 {
560 #ifdef DEBUG
561 dev_dbg(&spi->dev, "set: threshold decrement");
562 #endif
563
564 switch (thresholdDecrement) {
565 case dec_every8th: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_EVERY_8TH));
566 case dec_every4th: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_EVERY_4TH));
567 case dec_every2nd: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_EVERY_2ND));
568 case dec_once: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_ONCE));
569 case dec_twice: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_TWICE));
570 case dec_4times: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_4_TIMES));
571 case dec_8times: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_8_TIMES));
572 case dec_16times: return WRITE_REG(REG_OOKPEAK, ((READ_REG(REG_OOKPEAK) & ~MASK_OOKPEAK_THRESDEC) | OOKPEAK_THRESHDEC_16_TIMES));
573 default:
574 dev_dbg(&spi->dev, "set: illegal input param");
575 return -EINVAL;
576 }
577 }
578
579 int rf69_set_dio_mapping(struct spi_device *spi, u8 DIONumber, u8 value)
580 {
581 u8 mask;
582 u8 shift;
583 u8 regaddr;
584 u8 regValue;
585
586 #ifdef DEBUG
587 dev_dbg(&spi->dev, "set: DIO mapping");
588 #endif
589
590 switch (DIONumber) {
591 case 0:
592 mask = MASK_DIO0; shift = SHIFT_DIO0; regaddr = REG_DIOMAPPING1;
593 break;
594 case 1:
595 mask = MASK_DIO1; shift = SHIFT_DIO1; regaddr = REG_DIOMAPPING1;
596 break;
597 case 2:
598 mask = MASK_DIO2; shift = SHIFT_DIO2; regaddr = REG_DIOMAPPING1;
599 break;
600 case 3:
601 mask = MASK_DIO3; shift = SHIFT_DIO3; regaddr = REG_DIOMAPPING1;
602 break;
603 case 4:
604 mask = MASK_DIO4; shift = SHIFT_DIO4; regaddr = REG_DIOMAPPING2;
605 break;
606 case 5:
607 mask = MASK_DIO5; shift = SHIFT_DIO5; regaddr = REG_DIOMAPPING2;
608 break;
609 default:
610 dev_dbg(&spi->dev, "set: illegal input param");
611 return -EINVAL;
612 }
613
614 // read reg
615 regValue = READ_REG(regaddr);
616 // delete old value
617 regValue = regValue & ~mask;
618 // add new value
619 regValue = regValue | value << shift;
620 // write back
621 return WRITE_REG(regaddr, regValue);
622 }
623
624 bool rf69_get_flag(struct spi_device *spi, enum flag flag)
625 {
626 #ifdef DEBUG
627 dev_dbg(&spi->dev, "get: flag");
628 #endif
629
630 switch (flag) {
631 case modeSwitchCompleted: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_MODE_READY);
632 case readyToReceive: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_RX_READY);
633 case readyToSend: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_TX_READY);
634 case pllLocked: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_PLL_LOCK);
635 case rssiExceededThreshold: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_RSSI);
636 case timeout: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_TIMEOUT);
637 case automode: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_AUTOMODE);
638 case syncAddressMatch: return (READ_REG(REG_IRQFLAGS1) & MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH);
639 case fifoFull: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_FULL);
640 /* case fifoNotEmpty: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_NOT_EMPTY); */
641 case fifoEmpty: return !(READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_NOT_EMPTY);
642 case fifoLevelBelowThreshold: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_LEVEL);
643 case fifoOverrun: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_OVERRUN);
644 case packetSent: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_PACKET_SENT);
645 case payloadReady: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_PAYLOAD_READY);
646 case crcOk: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_CRC_OK);
647 case batteryLow: return (READ_REG(REG_IRQFLAGS2) & MASK_IRQFLAGS2_LOW_BAT);
648 default: return false;
649 }
650 }
651
652 int rf69_reset_flag(struct spi_device *spi, enum flag flag)
653 {
654 #ifdef DEBUG
655 dev_dbg(&spi->dev, "reset: flag");
656 #endif
657
658 switch (flag) {
659 case rssiExceededThreshold: return WRITE_REG(REG_IRQFLAGS1, MASK_IRQFLAGS1_RSSI);
660 case syncAddressMatch: return WRITE_REG(REG_IRQFLAGS1, MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH);
661 case fifoOverrun: return WRITE_REG(REG_IRQFLAGS2, MASK_IRQFLAGS2_FIFO_OVERRUN);
662 default:
663 dev_dbg(&spi->dev, "set: illegal input param");
664 return -EINVAL;
665 }
666 }
667
668 int rf69_set_rssi_threshold(struct spi_device *spi, u8 threshold)
669 {
670 #ifdef DEBUG
671 dev_dbg(&spi->dev, "set: rssi threshold");
672 #endif
673
674 /* no value check needed - u8 exactly matches register size */
675
676 return WRITE_REG(REG_RSSITHRESH, threshold);
677 }
678
679 int rf69_set_rx_start_timeout(struct spi_device *spi, u8 timeout)
680 {
681 #ifdef DEBUG
682 dev_dbg(&spi->dev, "set: start timeout");
683 #endif
684
685 /* no value check needed - u8 exactly matches register size */
686
687 return WRITE_REG(REG_RXTIMEOUT1, timeout);
688 }
689
690 int rf69_set_rssi_timeout(struct spi_device *spi, u8 timeout)
691 {
692 #ifdef DEBUG
693 dev_dbg(&spi->dev, "set: rssi timeout");
694 #endif
695
696 /* no value check needed - u8 exactly matches register size */
697
698 return WRITE_REG(REG_RXTIMEOUT2, timeout);
699 }
700
701 int rf69_set_preamble_length(struct spi_device *spi, u16 preambleLength)
702 {
703 int retval;
704 u8 msb, lsb;
705
706 #ifdef DEBUG
707 dev_dbg(&spi->dev, "set: preamble length");
708 #endif
709
710 /* no value check needed - u16 exactly matches register size */
711
712 /* calculate reg settings */
713 msb = (preambleLength&0xff00) >> 8;
714 lsb = (preambleLength&0xff);
715
716 /* transmit to chip */
717 retval = WRITE_REG(REG_PREAMBLE_MSB, msb);
718 if (retval)
719 return retval;
720 return WRITE_REG(REG_PREAMBLE_LSB, lsb);
721 }
722
723 int rf69_set_sync_enable(struct spi_device *spi, enum optionOnOff optionOnOff)
724 {
725 #ifdef DEBUG
726 dev_dbg(&spi->dev, "set: sync enable");
727 #endif
728
729 switch (optionOnOff) {
730 case optionOn: return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) | MASK_SYNC_CONFIG_SYNC_ON));
731 case optionOff: return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) & ~MASK_SYNC_CONFIG_SYNC_ON));
732 default:
733 dev_dbg(&spi->dev, "set: illegal input param");
734 return -EINVAL;
735 }
736 }
737
738 int rf69_set_fifo_fill_condition(struct spi_device *spi, enum fifoFillCondition fifoFillCondition)
739 {
740 #ifdef DEBUG
741 dev_dbg(&spi->dev, "set: fifo fill condition");
742 #endif
743
744 switch (fifoFillCondition) {
745 case always: return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) | MASK_SYNC_CONFIG_FIFO_FILL_CONDITION));
746 case afterSyncInterrupt: return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) & ~MASK_SYNC_CONFIG_FIFO_FILL_CONDITION));
747 default:
748 dev_dbg(&spi->dev, "set: illegal input param");
749 return -EINVAL;
750 }
751 }
752
753 int rf69_set_sync_size(struct spi_device *spi, u8 syncSize)
754 {
755 #ifdef DEBUG
756 dev_dbg(&spi->dev, "set: sync size");
757 #endif
758
759 // check input value
760 if (syncSize > 0x07) {
761 dev_dbg(&spi->dev, "set: illegal input param");
762 return -EINVAL;
763 }
764
765 // write value
766 return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) & ~MASK_SYNC_CONFIG_SYNC_SIZE) | (syncSize << 3));
767 }
768
769 int rf69_set_sync_tolerance(struct spi_device *spi, u8 syncTolerance)
770 {
771 #ifdef DEBUG
772 dev_dbg(&spi->dev, "set: sync tolerance");
773 #endif
774
775 // check input value
776 if (syncTolerance > 0x07) {
777 dev_dbg(&spi->dev, "set: illegal input param");
778 return -EINVAL;
779 }
780
781 // write value
782 return WRITE_REG(REG_SYNC_CONFIG, (READ_REG(REG_SYNC_CONFIG) & ~MASK_SYNC_CONFIG_SYNC_SIZE) | syncTolerance);
783 }
784
785 int rf69_set_sync_values(struct spi_device *spi, u8 syncValues[8])
786 {
787 int retval = 0;
788
789 #ifdef DEBUG
790 dev_dbg(&spi->dev, "set: sync values");
791 #endif
792
793 retval += WRITE_REG(REG_SYNCVALUE1, syncValues[0]);
794 retval += WRITE_REG(REG_SYNCVALUE2, syncValues[1]);
795 retval += WRITE_REG(REG_SYNCVALUE3, syncValues[2]);
796 retval += WRITE_REG(REG_SYNCVALUE4, syncValues[3]);
797 retval += WRITE_REG(REG_SYNCVALUE5, syncValues[4]);
798 retval += WRITE_REG(REG_SYNCVALUE6, syncValues[5]);
799 retval += WRITE_REG(REG_SYNCVALUE7, syncValues[6]);
800 retval += WRITE_REG(REG_SYNCVALUE8, syncValues[7]);
801
802 return retval;
803 }
804
805 int rf69_set_packet_format(struct spi_device *spi, enum packetFormat packetFormat)
806 {
807 #ifdef DEBUG
808 dev_dbg(&spi->dev, "set: packet format");
809 #endif
810
811 switch (packetFormat) {
812 case packetLengthVar: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) | MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE));
813 case packetLengthFix: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE));
814 default:
815 dev_dbg(&spi->dev, "set: illegal input param");
816 return -EINVAL;
817 }
818 }
819
820 int rf69_set_crc_enable(struct spi_device *spi, enum optionOnOff optionOnOff)
821 {
822 #ifdef DEBUG
823 dev_dbg(&spi->dev, "set: crc enable");
824 #endif
825
826 switch (optionOnOff) {
827 case optionOn: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) | MASK_PACKETCONFIG1_CRC_ON));
828 case optionOff: return WRITE_REG(REG_PACKETCONFIG1, (READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_CRC_ON));
829 default:
830 dev_dbg(&spi->dev, "set: illegal input param");
831 return -EINVAL;
832 }
833 }
834
835 int rf69_set_adressFiltering(struct spi_device *spi, enum addressFiltering addressFiltering)
836 {
837 #ifdef DEBUG
838 dev_dbg(&spi->dev, "set: address filtering");
839 #endif
840
841 switch (addressFiltering) {
842 case filteringOff: return WRITE_REG(REG_PACKETCONFIG1, ((READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_ADDRESSFILTERING) | PACKETCONFIG1_ADDRESSFILTERING_OFF));
843 case nodeAddress: return WRITE_REG(REG_PACKETCONFIG1, ((READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_ADDRESSFILTERING) | PACKETCONFIG1_ADDRESSFILTERING_NODE));
844 case nodeOrBroadcastAddress: return WRITE_REG(REG_PACKETCONFIG1, ((READ_REG(REG_PACKETCONFIG1) & ~MASK_PACKETCONFIG1_ADDRESSFILTERING) | PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST));
845 default:
846 dev_dbg(&spi->dev, "set: illegal input param");
847 return -EINVAL;
848 }
849 }
850
851 int rf69_set_payload_length(struct spi_device *spi, u8 payloadLength)
852 {
853 #ifdef DEBUG
854 dev_dbg(&spi->dev, "set: payload length");
855 #endif
856
857 return WRITE_REG(REG_PAYLOAD_LENGTH, payloadLength);
858 }
859
860 u8 rf69_get_payload_length(struct spi_device *spi)
861 {
862 #ifdef DEBUG
863 dev_dbg(&spi->dev, "get: payload length");
864 #endif
865
866 return (u8) READ_REG(REG_PAYLOAD_LENGTH);
867 }
868
869 int rf69_set_node_address(struct spi_device *spi, u8 nodeAddress)
870 {
871 #ifdef DEBUG
872 dev_dbg(&spi->dev, "set: node address");
873 #endif
874
875 return WRITE_REG(REG_NODEADRS, nodeAddress);
876 }
877
878 int rf69_set_broadcast_address(struct spi_device *spi, u8 broadcastAddress)
879 {
880 #ifdef DEBUG
881 dev_dbg(&spi->dev, "set: broadcast address");
882 #endif
883
884 return WRITE_REG(REG_BROADCASTADRS, broadcastAddress);
885 }
886
887 int rf69_set_tx_start_condition(struct spi_device *spi, enum txStartCondition txStartCondition)
888 {
889 #ifdef DEBUG
890 dev_dbg(&spi->dev, "set: start condition");
891 #endif
892
893 switch (txStartCondition) {
894 case fifoLevel: return WRITE_REG(REG_FIFO_THRESH, (READ_REG(REG_FIFO_THRESH) & ~MASK_FIFO_THRESH_TXSTART));
895 case fifoNotEmpty: return WRITE_REG(REG_FIFO_THRESH, (READ_REG(REG_FIFO_THRESH) | MASK_FIFO_THRESH_TXSTART));
896 default:
897 dev_dbg(&spi->dev, "set: illegal input param");
898 return -EINVAL;
899 }
900 }
901
902 int rf69_set_fifo_threshold(struct spi_device *spi, u8 threshold)
903 {
904 int retval;
905
906 #ifdef DEBUG
907 dev_dbg(&spi->dev, "set: fifo threshold");
908 #endif
909
910 // check input value
911 if (threshold & 0x80) {
912 dev_dbg(&spi->dev, "set: illegal input param");
913 return -EINVAL;
914 }
915
916 // write value
917 retval = WRITE_REG(REG_FIFO_THRESH, (READ_REG(REG_FIFO_THRESH) & ~MASK_FIFO_THRESH_VALUE) | threshold);
918 if (retval)
919 return retval;
920
921 // access the fifo to activate new threshold
922 return rf69_read_fifo(spi, (u8 *)&retval, 1); // retval used as buffer
923 }
924
925 int rf69_set_dagc(struct spi_device *spi, enum dagc dagc)
926 {
927 #ifdef DEBUG
928 dev_dbg(&spi->dev, "set: dagc");
929 #endif
930
931 switch (dagc) {
932 case normalMode: return WRITE_REG(REG_TESTDAGC, DAGC_NORMAL);
933 case improve: return WRITE_REG(REG_TESTDAGC, DAGC_IMPROVED_LOWBETA0);
934 case improve4LowModulationIndex: return WRITE_REG(REG_TESTDAGC, DAGC_IMPROVED_LOWBETA1);
935 default:
936 dev_dbg(&spi->dev, "set: illegal input param");
937 return -EINVAL;
938 }
939 }
940
941 /*-------------------------------------------------------------------------*/
942
943 int rf69_read_fifo (struct spi_device *spi, u8 *buffer, unsigned int size)
944 {
945 #ifdef DEBUG_FIFO_ACCESS
946 int i;
947 #endif
948 struct spi_transfer transfer;
949 u8 local_buffer[FIFO_SIZE + 1];
950 int retval;
951
952 if (size > FIFO_SIZE) {
953 #ifdef DEBUG
954 dev_dbg(&spi->dev, "read fifo: passed in buffer bigger then internal buffer \n");
955 #endif
956 return -EMSGSIZE;
957 }
958
959 /* prepare a bidirectional transfer */
960 local_buffer[0] = REG_FIFO;
961 memset(&transfer, 0, sizeof(transfer));
962 transfer.tx_buf = local_buffer;
963 transfer.rx_buf = local_buffer;
964 transfer.len = size+1;
965
966 retval = spi_sync_transfer(spi, &transfer, 1);
967
968 #ifdef DEBUG_FIFO_ACCESS
969 for (i = 0; i < size; i++)
970 dev_dbg(&spi->dev, "%d - 0x%x\n", i, local_buffer[i+1]);
971 #endif
972
973 memcpy(buffer, &local_buffer[1], size); // TODO: ohne memcopy wäre schöner
974
975 return retval;
976 }
977
978 int rf69_write_fifo(struct spi_device *spi, u8 *buffer, unsigned int size)
979 {
980 #ifdef DEBUG_FIFO_ACCESS
981 int i;
982 #endif
983 char spi_address = REG_FIFO | WRITE_BIT;
984 u8 local_buffer[FIFO_SIZE + 1];
985
986 if (size > FIFO_SIZE) {
987 #ifdef DEBUG
988 dev_dbg(&spi->dev, "read fifo: passed in buffer bigger then internal buffer \n");
989 #endif
990 return -EMSGSIZE;
991 }
992
993 local_buffer[0] = spi_address;
994 memcpy(&local_buffer[1], buffer, size); // TODO: ohne memcopy wäre schöner
995
996 #ifdef DEBUG_FIFO_ACCESS
997 for (i = 0; i < size; i++)
998 dev_dbg(&spi->dev, "0x%x\n", buffer[i]);
999 #endif
1000
1001 return spi_write (spi, local_buffer, size + 1);
1002 }
1003
1004 /*-------------------------------------------------------------------------*/
1005
1006 u8 rf69_read_reg(struct spi_device *spi, u8 addr)
1007 {
1008 int retval;
1009
1010 retval = spi_w8r8(spi, addr);
1011
1012 #ifdef DEBUG_VALUES
1013 if (retval < 0)
1014 /* should never happen, since we already checked,
1015 * that module is connected. Therefore no error
1016 * handling, just an optional error message...
1017 */
1018 dev_dbg(&spi->dev, "read 0x%x FAILED\n",
1019 addr);
1020 else
1021 dev_dbg(&spi->dev, "read 0x%x from reg 0x%x\n",
1022 retval,
1023 addr);
1024 #endif
1025
1026 return retval;
1027 }
1028
1029 int rf69_write_reg(struct spi_device *spi, u8 addr, u8 value)
1030 {
1031 int retval;
1032 char buffer[2];
1033
1034 buffer[0] = addr | WRITE_BIT;
1035 buffer[1] = value;
1036
1037 retval = spi_write(spi, &buffer, 2);
1038
1039 #ifdef DEBUG_VALUES
1040 if (retval < 0)
1041 /* should never happen, since we already checked,
1042 * that module is connected. Therefore no error
1043 * handling, just an optional error message...
1044 */
1045 dev_dbg(&spi->dev, "write 0x%x to 0x%x FAILED\n",
1046 value,
1047 addr);
1048 else
1049 dev_dbg(&spi->dev, "wrote 0x%x to reg 0x%x\n",
1050 value,
1051 addr);
1052 #endif
1053
1054 return retval;
1055 }
1056
1057
Ubuntu Focal Linux kernel mirror