3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2015 Intel Corporation.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
21 * Copyright(c) 2015 Intel Corporation.
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
27 * - Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * - Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in
31 * the documentation and/or other materials provided with the
33 * - Neither the name of Intel Corporation nor the names of its
34 * contributors may be used to endorse or promote products derived
35 * from this software without specific prior written permission.
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 #include <linux/pci.h>
52 #include <linux/netdevice.h>
53 #include <linux/vmalloc.h>
54 #include <linux/delay.h>
55 #include <linux/idr.h>
56 #include <linux/module.h>
57 #include <linux/printk.h>
58 #include <linux/hrtimer.h>
70 #define pr_fmt(fmt) DRIVER_NAME ": " fmt
73 * min buffers we want to have per context, after driver
75 #define HFI1_MIN_USER_CTXT_BUFCNT 7
77 #define HFI1_MIN_HDRQ_EGRBUF_CNT 2
78 #define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024) /* 4KB */
79 #define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024) /* 256KB */
82 * Number of user receive contexts we are configured to use (to allow for more
83 * pio buffers per ctxt, etc.) Zero means use one user context per CPU.
85 int num_user_contexts
= -1;
86 module_param_named(num_user_contexts
, num_user_contexts
, uint
, S_IRUGO
);
88 num_user_contexts
, "Set max number of user contexts to use");
90 u8 krcvqs
[RXE_NUM_DATA_VL
];
92 module_param_array(krcvqs
, byte
, &krcvqsset
, S_IRUGO
);
93 MODULE_PARM_DESC(krcvqs
, "Array of the number of non-control kernel receive queues by VL");
95 /* computed based on above array */
98 static unsigned hfi1_rcvarr_split
= 25;
99 module_param_named(rcvarr_split
, hfi1_rcvarr_split
, uint
, S_IRUGO
);
100 MODULE_PARM_DESC(rcvarr_split
, "Percent of context's RcvArray entries used for Eager buffers");
102 static uint eager_buffer_size
= (2 << 20); /* 2MB */
103 module_param(eager_buffer_size
, uint
, S_IRUGO
);
104 MODULE_PARM_DESC(eager_buffer_size
, "Size of the eager buffers, default: 2MB");
106 static uint rcvhdrcnt
= 2048; /* 2x the max eager buffer count */
107 module_param_named(rcvhdrcnt
, rcvhdrcnt
, uint
, S_IRUGO
);
108 MODULE_PARM_DESC(rcvhdrcnt
, "Receive header queue count (default 2048)");
110 static uint hfi1_hdrq_entsize
= 32;
111 module_param_named(hdrq_entsize
, hfi1_hdrq_entsize
, uint
, S_IRUGO
);
112 MODULE_PARM_DESC(hdrq_entsize
, "Size of header queue entries: 2 - 8B, 16 - 64B (default), 32 - 128B");
114 unsigned int user_credit_return_threshold
= 33; /* default is 33% */
115 module_param(user_credit_return_threshold
, uint
, S_IRUGO
);
116 MODULE_PARM_DESC(user_credit_return_threshold
, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)");
118 static inline u64
encode_rcv_header_entry_size(u16
);
120 static struct idr hfi1_unit_table
;
121 u32 hfi1_cpulist_count
;
122 unsigned long *hfi1_cpulist
;
125 * Common code for creating the receive context array.
127 int hfi1_create_ctxts(struct hfi1_devdata
*dd
)
131 int local_node_id
= pcibus_to_node(dd
->pcidev
->bus
);
133 /* Control context has to be always 0 */
134 BUILD_BUG_ON(HFI1_CTRL_CTXT
!= 0);
136 if (local_node_id
< 0)
137 local_node_id
= numa_node_id();
138 dd
->assigned_node_id
= local_node_id
;
140 dd
->rcd
= kcalloc(dd
->num_rcv_contexts
, sizeof(*dd
->rcd
), GFP_KERNEL
);
144 /* create one or more kernel contexts */
145 for (i
= 0; i
< dd
->first_user_ctxt
; ++i
) {
146 struct hfi1_pportdata
*ppd
;
147 struct hfi1_ctxtdata
*rcd
;
149 ppd
= dd
->pport
+ (i
% dd
->num_pports
);
150 rcd
= hfi1_create_ctxtdata(ppd
, i
);
153 "Unable to allocate kernel receive context, failing\n");
157 * Set up the kernel context flags here and now because they
158 * use default values for all receive side memories. User
159 * contexts will be handled as they are created.
161 rcd
->flags
= HFI1_CAP_KGET(MULTI_PKT_EGR
) |
162 HFI1_CAP_KGET(NODROP_RHQ_FULL
) |
163 HFI1_CAP_KGET(NODROP_EGR_FULL
) |
164 HFI1_CAP_KGET(DMA_RTAIL
);
166 /* Control context must use DMA_RTAIL */
167 if (rcd
->ctxt
== HFI1_CTRL_CTXT
)
168 rcd
->flags
|= HFI1_CAP_DMA_RTAIL
;
171 rcd
->sc
= sc_alloc(dd
, SC_ACK
, rcd
->rcvhdrqentsize
, dd
->node
);
174 "Unable to allocate kernel send context, failing\n");
175 dd
->rcd
[rcd
->ctxt
] = NULL
;
176 hfi1_free_ctxtdata(dd
, rcd
);
180 ret
= hfi1_init_ctxt(rcd
->sc
);
183 "Failed to setup kernel receive context, failing\n");
185 dd
->rcd
[rcd
->ctxt
] = NULL
;
186 hfi1_free_ctxtdata(dd
, rcd
);
202 * Common code for user and kernel context setup.
204 struct hfi1_ctxtdata
*hfi1_create_ctxtdata(struct hfi1_pportdata
*ppd
, u32 ctxt
)
206 struct hfi1_devdata
*dd
= ppd
->dd
;
207 struct hfi1_ctxtdata
*rcd
;
208 unsigned kctxt_ngroups
= 0;
211 if (dd
->rcv_entries
.nctxt_extra
>
212 dd
->num_rcv_contexts
- dd
->first_user_ctxt
)
213 kctxt_ngroups
= (dd
->rcv_entries
.nctxt_extra
-
214 (dd
->num_rcv_contexts
- dd
->first_user_ctxt
));
215 rcd
= kzalloc(sizeof(*rcd
), GFP_KERNEL
);
217 u32 rcvtids
, max_entries
;
219 hfi1_cdbg(PROC
, "setting up context %u\n", ctxt
);
221 INIT_LIST_HEAD(&rcd
->qp_wait_list
);
227 rcd
->numa_id
= numa_node_id();
228 rcd
->rcv_array_groups
= dd
->rcv_entries
.ngroups
;
230 spin_lock_init(&rcd
->exp_lock
);
233 * Calculate the context's RcvArray entry starting point.
234 * We do this here because we have to take into account all
235 * the RcvArray entries that previous context would have
236 * taken and we have to account for any extra groups
237 * assigned to the kernel or user contexts.
239 if (ctxt
< dd
->first_user_ctxt
) {
240 if (ctxt
< kctxt_ngroups
) {
241 base
= ctxt
* (dd
->rcv_entries
.ngroups
+ 1);
242 rcd
->rcv_array_groups
++;
244 base
= kctxt_ngroups
+
245 (ctxt
* dd
->rcv_entries
.ngroups
);
247 u16 ct
= ctxt
- dd
->first_user_ctxt
;
249 base
= ((dd
->n_krcv_queues
* dd
->rcv_entries
.ngroups
) +
251 if (ct
< dd
->rcv_entries
.nctxt_extra
) {
252 base
+= ct
* (dd
->rcv_entries
.ngroups
+ 1);
253 rcd
->rcv_array_groups
++;
255 base
+= dd
->rcv_entries
.nctxt_extra
+
256 (ct
* dd
->rcv_entries
.ngroups
);
258 rcd
->eager_base
= base
* dd
->rcv_entries
.group_size
;
260 /* Validate and initialize Rcv Hdr Q variables */
261 if (rcvhdrcnt
% HDRQ_INCREMENT
) {
263 "ctxt%u: header queue count %d must be divisible by %d\n",
264 rcd
->ctxt
, rcvhdrcnt
, HDRQ_INCREMENT
);
267 rcd
->rcvhdrq_cnt
= rcvhdrcnt
;
268 rcd
->rcvhdrqentsize
= hfi1_hdrq_entsize
;
270 * Simple Eager buffer allocation: we have already pre-allocated
271 * the number of RcvArray entry groups. Each ctxtdata structure
272 * holds the number of groups for that context.
274 * To follow CSR requirements and maintain cacheline alignment,
275 * make sure all sizes and bases are multiples of group_size.
277 * The expected entry count is what is left after assigning
280 max_entries
= rcd
->rcv_array_groups
*
281 dd
->rcv_entries
.group_size
;
282 rcvtids
= ((max_entries
* hfi1_rcvarr_split
) / 100);
283 rcd
->egrbufs
.count
= round_down(rcvtids
,
284 dd
->rcv_entries
.group_size
);
285 if (rcd
->egrbufs
.count
> MAX_EAGER_ENTRIES
) {
286 dd_dev_err(dd
, "ctxt%u: requested too many RcvArray entries.\n",
288 rcd
->egrbufs
.count
= MAX_EAGER_ENTRIES
;
291 "ctxt%u: max Eager buffer RcvArray entries: %u\n",
292 rcd
->ctxt
, rcd
->egrbufs
.count
);
295 * Allocate array that will hold the eager buffer accounting
297 * This will allocate the maximum possible buffer count based
298 * on the value of the RcvArray split parameter.
299 * The resulting value will be rounded down to the closest
300 * multiple of dd->rcv_entries.group_size.
302 rcd
->egrbufs
.buffers
= kcalloc(rcd
->egrbufs
.count
,
303 sizeof(*rcd
->egrbufs
.buffers
),
305 if (!rcd
->egrbufs
.buffers
)
307 rcd
->egrbufs
.rcvtids
= kcalloc(rcd
->egrbufs
.count
,
308 sizeof(*rcd
->egrbufs
.rcvtids
),
310 if (!rcd
->egrbufs
.rcvtids
)
312 rcd
->egrbufs
.size
= eager_buffer_size
;
314 * The size of the buffers programmed into the RcvArray
315 * entries needs to be big enough to handle the highest
318 if (rcd
->egrbufs
.size
< hfi1_max_mtu
) {
319 rcd
->egrbufs
.size
= __roundup_pow_of_two(hfi1_max_mtu
);
321 "ctxt%u: eager bufs size too small. Adjusting to %zu\n",
322 rcd
->ctxt
, rcd
->egrbufs
.size
);
324 rcd
->egrbufs
.rcvtid_size
= HFI1_MAX_EAGER_BUFFER_SIZE
;
326 if (ctxt
< dd
->first_user_ctxt
) { /* N/A for PSM contexts */
327 rcd
->opstats
= kzalloc(sizeof(*rcd
->opstats
),
336 kfree(rcd
->egrbufs
.rcvtids
);
337 kfree(rcd
->egrbufs
.buffers
);
343 * Convert a receive header entry size that to the encoding used in the CSR.
345 * Return a zero if the given size is invalid.
347 static inline u64
encode_rcv_header_entry_size(u16 size
)
349 /* there are only 3 valid receive header entry sizes */
356 return 0; /* invalid */
360 * Select the largest ccti value over all SLs to determine the intra-
361 * packet gap for the link.
363 * called with cca_timer_lock held (to protect access to cca_timer
364 * array), and rcu_read_lock() (to protect access to cc_state).
366 void set_link_ipg(struct hfi1_pportdata
*ppd
)
368 struct hfi1_devdata
*dd
= ppd
->dd
;
369 struct cc_state
*cc_state
;
371 u16 cce
, ccti_limit
, max_ccti
= 0;
374 u32 current_egress_rate
; /* Mbits /sec */
377 * max_pkt_time is the maximum packet egress time in units
378 * of the fabric clock period 1/(805 MHz).
381 cc_state
= get_cc_state(ppd
);
383 if (cc_state
== NULL
)
385 * This should _never_ happen - rcu_read_lock() is held,
386 * and set_link_ipg() should not be called if cc_state
391 for (i
= 0; i
< OPA_MAX_SLS
; i
++) {
392 u16 ccti
= ppd
->cca_timer
[i
].ccti
;
398 ccti_limit
= cc_state
->cct
.ccti_limit
;
399 if (max_ccti
> ccti_limit
)
400 max_ccti
= ccti_limit
;
402 cce
= cc_state
->cct
.entries
[max_ccti
].entry
;
403 shift
= (cce
& 0xc000) >> 14;
404 mult
= (cce
& 0x3fff);
406 current_egress_rate
= active_egress_rate(ppd
);
408 max_pkt_time
= egress_cycles(ppd
->ibmaxlen
, current_egress_rate
);
410 src
= (max_pkt_time
>> shift
) * mult
;
412 src
&= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK
;
413 src
<<= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT
;
415 write_csr(dd
, SEND_STATIC_RATE_CONTROL
, src
);
418 static enum hrtimer_restart
cca_timer_fn(struct hrtimer
*t
)
420 struct cca_timer
*cca_timer
;
421 struct hfi1_pportdata
*ppd
;
423 u16 ccti
, ccti_timer
, ccti_min
;
424 struct cc_state
*cc_state
;
427 cca_timer
= container_of(t
, struct cca_timer
, hrtimer
);
428 ppd
= cca_timer
->ppd
;
433 cc_state
= get_cc_state(ppd
);
435 if (cc_state
== NULL
) {
437 return HRTIMER_NORESTART
;
441 * 1) decrement ccti for SL
442 * 2) calculate IPG for link (set_link_ipg())
443 * 3) restart timer, unless ccti is at min value
446 ccti_min
= cc_state
->cong_setting
.entries
[sl
].ccti_min
;
447 ccti_timer
= cc_state
->cong_setting
.entries
[sl
].ccti_timer
;
449 spin_lock_irqsave(&ppd
->cca_timer_lock
, flags
);
451 ccti
= cca_timer
->ccti
;
453 if (ccti
> ccti_min
) {
458 spin_unlock_irqrestore(&ppd
->cca_timer_lock
, flags
);
462 if (ccti
> ccti_min
) {
463 unsigned long nsec
= 1024 * ccti_timer
;
464 /* ccti_timer is in units of 1.024 usec */
465 hrtimer_forward_now(t
, ns_to_ktime(nsec
));
466 return HRTIMER_RESTART
;
468 return HRTIMER_NORESTART
;
472 * Common code for initializing the physical port structure.
474 void hfi1_init_pportdata(struct pci_dev
*pdev
, struct hfi1_pportdata
*ppd
,
475 struct hfi1_devdata
*dd
, u8 hw_pidx
, u8 port
)
478 uint default_pkey_idx
;
481 ppd
->hw_pidx
= hw_pidx
;
482 ppd
->port
= port
; /* IB port number, not index */
484 default_pkey_idx
= 1;
486 ppd
->pkeys
[default_pkey_idx
] = DEFAULT_P_KEY
;
488 hfi1_early_err(&pdev
->dev
,
489 "Faking data partition 0x8001 in idx %u\n",
491 ppd
->pkeys
[!default_pkey_idx
] = 0x8001;
494 INIT_WORK(&ppd
->link_vc_work
, handle_verify_cap
);
495 INIT_WORK(&ppd
->link_up_work
, handle_link_up
);
496 INIT_WORK(&ppd
->link_down_work
, handle_link_down
);
497 INIT_WORK(&ppd
->freeze_work
, handle_freeze
);
498 INIT_WORK(&ppd
->link_downgrade_work
, handle_link_downgrade
);
499 INIT_WORK(&ppd
->sma_message_work
, handle_sma_message
);
500 INIT_WORK(&ppd
->link_bounce_work
, handle_link_bounce
);
501 mutex_init(&ppd
->hls_lock
);
502 spin_lock_init(&ppd
->sdma_alllock
);
503 spin_lock_init(&ppd
->qsfp_info
.qsfp_lock
);
505 ppd
->sm_trap_qp
= 0x0;
510 spin_lock_init(&ppd
->cca_timer_lock
);
512 for (i
= 0; i
< OPA_MAX_SLS
; i
++) {
513 hrtimer_init(&ppd
->cca_timer
[i
].hrtimer
, CLOCK_MONOTONIC
,
515 ppd
->cca_timer
[i
].ppd
= ppd
;
516 ppd
->cca_timer
[i
].sl
= i
;
517 ppd
->cca_timer
[i
].ccti
= 0;
518 ppd
->cca_timer
[i
].hrtimer
.function
= cca_timer_fn
;
521 ppd
->cc_max_table_entries
= IB_CC_TABLE_CAP_DEFAULT
;
523 spin_lock_init(&ppd
->cc_state_lock
);
524 spin_lock_init(&ppd
->cc_log_lock
);
525 size
= sizeof(struct cc_state
);
526 RCU_INIT_POINTER(ppd
->cc_state
, kzalloc(size
, GFP_KERNEL
));
527 if (!rcu_dereference(ppd
->cc_state
))
533 hfi1_early_err(&pdev
->dev
,
534 "Congestion Control Agent disabled for port %d\n", port
);
538 * Do initialization for device that is only needed on
539 * first detect, not on resets.
541 static int loadtime_init(struct hfi1_devdata
*dd
)
547 * init_after_reset - re-initialize after a reset
548 * @dd: the hfi1_ib device
550 * sanity check at least some of the values after reset, and
551 * ensure no receive or transmit (explicitly, in case reset
554 static int init_after_reset(struct hfi1_devdata
*dd
)
559 * Ensure chip does no sends or receives, tail updates, or
560 * pioavail updates while we re-initialize. This is mostly
561 * for the driver data structures, not chip registers.
563 for (i
= 0; i
< dd
->num_rcv_contexts
; i
++)
564 hfi1_rcvctrl(dd
, HFI1_RCVCTRL_CTXT_DIS
|
565 HFI1_RCVCTRL_INTRAVAIL_DIS
|
566 HFI1_RCVCTRL_TAILUPD_DIS
, i
);
567 pio_send_control(dd
, PSC_GLOBAL_DISABLE
);
568 for (i
= 0; i
< dd
->num_send_contexts
; i
++)
569 sc_disable(dd
->send_contexts
[i
].sc
);
574 static void enable_chip(struct hfi1_devdata
*dd
)
579 /* enable PIO send */
580 pio_send_control(dd
, PSC_GLOBAL_ENABLE
);
583 * Enable kernel ctxts' receive and receive interrupt.
584 * Other ctxts done as user opens and initializes them.
586 rcvmask
= HFI1_RCVCTRL_CTXT_ENB
| HFI1_RCVCTRL_INTRAVAIL_ENB
;
587 for (i
= 0; i
< dd
->first_user_ctxt
; ++i
) {
588 rcvmask
|= HFI1_CAP_KGET_MASK(dd
->rcd
[i
]->flags
, DMA_RTAIL
) ?
589 HFI1_RCVCTRL_TAILUPD_ENB
: HFI1_RCVCTRL_TAILUPD_DIS
;
590 if (!HFI1_CAP_KGET_MASK(dd
->rcd
[i
]->flags
, MULTI_PKT_EGR
))
591 rcvmask
|= HFI1_RCVCTRL_ONE_PKT_EGR_ENB
;
592 if (HFI1_CAP_KGET_MASK(dd
->rcd
[i
]->flags
, NODROP_RHQ_FULL
))
593 rcvmask
|= HFI1_RCVCTRL_NO_RHQ_DROP_ENB
;
594 if (HFI1_CAP_KGET_MASK(dd
->rcd
[i
]->flags
, NODROP_EGR_FULL
))
595 rcvmask
|= HFI1_RCVCTRL_NO_EGR_DROP_ENB
;
596 hfi1_rcvctrl(dd
, rcvmask
, i
);
597 sc_enable(dd
->rcd
[i
]->sc
);
602 * create_workqueues - create per port workqueues
603 * @dd: the hfi1_ib device
605 static int create_workqueues(struct hfi1_devdata
*dd
)
608 struct hfi1_pportdata
*ppd
;
610 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
611 ppd
= dd
->pport
+ pidx
;
616 WQ_SYSFS
| WQ_HIGHPRI
| WQ_CPU_INTENSIVE
,
625 pr_err("alloc_workqueue failed for port %d\n", pidx
+ 1);
626 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
627 ppd
= dd
->pport
+ pidx
;
629 destroy_workqueue(ppd
->hfi1_wq
);
637 * hfi1_init - do the actual initialization sequence on the chip
638 * @dd: the hfi1_ib device
639 * @reinit: re-initializing, so don't allocate new memory
641 * Do the actual initialization sequence on the chip. This is done
642 * both from the init routine called from the PCI infrastructure, and
643 * when we reset the chip, or detect that it was reset internally,
644 * or it's administratively re-enabled.
646 * Memory allocation here and in called routines is only done in
647 * the first case (reinit == 0). We have to be careful, because even
648 * without memory allocation, we need to re-write all the chip registers
649 * TIDs, etc. after the reset or enable has completed.
651 int hfi1_init(struct hfi1_devdata
*dd
, int reinit
)
653 int ret
= 0, pidx
, lastfail
= 0;
655 struct hfi1_ctxtdata
*rcd
;
656 struct hfi1_pportdata
*ppd
;
658 /* Set up recv low level handlers */
659 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_EXPECTED
] =
660 kdeth_process_expected
;
661 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_EAGER
] =
663 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_IB
] = process_receive_ib
;
664 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_ERROR
] =
665 process_receive_error
;
666 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_BYPASS
] =
667 process_receive_bypass
;
668 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_INVALID5
] =
669 process_receive_invalid
;
670 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_INVALID6
] =
671 process_receive_invalid
;
672 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_INVALID7
] =
673 process_receive_invalid
;
674 dd
->rhf_rcv_function_map
= dd
->normal_rhf_rcv_functions
;
676 /* Set up send low level handlers */
677 dd
->process_pio_send
= hfi1_verbs_send_pio
;
678 dd
->process_dma_send
= hfi1_verbs_send_dma
;
679 dd
->pio_inline_send
= pio_copy
;
682 atomic_set(&dd
->drop_packet
, DROP_PACKET_ON
);
685 atomic_set(&dd
->drop_packet
, DROP_PACKET_OFF
);
689 /* make sure the link is not "up" */
690 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
691 ppd
= dd
->pport
+ pidx
;
696 ret
= init_after_reset(dd
);
698 ret
= loadtime_init(dd
);
702 /* allocate dummy tail memory for all receive contexts */
703 dd
->rcvhdrtail_dummy_kvaddr
= dma_zalloc_coherent(
704 &dd
->pcidev
->dev
, sizeof(u64
),
705 &dd
->rcvhdrtail_dummy_physaddr
,
708 if (!dd
->rcvhdrtail_dummy_kvaddr
) {
709 dd_dev_err(dd
, "cannot allocate dummy tail memory\n");
714 /* dd->rcd can be NULL if early initialization failed */
715 for (i
= 0; dd
->rcd
&& i
< dd
->first_user_ctxt
; ++i
) {
717 * Set up the (kernel) rcvhdr queue and egr TIDs. If doing
718 * re-init, the simplest way to handle this is to free
719 * existing, and re-allocate.
720 * Need to re-create rest of ctxt 0 ctxtdata as well.
726 rcd
->do_interrupt
= &handle_receive_interrupt
;
728 lastfail
= hfi1_create_rcvhdrq(dd
, rcd
);
730 lastfail
= hfi1_setup_eagerbufs(rcd
);
733 "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
738 /* Allocate enough memory for user event notification. */
739 len
= ALIGN(dd
->chip_rcv_contexts
* HFI1_MAX_SHARED_CTXTS
*
740 sizeof(*dd
->events
), PAGE_SIZE
);
741 dd
->events
= vmalloc_user(len
);
743 dd_dev_err(dd
, "Failed to allocate user events page\n");
745 * Allocate a page for device and port status.
746 * Page will be shared amongst all user processes.
748 dd
->status
= vmalloc_user(PAGE_SIZE
);
750 dd_dev_err(dd
, "Failed to allocate dev status page\n");
752 dd
->freezelen
= PAGE_SIZE
- (sizeof(*dd
->status
) -
753 sizeof(dd
->status
->freezemsg
));
754 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
755 ppd
= dd
->pport
+ pidx
;
757 /* Currently, we only have one port */
758 ppd
->statusp
= &dd
->status
->port
;
763 /* enable chip even if we have an error, so we can debug cause */
766 ret
= hfi1_cq_init(dd
);
769 * Set status even if port serdes is not initialized
770 * so that diags will work.
773 dd
->status
->dev
|= HFI1_STATUS_CHIP_PRESENT
|
776 /* enable all interrupts from the chip */
777 set_intr_state(dd
, 1);
779 /* chip is OK for user apps; mark it as initialized */
780 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
781 ppd
= dd
->pport
+ pidx
;
783 /* initialize the qsfp if it exists
784 * Requires interrupts to be enabled so we are notified
785 * when the QSFP completes reset, and has
786 * to be done before bringing up the SERDES
790 /* start the serdes - must be after interrupts are
791 enabled so we are notified when the link goes up */
792 lastfail
= bringup_serdes(ppd
);
795 "Failed to bring up port %u\n",
799 * Set status even if port serdes is not initialized
800 * so that diags will work.
803 *ppd
->statusp
|= HFI1_STATUS_CHIP_PRESENT
|
805 if (!ppd
->link_speed_enabled
)
810 /* if ret is non-zero, we probably should do some cleanup here... */
814 static inline struct hfi1_devdata
*__hfi1_lookup(int unit
)
816 return idr_find(&hfi1_unit_table
, unit
);
819 struct hfi1_devdata
*hfi1_lookup(int unit
)
821 struct hfi1_devdata
*dd
;
824 spin_lock_irqsave(&hfi1_devs_lock
, flags
);
825 dd
= __hfi1_lookup(unit
);
826 spin_unlock_irqrestore(&hfi1_devs_lock
, flags
);
832 * Stop the timers during unit shutdown, or after an error late
835 static void stop_timers(struct hfi1_devdata
*dd
)
837 struct hfi1_pportdata
*ppd
;
840 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
841 ppd
= dd
->pport
+ pidx
;
842 if (ppd
->led_override_timer
.data
) {
843 del_timer_sync(&ppd
->led_override_timer
);
844 atomic_set(&ppd
->led_override_timer_active
, 0);
850 * shutdown_device - shut down a device
851 * @dd: the hfi1_ib device
853 * This is called to make the device quiet when we are about to
854 * unload the driver, and also when the device is administratively
855 * disabled. It does not free any data structures.
856 * Everything it does has to be setup again by hfi1_init(dd, 1)
858 static void shutdown_device(struct hfi1_devdata
*dd
)
860 struct hfi1_pportdata
*ppd
;
864 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
865 ppd
= dd
->pport
+ pidx
;
869 *ppd
->statusp
&= ~(HFI1_STATUS_IB_CONF
|
870 HFI1_STATUS_IB_READY
);
872 dd
->flags
&= ~HFI1_INITTED
;
874 /* mask interrupts, but not errors */
875 set_intr_state(dd
, 0);
877 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
878 ppd
= dd
->pport
+ pidx
;
879 for (i
= 0; i
< dd
->num_rcv_contexts
; i
++)
880 hfi1_rcvctrl(dd
, HFI1_RCVCTRL_TAILUPD_DIS
|
881 HFI1_RCVCTRL_CTXT_DIS
|
882 HFI1_RCVCTRL_INTRAVAIL_DIS
|
883 HFI1_RCVCTRL_PKEY_DIS
|
884 HFI1_RCVCTRL_ONE_PKT_EGR_DIS
, i
);
886 * Gracefully stop all sends allowing any in progress to
889 for (i
= 0; i
< dd
->num_send_contexts
; i
++)
890 sc_flush(dd
->send_contexts
[i
].sc
);
894 * Enough for anything that's going to trickle out to have actually
899 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
900 ppd
= dd
->pport
+ pidx
;
902 /* disable all contexts */
903 for (i
= 0; i
< dd
->num_send_contexts
; i
++)
904 sc_disable(dd
->send_contexts
[i
].sc
);
905 /* disable the send device */
906 pio_send_control(dd
, PSC_GLOBAL_DISABLE
);
909 * Clear SerdesEnable.
910 * We can't count on interrupts since we are stopping.
912 hfi1_quiet_serdes(ppd
);
915 destroy_workqueue(ppd
->hfi1_wq
);
923 * hfi1_free_ctxtdata - free a context's allocated data
924 * @dd: the hfi1_ib device
925 * @rcd: the ctxtdata structure
927 * free up any allocated data for a context
928 * This should not touch anything that would affect a simultaneous
929 * re-allocation of context data, because it is called after hfi1_mutex
930 * is released (and can be called from reinit as well).
931 * It should never change any chip state, or global driver state.
933 void hfi1_free_ctxtdata(struct hfi1_devdata
*dd
, struct hfi1_ctxtdata
*rcd
)
941 dma_free_coherent(&dd
->pcidev
->dev
, rcd
->rcvhdrq_size
,
942 rcd
->rcvhdrq
, rcd
->rcvhdrq_phys
);
944 if (rcd
->rcvhdrtail_kvaddr
) {
945 dma_free_coherent(&dd
->pcidev
->dev
, PAGE_SIZE
,
946 (void *)rcd
->rcvhdrtail_kvaddr
,
947 rcd
->rcvhdrqtailaddr_phys
);
948 rcd
->rcvhdrtail_kvaddr
= NULL
;
952 /* all the RcvArray entries should have been cleared by now */
953 kfree(rcd
->egrbufs
.rcvtids
);
955 for (e
= 0; e
< rcd
->egrbufs
.alloced
; e
++) {
956 if (rcd
->egrbufs
.buffers
[e
].phys
)
957 dma_free_coherent(&dd
->pcidev
->dev
,
958 rcd
->egrbufs
.buffers
[e
].len
,
959 rcd
->egrbufs
.buffers
[e
].addr
,
960 rcd
->egrbufs
.buffers
[e
].phys
);
962 kfree(rcd
->egrbufs
.buffers
);
965 vfree(rcd
->physshadow
);
966 vfree(rcd
->tid_pg_list
);
967 vfree(rcd
->user_event_mask
);
968 vfree(rcd
->subctxt_uregbase
);
969 vfree(rcd
->subctxt_rcvegrbuf
);
970 vfree(rcd
->subctxt_rcvhdr_base
);
971 kfree(rcd
->tidusemap
);
976 void hfi1_free_devdata(struct hfi1_devdata
*dd
)
980 spin_lock_irqsave(&hfi1_devs_lock
, flags
);
981 idr_remove(&hfi1_unit_table
, dd
->unit
);
983 spin_unlock_irqrestore(&hfi1_devs_lock
, flags
);
984 hfi1_dbg_ibdev_exit(&dd
->verbs_dev
);
985 rcu_barrier(); /* wait for rcu callbacks to complete */
986 free_percpu(dd
->int_counter
);
987 free_percpu(dd
->rcv_limit
);
988 ib_dealloc_device(&dd
->verbs_dev
.ibdev
);
992 * Allocate our primary per-unit data structure. Must be done via verbs
993 * allocator, because the verbs cleanup process both does cleanup and
994 * free of the data structure.
995 * "extra" is for chip-specific data.
997 * Use the idr mechanism to get a unit number for this unit.
999 struct hfi1_devdata
*hfi1_alloc_devdata(struct pci_dev
*pdev
, size_t extra
)
1001 unsigned long flags
;
1002 struct hfi1_devdata
*dd
;
1005 dd
= (struct hfi1_devdata
*)ib_alloc_device(sizeof(*dd
) + extra
);
1007 return ERR_PTR(-ENOMEM
);
1008 /* extra is * number of ports */
1009 dd
->num_pports
= extra
/ sizeof(struct hfi1_pportdata
);
1010 dd
->pport
= (struct hfi1_pportdata
*)(dd
+ 1);
1012 INIT_LIST_HEAD(&dd
->list
);
1013 dd
->node
= dev_to_node(&pdev
->dev
);
1016 idr_preload(GFP_KERNEL
);
1017 spin_lock_irqsave(&hfi1_devs_lock
, flags
);
1019 ret
= idr_alloc(&hfi1_unit_table
, dd
, 0, 0, GFP_NOWAIT
);
1022 list_add(&dd
->list
, &hfi1_dev_list
);
1025 spin_unlock_irqrestore(&hfi1_devs_lock
, flags
);
1029 hfi1_early_err(&pdev
->dev
,
1030 "Could not allocate unit ID: error %d\n", -ret
);
1034 * Initialize all locks for the device. This needs to be as early as
1035 * possible so locks are usable.
1037 spin_lock_init(&dd
->sc_lock
);
1038 spin_lock_init(&dd
->sendctrl_lock
);
1039 spin_lock_init(&dd
->rcvctrl_lock
);
1040 spin_lock_init(&dd
->uctxt_lock
);
1041 spin_lock_init(&dd
->hfi1_diag_trans_lock
);
1042 spin_lock_init(&dd
->sc_init_lock
);
1043 spin_lock_init(&dd
->dc8051_lock
);
1044 spin_lock_init(&dd
->dc8051_memlock
);
1045 mutex_init(&dd
->qsfp_i2c_mutex
);
1046 seqlock_init(&dd
->sc2vl_lock
);
1047 spin_lock_init(&dd
->sde_map_lock
);
1048 init_waitqueue_head(&dd
->event_queue
);
1050 dd
->int_counter
= alloc_percpu(u64
);
1051 if (!dd
->int_counter
) {
1053 hfi1_early_err(&pdev
->dev
,
1054 "Could not allocate per-cpu int_counter\n");
1058 dd
->rcv_limit
= alloc_percpu(u64
);
1059 if (!dd
->rcv_limit
) {
1061 hfi1_early_err(&pdev
->dev
,
1062 "Could not allocate per-cpu rcv_limit\n");
1066 if (!hfi1_cpulist_count
) {
1067 u32 count
= num_online_cpus();
1069 hfi1_cpulist
= kcalloc(BITS_TO_LONGS(count
), sizeof(long),
1072 hfi1_cpulist_count
= count
;
1076 "Could not alloc cpulist info, cpu affinity might be wrong\n");
1078 hfi1_dbg_ibdev_init(&dd
->verbs_dev
);
1082 if (!list_empty(&dd
->list
))
1083 list_del_init(&dd
->list
);
1084 ib_dealloc_device(&dd
->verbs_dev
.ibdev
);
1085 return ERR_PTR(ret
);
1089 * Called from freeze mode handlers, and from PCI error
1090 * reporting code. Should be paranoid about state of
1091 * system and data structures.
1093 void hfi1_disable_after_error(struct hfi1_devdata
*dd
)
1095 if (dd
->flags
& HFI1_INITTED
) {
1098 dd
->flags
&= ~HFI1_INITTED
;
1100 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
1101 struct hfi1_pportdata
*ppd
;
1103 ppd
= dd
->pport
+ pidx
;
1104 if (dd
->flags
& HFI1_PRESENT
)
1105 set_link_state(ppd
, HLS_DN_DISABLE
);
1108 *ppd
->statusp
&= ~HFI1_STATUS_IB_READY
;
1113 * Mark as having had an error for driver, and also
1114 * for /sys and status word mapped to user programs.
1115 * This marks unit as not usable, until reset.
1118 dd
->status
->dev
|= HFI1_STATUS_HWERROR
;
1121 static void remove_one(struct pci_dev
*);
1122 static int init_one(struct pci_dev
*, const struct pci_device_id
*);
1124 #define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: "
1125 #define PFX DRIVER_NAME ": "
1127 static const struct pci_device_id hfi1_pci_tbl
[] = {
1128 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL0
) },
1129 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL1
) },
1133 MODULE_DEVICE_TABLE(pci
, hfi1_pci_tbl
);
1135 static struct pci_driver hfi1_pci_driver
= {
1136 .name
= DRIVER_NAME
,
1138 .remove
= remove_one
,
1139 .id_table
= hfi1_pci_tbl
,
1140 .err_handler
= &hfi1_pci_err_handler
,
1143 static void __init
compute_krcvqs(void)
1147 for (i
= 0; i
< krcvqsset
; i
++)
1148 n_krcvqs
+= krcvqs
[i
];
1152 * Do all the generic driver unit- and chip-independent memory
1153 * allocation and initialization.
1155 static int __init
hfi1_mod_init(void)
1163 /* validate max MTU before any devices start */
1164 if (!valid_opa_max_mtu(hfi1_max_mtu
)) {
1165 pr_err("Invalid max_mtu 0x%x, using 0x%x instead\n",
1166 hfi1_max_mtu
, HFI1_DEFAULT_MAX_MTU
);
1167 hfi1_max_mtu
= HFI1_DEFAULT_MAX_MTU
;
1169 /* valid CUs run from 1-128 in powers of 2 */
1170 if (hfi1_cu
> 128 || !is_power_of_2(hfi1_cu
))
1172 /* valid credit return threshold is 0-100, variable is unsigned */
1173 if (user_credit_return_threshold
> 100)
1174 user_credit_return_threshold
= 100;
1177 /* sanitize receive interrupt count, time must wait until after
1178 the hardware type is known */
1179 if (rcv_intr_count
> RCV_HDR_HEAD_COUNTER_MASK
)
1180 rcv_intr_count
= RCV_HDR_HEAD_COUNTER_MASK
;
1181 /* reject invalid combinations */
1182 if (rcv_intr_count
== 0 && rcv_intr_timeout
== 0) {
1183 pr_err("Invalid mode: both receive interrupt count and available timeout are zero - setting interrupt count to 1\n");
1186 if (rcv_intr_count
> 1 && rcv_intr_timeout
== 0) {
1188 * Avoid indefinite packet delivery by requiring a timeout
1191 pr_err("Invalid mode: receive interrupt count greater than 1 and available timeout is zero - setting available timeout to 1\n");
1192 rcv_intr_timeout
= 1;
1194 if (rcv_intr_dynamic
&& !(rcv_intr_count
> 1 && rcv_intr_timeout
> 0)) {
1196 * The dynamic algorithm expects a non-zero timeout
1199 pr_err("Invalid mode: dynamic receive interrupt mitigation with invalid count and timeout - turning dynamic off\n");
1200 rcv_intr_dynamic
= 0;
1203 /* sanitize link CRC options */
1204 link_crc_mask
&= SUPPORTED_CRCS
;
1207 * These must be called before the driver is registered with
1208 * the PCI subsystem.
1210 idr_init(&hfi1_unit_table
);
1213 ret
= pci_register_driver(&hfi1_pci_driver
);
1215 pr_err("Unable to register driver: error %d\n", -ret
);
1218 goto bail
; /* all OK */
1222 idr_destroy(&hfi1_unit_table
);
1228 module_init(hfi1_mod_init
);
1231 * Do the non-unit driver cleanup, memory free, etc. at unload.
1233 static void __exit
hfi1_mod_cleanup(void)
1235 pci_unregister_driver(&hfi1_pci_driver
);
1237 hfi1_cpulist_count
= 0;
1238 kfree(hfi1_cpulist
);
1240 idr_destroy(&hfi1_unit_table
);
1241 dispose_firmware(); /* asymmetric with obtain_firmware() */
1245 module_exit(hfi1_mod_cleanup
);
1247 /* this can only be called after a successful initialization */
1248 static void cleanup_device_data(struct hfi1_devdata
*dd
)
1252 struct hfi1_ctxtdata
**tmp
;
1253 unsigned long flags
;
1255 /* users can't do anything more with chip */
1256 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
1257 struct hfi1_pportdata
*ppd
= &dd
->pport
[pidx
];
1258 struct cc_state
*cc_state
;
1262 *ppd
->statusp
&= ~HFI1_STATUS_CHIP_PRESENT
;
1264 for (i
= 0; i
< OPA_MAX_SLS
; i
++)
1265 hrtimer_cancel(&ppd
->cca_timer
[i
].hrtimer
);
1267 spin_lock(&ppd
->cc_state_lock
);
1268 cc_state
= get_cc_state(ppd
);
1269 rcu_assign_pointer(ppd
->cc_state
, NULL
);
1270 spin_unlock(&ppd
->cc_state_lock
);
1273 call_rcu(&cc_state
->rcu
, cc_state_reclaim
);
1276 free_credit_return(dd
);
1279 * Free any resources still in use (usually just kernel contexts)
1280 * at unload; we do for ctxtcnt, because that's what we allocate.
1281 * We acquire lock to be really paranoid that rcd isn't being
1282 * accessed from some interrupt-related code (that should not happen,
1283 * but best to be sure).
1285 spin_lock_irqsave(&dd
->uctxt_lock
, flags
);
1288 spin_unlock_irqrestore(&dd
->uctxt_lock
, flags
);
1290 if (dd
->rcvhdrtail_dummy_kvaddr
) {
1291 dma_free_coherent(&dd
->pcidev
->dev
, sizeof(u64
),
1292 (void *)dd
->rcvhdrtail_dummy_kvaddr
,
1293 dd
->rcvhdrtail_dummy_physaddr
);
1294 dd
->rcvhdrtail_dummy_kvaddr
= NULL
;
1297 for (ctxt
= 0; tmp
&& ctxt
< dd
->num_rcv_contexts
; ctxt
++) {
1298 struct hfi1_ctxtdata
*rcd
= tmp
[ctxt
];
1300 tmp
[ctxt
] = NULL
; /* debugging paranoia */
1302 hfi1_clear_tids(rcd
);
1303 hfi1_free_ctxtdata(dd
, rcd
);
1307 /* must follow rcv context free - need to remove rcv's hooks */
1308 for (ctxt
= 0; ctxt
< dd
->num_send_contexts
; ctxt
++)
1309 sc_free(dd
->send_contexts
[ctxt
].sc
);
1310 dd
->num_send_contexts
= 0;
1311 kfree(dd
->send_contexts
);
1312 dd
->send_contexts
= NULL
;
1313 kfree(dd
->boardname
);
1320 * Clean up on unit shutdown, or error during unit load after
1321 * successful initialization.
1323 static void postinit_cleanup(struct hfi1_devdata
*dd
)
1325 hfi1_start_cleanup(dd
);
1327 hfi1_pcie_ddcleanup(dd
);
1328 hfi1_pcie_cleanup(dd
->pcidev
);
1330 cleanup_device_data(dd
);
1332 hfi1_free_devdata(dd
);
1335 static int init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1337 int ret
= 0, j
, pidx
, initfail
;
1338 struct hfi1_devdata
*dd
= NULL
;
1339 struct hfi1_pportdata
*ppd
;
1341 /* First, lock the non-writable module parameters */
1344 /* Validate some global module parameters */
1345 if (rcvhdrcnt
<= HFI1_MIN_HDRQ_EGRBUF_CNT
) {
1346 hfi1_early_err(&pdev
->dev
, "Header queue count too small\n");
1350 /* use the encoding function as a sanitization check */
1351 if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize
)) {
1352 hfi1_early_err(&pdev
->dev
, "Invalid HdrQ Entry size %u\n",
1358 /* The receive eager buffer size must be set before the receive
1359 * contexts are created.
1361 * Set the eager buffer size. Validate that it falls in a range
1362 * allowed by the hardware - all powers of 2 between the min and
1363 * max. The maximum valid MTU is within the eager buffer range
1364 * so we do not need to cap the max_mtu by an eager buffer size
1367 if (eager_buffer_size
) {
1368 if (!is_power_of_2(eager_buffer_size
))
1370 roundup_pow_of_two(eager_buffer_size
);
1372 clamp_val(eager_buffer_size
,
1373 MIN_EAGER_BUFFER
* 8,
1374 MAX_EAGER_BUFFER_TOTAL
);
1375 hfi1_early_info(&pdev
->dev
, "Eager buffer size %u\n",
1378 hfi1_early_err(&pdev
->dev
, "Invalid Eager buffer size of 0\n");
1383 /* restrict value of hfi1_rcvarr_split */
1384 hfi1_rcvarr_split
= clamp_val(hfi1_rcvarr_split
, 0, 100);
1386 ret
= hfi1_pcie_init(pdev
, ent
);
1391 * Do device-specific initialization, function table setup, dd
1394 switch (ent
->device
) {
1395 case PCI_DEVICE_ID_INTEL0
:
1396 case PCI_DEVICE_ID_INTEL1
:
1397 dd
= hfi1_init_dd(pdev
, ent
);
1400 hfi1_early_err(&pdev
->dev
,
1401 "Failing on unknown Intel deviceid 0x%x\n",
1409 goto clean_bail
; /* error already printed */
1411 ret
= create_workqueues(dd
);
1415 /* do the generic initialization */
1416 initfail
= hfi1_init(dd
, 0);
1418 ret
= hfi1_register_ib_device(dd
);
1421 * Now ready for use. this should be cleared whenever we
1422 * detect a reset, or initiate one. If earlier failure,
1423 * we still create devices, so diags, etc. can be used
1424 * to determine cause of problem.
1426 if (!initfail
&& !ret
)
1427 dd
->flags
|= HFI1_INITTED
;
1429 j
= hfi1_device_create(dd
);
1431 dd_dev_err(dd
, "Failed to create /dev devices: %d\n", -j
);
1433 if (initfail
|| ret
) {
1435 flush_workqueue(ib_wq
);
1436 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
1437 hfi1_quiet_serdes(dd
->pport
+ pidx
);
1438 ppd
= dd
->pport
+ pidx
;
1440 destroy_workqueue(ppd
->hfi1_wq
);
1441 ppd
->hfi1_wq
= NULL
;
1445 hfi1_device_remove(dd
);
1447 hfi1_unregister_ib_device(dd
);
1448 postinit_cleanup(dd
);
1451 goto bail
; /* everything already cleaned */
1459 hfi1_pcie_cleanup(pdev
);
1464 static void remove_one(struct pci_dev
*pdev
)
1466 struct hfi1_devdata
*dd
= pci_get_drvdata(pdev
);
1468 /* unregister from IB core */
1469 hfi1_unregister_ib_device(dd
);
1472 * Disable the IB link, disable interrupts on the device,
1473 * clear dma engines, etc.
1475 shutdown_device(dd
);
1479 /* wait until all of our (qsfp) queue_work() calls complete */
1480 flush_workqueue(ib_wq
);
1482 hfi1_device_remove(dd
);
1484 postinit_cleanup(dd
);
1488 * hfi1_create_rcvhdrq - create a receive header queue
1489 * @dd: the hfi1_ib device
1490 * @rcd: the context data
1492 * This must be contiguous memory (from an i/o perspective), and must be
1493 * DMA'able (which means for some systems, it will go through an IOMMU,
1494 * or be forced into a low address range).
1496 int hfi1_create_rcvhdrq(struct hfi1_devdata
*dd
, struct hfi1_ctxtdata
*rcd
)
1501 if (!rcd
->rcvhdrq
) {
1502 dma_addr_t phys_hdrqtail
;
1506 * rcvhdrqentsize is in DWs, so we have to convert to bytes
1509 amt
= ALIGN(rcd
->rcvhdrq_cnt
* rcd
->rcvhdrqentsize
*
1510 sizeof(u32
), PAGE_SIZE
);
1512 gfp_flags
= (rcd
->ctxt
>= dd
->first_user_ctxt
) ?
1513 GFP_USER
: GFP_KERNEL
;
1514 rcd
->rcvhdrq
= dma_zalloc_coherent(
1515 &dd
->pcidev
->dev
, amt
, &rcd
->rcvhdrq_phys
,
1516 gfp_flags
| __GFP_COMP
);
1518 if (!rcd
->rcvhdrq
) {
1520 "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
1525 /* Event mask is per device now and is in hfi1_devdata */
1526 /*if (rcd->ctxt >= dd->first_user_ctxt) {
1527 rcd->user_event_mask = vmalloc_user(PAGE_SIZE);
1528 if (!rcd->user_event_mask)
1529 goto bail_free_hdrq;
1532 if (HFI1_CAP_KGET_MASK(rcd
->flags
, DMA_RTAIL
)) {
1533 rcd
->rcvhdrtail_kvaddr
= dma_zalloc_coherent(
1534 &dd
->pcidev
->dev
, PAGE_SIZE
, &phys_hdrqtail
,
1536 if (!rcd
->rcvhdrtail_kvaddr
)
1538 rcd
->rcvhdrqtailaddr_phys
= phys_hdrqtail
;
1541 rcd
->rcvhdrq_size
= amt
;
1544 * These values are per-context:
1549 reg
= ((u64
)(rcd
->rcvhdrq_cnt
>> HDRQ_SIZE_SHIFT
)
1550 & RCV_HDR_CNT_CNT_MASK
)
1551 << RCV_HDR_CNT_CNT_SHIFT
;
1552 write_kctxt_csr(dd
, rcd
->ctxt
, RCV_HDR_CNT
, reg
);
1553 reg
= (encode_rcv_header_entry_size(rcd
->rcvhdrqentsize
)
1554 & RCV_HDR_ENT_SIZE_ENT_SIZE_MASK
)
1555 << RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT
;
1556 write_kctxt_csr(dd
, rcd
->ctxt
, RCV_HDR_ENT_SIZE
, reg
);
1557 reg
= (dd
->rcvhdrsize
& RCV_HDR_SIZE_HDR_SIZE_MASK
)
1558 << RCV_HDR_SIZE_HDR_SIZE_SHIFT
;
1559 write_kctxt_csr(dd
, rcd
->ctxt
, RCV_HDR_SIZE
, reg
);
1562 * Program dummy tail address for every receive context
1563 * before enabling any receive context
1565 write_kctxt_csr(dd
, rcd
->ctxt
, RCV_HDR_TAIL_ADDR
,
1566 dd
->rcvhdrtail_dummy_physaddr
);
1572 "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
1574 vfree(rcd
->user_event_mask
);
1575 rcd
->user_event_mask
= NULL
;
1576 dma_free_coherent(&dd
->pcidev
->dev
, amt
, rcd
->rcvhdrq
,
1578 rcd
->rcvhdrq
= NULL
;
1584 * allocate eager buffers, both kernel and user contexts.
1585 * @rcd: the context we are setting up.
1587 * Allocate the eager TID buffers and program them into hip.
1588 * They are no longer completely contiguous, we do multiple allocation
1589 * calls. Otherwise we get the OOM code involved, by asking for too
1590 * much per call, with disastrous results on some kernels.
1592 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata
*rcd
)
1594 struct hfi1_devdata
*dd
= rcd
->dd
;
1595 u32 max_entries
, egrtop
, alloced_bytes
= 0, idx
= 0;
1599 u16 round_mtu
= roundup_pow_of_two(hfi1_max_mtu
);
1602 * GFP_USER, but without GFP_FS, so buffer cache can be
1603 * coalesced (we hope); otherwise, even at order 4,
1604 * heavy filesystem activity makes these fail, and we can
1605 * use compound pages.
1607 gfp_flags
= __GFP_RECLAIM
| __GFP_IO
| __GFP_COMP
;
1610 * The minimum size of the eager buffers is a groups of MTU-sized
1612 * The global eager_buffer_size parameter is checked against the
1613 * theoretical lower limit of the value. Here, we check against the
1616 if (rcd
->egrbufs
.size
< (round_mtu
* dd
->rcv_entries
.group_size
))
1617 rcd
->egrbufs
.size
= round_mtu
* dd
->rcv_entries
.group_size
;
1619 * If using one-pkt-per-egr-buffer, lower the eager buffer
1620 * size to the max MTU (page-aligned).
1622 if (!HFI1_CAP_KGET_MASK(rcd
->flags
, MULTI_PKT_EGR
))
1623 rcd
->egrbufs
.rcvtid_size
= round_mtu
;
1626 * Eager buffers sizes of 1MB or less require smaller TID sizes
1627 * to satisfy the "multiple of 8 RcvArray entries" requirement.
1629 if (rcd
->egrbufs
.size
<= (1 << 20))
1630 rcd
->egrbufs
.rcvtid_size
= max((unsigned long)round_mtu
,
1631 rounddown_pow_of_two(rcd
->egrbufs
.size
/ 8));
1633 while (alloced_bytes
< rcd
->egrbufs
.size
&&
1634 rcd
->egrbufs
.alloced
< rcd
->egrbufs
.count
) {
1635 rcd
->egrbufs
.buffers
[idx
].addr
=
1636 dma_zalloc_coherent(&dd
->pcidev
->dev
,
1637 rcd
->egrbufs
.rcvtid_size
,
1638 &rcd
->egrbufs
.buffers
[idx
].phys
,
1640 if (rcd
->egrbufs
.buffers
[idx
].addr
) {
1641 rcd
->egrbufs
.buffers
[idx
].len
=
1642 rcd
->egrbufs
.rcvtid_size
;
1643 rcd
->egrbufs
.rcvtids
[rcd
->egrbufs
.alloced
].addr
=
1644 rcd
->egrbufs
.buffers
[idx
].addr
;
1645 rcd
->egrbufs
.rcvtids
[rcd
->egrbufs
.alloced
].phys
=
1646 rcd
->egrbufs
.buffers
[idx
].phys
;
1647 rcd
->egrbufs
.alloced
++;
1648 alloced_bytes
+= rcd
->egrbufs
.rcvtid_size
;
1655 * Fail the eager buffer allocation if:
1656 * - we are already using the lowest acceptable size
1657 * - we are using one-pkt-per-egr-buffer (this implies
1658 * that we are accepting only one size)
1660 if (rcd
->egrbufs
.rcvtid_size
== round_mtu
||
1661 !HFI1_CAP_KGET_MASK(rcd
->flags
, MULTI_PKT_EGR
)) {
1662 dd_dev_err(dd
, "ctxt%u: Failed to allocate eager buffers\n",
1664 goto bail_rcvegrbuf_phys
;
1667 new_size
= rcd
->egrbufs
.rcvtid_size
/ 2;
1670 * If the first attempt to allocate memory failed, don't
1671 * fail everything but continue with the next lower
1675 rcd
->egrbufs
.rcvtid_size
= new_size
;
1680 * Re-partition already allocated buffers to a smaller
1683 rcd
->egrbufs
.alloced
= 0;
1684 for (i
= 0, j
= 0, offset
= 0; j
< idx
; i
++) {
1685 if (i
>= rcd
->egrbufs
.count
)
1687 rcd
->egrbufs
.rcvtids
[i
].phys
=
1688 rcd
->egrbufs
.buffers
[j
].phys
+ offset
;
1689 rcd
->egrbufs
.rcvtids
[i
].addr
=
1690 rcd
->egrbufs
.buffers
[j
].addr
+ offset
;
1691 rcd
->egrbufs
.alloced
++;
1692 if ((rcd
->egrbufs
.buffers
[j
].phys
+ offset
+
1694 (rcd
->egrbufs
.buffers
[j
].phys
+
1695 rcd
->egrbufs
.buffers
[j
].len
)) {
1701 rcd
->egrbufs
.rcvtid_size
= new_size
;
1704 rcd
->egrbufs
.numbufs
= idx
;
1705 rcd
->egrbufs
.size
= alloced_bytes
;
1708 "ctxt%u: Alloced %u rcv tid entries @ %uKB, total %zuKB\n",
1709 rcd
->ctxt
, rcd
->egrbufs
.alloced
, rcd
->egrbufs
.rcvtid_size
,
1714 * Set the contexts rcv array head update threshold to the closest
1715 * power of 2 (so we can use a mask instead of modulo) below half
1716 * the allocated entries.
1718 rcd
->egrbufs
.threshold
=
1719 rounddown_pow_of_two(rcd
->egrbufs
.alloced
/ 2);
1721 * Compute the expected RcvArray entry base. This is done after
1722 * allocating the eager buffers in order to maximize the
1723 * expected RcvArray entries for the context.
1725 max_entries
= rcd
->rcv_array_groups
* dd
->rcv_entries
.group_size
;
1726 egrtop
= roundup(rcd
->egrbufs
.alloced
, dd
->rcv_entries
.group_size
);
1727 rcd
->expected_count
= max_entries
- egrtop
;
1728 if (rcd
->expected_count
> MAX_TID_PAIR_ENTRIES
* 2)
1729 rcd
->expected_count
= MAX_TID_PAIR_ENTRIES
* 2;
1731 rcd
->expected_base
= rcd
->eager_base
+ egrtop
;
1732 hfi1_cdbg(PROC
, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u\n",
1733 rcd
->ctxt
, rcd
->egrbufs
.alloced
, rcd
->expected_count
,
1734 rcd
->eager_base
, rcd
->expected_base
);
1736 if (!hfi1_rcvbuf_validate(rcd
->egrbufs
.rcvtid_size
, PT_EAGER
, &order
)) {
1738 "ctxt%u: current Eager buffer size is invalid %u\n",
1739 rcd
->ctxt
, rcd
->egrbufs
.rcvtid_size
);
1744 for (idx
= 0; idx
< rcd
->egrbufs
.alloced
; idx
++) {
1745 hfi1_put_tid(dd
, rcd
->eager_base
+ idx
, PT_EAGER
,
1746 rcd
->egrbufs
.rcvtids
[idx
].phys
, order
);
1751 bail_rcvegrbuf_phys
:
1752 for (idx
= 0; idx
< rcd
->egrbufs
.alloced
&&
1753 rcd
->egrbufs
.buffers
[idx
].addr
;
1755 dma_free_coherent(&dd
->pcidev
->dev
,
1756 rcd
->egrbufs
.buffers
[idx
].len
,
1757 rcd
->egrbufs
.buffers
[idx
].addr
,
1758 rcd
->egrbufs
.buffers
[idx
].phys
);
1759 rcd
->egrbufs
.buffers
[idx
].addr
= NULL
;
1760 rcd
->egrbufs
.buffers
[idx
].phys
= 0;
1761 rcd
->egrbufs
.buffers
[idx
].len
= 0;