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1 /*
2 * Copyright(c) 2015, 2016 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48 #include "hfi.h"
49 #include "efivar.h"
50
51 void get_platform_config(struct hfi1_devdata *dd)
52 {
53 int ret = 0;
54 unsigned long size = 0;
55 u8 *temp_platform_config = NULL;
56
57 ret = read_hfi1_efi_var(dd, "configuration", &size,
58 (void **)&temp_platform_config);
59 if (ret) {
60 dd_dev_info(dd,
61 "%s: Failed to get platform config from UEFI, falling back to request firmware\n",
62 __func__);
63 /* fall back to request firmware */
64 platform_config_load = 1;
65 goto bail;
66 }
67
68 dd->platform_config.data = temp_platform_config;
69 dd->platform_config.size = size;
70
71 bail:
72 /* exit */;
73 }
74
75 void free_platform_config(struct hfi1_devdata *dd)
76 {
77 if (!platform_config_load) {
78 /*
79 * was loaded from EFI, release memory
80 * allocated by read_efi_var
81 */
82 kfree(dd->platform_config.data);
83 }
84 /*
85 * else do nothing, dispose_firmware will release
86 * struct firmware platform_config on driver exit
87 */
88 }
89
90 int set_qsfp_tx(struct hfi1_pportdata *ppd, int on)
91 {
92 u8 tx_ctrl_byte = on ? 0x0 : 0xF;
93 int ret = 0;
94
95 ret = qsfp_write(ppd, ppd->dd->hfi1_id, QSFP_TX_CTRL_BYTE_OFFS,
96 &tx_ctrl_byte, 1);
97 /* we expected 1, so consider 0 an error */
98 if (ret == 0)
99 ret = -EIO;
100 else if (ret == 1)
101 ret = 0;
102 return ret;
103 }
104
105 static int qual_power(struct hfi1_pportdata *ppd)
106 {
107 u32 cable_power_class = 0, power_class_max = 0;
108 u8 *cache = ppd->qsfp_info.cache;
109 int ret = 0;
110
111 ret = get_platform_config_field(
112 ppd->dd, PLATFORM_CONFIG_SYSTEM_TABLE, 0,
113 SYSTEM_TABLE_QSFP_POWER_CLASS_MAX, &power_class_max, 4);
114 if (ret)
115 return ret;
116
117 cable_power_class = get_qsfp_power_class(cache[QSFP_MOD_PWR_OFFS]);
118
119 if (cable_power_class > power_class_max)
120 ppd->offline_disabled_reason =
121 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_POWER_POLICY);
122
123 if (ppd->offline_disabled_reason ==
124 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_POWER_POLICY)) {
125 dd_dev_info(
126 ppd->dd,
127 "%s: Port disabled due to system power restrictions\n",
128 __func__);
129 ret = -EPERM;
130 }
131 return ret;
132 }
133
134 static int qual_bitrate(struct hfi1_pportdata *ppd)
135 {
136 u16 lss = ppd->link_speed_supported, lse = ppd->link_speed_enabled;
137 u8 *cache = ppd->qsfp_info.cache;
138
139 if ((lss & OPA_LINK_SPEED_25G) && (lse & OPA_LINK_SPEED_25G) &&
140 cache[QSFP_NOM_BIT_RATE_250_OFFS] < 0x64)
141 ppd->offline_disabled_reason =
142 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_LINKSPEED_POLICY);
143
144 if ((lss & OPA_LINK_SPEED_12_5G) && (lse & OPA_LINK_SPEED_12_5G) &&
145 cache[QSFP_NOM_BIT_RATE_100_OFFS] < 0x7D)
146 ppd->offline_disabled_reason =
147 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_LINKSPEED_POLICY);
148
149 if (ppd->offline_disabled_reason ==
150 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_LINKSPEED_POLICY)) {
151 dd_dev_info(
152 ppd->dd,
153 "%s: Cable failed bitrate check, disabling port\n",
154 __func__);
155 return -EPERM;
156 }
157 return 0;
158 }
159
160 static int set_qsfp_high_power(struct hfi1_pportdata *ppd)
161 {
162 u8 cable_power_class = 0, power_ctrl_byte = 0;
163 u8 *cache = ppd->qsfp_info.cache;
164 int ret;
165
166 cable_power_class = get_qsfp_power_class(cache[QSFP_MOD_PWR_OFFS]);
167
168 if (cable_power_class > QSFP_POWER_CLASS_1) {
169 power_ctrl_byte = cache[QSFP_PWR_CTRL_BYTE_OFFS];
170
171 power_ctrl_byte |= 1;
172 power_ctrl_byte &= ~(0x2);
173
174 ret = qsfp_write(ppd, ppd->dd->hfi1_id,
175 QSFP_PWR_CTRL_BYTE_OFFS,
176 &power_ctrl_byte, 1);
177 if (ret != 1)
178 return -EIO;
179
180 if (cable_power_class > QSFP_POWER_CLASS_4) {
181 power_ctrl_byte |= (1 << 2);
182 ret = qsfp_write(ppd, ppd->dd->hfi1_id,
183 QSFP_PWR_CTRL_BYTE_OFFS,
184 &power_ctrl_byte, 1);
185 if (ret != 1)
186 return -EIO;
187 }
188
189 /* SFF 8679 rev 1.7 LPMode Deassert time */
190 msleep(300);
191 }
192 return 0;
193 }
194
195 static void apply_rx_cdr(struct hfi1_pportdata *ppd,
196 u32 rx_preset_index,
197 u8 *cdr_ctrl_byte)
198 {
199 u32 rx_preset;
200 u8 *cache = ppd->qsfp_info.cache;
201 int cable_power_class;
202
203 if (!((cache[QSFP_MOD_PWR_OFFS] & 0x4) &&
204 (cache[QSFP_CDR_INFO_OFFS] & 0x40)))
205 return;
206
207 /* RX CDR present, bypass supported */
208 cable_power_class = get_qsfp_power_class(cache[QSFP_MOD_PWR_OFFS]);
209
210 if (cable_power_class <= QSFP_POWER_CLASS_3) {
211 /* Power class <= 3, ignore config & turn RX CDR on */
212 *cdr_ctrl_byte |= 0xF;
213 return;
214 }
215
216 get_platform_config_field(
217 ppd->dd, PLATFORM_CONFIG_RX_PRESET_TABLE,
218 rx_preset_index, RX_PRESET_TABLE_QSFP_RX_CDR_APPLY,
219 &rx_preset, 4);
220
221 if (!rx_preset) {
222 dd_dev_info(
223 ppd->dd,
224 "%s: RX_CDR_APPLY is set to disabled\n",
225 __func__);
226 return;
227 }
228 get_platform_config_field(
229 ppd->dd, PLATFORM_CONFIG_RX_PRESET_TABLE,
230 rx_preset_index, RX_PRESET_TABLE_QSFP_RX_CDR,
231 &rx_preset, 4);
232
233 /* Expand cdr setting to all 4 lanes */
234 rx_preset = (rx_preset | (rx_preset << 1) |
235 (rx_preset << 2) | (rx_preset << 3));
236
237 if (rx_preset) {
238 *cdr_ctrl_byte |= rx_preset;
239 } else {
240 *cdr_ctrl_byte &= rx_preset;
241 /* Preserve current TX CDR status */
242 *cdr_ctrl_byte |= (cache[QSFP_CDR_CTRL_BYTE_OFFS] & 0xF0);
243 }
244 }
245
246 static void apply_tx_cdr(struct hfi1_pportdata *ppd,
247 u32 tx_preset_index,
248 u8 *cdr_ctrl_byte)
249 {
250 u32 tx_preset;
251 u8 *cache = ppd->qsfp_info.cache;
252 int cable_power_class;
253
254 if (!((cache[QSFP_MOD_PWR_OFFS] & 0x8) &&
255 (cache[QSFP_CDR_INFO_OFFS] & 0x80)))
256 return;
257
258 /* TX CDR present, bypass supported */
259 cable_power_class = get_qsfp_power_class(cache[QSFP_MOD_PWR_OFFS]);
260
261 if (cable_power_class <= QSFP_POWER_CLASS_3) {
262 /* Power class <= 3, ignore config & turn TX CDR on */
263 *cdr_ctrl_byte |= 0xF0;
264 return;
265 }
266
267 get_platform_config_field(
268 ppd->dd,
269 PLATFORM_CONFIG_TX_PRESET_TABLE, tx_preset_index,
270 TX_PRESET_TABLE_QSFP_TX_CDR_APPLY, &tx_preset, 4);
271
272 if (!tx_preset) {
273 dd_dev_info(
274 ppd->dd,
275 "%s: TX_CDR_APPLY is set to disabled\n",
276 __func__);
277 return;
278 }
279 get_platform_config_field(
280 ppd->dd,
281 PLATFORM_CONFIG_TX_PRESET_TABLE,
282 tx_preset_index,
283 TX_PRESET_TABLE_QSFP_TX_CDR, &tx_preset, 4);
284
285 /* Expand cdr setting to all 4 lanes */
286 tx_preset = (tx_preset | (tx_preset << 1) |
287 (tx_preset << 2) | (tx_preset << 3));
288
289 if (tx_preset)
290 *cdr_ctrl_byte |= (tx_preset << 4);
291 else
292 /* Preserve current/determined RX CDR status */
293 *cdr_ctrl_byte &= ((tx_preset << 4) | 0xF);
294 }
295
296 static void apply_cdr_settings(
297 struct hfi1_pportdata *ppd, u32 rx_preset_index,
298 u32 tx_preset_index)
299 {
300 u8 *cache = ppd->qsfp_info.cache;
301 u8 cdr_ctrl_byte = cache[QSFP_CDR_CTRL_BYTE_OFFS];
302
303 apply_rx_cdr(ppd, rx_preset_index, &cdr_ctrl_byte);
304
305 apply_tx_cdr(ppd, tx_preset_index, &cdr_ctrl_byte);
306
307 qsfp_write(ppd, ppd->dd->hfi1_id, QSFP_CDR_CTRL_BYTE_OFFS,
308 &cdr_ctrl_byte, 1);
309 }
310
311 static void apply_tx_eq_auto(struct hfi1_pportdata *ppd)
312 {
313 u8 *cache = ppd->qsfp_info.cache;
314 u8 tx_eq;
315
316 if (!(cache[QSFP_EQ_INFO_OFFS] & 0x8))
317 return;
318 /* Disable adaptive TX EQ if present */
319 tx_eq = cache[(128 * 3) + 241];
320 tx_eq &= 0xF0;
321 qsfp_write(ppd, ppd->dd->hfi1_id, (256 * 3) + 241, &tx_eq, 1);
322 }
323
324 static void apply_tx_eq_prog(struct hfi1_pportdata *ppd, u32 tx_preset_index)
325 {
326 u8 *cache = ppd->qsfp_info.cache;
327 u32 tx_preset;
328 u8 tx_eq;
329
330 if (!(cache[QSFP_EQ_INFO_OFFS] & 0x4))
331 return;
332
333 get_platform_config_field(
334 ppd->dd, PLATFORM_CONFIG_TX_PRESET_TABLE,
335 tx_preset_index, TX_PRESET_TABLE_QSFP_TX_EQ_APPLY,
336 &tx_preset, 4);
337 if (!tx_preset) {
338 dd_dev_info(
339 ppd->dd,
340 "%s: TX_EQ_APPLY is set to disabled\n",
341 __func__);
342 return;
343 }
344 get_platform_config_field(
345 ppd->dd, PLATFORM_CONFIG_TX_PRESET_TABLE,
346 tx_preset_index, TX_PRESET_TABLE_QSFP_TX_EQ,
347 &tx_preset, 4);
348
349 if (((cache[(128 * 3) + 224] & 0xF0) >> 4) < tx_preset) {
350 dd_dev_info(
351 ppd->dd,
352 "%s: TX EQ %x unsupported\n",
353 __func__, tx_preset);
354
355 dd_dev_info(
356 ppd->dd,
357 "%s: Applying EQ %x\n",
358 __func__, cache[608] & 0xF0);
359
360 tx_preset = (cache[608] & 0xF0) >> 4;
361 }
362
363 tx_eq = tx_preset | (tx_preset << 4);
364 qsfp_write(ppd, ppd->dd->hfi1_id, (256 * 3) + 234, &tx_eq, 1);
365 qsfp_write(ppd, ppd->dd->hfi1_id, (256 * 3) + 235, &tx_eq, 1);
366 }
367
368 static void apply_rx_eq_emp(struct hfi1_pportdata *ppd, u32 rx_preset_index)
369 {
370 u32 rx_preset;
371 u8 rx_eq, *cache = ppd->qsfp_info.cache;
372
373 if (!(cache[QSFP_EQ_INFO_OFFS] & 0x2))
374 return;
375 get_platform_config_field(
376 ppd->dd, PLATFORM_CONFIG_RX_PRESET_TABLE,
377 rx_preset_index, RX_PRESET_TABLE_QSFP_RX_EMP_APPLY,
378 &rx_preset, 4);
379
380 if (!rx_preset) {
381 dd_dev_info(
382 ppd->dd,
383 "%s: RX_EMP_APPLY is set to disabled\n",
384 __func__);
385 return;
386 }
387 get_platform_config_field(
388 ppd->dd, PLATFORM_CONFIG_RX_PRESET_TABLE,
389 rx_preset_index, RX_PRESET_TABLE_QSFP_RX_EMP,
390 &rx_preset, 4);
391
392 if ((cache[(128 * 3) + 224] & 0xF) < rx_preset) {
393 dd_dev_info(
394 ppd->dd,
395 "%s: Requested RX EMP %x\n",
396 __func__, rx_preset);
397
398 dd_dev_info(
399 ppd->dd,
400 "%s: Applying supported EMP %x\n",
401 __func__, cache[608] & 0xF);
402
403 rx_preset = cache[608] & 0xF;
404 }
405
406 rx_eq = rx_preset | (rx_preset << 4);
407
408 qsfp_write(ppd, ppd->dd->hfi1_id, (256 * 3) + 236, &rx_eq, 1);
409 qsfp_write(ppd, ppd->dd->hfi1_id, (256 * 3) + 237, &rx_eq, 1);
410 }
411
412 static void apply_eq_settings(struct hfi1_pportdata *ppd,
413 u32 rx_preset_index, u32 tx_preset_index)
414 {
415 u8 *cache = ppd->qsfp_info.cache;
416
417 /* no point going on w/o a page 3 */
418 if (cache[2] & 4) {
419 dd_dev_info(ppd->dd,
420 "%s: Upper page 03 not present\n",
421 __func__);
422 return;
423 }
424
425 apply_tx_eq_auto(ppd);
426
427 apply_tx_eq_prog(ppd, tx_preset_index);
428
429 apply_rx_eq_emp(ppd, rx_preset_index);
430 }
431
432 static void apply_rx_amplitude_settings(
433 struct hfi1_pportdata *ppd, u32 rx_preset_index,
434 u32 tx_preset_index)
435 {
436 u32 rx_preset;
437 u8 rx_amp = 0, i = 0, preferred = 0, *cache = ppd->qsfp_info.cache;
438
439 /* no point going on w/o a page 3 */
440 if (cache[2] & 4) {
441 dd_dev_info(ppd->dd,
442 "%s: Upper page 03 not present\n",
443 __func__);
444 return;
445 }
446 if (!(cache[QSFP_EQ_INFO_OFFS] & 0x1)) {
447 dd_dev_info(ppd->dd,
448 "%s: RX_AMP_APPLY is set to disabled\n",
449 __func__);
450 return;
451 }
452
453 get_platform_config_field(ppd->dd,
454 PLATFORM_CONFIG_RX_PRESET_TABLE,
455 rx_preset_index,
456 RX_PRESET_TABLE_QSFP_RX_AMP_APPLY,
457 &rx_preset, 4);
458
459 if (!rx_preset) {
460 dd_dev_info(ppd->dd,
461 "%s: RX_AMP_APPLY is set to disabled\n",
462 __func__);
463 return;
464 }
465 get_platform_config_field(ppd->dd,
466 PLATFORM_CONFIG_RX_PRESET_TABLE,
467 rx_preset_index,
468 RX_PRESET_TABLE_QSFP_RX_AMP,
469 &rx_preset, 4);
470
471 dd_dev_info(ppd->dd,
472 "%s: Requested RX AMP %x\n",
473 __func__,
474 rx_preset);
475
476 for (i = 0; i < 4; i++) {
477 if (cache[(128 * 3) + 225] & (1 << i)) {
478 preferred = i;
479 if (preferred == rx_preset)
480 break;
481 }
482 }
483
484 /*
485 * Verify that preferred RX amplitude is not just a
486 * fall through of the default
487 */
488 if (!preferred && !(cache[(128 * 3) + 225] & 0x1)) {
489 dd_dev_info(ppd->dd, "No supported RX AMP, not applying\n");
490 return;
491 }
492
493 dd_dev_info(ppd->dd,
494 "%s: Applying RX AMP %x\n", __func__, preferred);
495
496 rx_amp = preferred | (preferred << 4);
497 qsfp_write(ppd, ppd->dd->hfi1_id, (256 * 3) + 238, &rx_amp, 1);
498 qsfp_write(ppd, ppd->dd->hfi1_id, (256 * 3) + 239, &rx_amp, 1);
499 }
500
501 #define OPA_INVALID_INDEX 0xFFF
502
503 static void apply_tx_lanes(struct hfi1_pportdata *ppd, u8 field_id,
504 u32 config_data, const char *message)
505 {
506 u8 i;
507 int ret = HCMD_SUCCESS;
508
509 for (i = 0; i < 4; i++) {
510 ret = load_8051_config(ppd->dd, field_id, i, config_data);
511 if (ret != HCMD_SUCCESS) {
512 dd_dev_err(
513 ppd->dd,
514 "%s: %s for lane %u failed\n",
515 message, __func__, i);
516 }
517 }
518 }
519
520 static void apply_tunings(
521 struct hfi1_pportdata *ppd, u32 tx_preset_index,
522 u8 tuning_method, u32 total_atten, u8 limiting_active)
523 {
524 int ret = 0;
525 u32 config_data = 0, tx_preset = 0;
526 u8 precur = 0, attn = 0, postcur = 0, external_device_config = 0;
527 u8 *cache = ppd->qsfp_info.cache;
528
529 /* Enable external device config if channel is limiting active */
530 read_8051_config(ppd->dd, LINK_OPTIMIZATION_SETTINGS,
531 GENERAL_CONFIG, &config_data);
532 config_data |= limiting_active;
533 ret = load_8051_config(ppd->dd, LINK_OPTIMIZATION_SETTINGS,
534 GENERAL_CONFIG, config_data);
535 if (ret != HCMD_SUCCESS)
536 dd_dev_err(
537 ppd->dd,
538 "%s: Failed to set enable external device config\n",
539 __func__);
540
541 config_data = 0; /* re-init */
542 /* Pass tuning method to 8051 */
543 read_8051_config(ppd->dd, LINK_TUNING_PARAMETERS, GENERAL_CONFIG,
544 &config_data);
545 config_data |= tuning_method;
546 ret = load_8051_config(ppd->dd, LINK_TUNING_PARAMETERS, GENERAL_CONFIG,
547 config_data);
548 if (ret != HCMD_SUCCESS)
549 dd_dev_err(ppd->dd, "%s: Failed to set tuning method\n",
550 __func__);
551
552 /* Set same channel loss for both TX and RX */
553 config_data = 0 | (total_atten << 16) | (total_atten << 24);
554 apply_tx_lanes(ppd, CHANNEL_LOSS_SETTINGS, config_data,
555 "Setting channel loss");
556
557 /* Inform 8051 of cable capabilities */
558 if (ppd->qsfp_info.cache_valid) {
559 external_device_config =
560 ((cache[QSFP_MOD_PWR_OFFS] & 0x4) << 3) |
561 ((cache[QSFP_MOD_PWR_OFFS] & 0x8) << 2) |
562 ((cache[QSFP_EQ_INFO_OFFS] & 0x2) << 1) |
563 (cache[QSFP_EQ_INFO_OFFS] & 0x4);
564 ret = read_8051_config(ppd->dd, DC_HOST_COMM_SETTINGS,
565 GENERAL_CONFIG, &config_data);
566 /* Clear, then set the external device config field */
567 config_data &= ~(0xFF << 24);
568 config_data |= (external_device_config << 24);
569 ret = load_8051_config(ppd->dd, DC_HOST_COMM_SETTINGS,
570 GENERAL_CONFIG, config_data);
571 if (ret != HCMD_SUCCESS)
572 dd_dev_info(ppd->dd,
573 "%s: Failed set ext device config params\n",
574 __func__);
575 }
576
577 if (tx_preset_index == OPA_INVALID_INDEX) {
578 if (ppd->port_type == PORT_TYPE_QSFP && limiting_active)
579 dd_dev_info(ppd->dd, "%s: Invalid Tx preset index\n",
580 __func__);
581 return;
582 }
583
584 /* Following for limiting active channels only */
585 get_platform_config_field(
586 ppd->dd, PLATFORM_CONFIG_TX_PRESET_TABLE, tx_preset_index,
587 TX_PRESET_TABLE_PRECUR, &tx_preset, 4);
588 precur = tx_preset;
589
590 get_platform_config_field(
591 ppd->dd, PLATFORM_CONFIG_TX_PRESET_TABLE,
592 tx_preset_index, TX_PRESET_TABLE_ATTN, &tx_preset, 4);
593 attn = tx_preset;
594
595 get_platform_config_field(
596 ppd->dd, PLATFORM_CONFIG_TX_PRESET_TABLE,
597 tx_preset_index, TX_PRESET_TABLE_POSTCUR, &tx_preset, 4);
598 postcur = tx_preset;
599
600 config_data = precur | (attn << 8) | (postcur << 16);
601
602 apply_tx_lanes(ppd, TX_EQ_SETTINGS, config_data,
603 "Applying TX settings");
604 }
605
606 /* Must be holding the QSFP i2c resource */
607 static int tune_active_qsfp(struct hfi1_pportdata *ppd, u32 *ptr_tx_preset,
608 u32 *ptr_rx_preset, u32 *ptr_total_atten)
609 {
610 int ret;
611 u16 lss = ppd->link_speed_supported, lse = ppd->link_speed_enabled;
612 u8 *cache = ppd->qsfp_info.cache;
613
614 ppd->qsfp_info.limiting_active = 1;
615
616 ret = set_qsfp_tx(ppd, 0);
617 if (ret)
618 return ret;
619
620 ret = qual_power(ppd);
621 if (ret)
622 return ret;
623
624 ret = qual_bitrate(ppd);
625 if (ret)
626 return ret;
627
628 if (ppd->qsfp_info.reset_needed) {
629 reset_qsfp(ppd);
630 ppd->qsfp_info.reset_needed = 0;
631 refresh_qsfp_cache(ppd, &ppd->qsfp_info);
632 } else {
633 ppd->qsfp_info.reset_needed = 1;
634 }
635
636 ret = set_qsfp_high_power(ppd);
637 if (ret)
638 return ret;
639
640 if (cache[QSFP_EQ_INFO_OFFS] & 0x4) {
641 ret = get_platform_config_field(
642 ppd->dd,
643 PLATFORM_CONFIG_PORT_TABLE, 0,
644 PORT_TABLE_TX_PRESET_IDX_ACTIVE_EQ,
645 ptr_tx_preset, 4);
646 if (ret) {
647 *ptr_tx_preset = OPA_INVALID_INDEX;
648 return ret;
649 }
650 } else {
651 ret = get_platform_config_field(
652 ppd->dd,
653 PLATFORM_CONFIG_PORT_TABLE, 0,
654 PORT_TABLE_TX_PRESET_IDX_ACTIVE_NO_EQ,
655 ptr_tx_preset, 4);
656 if (ret) {
657 *ptr_tx_preset = OPA_INVALID_INDEX;
658 return ret;
659 }
660 }
661
662 ret = get_platform_config_field(
663 ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0,
664 PORT_TABLE_RX_PRESET_IDX, ptr_rx_preset, 4);
665 if (ret) {
666 *ptr_rx_preset = OPA_INVALID_INDEX;
667 return ret;
668 }
669
670 if ((lss & OPA_LINK_SPEED_25G) && (lse & OPA_LINK_SPEED_25G))
671 get_platform_config_field(
672 ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0,
673 PORT_TABLE_LOCAL_ATTEN_25G, ptr_total_atten, 4);
674 else if ((lss & OPA_LINK_SPEED_12_5G) && (lse & OPA_LINK_SPEED_12_5G))
675 get_platform_config_field(
676 ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0,
677 PORT_TABLE_LOCAL_ATTEN_12G, ptr_total_atten, 4);
678
679 apply_cdr_settings(ppd, *ptr_rx_preset, *ptr_tx_preset);
680
681 apply_eq_settings(ppd, *ptr_rx_preset, *ptr_tx_preset);
682
683 apply_rx_amplitude_settings(ppd, *ptr_rx_preset, *ptr_tx_preset);
684
685 ret = set_qsfp_tx(ppd, 1);
686
687 return ret;
688 }
689
690 static int tune_qsfp(struct hfi1_pportdata *ppd,
691 u32 *ptr_tx_preset, u32 *ptr_rx_preset,
692 u8 *ptr_tuning_method, u32 *ptr_total_atten)
693 {
694 u32 cable_atten = 0, remote_atten = 0, platform_atten = 0;
695 u16 lss = ppd->link_speed_supported, lse = ppd->link_speed_enabled;
696 int ret = 0;
697 u8 *cache = ppd->qsfp_info.cache;
698
699 switch ((cache[QSFP_MOD_TECH_OFFS] & 0xF0) >> 4) {
700 case 0xA ... 0xB:
701 ret = get_platform_config_field(
702 ppd->dd,
703 PLATFORM_CONFIG_PORT_TABLE, 0,
704 PORT_TABLE_LOCAL_ATTEN_25G,
705 &platform_atten, 4);
706 if (ret)
707 return ret;
708
709 if ((lss & OPA_LINK_SPEED_25G) && (lse & OPA_LINK_SPEED_25G))
710 cable_atten = cache[QSFP_CU_ATTEN_12G_OFFS];
711 else if ((lss & OPA_LINK_SPEED_12_5G) &&
712 (lse & OPA_LINK_SPEED_12_5G))
713 cable_atten = cache[QSFP_CU_ATTEN_7G_OFFS];
714
715 /* Fallback to configured attenuation if cable memory is bad */
716 if (cable_atten == 0 || cable_atten > 36) {
717 ret = get_platform_config_field(
718 ppd->dd,
719 PLATFORM_CONFIG_SYSTEM_TABLE, 0,
720 SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G,
721 &cable_atten, 4);
722 if (ret)
723 return ret;
724 }
725
726 ret = get_platform_config_field(
727 ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0,
728 PORT_TABLE_REMOTE_ATTEN_25G, &remote_atten, 4);
729 if (ret)
730 return ret;
731
732 *ptr_total_atten = platform_atten + cable_atten + remote_atten;
733
734 *ptr_tuning_method = OPA_PASSIVE_TUNING;
735 break;
736 case 0x0 ... 0x9: /* fallthrough */
737 case 0xC: /* fallthrough */
738 case 0xE:
739 ret = tune_active_qsfp(ppd, ptr_tx_preset, ptr_rx_preset,
740 ptr_total_atten);
741 if (ret)
742 return ret;
743
744 *ptr_tuning_method = OPA_ACTIVE_TUNING;
745 break;
746 case 0xD: /* fallthrough */
747 case 0xF:
748 default:
749 dd_dev_info(ppd->dd, "%s: Unknown/unsupported cable\n",
750 __func__);
751 break;
752 }
753 return ret;
754 }
755
756 /*
757 * This function communicates its success or failure via ppd->driver_link_ready
758 * Thus, it depends on its association with start_link(...) which checks
759 * driver_link_ready before proceeding with the link negotiation and
760 * initialization process.
761 */
762 void tune_serdes(struct hfi1_pportdata *ppd)
763 {
764 int ret = 0;
765 u32 total_atten = 0;
766 u32 remote_atten = 0, platform_atten = 0;
767 u32 rx_preset_index, tx_preset_index;
768 u8 tuning_method = 0, limiting_active = 0;
769 struct hfi1_devdata *dd = ppd->dd;
770
771 rx_preset_index = OPA_INVALID_INDEX;
772 tx_preset_index = OPA_INVALID_INDEX;
773
774 /* the link defaults to enabled */
775 ppd->link_enabled = 1;
776 /* the driver link ready state defaults to not ready */
777 ppd->driver_link_ready = 0;
778 ppd->offline_disabled_reason = HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE);
779
780 /* Skip the tuning for testing (loopback != none) and simulations */
781 if (loopback != LOOPBACK_NONE ||
782 ppd->dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
783 ppd->driver_link_ready = 1;
784 return;
785 }
786
787 ret = get_platform_config_field(ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0,
788 PORT_TABLE_PORT_TYPE, &ppd->port_type,
789 4);
790 if (ret)
791 ppd->port_type = PORT_TYPE_UNKNOWN;
792
793 switch (ppd->port_type) {
794 case PORT_TYPE_DISCONNECTED:
795 ppd->offline_disabled_reason =
796 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_DISCONNECTED);
797 dd_dev_info(dd, "%s: Port disconnected, disabling port\n",
798 __func__);
799 goto bail;
800 case PORT_TYPE_FIXED:
801 /* platform_atten, remote_atten pre-zeroed to catch error */
802 get_platform_config_field(
803 ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0,
804 PORT_TABLE_LOCAL_ATTEN_25G, &platform_atten, 4);
805
806 get_platform_config_field(
807 ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0,
808 PORT_TABLE_REMOTE_ATTEN_25G, &remote_atten, 4);
809
810 total_atten = platform_atten + remote_atten;
811
812 tuning_method = OPA_PASSIVE_TUNING;
813 break;
814 case PORT_TYPE_VARIABLE:
815 if (qsfp_mod_present(ppd)) {
816 /*
817 * platform_atten, remote_atten pre-zeroed to
818 * catch error
819 */
820 get_platform_config_field(
821 ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0,
822 PORT_TABLE_LOCAL_ATTEN_25G,
823 &platform_atten, 4);
824
825 get_platform_config_field(
826 ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0,
827 PORT_TABLE_REMOTE_ATTEN_25G,
828 &remote_atten, 4);
829
830 total_atten = platform_atten + remote_atten;
831
832 tuning_method = OPA_PASSIVE_TUNING;
833 } else {
834 ppd->offline_disabled_reason =
835 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_CHASSIS_CONFIG);
836 goto bail;
837 }
838 break;
839 case PORT_TYPE_QSFP:
840 if (qsfp_mod_present(ppd)) {
841 ret = acquire_chip_resource(ppd->dd,
842 qsfp_resource(ppd->dd),
843 QSFP_WAIT);
844 if (ret) {
845 dd_dev_err(ppd->dd, "%s: hfi%d: cannot lock i2c chain\n",
846 __func__, (int)ppd->dd->hfi1_id);
847 goto bail;
848 }
849 refresh_qsfp_cache(ppd, &ppd->qsfp_info);
850
851 if (ppd->qsfp_info.cache_valid) {
852 ret = tune_qsfp(ppd,
853 &tx_preset_index,
854 &rx_preset_index,
855 &tuning_method,
856 &total_atten);
857
858 /*
859 * We may have modified the QSFP memory, so
860 * update the cache to reflect the changes
861 */
862 refresh_qsfp_cache(ppd, &ppd->qsfp_info);
863 limiting_active =
864 ppd->qsfp_info.limiting_active;
865 } else {
866 dd_dev_err(dd,
867 "%s: Reading QSFP memory failed\n",
868 __func__);
869 ret = -EINVAL; /* a fail indication */
870 }
871 release_chip_resource(ppd->dd, qsfp_resource(ppd->dd));
872 if (ret)
873 goto bail;
874 } else {
875 ppd->offline_disabled_reason =
876 HFI1_ODR_MASK(
877 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED);
878 goto bail;
879 }
880 break;
881 default:
882 dd_dev_info(ppd->dd, "%s: Unknown port type\n", __func__);
883 ppd->port_type = PORT_TYPE_UNKNOWN;
884 tuning_method = OPA_UNKNOWN_TUNING;
885 total_atten = 0;
886 limiting_active = 0;
887 tx_preset_index = OPA_INVALID_INDEX;
888 break;
889 }
890
891 if (ppd->offline_disabled_reason ==
892 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE))
893 apply_tunings(ppd, tx_preset_index, tuning_method,
894 total_atten, limiting_active);
895
896 if (!ret)
897 ppd->driver_link_ready = 1;
898
899 return;
900 bail:
901 ppd->driver_link_ready = 0;
902 }