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1 /*
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2015 Intel Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * BSD LICENSE
20 *
21 * Copyright(c) 2015 Intel Corporation.
22 *
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
25 * are met:
26 *
27 * - Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * - Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in
31 * the documentation and/or other materials provided with the
32 * distribution.
33 * - Neither the name of Intel Corporation nor the names of its
34 * contributors may be used to endorse or promote products derived
35 * from this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 */
50
51 #include <linux/spinlock.h>
52
53 #include "hfi.h"
54 #include "mad.h"
55 #include "qp.h"
56 #include "sdma.h"
57
58 /*
59 * Convert the AETH RNR timeout code into the number of microseconds.
60 */
61 const u32 ib_hfi1_rnr_table[32] = {
62 655360, /* 00: 655.36 */
63 10, /* 01: .01 */
64 20, /* 02 .02 */
65 30, /* 03: .03 */
66 40, /* 04: .04 */
67 60, /* 05: .06 */
68 80, /* 06: .08 */
69 120, /* 07: .12 */
70 160, /* 08: .16 */
71 240, /* 09: .24 */
72 320, /* 0A: .32 */
73 480, /* 0B: .48 */
74 640, /* 0C: .64 */
75 960, /* 0D: .96 */
76 1280, /* 0E: 1.28 */
77 1920, /* 0F: 1.92 */
78 2560, /* 10: 2.56 */
79 3840, /* 11: 3.84 */
80 5120, /* 12: 5.12 */
81 7680, /* 13: 7.68 */
82 10240, /* 14: 10.24 */
83 15360, /* 15: 15.36 */
84 20480, /* 16: 20.48 */
85 30720, /* 17: 30.72 */
86 40960, /* 18: 40.96 */
87 61440, /* 19: 61.44 */
88 81920, /* 1A: 81.92 */
89 122880, /* 1B: 122.88 */
90 163840, /* 1C: 163.84 */
91 245760, /* 1D: 245.76 */
92 327680, /* 1E: 327.68 */
93 491520 /* 1F: 491.52 */
94 };
95
96 /*
97 * Validate a RWQE and fill in the SGE state.
98 * Return 1 if OK.
99 */
100 static int init_sge(struct hfi1_qp *qp, struct hfi1_rwqe *wqe)
101 {
102 int i, j, ret;
103 struct ib_wc wc;
104 struct hfi1_lkey_table *rkt;
105 struct hfi1_pd *pd;
106 struct hfi1_sge_state *ss;
107
108 rkt = &to_idev(qp->ibqp.device)->lk_table;
109 pd = to_ipd(qp->ibqp.srq ? qp->ibqp.srq->pd : qp->ibqp.pd);
110 ss = &qp->r_sge;
111 ss->sg_list = qp->r_sg_list;
112 qp->r_len = 0;
113 for (i = j = 0; i < wqe->num_sge; i++) {
114 if (wqe->sg_list[i].length == 0)
115 continue;
116 /* Check LKEY */
117 if (!hfi1_lkey_ok(rkt, pd, j ? &ss->sg_list[j - 1] : &ss->sge,
118 &wqe->sg_list[i], IB_ACCESS_LOCAL_WRITE))
119 goto bad_lkey;
120 qp->r_len += wqe->sg_list[i].length;
121 j++;
122 }
123 ss->num_sge = j;
124 ss->total_len = qp->r_len;
125 ret = 1;
126 goto bail;
127
128 bad_lkey:
129 while (j) {
130 struct hfi1_sge *sge = --j ? &ss->sg_list[j - 1] : &ss->sge;
131
132 hfi1_put_mr(sge->mr);
133 }
134 ss->num_sge = 0;
135 memset(&wc, 0, sizeof(wc));
136 wc.wr_id = wqe->wr_id;
137 wc.status = IB_WC_LOC_PROT_ERR;
138 wc.opcode = IB_WC_RECV;
139 wc.qp = &qp->ibqp;
140 /* Signal solicited completion event. */
141 hfi1_cq_enter(to_icq(qp->ibqp.recv_cq), &wc, 1);
142 ret = 0;
143 bail:
144 return ret;
145 }
146
147 /**
148 * hfi1_get_rwqe - copy the next RWQE into the QP's RWQE
149 * @qp: the QP
150 * @wr_id_only: update qp->r_wr_id only, not qp->r_sge
151 *
152 * Return -1 if there is a local error, 0 if no RWQE is available,
153 * otherwise return 1.
154 *
155 * Can be called from interrupt level.
156 */
157 int hfi1_get_rwqe(struct hfi1_qp *qp, int wr_id_only)
158 {
159 unsigned long flags;
160 struct hfi1_rq *rq;
161 struct hfi1_rwq *wq;
162 struct hfi1_srq *srq;
163 struct hfi1_rwqe *wqe;
164 void (*handler)(struct ib_event *, void *);
165 u32 tail;
166 int ret;
167
168 if (qp->ibqp.srq) {
169 srq = to_isrq(qp->ibqp.srq);
170 handler = srq->ibsrq.event_handler;
171 rq = &srq->rq;
172 } else {
173 srq = NULL;
174 handler = NULL;
175 rq = &qp->r_rq;
176 }
177
178 spin_lock_irqsave(&rq->lock, flags);
179 if (!(ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK)) {
180 ret = 0;
181 goto unlock;
182 }
183
184 wq = rq->wq;
185 tail = wq->tail;
186 /* Validate tail before using it since it is user writable. */
187 if (tail >= rq->size)
188 tail = 0;
189 if (unlikely(tail == wq->head)) {
190 ret = 0;
191 goto unlock;
192 }
193 /* Make sure entry is read after head index is read. */
194 smp_rmb();
195 wqe = get_rwqe_ptr(rq, tail);
196 /*
197 * Even though we update the tail index in memory, the verbs
198 * consumer is not supposed to post more entries until a
199 * completion is generated.
200 */
201 if (++tail >= rq->size)
202 tail = 0;
203 wq->tail = tail;
204 if (!wr_id_only && !init_sge(qp, wqe)) {
205 ret = -1;
206 goto unlock;
207 }
208 qp->r_wr_id = wqe->wr_id;
209
210 ret = 1;
211 set_bit(HFI1_R_WRID_VALID, &qp->r_aflags);
212 if (handler) {
213 u32 n;
214
215 /*
216 * Validate head pointer value and compute
217 * the number of remaining WQEs.
218 */
219 n = wq->head;
220 if (n >= rq->size)
221 n = 0;
222 if (n < tail)
223 n += rq->size - tail;
224 else
225 n -= tail;
226 if (n < srq->limit) {
227 struct ib_event ev;
228
229 srq->limit = 0;
230 spin_unlock_irqrestore(&rq->lock, flags);
231 ev.device = qp->ibqp.device;
232 ev.element.srq = qp->ibqp.srq;
233 ev.event = IB_EVENT_SRQ_LIMIT_REACHED;
234 handler(&ev, srq->ibsrq.srq_context);
235 goto bail;
236 }
237 }
238 unlock:
239 spin_unlock_irqrestore(&rq->lock, flags);
240 bail:
241 return ret;
242 }
243
244 /*
245 * Switch to alternate path.
246 * The QP s_lock should be held and interrupts disabled.
247 */
248 void hfi1_migrate_qp(struct hfi1_qp *qp)
249 {
250 struct ib_event ev;
251
252 qp->s_mig_state = IB_MIG_MIGRATED;
253 qp->remote_ah_attr = qp->alt_ah_attr;
254 qp->port_num = qp->alt_ah_attr.port_num;
255 qp->s_pkey_index = qp->s_alt_pkey_index;
256 qp->s_flags |= HFI1_S_AHG_CLEAR;
257
258 ev.device = qp->ibqp.device;
259 ev.element.qp = &qp->ibqp;
260 ev.event = IB_EVENT_PATH_MIG;
261 qp->ibqp.event_handler(&ev, qp->ibqp.qp_context);
262 }
263
264 static __be64 get_sguid(struct hfi1_ibport *ibp, unsigned index)
265 {
266 if (!index) {
267 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
268
269 return cpu_to_be64(ppd->guid);
270 }
271 return ibp->guids[index - 1];
272 }
273
274 static int gid_ok(union ib_gid *gid, __be64 gid_prefix, __be64 id)
275 {
276 return (gid->global.interface_id == id &&
277 (gid->global.subnet_prefix == gid_prefix ||
278 gid->global.subnet_prefix == IB_DEFAULT_GID_PREFIX));
279 }
280
281 /*
282 *
283 * This should be called with the QP r_lock held.
284 *
285 * The s_lock will be acquired around the hfi1_migrate_qp() call.
286 */
287 int hfi1_ruc_check_hdr(struct hfi1_ibport *ibp, struct hfi1_ib_header *hdr,
288 int has_grh, struct hfi1_qp *qp, u32 bth0)
289 {
290 __be64 guid;
291 unsigned long flags;
292 u8 sc5 = ibp->sl_to_sc[qp->remote_ah_attr.sl];
293
294 if (qp->s_mig_state == IB_MIG_ARMED && (bth0 & IB_BTH_MIG_REQ)) {
295 if (!has_grh) {
296 if (qp->alt_ah_attr.ah_flags & IB_AH_GRH)
297 goto err;
298 } else {
299 if (!(qp->alt_ah_attr.ah_flags & IB_AH_GRH))
300 goto err;
301 guid = get_sguid(ibp, qp->alt_ah_attr.grh.sgid_index);
302 if (!gid_ok(&hdr->u.l.grh.dgid, ibp->gid_prefix, guid))
303 goto err;
304 if (!gid_ok(&hdr->u.l.grh.sgid,
305 qp->alt_ah_attr.grh.dgid.global.subnet_prefix,
306 qp->alt_ah_attr.grh.dgid.global.interface_id))
307 goto err;
308 }
309 if (unlikely(rcv_pkey_check(ppd_from_ibp(ibp), (u16)bth0,
310 sc5, be16_to_cpu(hdr->lrh[3])))) {
311 hfi1_bad_pqkey(ibp, IB_NOTICE_TRAP_BAD_PKEY,
312 (u16)bth0,
313 (be16_to_cpu(hdr->lrh[0]) >> 4) & 0xF,
314 0, qp->ibqp.qp_num,
315 hdr->lrh[3], hdr->lrh[1]);
316 goto err;
317 }
318 /* Validate the SLID. See Ch. 9.6.1.5 and 17.2.8 */
319 if (be16_to_cpu(hdr->lrh[3]) != qp->alt_ah_attr.dlid ||
320 ppd_from_ibp(ibp)->port != qp->alt_ah_attr.port_num)
321 goto err;
322 spin_lock_irqsave(&qp->s_lock, flags);
323 hfi1_migrate_qp(qp);
324 spin_unlock_irqrestore(&qp->s_lock, flags);
325 } else {
326 if (!has_grh) {
327 if (qp->remote_ah_attr.ah_flags & IB_AH_GRH)
328 goto err;
329 } else {
330 if (!(qp->remote_ah_attr.ah_flags & IB_AH_GRH))
331 goto err;
332 guid = get_sguid(ibp,
333 qp->remote_ah_attr.grh.sgid_index);
334 if (!gid_ok(&hdr->u.l.grh.dgid, ibp->gid_prefix, guid))
335 goto err;
336 if (!gid_ok(&hdr->u.l.grh.sgid,
337 qp->remote_ah_attr.grh.dgid.global.subnet_prefix,
338 qp->remote_ah_attr.grh.dgid.global.interface_id))
339 goto err;
340 }
341 if (unlikely(rcv_pkey_check(ppd_from_ibp(ibp), (u16)bth0,
342 sc5, be16_to_cpu(hdr->lrh[3])))) {
343 hfi1_bad_pqkey(ibp, IB_NOTICE_TRAP_BAD_PKEY,
344 (u16)bth0,
345 (be16_to_cpu(hdr->lrh[0]) >> 4) & 0xF,
346 0, qp->ibqp.qp_num,
347 hdr->lrh[3], hdr->lrh[1]);
348 goto err;
349 }
350 /* Validate the SLID. See Ch. 9.6.1.5 */
351 if (be16_to_cpu(hdr->lrh[3]) != qp->remote_ah_attr.dlid ||
352 ppd_from_ibp(ibp)->port != qp->port_num)
353 goto err;
354 if (qp->s_mig_state == IB_MIG_REARM &&
355 !(bth0 & IB_BTH_MIG_REQ))
356 qp->s_mig_state = IB_MIG_ARMED;
357 }
358
359 return 0;
360
361 err:
362 return 1;
363 }
364
365 /**
366 * ruc_loopback - handle UC and RC loopback requests
367 * @sqp: the sending QP
368 *
369 * This is called from hfi1_do_send() to
370 * forward a WQE addressed to the same HFI.
371 * Note that although we are single threaded due to the tasklet, we still
372 * have to protect against post_send(). We don't have to worry about
373 * receive interrupts since this is a connected protocol and all packets
374 * will pass through here.
375 */
376 static void ruc_loopback(struct hfi1_qp *sqp)
377 {
378 struct hfi1_ibport *ibp = to_iport(sqp->ibqp.device, sqp->port_num);
379 struct hfi1_qp *qp;
380 struct hfi1_swqe *wqe;
381 struct hfi1_sge *sge;
382 unsigned long flags;
383 struct ib_wc wc;
384 u64 sdata;
385 atomic64_t *maddr;
386 enum ib_wc_status send_status;
387 int release;
388 int ret;
389
390 rcu_read_lock();
391
392 /*
393 * Note that we check the responder QP state after
394 * checking the requester's state.
395 */
396 qp = hfi1_lookup_qpn(ibp, sqp->remote_qpn);
397
398 spin_lock_irqsave(&sqp->s_lock, flags);
399
400 /* Return if we are already busy processing a work request. */
401 if ((sqp->s_flags & (HFI1_S_BUSY | HFI1_S_ANY_WAIT)) ||
402 !(ib_hfi1_state_ops[sqp->state] & HFI1_PROCESS_OR_FLUSH_SEND))
403 goto unlock;
404
405 sqp->s_flags |= HFI1_S_BUSY;
406
407 again:
408 if (sqp->s_last == sqp->s_head)
409 goto clr_busy;
410 wqe = get_swqe_ptr(sqp, sqp->s_last);
411
412 /* Return if it is not OK to start a new work request. */
413 if (!(ib_hfi1_state_ops[sqp->state] & HFI1_PROCESS_NEXT_SEND_OK)) {
414 if (!(ib_hfi1_state_ops[sqp->state] & HFI1_FLUSH_SEND))
415 goto clr_busy;
416 /* We are in the error state, flush the work request. */
417 send_status = IB_WC_WR_FLUSH_ERR;
418 goto flush_send;
419 }
420
421 /*
422 * We can rely on the entry not changing without the s_lock
423 * being held until we update s_last.
424 * We increment s_cur to indicate s_last is in progress.
425 */
426 if (sqp->s_last == sqp->s_cur) {
427 if (++sqp->s_cur >= sqp->s_size)
428 sqp->s_cur = 0;
429 }
430 spin_unlock_irqrestore(&sqp->s_lock, flags);
431
432 if (!qp || !(ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_RECV_OK) ||
433 qp->ibqp.qp_type != sqp->ibqp.qp_type) {
434 ibp->n_pkt_drops++;
435 /*
436 * For RC, the requester would timeout and retry so
437 * shortcut the timeouts and just signal too many retries.
438 */
439 if (sqp->ibqp.qp_type == IB_QPT_RC)
440 send_status = IB_WC_RETRY_EXC_ERR;
441 else
442 send_status = IB_WC_SUCCESS;
443 goto serr;
444 }
445
446 memset(&wc, 0, sizeof(wc));
447 send_status = IB_WC_SUCCESS;
448
449 release = 1;
450 sqp->s_sge.sge = wqe->sg_list[0];
451 sqp->s_sge.sg_list = wqe->sg_list + 1;
452 sqp->s_sge.num_sge = wqe->wr.num_sge;
453 sqp->s_len = wqe->length;
454 switch (wqe->wr.opcode) {
455 case IB_WR_SEND_WITH_IMM:
456 wc.wc_flags = IB_WC_WITH_IMM;
457 wc.ex.imm_data = wqe->wr.ex.imm_data;
458 /* FALLTHROUGH */
459 case IB_WR_SEND:
460 ret = hfi1_get_rwqe(qp, 0);
461 if (ret < 0)
462 goto op_err;
463 if (!ret)
464 goto rnr_nak;
465 break;
466
467 case IB_WR_RDMA_WRITE_WITH_IMM:
468 if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_WRITE)))
469 goto inv_err;
470 wc.wc_flags = IB_WC_WITH_IMM;
471 wc.ex.imm_data = wqe->wr.ex.imm_data;
472 ret = hfi1_get_rwqe(qp, 1);
473 if (ret < 0)
474 goto op_err;
475 if (!ret)
476 goto rnr_nak;
477 /* FALLTHROUGH */
478 case IB_WR_RDMA_WRITE:
479 if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_WRITE)))
480 goto inv_err;
481 if (wqe->length == 0)
482 break;
483 if (unlikely(!hfi1_rkey_ok(qp, &qp->r_sge.sge, wqe->length,
484 wqe->rdma_wr.remote_addr,
485 wqe->rdma_wr.rkey,
486 IB_ACCESS_REMOTE_WRITE)))
487 goto acc_err;
488 qp->r_sge.sg_list = NULL;
489 qp->r_sge.num_sge = 1;
490 qp->r_sge.total_len = wqe->length;
491 break;
492
493 case IB_WR_RDMA_READ:
494 if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_READ)))
495 goto inv_err;
496 if (unlikely(!hfi1_rkey_ok(qp, &sqp->s_sge.sge, wqe->length,
497 wqe->rdma_wr.remote_addr,
498 wqe->rdma_wr.rkey,
499 IB_ACCESS_REMOTE_READ)))
500 goto acc_err;
501 release = 0;
502 sqp->s_sge.sg_list = NULL;
503 sqp->s_sge.num_sge = 1;
504 qp->r_sge.sge = wqe->sg_list[0];
505 qp->r_sge.sg_list = wqe->sg_list + 1;
506 qp->r_sge.num_sge = wqe->wr.num_sge;
507 qp->r_sge.total_len = wqe->length;
508 break;
509
510 case IB_WR_ATOMIC_CMP_AND_SWP:
511 case IB_WR_ATOMIC_FETCH_AND_ADD:
512 if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)))
513 goto inv_err;
514 if (unlikely(!hfi1_rkey_ok(qp, &qp->r_sge.sge, sizeof(u64),
515 wqe->atomic_wr.remote_addr,
516 wqe->atomic_wr.rkey,
517 IB_ACCESS_REMOTE_ATOMIC)))
518 goto acc_err;
519 /* Perform atomic OP and save result. */
520 maddr = (atomic64_t *) qp->r_sge.sge.vaddr;
521 sdata = wqe->atomic_wr.compare_add;
522 *(u64 *) sqp->s_sge.sge.vaddr =
523 (wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD) ?
524 (u64) atomic64_add_return(sdata, maddr) - sdata :
525 (u64) cmpxchg((u64 *) qp->r_sge.sge.vaddr,
526 sdata, wqe->atomic_wr.swap);
527 hfi1_put_mr(qp->r_sge.sge.mr);
528 qp->r_sge.num_sge = 0;
529 goto send_comp;
530
531 default:
532 send_status = IB_WC_LOC_QP_OP_ERR;
533 goto serr;
534 }
535
536 sge = &sqp->s_sge.sge;
537 while (sqp->s_len) {
538 u32 len = sqp->s_len;
539
540 if (len > sge->length)
541 len = sge->length;
542 if (len > sge->sge_length)
543 len = sge->sge_length;
544 WARN_ON_ONCE(len == 0);
545 hfi1_copy_sge(&qp->r_sge, sge->vaddr, len, release);
546 sge->vaddr += len;
547 sge->length -= len;
548 sge->sge_length -= len;
549 if (sge->sge_length == 0) {
550 if (!release)
551 hfi1_put_mr(sge->mr);
552 if (--sqp->s_sge.num_sge)
553 *sge = *sqp->s_sge.sg_list++;
554 } else if (sge->length == 0 && sge->mr->lkey) {
555 if (++sge->n >= HFI1_SEGSZ) {
556 if (++sge->m >= sge->mr->mapsz)
557 break;
558 sge->n = 0;
559 }
560 sge->vaddr =
561 sge->mr->map[sge->m]->segs[sge->n].vaddr;
562 sge->length =
563 sge->mr->map[sge->m]->segs[sge->n].length;
564 }
565 sqp->s_len -= len;
566 }
567 if (release)
568 hfi1_put_ss(&qp->r_sge);
569
570 if (!test_and_clear_bit(HFI1_R_WRID_VALID, &qp->r_aflags))
571 goto send_comp;
572
573 if (wqe->wr.opcode == IB_WR_RDMA_WRITE_WITH_IMM)
574 wc.opcode = IB_WC_RECV_RDMA_WITH_IMM;
575 else
576 wc.opcode = IB_WC_RECV;
577 wc.wr_id = qp->r_wr_id;
578 wc.status = IB_WC_SUCCESS;
579 wc.byte_len = wqe->length;
580 wc.qp = &qp->ibqp;
581 wc.src_qp = qp->remote_qpn;
582 wc.slid = qp->remote_ah_attr.dlid;
583 wc.sl = qp->remote_ah_attr.sl;
584 wc.port_num = 1;
585 /* Signal completion event if the solicited bit is set. */
586 hfi1_cq_enter(to_icq(qp->ibqp.recv_cq), &wc,
587 wqe->wr.send_flags & IB_SEND_SOLICITED);
588
589 send_comp:
590 spin_lock_irqsave(&sqp->s_lock, flags);
591 ibp->n_loop_pkts++;
592 flush_send:
593 sqp->s_rnr_retry = sqp->s_rnr_retry_cnt;
594 hfi1_send_complete(sqp, wqe, send_status);
595 goto again;
596
597 rnr_nak:
598 /* Handle RNR NAK */
599 if (qp->ibqp.qp_type == IB_QPT_UC)
600 goto send_comp;
601 ibp->n_rnr_naks++;
602 /*
603 * Note: we don't need the s_lock held since the BUSY flag
604 * makes this single threaded.
605 */
606 if (sqp->s_rnr_retry == 0) {
607 send_status = IB_WC_RNR_RETRY_EXC_ERR;
608 goto serr;
609 }
610 if (sqp->s_rnr_retry_cnt < 7)
611 sqp->s_rnr_retry--;
612 spin_lock_irqsave(&sqp->s_lock, flags);
613 if (!(ib_hfi1_state_ops[sqp->state] & HFI1_PROCESS_RECV_OK))
614 goto clr_busy;
615 sqp->s_flags |= HFI1_S_WAIT_RNR;
616 sqp->s_timer.function = hfi1_rc_rnr_retry;
617 sqp->s_timer.expires = jiffies +
618 usecs_to_jiffies(ib_hfi1_rnr_table[qp->r_min_rnr_timer]);
619 add_timer(&sqp->s_timer);
620 goto clr_busy;
621
622 op_err:
623 send_status = IB_WC_REM_OP_ERR;
624 wc.status = IB_WC_LOC_QP_OP_ERR;
625 goto err;
626
627 inv_err:
628 send_status = IB_WC_REM_INV_REQ_ERR;
629 wc.status = IB_WC_LOC_QP_OP_ERR;
630 goto err;
631
632 acc_err:
633 send_status = IB_WC_REM_ACCESS_ERR;
634 wc.status = IB_WC_LOC_PROT_ERR;
635 err:
636 /* responder goes to error state */
637 hfi1_rc_error(qp, wc.status);
638
639 serr:
640 spin_lock_irqsave(&sqp->s_lock, flags);
641 hfi1_send_complete(sqp, wqe, send_status);
642 if (sqp->ibqp.qp_type == IB_QPT_RC) {
643 int lastwqe = hfi1_error_qp(sqp, IB_WC_WR_FLUSH_ERR);
644
645 sqp->s_flags &= ~HFI1_S_BUSY;
646 spin_unlock_irqrestore(&sqp->s_lock, flags);
647 if (lastwqe) {
648 struct ib_event ev;
649
650 ev.device = sqp->ibqp.device;
651 ev.element.qp = &sqp->ibqp;
652 ev.event = IB_EVENT_QP_LAST_WQE_REACHED;
653 sqp->ibqp.event_handler(&ev, sqp->ibqp.qp_context);
654 }
655 goto done;
656 }
657 clr_busy:
658 sqp->s_flags &= ~HFI1_S_BUSY;
659 unlock:
660 spin_unlock_irqrestore(&sqp->s_lock, flags);
661 done:
662 rcu_read_unlock();
663 }
664
665 /**
666 * hfi1_make_grh - construct a GRH header
667 * @ibp: a pointer to the IB port
668 * @hdr: a pointer to the GRH header being constructed
669 * @grh: the global route address to send to
670 * @hwords: the number of 32 bit words of header being sent
671 * @nwords: the number of 32 bit words of data being sent
672 *
673 * Return the size of the header in 32 bit words.
674 */
675 u32 hfi1_make_grh(struct hfi1_ibport *ibp, struct ib_grh *hdr,
676 struct ib_global_route *grh, u32 hwords, u32 nwords)
677 {
678 hdr->version_tclass_flow =
679 cpu_to_be32((IB_GRH_VERSION << IB_GRH_VERSION_SHIFT) |
680 (grh->traffic_class << IB_GRH_TCLASS_SHIFT) |
681 (grh->flow_label << IB_GRH_FLOW_SHIFT));
682 hdr->paylen = cpu_to_be16((hwords - 2 + nwords + SIZE_OF_CRC) << 2);
683 /* next_hdr is defined by C8-7 in ch. 8.4.1 */
684 hdr->next_hdr = IB_GRH_NEXT_HDR;
685 hdr->hop_limit = grh->hop_limit;
686 /* The SGID is 32-bit aligned. */
687 hdr->sgid.global.subnet_prefix = ibp->gid_prefix;
688 hdr->sgid.global.interface_id =
689 grh->sgid_index && grh->sgid_index < ARRAY_SIZE(ibp->guids) ?
690 ibp->guids[grh->sgid_index - 1] :
691 cpu_to_be64(ppd_from_ibp(ibp)->guid);
692 hdr->dgid = grh->dgid;
693
694 /* GRH header size in 32-bit words. */
695 return sizeof(struct ib_grh) / sizeof(u32);
696 }
697
698 #define BTH2_OFFSET (offsetof(struct hfi1_pio_header, hdr.u.oth.bth[2]) / 4)
699
700 /**
701 * build_ahg - create ahg in s_hdr
702 * @qp: a pointer to QP
703 * @npsn: the next PSN for the request/response
704 *
705 * This routine handles the AHG by allocating an ahg entry and causing the
706 * copy of the first middle.
707 *
708 * Subsequent middles use the copied entry, editing the
709 * PSN with 1 or 2 edits.
710 */
711 static inline void build_ahg(struct hfi1_qp *qp, u32 npsn)
712 {
713 if (unlikely(qp->s_flags & HFI1_S_AHG_CLEAR))
714 clear_ahg(qp);
715 if (!(qp->s_flags & HFI1_S_AHG_VALID)) {
716 /* first middle that needs copy */
717 if (qp->s_ahgidx < 0) {
718 if (!qp->s_sde)
719 qp->s_sde = qp_to_sdma_engine(qp, qp->s_sc);
720 qp->s_ahgidx = sdma_ahg_alloc(qp->s_sde);
721 }
722 if (qp->s_ahgidx >= 0) {
723 qp->s_ahgpsn = npsn;
724 qp->s_hdr->tx_flags |= SDMA_TXREQ_F_AHG_COPY;
725 /* save to protect a change in another thread */
726 qp->s_hdr->sde = qp->s_sde;
727 qp->s_hdr->ahgidx = qp->s_ahgidx;
728 qp->s_flags |= HFI1_S_AHG_VALID;
729 }
730 } else {
731 /* subsequent middle after valid */
732 if (qp->s_ahgidx >= 0) {
733 qp->s_hdr->tx_flags |= SDMA_TXREQ_F_USE_AHG;
734 qp->s_hdr->ahgidx = qp->s_ahgidx;
735 qp->s_hdr->ahgcount++;
736 qp->s_hdr->ahgdesc[0] =
737 sdma_build_ahg_descriptor(
738 (__force u16)cpu_to_be16((u16)npsn),
739 BTH2_OFFSET,
740 16,
741 16);
742 if ((npsn & 0xffff0000) !=
743 (qp->s_ahgpsn & 0xffff0000)) {
744 qp->s_hdr->ahgcount++;
745 qp->s_hdr->ahgdesc[1] =
746 sdma_build_ahg_descriptor(
747 (__force u16)cpu_to_be16(
748 (u16)(npsn >> 16)),
749 BTH2_OFFSET,
750 0,
751 16);
752 }
753 }
754 }
755 }
756
757 void hfi1_make_ruc_header(struct hfi1_qp *qp, struct hfi1_other_headers *ohdr,
758 u32 bth0, u32 bth2, int middle)
759 {
760 struct hfi1_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
761 u16 lrh0;
762 u32 nwords;
763 u32 extra_bytes;
764 u8 sc5;
765 u32 bth1;
766
767 /* Construct the header. */
768 extra_bytes = -qp->s_cur_size & 3;
769 nwords = (qp->s_cur_size + extra_bytes) >> 2;
770 lrh0 = HFI1_LRH_BTH;
771 if (unlikely(qp->remote_ah_attr.ah_flags & IB_AH_GRH)) {
772 qp->s_hdrwords += hfi1_make_grh(ibp, &qp->s_hdr->ibh.u.l.grh,
773 &qp->remote_ah_attr.grh,
774 qp->s_hdrwords, nwords);
775 lrh0 = HFI1_LRH_GRH;
776 middle = 0;
777 }
778 sc5 = ibp->sl_to_sc[qp->remote_ah_attr.sl];
779 lrh0 |= (sc5 & 0xf) << 12 | (qp->remote_ah_attr.sl & 0xf) << 4;
780 qp->s_sc = sc5;
781 /*
782 * reset s_hdr/AHG fields
783 *
784 * This insures that the ahgentry/ahgcount
785 * are at a non-AHG default to protect
786 * build_verbs_tx_desc() from using
787 * an include ahgidx.
788 *
789 * build_ahg() will modify as appropriate
790 * to use the AHG feature.
791 */
792 qp->s_hdr->tx_flags = 0;
793 qp->s_hdr->ahgcount = 0;
794 qp->s_hdr->ahgidx = 0;
795 qp->s_hdr->sde = NULL;
796 if (qp->s_mig_state == IB_MIG_MIGRATED)
797 bth0 |= IB_BTH_MIG_REQ;
798 else
799 middle = 0;
800 if (middle)
801 build_ahg(qp, bth2);
802 else
803 qp->s_flags &= ~HFI1_S_AHG_VALID;
804 qp->s_hdr->ibh.lrh[0] = cpu_to_be16(lrh0);
805 qp->s_hdr->ibh.lrh[1] = cpu_to_be16(qp->remote_ah_attr.dlid);
806 qp->s_hdr->ibh.lrh[2] =
807 cpu_to_be16(qp->s_hdrwords + nwords + SIZE_OF_CRC);
808 qp->s_hdr->ibh.lrh[3] = cpu_to_be16(ppd_from_ibp(ibp)->lid |
809 qp->remote_ah_attr.src_path_bits);
810 bth0 |= hfi1_get_pkey(ibp, qp->s_pkey_index);
811 bth0 |= extra_bytes << 20;
812 ohdr->bth[0] = cpu_to_be32(bth0);
813 bth1 = qp->remote_qpn;
814 if (qp->s_flags & HFI1_S_ECN) {
815 qp->s_flags &= ~HFI1_S_ECN;
816 /* we recently received a FECN, so return a BECN */
817 bth1 |= (HFI1_BECN_MASK << HFI1_BECN_SHIFT);
818 }
819 ohdr->bth[1] = cpu_to_be32(bth1);
820 ohdr->bth[2] = cpu_to_be32(bth2);
821 }
822
823 /* when sending, force a reschedule every one of these periods */
824 #define SEND_RESCHED_TIMEOUT (5 * HZ) /* 5s in jiffies */
825
826 /**
827 * hfi1_do_send - perform a send on a QP
828 * @work: contains a pointer to the QP
829 *
830 * Process entries in the send work queue until credit or queue is
831 * exhausted. Only allow one CPU to send a packet per QP (tasklet).
832 * Otherwise, two threads could send packets out of order.
833 */
834 void hfi1_do_send(struct work_struct *work)
835 {
836 struct iowait *wait = container_of(work, struct iowait, iowork);
837 struct hfi1_qp *qp = container_of(wait, struct hfi1_qp, s_iowait);
838 struct hfi1_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
839 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
840 int (*make_req)(struct hfi1_qp *qp);
841 unsigned long flags;
842 unsigned long timeout;
843
844 if ((qp->ibqp.qp_type == IB_QPT_RC ||
845 qp->ibqp.qp_type == IB_QPT_UC) &&
846 !loopback &&
847 (qp->remote_ah_attr.dlid & ~((1 << ppd->lmc) - 1)) == ppd->lid) {
848 ruc_loopback(qp);
849 return;
850 }
851
852 if (qp->ibqp.qp_type == IB_QPT_RC)
853 make_req = hfi1_make_rc_req;
854 else if (qp->ibqp.qp_type == IB_QPT_UC)
855 make_req = hfi1_make_uc_req;
856 else
857 make_req = hfi1_make_ud_req;
858
859 spin_lock_irqsave(&qp->s_lock, flags);
860
861 /* Return if we are already busy processing a work request. */
862 if (!hfi1_send_ok(qp)) {
863 spin_unlock_irqrestore(&qp->s_lock, flags);
864 return;
865 }
866
867 qp->s_flags |= HFI1_S_BUSY;
868
869 spin_unlock_irqrestore(&qp->s_lock, flags);
870
871 timeout = jiffies + SEND_RESCHED_TIMEOUT;
872 do {
873 /* Check for a constructed packet to be sent. */
874 if (qp->s_hdrwords != 0) {
875 /*
876 * If the packet cannot be sent now, return and
877 * the send tasklet will be woken up later.
878 */
879 if (hfi1_verbs_send(qp, qp->s_hdr, qp->s_hdrwords,
880 qp->s_cur_sge, qp->s_cur_size))
881 break;
882 /* Record that s_hdr is empty. */
883 qp->s_hdrwords = 0;
884 }
885
886 /* allow other tasks to run */
887 if (unlikely(time_after(jiffies, timeout))) {
888 cond_resched();
889 ppd->dd->verbs_dev.n_send_schedule++;
890 timeout = jiffies + SEND_RESCHED_TIMEOUT;
891 }
892 } while (make_req(qp));
893 }
894
895 /*
896 * This should be called with s_lock held.
897 */
898 void hfi1_send_complete(struct hfi1_qp *qp, struct hfi1_swqe *wqe,
899 enum ib_wc_status status)
900 {
901 u32 old_last, last;
902 unsigned i;
903
904 if (!(ib_hfi1_state_ops[qp->state] & HFI1_PROCESS_OR_FLUSH_SEND))
905 return;
906
907 for (i = 0; i < wqe->wr.num_sge; i++) {
908 struct hfi1_sge *sge = &wqe->sg_list[i];
909
910 hfi1_put_mr(sge->mr);
911 }
912 if (qp->ibqp.qp_type == IB_QPT_UD ||
913 qp->ibqp.qp_type == IB_QPT_SMI ||
914 qp->ibqp.qp_type == IB_QPT_GSI)
915 atomic_dec(&to_iah(wqe->ud_wr.ah)->refcount);
916
917 /* See ch. 11.2.4.1 and 10.7.3.1 */
918 if (!(qp->s_flags & HFI1_S_SIGNAL_REQ_WR) ||
919 (wqe->wr.send_flags & IB_SEND_SIGNALED) ||
920 status != IB_WC_SUCCESS) {
921 struct ib_wc wc;
922
923 memset(&wc, 0, sizeof(wc));
924 wc.wr_id = wqe->wr.wr_id;
925 wc.status = status;
926 wc.opcode = ib_hfi1_wc_opcode[wqe->wr.opcode];
927 wc.qp = &qp->ibqp;
928 if (status == IB_WC_SUCCESS)
929 wc.byte_len = wqe->length;
930 hfi1_cq_enter(to_icq(qp->ibqp.send_cq), &wc,
931 status != IB_WC_SUCCESS);
932 }
933
934 last = qp->s_last;
935 old_last = last;
936 if (++last >= qp->s_size)
937 last = 0;
938 qp->s_last = last;
939 if (qp->s_acked == old_last)
940 qp->s_acked = last;
941 if (qp->s_cur == old_last)
942 qp->s_cur = last;
943 if (qp->s_tail == old_last)
944 qp->s_tail = last;
945 if (qp->state == IB_QPS_SQD && last == qp->s_cur)
946 qp->s_draining = 0;
947 }