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Staging: add Realtek 8192 PCI wireless driver
[mirror_ubuntu-bionic-kernel.git] / drivers / staging / rtl8192e / r8192E_dm.c
1 /*++
2 Copyright-c Realtek Semiconductor Corp. All rights reserved.
3
4 Module Name:
5 r8192U_dm.c
6
7 Abstract:
8 HW dynamic mechanism.
9
10 Major Change History:
11 When Who What
12 ---------- --------------- -------------------------------
13 2008-05-14 amy create version 0 porting from windows code.
14
15 --*/
16 #include "r8192E.h"
17 #include "r8192E_dm.h"
18 #include "r8192E_hw.h"
19 #include "r819xE_phy.h"
20 #include "r819xE_phyreg.h"
21 #include "r8190_rtl8256.h"
22 /*---------------------------Define Local Constant---------------------------*/
23 //
24 // Indicate different AP vendor for IOT issue.
25 //
26 #ifdef RTL8190P
27 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
28 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322};
29 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
30 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322};
31 #else
32 #ifdef RTL8192E
33 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
34 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322};
35 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
36 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322};
37 #else
38 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
39 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f};
40 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
41 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f};
42 #endif
43 #endif
44
45 #define RTK_UL_EDCA 0xa44f
46 #define RTK_DL_EDCA 0x5e4322
47 /*---------------------------Define Local Constant---------------------------*/
48
49
50 /*------------------------Define global variable-----------------------------*/
51 // Debug variable ?
52 dig_t dm_digtable;
53 // Store current shoftware write register content for MAC PHY.
54 u8 dm_shadow[16][256] = {{0}};
55 // For Dynamic Rx Path Selection by Signal Strength
56 DRxPathSel DM_RxPathSelTable;
57 /*------------------------Define global variable-----------------------------*/
58
59
60 /*------------------------Define local variable------------------------------*/
61 /*------------------------Define local variable------------------------------*/
62
63
64 /*--------------------Define export function prototype-----------------------*/
65 extern void init_hal_dm(struct net_device *dev);
66 extern void deinit_hal_dm(struct net_device *dev);
67
68 extern void hal_dm_watchdog(struct net_device *dev);
69
70
71 extern void init_rate_adaptive(struct net_device *dev);
72 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
73 extern void dm_txpower_trackingcallback(struct work_struct *work);
74 #else
75 extern void dm_txpower_trackingcallback(struct net_device *dev);
76 #endif
77
78 extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14);
79 extern void dm_restore_dynamic_mechanism_state(struct net_device *dev);
80 extern void dm_backup_dynamic_mechanism_state(struct net_device *dev);
81 extern void dm_change_dynamic_initgain_thresh(struct net_device *dev,
82 u32 dm_type,
83 u32 dm_value);
84 extern void DM_ChangeFsyncSetting(struct net_device *dev,
85 s32 DM_Type,
86 s32 DM_Value);
87 extern void dm_force_tx_fw_info(struct net_device *dev,
88 u32 force_type,
89 u32 force_value);
90 extern void dm_init_edca_turbo(struct net_device *dev);
91 extern void dm_rf_operation_test_callback(unsigned long data);
92 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
93 extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
94 #else
95 extern void dm_rf_pathcheck_workitemcallback(struct net_device *dev);
96 #endif
97 extern void dm_fsync_timer_callback(unsigned long data);
98 #if 0
99 extern bool dm_check_lbus_status(struct net_device *dev);
100 #endif
101 extern void dm_check_fsync(struct net_device *dev);
102 extern void dm_shadow_init(struct net_device *dev);
103 extern void dm_initialize_txpower_tracking(struct net_device *dev);
104
105 #ifdef RTL8192E
106 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
107 extern void dm_gpio_change_rf_callback(struct work_struct *work);
108 #else
109 extern void dm_gpio_change_rf_callback(struct net_device *dev);
110 #endif
111 #endif
112
113
114
115 /*--------------------Define export function prototype-----------------------*/
116
117
118 /*---------------------Define local function prototype-----------------------*/
119 // DM --> Rate Adaptive
120 static void dm_check_rate_adaptive(struct net_device *dev);
121
122 // DM --> Bandwidth switch
123 static void dm_init_bandwidth_autoswitch(struct net_device *dev);
124 static void dm_bandwidth_autoswitch( struct net_device *dev);
125
126 // DM --> TX power control
127 //static void dm_initialize_txpower_tracking(struct net_device *dev);
128
129 static void dm_check_txpower_tracking(struct net_device *dev);
130
131
132
133 //static void dm_txpower_reset_recovery(struct net_device *dev);
134
135
136 // DM --> BB init gain restore
137 #ifndef RTL8192U
138 static void dm_bb_initialgain_restore(struct net_device *dev);
139
140
141 // DM --> BB init gain backup
142 static void dm_bb_initialgain_backup(struct net_device *dev);
143 #endif
144
145 // DM --> Dynamic Init Gain by RSSI
146 static void dm_dig_init(struct net_device *dev);
147 static void dm_ctrl_initgain_byrssi(struct net_device *dev);
148 static void dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev);
149 static void dm_ctrl_initgain_byrssi_by_driverrssi( struct net_device *dev);
150 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev);
151 static void dm_initial_gain(struct net_device *dev);
152 static void dm_pd_th(struct net_device *dev);
153 static void dm_cs_ratio(struct net_device *dev);
154
155 static void dm_init_ctstoself(struct net_device *dev);
156 // DM --> EDCA turboe mode control
157 static void dm_check_edca_turbo(struct net_device *dev);
158
159 // DM --> HW RF control
160 static void dm_check_rfctrl_gpio(struct net_device *dev);
161
162 #ifndef RTL8190P
163 //static void dm_gpio_change_rf(struct net_device *dev);
164 #endif
165 // DM --> Check PBC
166 static void dm_check_pbc_gpio(struct net_device *dev);
167
168
169 // DM --> Check current RX RF path state
170 static void dm_check_rx_path_selection(struct net_device *dev);
171 static void dm_init_rxpath_selection(struct net_device *dev);
172 static void dm_rxpath_sel_byrssi(struct net_device *dev);
173
174
175 // DM --> Fsync for broadcom ap
176 static void dm_init_fsync(struct net_device *dev);
177 static void dm_deInit_fsync(struct net_device *dev);
178
179 //Added by vivi, 20080522
180 static void dm_check_txrateandretrycount(struct net_device *dev);
181
182 /*---------------------Define local function prototype-----------------------*/
183
184 /*---------------------Define of Tx Power Control For Near/Far Range --------*/ //Add by Jacken 2008/02/18
185 static void dm_init_dynamic_txpower(struct net_device *dev);
186 static void dm_dynamic_txpower(struct net_device *dev);
187
188
189 // DM --> For rate adaptive and DIG, we must send RSSI to firmware
190 static void dm_send_rssi_tofw(struct net_device *dev);
191 static void dm_ctstoself(struct net_device *dev);
192 /*---------------------------Define function prototype------------------------*/
193 //================================================================================
194 // HW Dynamic mechanism interface.
195 //================================================================================
196
197 //
198 // Description:
199 // Prepare SW resource for HW dynamic mechanism.
200 //
201 // Assumption:
202 // This function is only invoked at driver intialization once.
203 //
204 //
205 extern void
206 init_hal_dm(struct net_device *dev)
207 {
208 struct r8192_priv *priv = ieee80211_priv(dev);
209
210 // Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism.
211 priv->undecorated_smoothed_pwdb = -1;
212
213 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
214 dm_init_dynamic_txpower(dev);
215 init_rate_adaptive(dev);
216 //dm_initialize_txpower_tracking(dev);
217 dm_dig_init(dev);
218 dm_init_edca_turbo(dev);
219 dm_init_bandwidth_autoswitch(dev);
220 dm_init_fsync(dev);
221 dm_init_rxpath_selection(dev);
222 dm_init_ctstoself(dev);
223 #ifdef RTL8192E
224 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
225 INIT_DELAYED_WORK(&priv->gpio_change_rf_wq, dm_gpio_change_rf_callback);
226 #else
227 INIT_WORK(&priv->gpio_change_rf_wq, (void(*)(void*)) dm_gpio_change_rf_callback,dev);
228 #endif
229 #endif
230
231 } // InitHalDm
232
233 extern void deinit_hal_dm(struct net_device *dev)
234 {
235
236 dm_deInit_fsync(dev);
237
238 }
239
240
241 #ifdef USB_RX_AGGREGATION_SUPPORT
242 void dm_CheckRxAggregation(struct net_device *dev) {
243 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
244 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
245 static unsigned long lastTxOkCnt = 0;
246 static unsigned long lastRxOkCnt = 0;
247 unsigned long curTxOkCnt = 0;
248 unsigned long curRxOkCnt = 0;
249
250 /*
251 if (pHalData->bForcedUsbRxAggr) {
252 if (pHalData->ForcedUsbRxAggrInfo == 0) {
253 if (pHalData->bCurrentRxAggrEnable) {
254 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE);
255 }
256 } else {
257 if (!pHalData->bCurrentRxAggrEnable || (pHalData->ForcedUsbRxAggrInfo != pHalData->LastUsbRxAggrInfoSetting)) {
258 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, TRUE);
259 }
260 }
261 return;
262 }
263
264 */
265 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
266 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
267
268 if((curTxOkCnt + curRxOkCnt) < 15000000) {
269 return;
270 }
271
272 if(curTxOkCnt > 4*curRxOkCnt) {
273 if (priv->bCurrentRxAggrEnable) {
274 write_nic_dword(dev, 0x1a8, 0);
275 priv->bCurrentRxAggrEnable = false;
276 }
277 }else{
278 if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) {
279 u32 ulValue;
280 ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
281 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
282 /*
283 * If usb rx firmware aggregation is enabled,
284 * when anyone of three threshold conditions above is reached,
285 * firmware will send aggregated packet to driver.
286 */
287 write_nic_dword(dev, 0x1a8, ulValue);
288 priv->bCurrentRxAggrEnable = true;
289 }
290 }
291
292 lastTxOkCnt = priv->stats.txbytesunicast;
293 lastRxOkCnt = priv->stats.rxbytesunicast;
294 } // dm_CheckEdcaTurbo
295 #endif
296
297
298
299 extern void hal_dm_watchdog(struct net_device *dev)
300 {
301 //struct r8192_priv *priv = ieee80211_priv(dev);
302
303 //static u8 previous_bssid[6] ={0};
304
305 /*Add by amy 2008/05/15 ,porting from windows code.*/
306 dm_check_rate_adaptive(dev);
307 dm_dynamic_txpower(dev);
308 dm_check_txrateandretrycount(dev);
309
310 dm_check_txpower_tracking(dev);
311
312 dm_ctrl_initgain_byrssi(dev);
313 dm_check_edca_turbo(dev);
314 dm_bandwidth_autoswitch(dev);
315
316 dm_check_rfctrl_gpio(dev);
317 dm_check_rx_path_selection(dev);
318 dm_check_fsync(dev);
319
320 // Add by amy 2008-05-15 porting from windows code.
321 dm_check_pbc_gpio(dev);
322 dm_send_rssi_tofw(dev);
323 dm_ctstoself(dev);
324
325 #ifdef USB_RX_AGGREGATION_SUPPORT
326 dm_CheckRxAggregation(dev);
327 #endif
328 } //HalDmWatchDog
329
330
331 /*
332 * Decide Rate Adaptive Set according to distance (signal strength)
333 * 01/11/2008 MHC Modify input arguments and RATR table level.
334 * 01/16/2008 MHC RF_Type is assigned in ReadAdapterInfo(). We must call
335 * the function after making sure RF_Type.
336 */
337 extern void init_rate_adaptive(struct net_device * dev)
338 {
339
340 struct r8192_priv *priv = ieee80211_priv(dev);
341 prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive;
342
343 pra->ratr_state = DM_RATR_STA_MAX;
344 pra->high2low_rssi_thresh_for_ra = RateAdaptiveTH_High;
345 pra->low2high_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M+5;
346 pra->low2high_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M+5;
347
348 pra->high_rssi_thresh_for_ra = RateAdaptiveTH_High+5;
349 pra->low_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M;
350 pra->low_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M;
351
352 if(priv->CustomerID == RT_CID_819x_Netcore)
353 pra->ping_rssi_enable = 1;
354 else
355 pra->ping_rssi_enable = 0;
356 pra->ping_rssi_thresh_for_ra = 15;
357
358
359 if (priv->rf_type == RF_2T4R)
360 {
361 // 07/10/08 MH Modify for RA smooth scheme.
362 /* 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.*/
363 pra->upper_rssi_threshold_ratr = 0x8f0f0000;
364 pra->middle_rssi_threshold_ratr = 0x8f0ff000;
365 pra->low_rssi_threshold_ratr = 0x8f0ff001;
366 pra->low_rssi_threshold_ratr_40M = 0x8f0ff005;
367 pra->low_rssi_threshold_ratr_20M = 0x8f0ff001;
368 pra->ping_rssi_ratr = 0x0000000d;//cosa add for test
369 }
370 else if (priv->rf_type == RF_1T2R)
371 {
372 pra->upper_rssi_threshold_ratr = 0x000f0000;
373 pra->middle_rssi_threshold_ratr = 0x000ff000;
374 pra->low_rssi_threshold_ratr = 0x000ff001;
375 pra->low_rssi_threshold_ratr_40M = 0x000ff005;
376 pra->low_rssi_threshold_ratr_20M = 0x000ff001;
377 pra->ping_rssi_ratr = 0x0000000d;//cosa add for test
378 }
379
380 } // InitRateAdaptive
381
382
383 /*-----------------------------------------------------------------------------
384 * Function: dm_check_rate_adaptive()
385 *
386 * Overview:
387 *
388 * Input: NONE
389 *
390 * Output: NONE
391 *
392 * Return: NONE
393 *
394 * Revised History:
395 * When Who Remark
396 * 05/26/08 amy Create version 0 proting from windows code.
397 *
398 *---------------------------------------------------------------------------*/
399 static void dm_check_rate_adaptive(struct net_device * dev)
400 {
401 struct r8192_priv *priv = ieee80211_priv(dev);
402 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
403 prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive;
404 u32 currentRATR, targetRATR = 0;
405 u32 LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0;
406 bool bshort_gi_enabled = false;
407 static u8 ping_rssi_state=0;
408
409
410 if(!priv->up)
411 {
412 RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n");
413 return;
414 }
415
416 if(pra->rate_adaptive_disabled)//this variable is set by ioctl.
417 return;
418
419 // TODO: Only 11n mode is implemented currently,
420 if( !(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
421 priv->ieee80211->mode == WIRELESS_MODE_N_5G))
422 return;
423
424 if( priv->ieee80211->state == IEEE80211_LINKED )
425 {
426 // RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");
427
428 //
429 // Check whether Short GI is enabled
430 //
431 bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) ||
432 (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz);
433
434
435 pra->upper_rssi_threshold_ratr =
436 (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
437
438 pra->middle_rssi_threshold_ratr =
439 (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
440
441 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
442 {
443 pra->low_rssi_threshold_ratr =
444 (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
445 }
446 else
447 {
448 pra->low_rssi_threshold_ratr =
449 (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
450 }
451 //cosa add for test
452 pra->ping_rssi_ratr =
453 (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
454
455 /* 2007/10/08 MH We support RA smooth scheme now. When it is the first
456 time to link with AP. We will not change upper/lower threshold. If
457 STA stay in high or low level, we must change two different threshold
458 to prevent jumping frequently. */
459 if (pra->ratr_state == DM_RATR_STA_HIGH)
460 {
461 HighRSSIThreshForRA = pra->high2low_rssi_thresh_for_ra;
462 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
463 (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
464 }
465 else if (pra->ratr_state == DM_RATR_STA_LOW)
466 {
467 HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
468 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
469 (pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M);
470 }
471 else
472 {
473 HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
474 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
475 (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
476 }
477
478 //DbgPrint("[DM] THresh H/L=%d/%d\n\r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA);
479 if(priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA)
480 {
481 //DbgPrint("[DM] RSSI=%d STA=HIGH\n\r", pHalData->UndecoratedSmoothedPWDB);
482 pra->ratr_state = DM_RATR_STA_HIGH;
483 targetRATR = pra->upper_rssi_threshold_ratr;
484 }else if(priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA)
485 {
486 //DbgPrint("[DM] RSSI=%d STA=Middle\n\r", pHalData->UndecoratedSmoothedPWDB);
487 pra->ratr_state = DM_RATR_STA_MIDDLE;
488 targetRATR = pra->middle_rssi_threshold_ratr;
489 }else
490 {
491 //DbgPrint("[DM] RSSI=%d STA=LOW\n\r", pHalData->UndecoratedSmoothedPWDB);
492 pra->ratr_state = DM_RATR_STA_LOW;
493 targetRATR = pra->low_rssi_threshold_ratr;
494 }
495
496 //cosa add for test
497 if(pra->ping_rssi_enable)
498 {
499 //pHalData->UndecoratedSmoothedPWDB = 19;
500 if(priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5))
501 {
502 if( (priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) ||
503 ping_rssi_state )
504 {
505 //DbgPrint("TestRSSI = %d, set RATR to 0x%x \n", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR);
506 pra->ratr_state = DM_RATR_STA_LOW;
507 targetRATR = pra->ping_rssi_ratr;
508 ping_rssi_state = 1;
509 }
510 //else
511 // DbgPrint("TestRSSI is between the range. \n");
512 }
513 else
514 {
515 //DbgPrint("TestRSSI Recover to 0x%x \n", targetRATR);
516 ping_rssi_state = 0;
517 }
518 }
519
520 // 2008.04.01
521 #if 1
522 // For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7.
523 if(priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev))
524 targetRATR &= 0xf00fffff;
525 #endif
526
527 //
528 // Check whether updating of RATR0 is required
529 //
530 currentRATR = read_nic_dword(dev, RATR0);
531 if( targetRATR != currentRATR )
532 {
533 u32 ratr_value;
534 ratr_value = targetRATR;
535 RT_TRACE(COMP_RATE,"currentRATR = %x, targetRATR = %x\n", currentRATR, targetRATR);
536 if(priv->rf_type == RF_1T2R)
537 {
538 ratr_value &= ~(RATE_ALL_OFDM_2SS);
539 }
540 write_nic_dword(dev, RATR0, ratr_value);
541 write_nic_byte(dev, UFWP, 1);
542
543 pra->last_ratr = targetRATR;
544 }
545
546 }
547 else
548 {
549 pra->ratr_state = DM_RATR_STA_MAX;
550 }
551
552 } // dm_CheckRateAdaptive
553
554
555 static void dm_init_bandwidth_autoswitch(struct net_device * dev)
556 {
557 struct r8192_priv *priv = ieee80211_priv(dev);
558
559 priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH;
560 priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW;
561 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
562 priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false;
563
564 } // dm_init_bandwidth_autoswitch
565
566
567 static void dm_bandwidth_autoswitch(struct net_device * dev)
568 {
569 struct r8192_priv *priv = ieee80211_priv(dev);
570
571 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ||!priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable){
572 return;
573 }else{
574 if(priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz == false){//If send packets in 40 Mhz in 20/40
575 if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz)
576 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true;
577 }else{//in force send packets in 20 Mhz in 20/40
578 if(priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz)
579 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
580
581 }
582 }
583 } // dm_BandwidthAutoSwitch
584
585 //OFDM default at 0db, index=6.
586 #ifndef RTL8190P
587 static u32 OFDMSwingTable[OFDM_Table_Length] = {
588 0x7f8001fe, // 0, +6db
589 0x71c001c7, // 1, +5db
590 0x65400195, // 2, +4db
591 0x5a400169, // 3, +3db
592 0x50800142, // 4, +2db
593 0x47c0011f, // 5, +1db
594 0x40000100, // 6, +0db ===> default, upper for higher temprature, lower for low temprature
595 0x390000e4, // 7, -1db
596 0x32c000cb, // 8, -2db
597 0x2d4000b5, // 9, -3db
598 0x288000a2, // 10, -4db
599 0x24000090, // 11, -5db
600 0x20000080, // 12, -6db
601 0x1c800072, // 13, -7db
602 0x19800066, // 14, -8db
603 0x26c0005b, // 15, -9db
604 0x24400051, // 16, -10db
605 0x12000048, // 17, -11db
606 0x10000040 // 18, -12db
607 };
608 static u8 CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = {
609 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0db ===> CCK40M default
610 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 1, -1db
611 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 2, -2db
612 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 3, -3db
613 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 4, -4db
614 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 5, -5db
615 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 6, -6db ===> CCK20M default
616 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 7, -7db
617 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 8, -8db
618 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 9, -9db
619 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 10, -10db
620 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} // 11, -11db
621 };
622
623 static u8 CCKSwingTable_Ch14[CCK_Table_length][8] = {
624 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0db ===> CCK40M default
625 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 1, -1db
626 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 2, -2db
627 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 3, -3db
628 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 4, -4db
629 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 5, -5db
630 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 6, -6db ===> CCK20M default
631 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 7, -7db
632 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 8, -8db
633 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 9, -9db
634 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 10, -10db
635 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} // 11, -11db
636 };
637 #endif
638 #define Pw_Track_Flag 0x11d
639 #define Tssi_Mea_Value 0x13c
640 #define Tssi_Report_Value1 0x134
641 #define Tssi_Report_Value2 0x13e
642 #define FW_Busy_Flag 0x13f
643 static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
644 {
645 struct r8192_priv *priv = ieee80211_priv(dev);
646 bool bHighpowerstate, viviflag = FALSE;
647 DCMD_TXCMD_T tx_cmd;
648 u8 powerlevelOFDM24G;
649 int i =0, j = 0, k = 0;
650 u8 RF_Type, tmp_report[5]={0, 0, 0, 0, 0};
651 u32 Value;
652 u8 Pwr_Flag;
653 u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver=0;
654 #ifdef RTL8192U
655 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
656 #endif
657 // bool rtStatus = true;
658 u32 delta=0;
659 RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
660 // write_nic_byte(dev, 0x1ba, 0);
661 write_nic_byte(dev, Pw_Track_Flag, 0);
662 write_nic_byte(dev, FW_Busy_Flag, 0);
663 priv->ieee80211->bdynamic_txpower_enable = false;
664 bHighpowerstate = priv->bDynamicTxHighPower;
665
666 powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24);
667 RF_Type = priv->rf_type;
668 Value = (RF_Type<<8) | powerlevelOFDM24G;
669
670 RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G);
671
672 for(j = 0; j<=30; j++)
673 { //fill tx_cmd
674
675 tx_cmd.Op = TXCMD_SET_TX_PWR_TRACKING;
676 tx_cmd.Length = 4;
677 tx_cmd.Value = Value;
678 #ifdef RTL8192U
679 rtStatus = SendTxCommandPacket(dev, &tx_cmd, 12);
680 if (rtStatus == RT_STATUS_FAILURE)
681 {
682 RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n");
683 }
684 #else
685 cmpk_message_handle_tx(dev, (u8*)&tx_cmd, DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
686 #endif
687 mdelay(1);
688 //DbgPrint("hi, vivi, strange\n");
689 for(i = 0;i <= 30; i++)
690 {
691 Pwr_Flag = read_nic_byte(dev, Pw_Track_Flag);
692
693 if (Pwr_Flag == 0)
694 {
695 mdelay(1);
696 continue;
697 }
698
699 Avg_TSSI_Meas = read_nic_word(dev, Tssi_Mea_Value);
700
701 if(Avg_TSSI_Meas == 0)
702 {
703 write_nic_byte(dev, Pw_Track_Flag, 0);
704 write_nic_byte(dev, FW_Busy_Flag, 0);
705 return;
706 }
707
708 for(k = 0;k < 5; k++)
709 {
710 if(k !=4)
711 tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value1+k);
712 else
713 tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value2);
714
715 RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
716 }
717
718 //check if the report value is right
719 for(k = 0;k < 5; k++)
720 {
721 if(tmp_report[k] <= 20)
722 {
723 viviflag =TRUE;
724 break;
725 }
726 }
727 if(viviflag ==TRUE)
728 {
729 write_nic_byte(dev, Pw_Track_Flag, 0);
730 viviflag = FALSE;
731 RT_TRACE(COMP_POWER_TRACKING, "we filted this data\n");
732 for(k = 0;k < 5; k++)
733 tmp_report[k] = 0;
734 break;
735 }
736
737 for(k = 0;k < 5; k++)
738 {
739 Avg_TSSI_Meas_from_driver += tmp_report[k];
740 }
741
742 Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5;
743 RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver);
744 TSSI_13dBm = priv->TSSI_13dBm;
745 RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm);
746
747 //if(abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)
748 // For MacOS-compatible
749 if(Avg_TSSI_Meas_from_driver > TSSI_13dBm)
750 delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm;
751 else
752 delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver;
753
754 if(delta <= E_FOR_TX_POWER_TRACK)
755 {
756 priv->ieee80211->bdynamic_txpower_enable = TRUE;
757 write_nic_byte(dev, Pw_Track_Flag, 0);
758 write_nic_byte(dev, FW_Busy_Flag, 0);
759 RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
760 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
761 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
762 #ifdef RTL8190P
763 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
764 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
765 #endif
766 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference);
767 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
768 return;
769 }
770 else
771 {
772 if(Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK)
773 {
774 if (RF_Type == RF_2T4R)
775 {
776
777 if((priv->rfa_txpowertrackingindex > 0) &&(priv->rfc_txpowertrackingindex > 0))
778 {
779 priv->rfa_txpowertrackingindex--;
780 if(priv->rfa_txpowertrackingindex_real > 4)
781 {
782 priv->rfa_txpowertrackingindex_real--;
783 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
784 }
785
786 priv->rfc_txpowertrackingindex--;
787 if(priv->rfc_txpowertrackingindex_real > 4)
788 {
789 priv->rfc_txpowertrackingindex_real--;
790 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
791 }
792 }
793 else
794 {
795 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
796 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
797 }
798 }
799 else
800 {
801 if(priv->rfc_txpowertrackingindex > 0)
802 {
803 priv->rfc_txpowertrackingindex--;
804 if(priv->rfc_txpowertrackingindex_real > 4)
805 {
806 priv->rfc_txpowertrackingindex_real--;
807 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
808 }
809 }
810 else
811 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
812 }
813 }
814 else
815 {
816 if (RF_Type == RF_2T4R)
817 {
818 if((priv->rfa_txpowertrackingindex < TxBBGainTableLength - 1) &&(priv->rfc_txpowertrackingindex < TxBBGainTableLength - 1))
819 {
820 priv->rfa_txpowertrackingindex++;
821 priv->rfa_txpowertrackingindex_real++;
822 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
823 priv->rfc_txpowertrackingindex++;
824 priv->rfc_txpowertrackingindex_real++;
825 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
826 }
827 else
828 {
829 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
830 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
831 }
832 }
833 else
834 {
835 if(priv->rfc_txpowertrackingindex < (TxBBGainTableLength - 1))
836 {
837 priv->rfc_txpowertrackingindex++;
838 priv->rfc_txpowertrackingindex_real++;
839 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
840 }
841 else
842 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
843 }
844 }
845 if (RF_Type == RF_2T4R)
846 priv->CCKPresentAttentuation_difference
847 = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default;
848 else
849 priv->CCKPresentAttentuation_difference
850 = priv->rfc_txpowertrackingindex - priv->rfc_txpowertracking_default;
851
852 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
853 priv->CCKPresentAttentuation
854 = priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
855 else
856 priv->CCKPresentAttentuation
857 = priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
858
859 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
860 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
861 if(priv->CCKPresentAttentuation < 0)
862 priv->CCKPresentAttentuation = 0;
863
864 if(1)
865 {
866 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
867 {
868 priv->bcck_in_ch14 = TRUE;
869 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
870 }
871 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
872 {
873 priv->bcck_in_ch14 = FALSE;
874 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
875 }
876 else
877 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
878 }
879 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
880 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
881 #ifdef RTL8190P
882 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
883 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
884 #endif
885 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference);
886 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
887
888 if (priv->CCKPresentAttentuation_difference <= -12||priv->CCKPresentAttentuation_difference >= 24)
889 {
890 priv->ieee80211->bdynamic_txpower_enable = TRUE;
891 write_nic_byte(dev, Pw_Track_Flag, 0);
892 write_nic_byte(dev, FW_Busy_Flag, 0);
893 RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n");
894 return;
895 }
896
897
898 }
899 write_nic_byte(dev, Pw_Track_Flag, 0);
900 Avg_TSSI_Meas_from_driver = 0;
901 for(k = 0;k < 5; k++)
902 tmp_report[k] = 0;
903 break;
904 }
905 write_nic_byte(dev, FW_Busy_Flag, 0);
906 }
907 priv->ieee80211->bdynamic_txpower_enable = TRUE;
908 write_nic_byte(dev, Pw_Track_Flag, 0);
909 }
910 #ifndef RTL8190P
911 static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
912 {
913 #define ThermalMeterVal 9
914 struct r8192_priv *priv = ieee80211_priv(dev);
915 u32 tmpRegA, TempCCk;
916 u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval;
917 int i =0, CCKSwingNeedUpdate=0;
918
919 if(!priv->btxpower_trackingInit)
920 {
921 //Query OFDM default setting
922 tmpRegA= rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord);
923 for(i=0; i<OFDM_Table_Length; i++) //find the index
924 {
925 if(tmpRegA == OFDMSwingTable[i])
926 {
927 priv->OFDM_index= (u8)i;
928 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n",
929 rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index);
930 }
931 }
932
933 //Query CCK default setting From 0xa22
934 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
935 for(i=0 ; i<CCK_Table_length ; i++)
936 {
937 if(TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0])
938 {
939 priv->CCK_index =(u8) i;
940 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n",
941 rCCK0_TxFilter1, TempCCk, priv->CCK_index);
942 break;
943 }
944 }
945 priv->btxpower_trackingInit = TRUE;
946 //pHalData->TXPowercount = 0;
947 return;
948 }
949
950 //==========================
951 // this is only for test, should be masked
952 #if 0
953 {
954 //UINT32 eRFPath;
955 //UINT32 start_rf, end_rf;
956 UINT32 curr_addr;
957 //UINT32 reg_addr;
958 //UINT32 reg_addr_end;
959 UINT32 reg_value;
960 //start_rf = RF90_PATH_A;
961 //end_rf = RF90_PATH_B;//RF90_PATH_MAX;
962 //reg_addr = 0x0;
963 //reg_addr_end = 0x2F;
964
965 for (curr_addr = 0; curr_addr < 0x2d; curr_addr++)
966 {
967 reg_value = PHY_QueryRFReg( Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A,
968 curr_addr, bMaskDWord);
969 }
970
971 pHalData->TXPowercount = 0;
972 return;
973 }
974 #endif
975 //==========================
976
977 // read and filter out unreasonable value
978 tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7]
979 RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d \n", tmpRegA);
980 if(tmpRegA < 3 || tmpRegA > 13)
981 return;
982 if(tmpRegA >= 12) // if over 12, TP will be bad when high temprature
983 tmpRegA = 12;
984 RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d \n", tmpRegA);
985 priv->ThermalMeter[0] = ThermalMeterVal; //We use fixed value by Bryant's suggestion
986 priv->ThermalMeter[1] = ThermalMeterVal; //We use fixed value by Bryant's suggestion
987
988 //Get current RF-A temprature index
989 if(priv->ThermalMeter[0] >= (u8)tmpRegA) //lower temprature
990 {
991 tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA);
992 tmpCCK40Mindex = tmpCCK20Mindex - 6;
993 if(tmpOFDMindex >= OFDM_Table_Length)
994 tmpOFDMindex = OFDM_Table_Length-1;
995 if(tmpCCK20Mindex >= CCK_Table_length)
996 tmpCCK20Mindex = CCK_Table_length-1;
997 if(tmpCCK40Mindex >= CCK_Table_length)
998 tmpCCK40Mindex = CCK_Table_length-1;
999 }
1000 else
1001 {
1002 tmpval = ((u8)tmpRegA - priv->ThermalMeter[0]);
1003 if(tmpval >= 6) // higher temprature
1004 tmpOFDMindex = tmpCCK20Mindex = 0; // max to +6dB
1005 else
1006 tmpOFDMindex = tmpCCK20Mindex = 6 - tmpval;
1007 tmpCCK40Mindex = 0;
1008 }
1009 //DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d",
1010 //((u1Byte)tmpRegA - pHalData->ThermalMeter[0]),
1011 //tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex);
1012 if(priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) //40M
1013 tmpCCKindex = tmpCCK40Mindex;
1014 else
1015 tmpCCKindex = tmpCCK20Mindex;
1016
1017 //record for bandwidth swith
1018 priv->Record_CCK_20Mindex = tmpCCK20Mindex;
1019 priv->Record_CCK_40Mindex = tmpCCK40Mindex;
1020 RT_TRACE(COMP_POWER_TRACKING, "Record_CCK_20Mindex / Record_CCK_40Mindex = %d / %d.\n",
1021 priv->Record_CCK_20Mindex, priv->Record_CCK_40Mindex);
1022
1023 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
1024 {
1025 priv->bcck_in_ch14 = TRUE;
1026 CCKSwingNeedUpdate = 1;
1027 }
1028 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
1029 {
1030 priv->bcck_in_ch14 = FALSE;
1031 CCKSwingNeedUpdate = 1;
1032 }
1033
1034 if(priv->CCK_index != tmpCCKindex)
1035 {
1036 priv->CCK_index = tmpCCKindex;
1037 CCKSwingNeedUpdate = 1;
1038 }
1039
1040 if(CCKSwingNeedUpdate)
1041 {
1042 //DbgPrint("Update CCK Swing, CCK_index = %d\n", pHalData->CCK_index);
1043 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1044 }
1045 if(priv->OFDM_index != tmpOFDMindex)
1046 {
1047 priv->OFDM_index = tmpOFDMindex;
1048 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]);
1049 RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n",
1050 priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]);
1051 }
1052 priv->txpower_count = 0;
1053 }
1054 #endif
1055 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
1056 extern void dm_txpower_trackingcallback(struct work_struct *work)
1057 {
1058 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
1059 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,txpower_tracking_wq);
1060 struct net_device *dev = priv->ieee80211->dev;
1061 #else
1062 extern void dm_txpower_trackingcallback(struct net_device *dev)
1063 {
1064 #ifndef RTL8190P
1065 struct r8192_priv *priv = ieee80211_priv(dev);
1066 #endif
1067 #endif
1068
1069 #ifdef RTL8190P
1070 dm_TXPowerTrackingCallback_TSSI(dev);
1071 #else
1072 //if(priv->bDcut == TRUE)
1073 if(priv->IC_Cut >= IC_VersionCut_D)
1074 dm_TXPowerTrackingCallback_TSSI(dev);
1075 else
1076 dm_TXPowerTrackingCallback_ThermalMeter(dev);
1077 #endif
1078 }
1079
1080
1081 static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev)
1082 {
1083
1084 struct r8192_priv *priv = ieee80211_priv(dev);
1085
1086 //Initial the Tx BB index and mapping value
1087 priv->txbbgain_table[0].txbb_iq_amplifygain = 12;
1088 priv->txbbgain_table[0].txbbgain_value=0x7f8001fe;
1089 priv->txbbgain_table[1].txbb_iq_amplifygain = 11;
1090 priv->txbbgain_table[1].txbbgain_value=0x788001e2;
1091 priv->txbbgain_table[2].txbb_iq_amplifygain = 10;
1092 priv->txbbgain_table[2].txbbgain_value=0x71c001c7;
1093 priv->txbbgain_table[3].txbb_iq_amplifygain = 9;
1094 priv->txbbgain_table[3].txbbgain_value=0x6b8001ae;
1095 priv->txbbgain_table[4].txbb_iq_amplifygain = 8;
1096 priv->txbbgain_table[4].txbbgain_value=0x65400195;
1097 priv->txbbgain_table[5].txbb_iq_amplifygain = 7;
1098 priv->txbbgain_table[5].txbbgain_value=0x5fc0017f;
1099 priv->txbbgain_table[6].txbb_iq_amplifygain = 6;
1100 priv->txbbgain_table[6].txbbgain_value=0x5a400169;
1101 priv->txbbgain_table[7].txbb_iq_amplifygain = 5;
1102 priv->txbbgain_table[7].txbbgain_value=0x55400155;
1103 priv->txbbgain_table[8].txbb_iq_amplifygain = 4;
1104 priv->txbbgain_table[8].txbbgain_value=0x50800142;
1105 priv->txbbgain_table[9].txbb_iq_amplifygain = 3;
1106 priv->txbbgain_table[9].txbbgain_value=0x4c000130;
1107 priv->txbbgain_table[10].txbb_iq_amplifygain = 2;
1108 priv->txbbgain_table[10].txbbgain_value=0x47c0011f;
1109 priv->txbbgain_table[11].txbb_iq_amplifygain = 1;
1110 priv->txbbgain_table[11].txbbgain_value=0x43c0010f;
1111 priv->txbbgain_table[12].txbb_iq_amplifygain = 0;
1112 priv->txbbgain_table[12].txbbgain_value=0x40000100;
1113 priv->txbbgain_table[13].txbb_iq_amplifygain = -1;
1114 priv->txbbgain_table[13].txbbgain_value=0x3c8000f2;
1115 priv->txbbgain_table[14].txbb_iq_amplifygain = -2;
1116 priv->txbbgain_table[14].txbbgain_value=0x390000e4;
1117 priv->txbbgain_table[15].txbb_iq_amplifygain = -3;
1118 priv->txbbgain_table[15].txbbgain_value=0x35c000d7;
1119 priv->txbbgain_table[16].txbb_iq_amplifygain = -4;
1120 priv->txbbgain_table[16].txbbgain_value=0x32c000cb;
1121 priv->txbbgain_table[17].txbb_iq_amplifygain = -5;
1122 priv->txbbgain_table[17].txbbgain_value=0x300000c0;
1123 priv->txbbgain_table[18].txbb_iq_amplifygain = -6;
1124 priv->txbbgain_table[18].txbbgain_value=0x2d4000b5;
1125 priv->txbbgain_table[19].txbb_iq_amplifygain = -7;
1126 priv->txbbgain_table[19].txbbgain_value=0x2ac000ab;
1127 priv->txbbgain_table[20].txbb_iq_amplifygain = -8;
1128 priv->txbbgain_table[20].txbbgain_value=0x288000a2;
1129 priv->txbbgain_table[21].txbb_iq_amplifygain = -9;
1130 priv->txbbgain_table[21].txbbgain_value=0x26000098;
1131 priv->txbbgain_table[22].txbb_iq_amplifygain = -10;
1132 priv->txbbgain_table[22].txbbgain_value=0x24000090;
1133 priv->txbbgain_table[23].txbb_iq_amplifygain = -11;
1134 priv->txbbgain_table[23].txbbgain_value=0x22000088;
1135 priv->txbbgain_table[24].txbb_iq_amplifygain = -12;
1136 priv->txbbgain_table[24].txbbgain_value=0x20000080;
1137 priv->txbbgain_table[25].txbb_iq_amplifygain = -13;
1138 priv->txbbgain_table[25].txbbgain_value=0x1a00006c;
1139 priv->txbbgain_table[26].txbb_iq_amplifygain = -14;
1140 priv->txbbgain_table[26].txbbgain_value=0x1c800072;
1141 priv->txbbgain_table[27].txbb_iq_amplifygain = -15;
1142 priv->txbbgain_table[27].txbbgain_value=0x18000060;
1143 priv->txbbgain_table[28].txbb_iq_amplifygain = -16;
1144 priv->txbbgain_table[28].txbbgain_value=0x19800066;
1145 priv->txbbgain_table[29].txbb_iq_amplifygain = -17;
1146 priv->txbbgain_table[29].txbbgain_value=0x15800056;
1147 priv->txbbgain_table[30].txbb_iq_amplifygain = -18;
1148 priv->txbbgain_table[30].txbbgain_value=0x26c0005b;
1149 priv->txbbgain_table[31].txbb_iq_amplifygain = -19;
1150 priv->txbbgain_table[31].txbbgain_value=0x14400051;
1151 priv->txbbgain_table[32].txbb_iq_amplifygain = -20;
1152 priv->txbbgain_table[32].txbbgain_value=0x24400051;
1153 priv->txbbgain_table[33].txbb_iq_amplifygain = -21;
1154 priv->txbbgain_table[33].txbbgain_value=0x1300004c;
1155 priv->txbbgain_table[34].txbb_iq_amplifygain = -22;
1156 priv->txbbgain_table[34].txbbgain_value=0x12000048;
1157 priv->txbbgain_table[35].txbb_iq_amplifygain = -23;
1158 priv->txbbgain_table[35].txbbgain_value=0x11000044;
1159 priv->txbbgain_table[36].txbb_iq_amplifygain = -24;
1160 priv->txbbgain_table[36].txbbgain_value=0x10000040;
1161
1162 //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1163 //This Table is for CH1~CH13
1164 priv->cck_txbbgain_table[0].ccktxbb_valuearray[0] = 0x36;
1165 priv->cck_txbbgain_table[0].ccktxbb_valuearray[1] = 0x35;
1166 priv->cck_txbbgain_table[0].ccktxbb_valuearray[2] = 0x2e;
1167 priv->cck_txbbgain_table[0].ccktxbb_valuearray[3] = 0x25;
1168 priv->cck_txbbgain_table[0].ccktxbb_valuearray[4] = 0x1c;
1169 priv->cck_txbbgain_table[0].ccktxbb_valuearray[5] = 0x12;
1170 priv->cck_txbbgain_table[0].ccktxbb_valuearray[6] = 0x09;
1171 priv->cck_txbbgain_table[0].ccktxbb_valuearray[7] = 0x04;
1172
1173 priv->cck_txbbgain_table[1].ccktxbb_valuearray[0] = 0x33;
1174 priv->cck_txbbgain_table[1].ccktxbb_valuearray[1] = 0x32;
1175 priv->cck_txbbgain_table[1].ccktxbb_valuearray[2] = 0x2b;
1176 priv->cck_txbbgain_table[1].ccktxbb_valuearray[3] = 0x23;
1177 priv->cck_txbbgain_table[1].ccktxbb_valuearray[4] = 0x1a;
1178 priv->cck_txbbgain_table[1].ccktxbb_valuearray[5] = 0x11;
1179 priv->cck_txbbgain_table[1].ccktxbb_valuearray[6] = 0x08;
1180 priv->cck_txbbgain_table[1].ccktxbb_valuearray[7] = 0x04;
1181
1182 priv->cck_txbbgain_table[2].ccktxbb_valuearray[0] = 0x30;
1183 priv->cck_txbbgain_table[2].ccktxbb_valuearray[1] = 0x2f;
1184 priv->cck_txbbgain_table[2].ccktxbb_valuearray[2] = 0x29;
1185 priv->cck_txbbgain_table[2].ccktxbb_valuearray[3] = 0x21;
1186 priv->cck_txbbgain_table[2].ccktxbb_valuearray[4] = 0x19;
1187 priv->cck_txbbgain_table[2].ccktxbb_valuearray[5] = 0x10;
1188 priv->cck_txbbgain_table[2].ccktxbb_valuearray[6] = 0x08;
1189 priv->cck_txbbgain_table[2].ccktxbb_valuearray[7] = 0x03;
1190
1191 priv->cck_txbbgain_table[3].ccktxbb_valuearray[0] = 0x2d;
1192 priv->cck_txbbgain_table[3].ccktxbb_valuearray[1] = 0x2d;
1193 priv->cck_txbbgain_table[3].ccktxbb_valuearray[2] = 0x27;
1194 priv->cck_txbbgain_table[3].ccktxbb_valuearray[3] = 0x1f;
1195 priv->cck_txbbgain_table[3].ccktxbb_valuearray[4] = 0x18;
1196 priv->cck_txbbgain_table[3].ccktxbb_valuearray[5] = 0x0f;
1197 priv->cck_txbbgain_table[3].ccktxbb_valuearray[6] = 0x08;
1198 priv->cck_txbbgain_table[3].ccktxbb_valuearray[7] = 0x03;
1199
1200 priv->cck_txbbgain_table[4].ccktxbb_valuearray[0] = 0x2b;
1201 priv->cck_txbbgain_table[4].ccktxbb_valuearray[1] = 0x2a;
1202 priv->cck_txbbgain_table[4].ccktxbb_valuearray[2] = 0x25;
1203 priv->cck_txbbgain_table[4].ccktxbb_valuearray[3] = 0x1e;
1204 priv->cck_txbbgain_table[4].ccktxbb_valuearray[4] = 0x16;
1205 priv->cck_txbbgain_table[4].ccktxbb_valuearray[5] = 0x0e;
1206 priv->cck_txbbgain_table[4].ccktxbb_valuearray[6] = 0x07;
1207 priv->cck_txbbgain_table[4].ccktxbb_valuearray[7] = 0x03;
1208
1209 priv->cck_txbbgain_table[5].ccktxbb_valuearray[0] = 0x28;
1210 priv->cck_txbbgain_table[5].ccktxbb_valuearray[1] = 0x28;
1211 priv->cck_txbbgain_table[5].ccktxbb_valuearray[2] = 0x22;
1212 priv->cck_txbbgain_table[5].ccktxbb_valuearray[3] = 0x1c;
1213 priv->cck_txbbgain_table[5].ccktxbb_valuearray[4] = 0x15;
1214 priv->cck_txbbgain_table[5].ccktxbb_valuearray[5] = 0x0d;
1215 priv->cck_txbbgain_table[5].ccktxbb_valuearray[6] = 0x07;
1216 priv->cck_txbbgain_table[5].ccktxbb_valuearray[7] = 0x03;
1217
1218 priv->cck_txbbgain_table[6].ccktxbb_valuearray[0] = 0x26;
1219 priv->cck_txbbgain_table[6].ccktxbb_valuearray[1] = 0x25;
1220 priv->cck_txbbgain_table[6].ccktxbb_valuearray[2] = 0x21;
1221 priv->cck_txbbgain_table[6].ccktxbb_valuearray[3] = 0x1b;
1222 priv->cck_txbbgain_table[6].ccktxbb_valuearray[4] = 0x14;
1223 priv->cck_txbbgain_table[6].ccktxbb_valuearray[5] = 0x0d;
1224 priv->cck_txbbgain_table[6].ccktxbb_valuearray[6] = 0x06;
1225 priv->cck_txbbgain_table[6].ccktxbb_valuearray[7] = 0x03;
1226
1227 priv->cck_txbbgain_table[7].ccktxbb_valuearray[0] = 0x24;
1228 priv->cck_txbbgain_table[7].ccktxbb_valuearray[1] = 0x23;
1229 priv->cck_txbbgain_table[7].ccktxbb_valuearray[2] = 0x1f;
1230 priv->cck_txbbgain_table[7].ccktxbb_valuearray[3] = 0x19;
1231 priv->cck_txbbgain_table[7].ccktxbb_valuearray[4] = 0x13;
1232 priv->cck_txbbgain_table[7].ccktxbb_valuearray[5] = 0x0c;
1233 priv->cck_txbbgain_table[7].ccktxbb_valuearray[6] = 0x06;
1234 priv->cck_txbbgain_table[7].ccktxbb_valuearray[7] = 0x03;
1235
1236 priv->cck_txbbgain_table[8].ccktxbb_valuearray[0] = 0x22;
1237 priv->cck_txbbgain_table[8].ccktxbb_valuearray[1] = 0x21;
1238 priv->cck_txbbgain_table[8].ccktxbb_valuearray[2] = 0x1d;
1239 priv->cck_txbbgain_table[8].ccktxbb_valuearray[3] = 0x18;
1240 priv->cck_txbbgain_table[8].ccktxbb_valuearray[4] = 0x11;
1241 priv->cck_txbbgain_table[8].ccktxbb_valuearray[5] = 0x0b;
1242 priv->cck_txbbgain_table[8].ccktxbb_valuearray[6] = 0x06;
1243 priv->cck_txbbgain_table[8].ccktxbb_valuearray[7] = 0x02;
1244
1245 priv->cck_txbbgain_table[9].ccktxbb_valuearray[0] = 0x20;
1246 priv->cck_txbbgain_table[9].ccktxbb_valuearray[1] = 0x20;
1247 priv->cck_txbbgain_table[9].ccktxbb_valuearray[2] = 0x1b;
1248 priv->cck_txbbgain_table[9].ccktxbb_valuearray[3] = 0x16;
1249 priv->cck_txbbgain_table[9].ccktxbb_valuearray[4] = 0x11;
1250 priv->cck_txbbgain_table[9].ccktxbb_valuearray[5] = 0x08;
1251 priv->cck_txbbgain_table[9].ccktxbb_valuearray[6] = 0x05;
1252 priv->cck_txbbgain_table[9].ccktxbb_valuearray[7] = 0x02;
1253
1254 priv->cck_txbbgain_table[10].ccktxbb_valuearray[0] = 0x1f;
1255 priv->cck_txbbgain_table[10].ccktxbb_valuearray[1] = 0x1e;
1256 priv->cck_txbbgain_table[10].ccktxbb_valuearray[2] = 0x1a;
1257 priv->cck_txbbgain_table[10].ccktxbb_valuearray[3] = 0x15;
1258 priv->cck_txbbgain_table[10].ccktxbb_valuearray[4] = 0x10;
1259 priv->cck_txbbgain_table[10].ccktxbb_valuearray[5] = 0x0a;
1260 priv->cck_txbbgain_table[10].ccktxbb_valuearray[6] = 0x05;
1261 priv->cck_txbbgain_table[10].ccktxbb_valuearray[7] = 0x02;
1262
1263 priv->cck_txbbgain_table[11].ccktxbb_valuearray[0] = 0x1d;
1264 priv->cck_txbbgain_table[11].ccktxbb_valuearray[1] = 0x1c;
1265 priv->cck_txbbgain_table[11].ccktxbb_valuearray[2] = 0x18;
1266 priv->cck_txbbgain_table[11].ccktxbb_valuearray[3] = 0x14;
1267 priv->cck_txbbgain_table[11].ccktxbb_valuearray[4] = 0x0f;
1268 priv->cck_txbbgain_table[11].ccktxbb_valuearray[5] = 0x0a;
1269 priv->cck_txbbgain_table[11].ccktxbb_valuearray[6] = 0x05;
1270 priv->cck_txbbgain_table[11].ccktxbb_valuearray[7] = 0x02;
1271
1272 priv->cck_txbbgain_table[12].ccktxbb_valuearray[0] = 0x1b;
1273 priv->cck_txbbgain_table[12].ccktxbb_valuearray[1] = 0x1a;
1274 priv->cck_txbbgain_table[12].ccktxbb_valuearray[2] = 0x17;
1275 priv->cck_txbbgain_table[12].ccktxbb_valuearray[3] = 0x13;
1276 priv->cck_txbbgain_table[12].ccktxbb_valuearray[4] = 0x0e;
1277 priv->cck_txbbgain_table[12].ccktxbb_valuearray[5] = 0x09;
1278 priv->cck_txbbgain_table[12].ccktxbb_valuearray[6] = 0x04;
1279 priv->cck_txbbgain_table[12].ccktxbb_valuearray[7] = 0x02;
1280
1281 priv->cck_txbbgain_table[13].ccktxbb_valuearray[0] = 0x1a;
1282 priv->cck_txbbgain_table[13].ccktxbb_valuearray[1] = 0x19;
1283 priv->cck_txbbgain_table[13].ccktxbb_valuearray[2] = 0x16;
1284 priv->cck_txbbgain_table[13].ccktxbb_valuearray[3] = 0x12;
1285 priv->cck_txbbgain_table[13].ccktxbb_valuearray[4] = 0x0d;
1286 priv->cck_txbbgain_table[13].ccktxbb_valuearray[5] = 0x09;
1287 priv->cck_txbbgain_table[13].ccktxbb_valuearray[6] = 0x04;
1288 priv->cck_txbbgain_table[13].ccktxbb_valuearray[7] = 0x02;
1289
1290 priv->cck_txbbgain_table[14].ccktxbb_valuearray[0] = 0x18;
1291 priv->cck_txbbgain_table[14].ccktxbb_valuearray[1] = 0x17;
1292 priv->cck_txbbgain_table[14].ccktxbb_valuearray[2] = 0x15;
1293 priv->cck_txbbgain_table[14].ccktxbb_valuearray[3] = 0x11;
1294 priv->cck_txbbgain_table[14].ccktxbb_valuearray[4] = 0x0c;
1295 priv->cck_txbbgain_table[14].ccktxbb_valuearray[5] = 0x08;
1296 priv->cck_txbbgain_table[14].ccktxbb_valuearray[6] = 0x04;
1297 priv->cck_txbbgain_table[14].ccktxbb_valuearray[7] = 0x02;
1298
1299 priv->cck_txbbgain_table[15].ccktxbb_valuearray[0] = 0x17;
1300 priv->cck_txbbgain_table[15].ccktxbb_valuearray[1] = 0x16;
1301 priv->cck_txbbgain_table[15].ccktxbb_valuearray[2] = 0x13;
1302 priv->cck_txbbgain_table[15].ccktxbb_valuearray[3] = 0x10;
1303 priv->cck_txbbgain_table[15].ccktxbb_valuearray[4] = 0x0c;
1304 priv->cck_txbbgain_table[15].ccktxbb_valuearray[5] = 0x08;
1305 priv->cck_txbbgain_table[15].ccktxbb_valuearray[6] = 0x04;
1306 priv->cck_txbbgain_table[15].ccktxbb_valuearray[7] = 0x02;
1307
1308 priv->cck_txbbgain_table[16].ccktxbb_valuearray[0] = 0x16;
1309 priv->cck_txbbgain_table[16].ccktxbb_valuearray[1] = 0x15;
1310 priv->cck_txbbgain_table[16].ccktxbb_valuearray[2] = 0x12;
1311 priv->cck_txbbgain_table[16].ccktxbb_valuearray[3] = 0x0f;
1312 priv->cck_txbbgain_table[16].ccktxbb_valuearray[4] = 0x0b;
1313 priv->cck_txbbgain_table[16].ccktxbb_valuearray[5] = 0x07;
1314 priv->cck_txbbgain_table[16].ccktxbb_valuearray[6] = 0x04;
1315 priv->cck_txbbgain_table[16].ccktxbb_valuearray[7] = 0x01;
1316
1317 priv->cck_txbbgain_table[17].ccktxbb_valuearray[0] = 0x14;
1318 priv->cck_txbbgain_table[17].ccktxbb_valuearray[1] = 0x14;
1319 priv->cck_txbbgain_table[17].ccktxbb_valuearray[2] = 0x11;
1320 priv->cck_txbbgain_table[17].ccktxbb_valuearray[3] = 0x0e;
1321 priv->cck_txbbgain_table[17].ccktxbb_valuearray[4] = 0x0b;
1322 priv->cck_txbbgain_table[17].ccktxbb_valuearray[5] = 0x07;
1323 priv->cck_txbbgain_table[17].ccktxbb_valuearray[6] = 0x03;
1324 priv->cck_txbbgain_table[17].ccktxbb_valuearray[7] = 0x02;
1325
1326 priv->cck_txbbgain_table[18].ccktxbb_valuearray[0] = 0x13;
1327 priv->cck_txbbgain_table[18].ccktxbb_valuearray[1] = 0x13;
1328 priv->cck_txbbgain_table[18].ccktxbb_valuearray[2] = 0x10;
1329 priv->cck_txbbgain_table[18].ccktxbb_valuearray[3] = 0x0d;
1330 priv->cck_txbbgain_table[18].ccktxbb_valuearray[4] = 0x0a;
1331 priv->cck_txbbgain_table[18].ccktxbb_valuearray[5] = 0x06;
1332 priv->cck_txbbgain_table[18].ccktxbb_valuearray[6] = 0x03;
1333 priv->cck_txbbgain_table[18].ccktxbb_valuearray[7] = 0x01;
1334
1335 priv->cck_txbbgain_table[19].ccktxbb_valuearray[0] = 0x12;
1336 priv->cck_txbbgain_table[19].ccktxbb_valuearray[1] = 0x12;
1337 priv->cck_txbbgain_table[19].ccktxbb_valuearray[2] = 0x0f;
1338 priv->cck_txbbgain_table[19].ccktxbb_valuearray[3] = 0x0c;
1339 priv->cck_txbbgain_table[19].ccktxbb_valuearray[4] = 0x09;
1340 priv->cck_txbbgain_table[19].ccktxbb_valuearray[5] = 0x06;
1341 priv->cck_txbbgain_table[19].ccktxbb_valuearray[6] = 0x03;
1342 priv->cck_txbbgain_table[19].ccktxbb_valuearray[7] = 0x01;
1343
1344 priv->cck_txbbgain_table[20].ccktxbb_valuearray[0] = 0x11;
1345 priv->cck_txbbgain_table[20].ccktxbb_valuearray[1] = 0x11;
1346 priv->cck_txbbgain_table[20].ccktxbb_valuearray[2] = 0x0f;
1347 priv->cck_txbbgain_table[20].ccktxbb_valuearray[3] = 0x0c;
1348 priv->cck_txbbgain_table[20].ccktxbb_valuearray[4] = 0x09;
1349 priv->cck_txbbgain_table[20].ccktxbb_valuearray[5] = 0x06;
1350 priv->cck_txbbgain_table[20].ccktxbb_valuearray[6] = 0x03;
1351 priv->cck_txbbgain_table[20].ccktxbb_valuearray[7] = 0x01;
1352
1353 priv->cck_txbbgain_table[21].ccktxbb_valuearray[0] = 0x10;
1354 priv->cck_txbbgain_table[21].ccktxbb_valuearray[1] = 0x10;
1355 priv->cck_txbbgain_table[21].ccktxbb_valuearray[2] = 0x0e;
1356 priv->cck_txbbgain_table[21].ccktxbb_valuearray[3] = 0x0b;
1357 priv->cck_txbbgain_table[21].ccktxbb_valuearray[4] = 0x08;
1358 priv->cck_txbbgain_table[21].ccktxbb_valuearray[5] = 0x05;
1359 priv->cck_txbbgain_table[21].ccktxbb_valuearray[6] = 0x03;
1360 priv->cck_txbbgain_table[21].ccktxbb_valuearray[7] = 0x01;
1361
1362 priv->cck_txbbgain_table[22].ccktxbb_valuearray[0] = 0x0f;
1363 priv->cck_txbbgain_table[22].ccktxbb_valuearray[1] = 0x0f;
1364 priv->cck_txbbgain_table[22].ccktxbb_valuearray[2] = 0x0d;
1365 priv->cck_txbbgain_table[22].ccktxbb_valuearray[3] = 0x0b;
1366 priv->cck_txbbgain_table[22].ccktxbb_valuearray[4] = 0x08;
1367 priv->cck_txbbgain_table[22].ccktxbb_valuearray[5] = 0x05;
1368 priv->cck_txbbgain_table[22].ccktxbb_valuearray[6] = 0x03;
1369 priv->cck_txbbgain_table[22].ccktxbb_valuearray[7] = 0x01;
1370
1371 //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1372 //This Table is for CH14
1373 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[0] = 0x36;
1374 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[1] = 0x35;
1375 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[2] = 0x2e;
1376 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[3] = 0x1b;
1377 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[4] = 0x00;
1378 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[5] = 0x00;
1379 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[6] = 0x00;
1380 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[7] = 0x00;
1381
1382 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[0] = 0x33;
1383 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[1] = 0x32;
1384 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[2] = 0x2b;
1385 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[3] = 0x19;
1386 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[4] = 0x00;
1387 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[5] = 0x00;
1388 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[6] = 0x00;
1389 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[7] = 0x00;
1390
1391 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[0] = 0x30;
1392 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[1] = 0x2f;
1393 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[2] = 0x29;
1394 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[3] = 0x18;
1395 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[4] = 0x00;
1396 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[5] = 0x00;
1397 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[6] = 0x00;
1398 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[7] = 0x00;
1399
1400 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[0] = 0x2d;
1401 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[1] = 0x2d;
1402 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[2] = 0x27;
1403 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[3] = 0x17;
1404 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[4] = 0x00;
1405 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[5] = 0x00;
1406 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[6] = 0x00;
1407 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[7] = 0x00;
1408
1409 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[0] = 0x2b;
1410 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[1] = 0x2a;
1411 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[2] = 0x25;
1412 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[3] = 0x15;
1413 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[4] = 0x00;
1414 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[5] = 0x00;
1415 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[6] = 0x00;
1416 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[7] = 0x00;
1417
1418 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[0] = 0x28;
1419 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[1] = 0x28;
1420 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[2] = 0x22;
1421 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[3] = 0x14;
1422 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[4] = 0x00;
1423 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[5] = 0x00;
1424 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[6] = 0x00;
1425 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[7] = 0x00;
1426
1427 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[0] = 0x26;
1428 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[1] = 0x25;
1429 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[2] = 0x21;
1430 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[3] = 0x13;
1431 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[4] = 0x00;
1432 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[5] = 0x00;
1433 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[6] = 0x00;
1434 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[7] = 0x00;
1435
1436 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[0] = 0x24;
1437 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[1] = 0x23;
1438 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[2] = 0x1f;
1439 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[3] = 0x12;
1440 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[4] = 0x00;
1441 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[5] = 0x00;
1442 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[6] = 0x00;
1443 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[7] = 0x00;
1444
1445 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[0] = 0x22;
1446 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[1] = 0x21;
1447 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[2] = 0x1d;
1448 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[3] = 0x11;
1449 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[4] = 0x00;
1450 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[5] = 0x00;
1451 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[6] = 0x00;
1452 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[7] = 0x00;
1453
1454 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[0] = 0x20;
1455 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[1] = 0x20;
1456 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[2] = 0x1b;
1457 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[3] = 0x10;
1458 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[4] = 0x00;
1459 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[5] = 0x00;
1460 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[6] = 0x00;
1461 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[7] = 0x00;
1462
1463 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[0] = 0x1f;
1464 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[1] = 0x1e;
1465 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[2] = 0x1a;
1466 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[3] = 0x0f;
1467 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[4] = 0x00;
1468 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[5] = 0x00;
1469 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[6] = 0x00;
1470 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[7] = 0x00;
1471
1472 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[0] = 0x1d;
1473 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[1] = 0x1c;
1474 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[2] = 0x18;
1475 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[3] = 0x0e;
1476 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[4] = 0x00;
1477 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[5] = 0x00;
1478 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[6] = 0x00;
1479 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[7] = 0x00;
1480
1481 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[0] = 0x1b;
1482 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[1] = 0x1a;
1483 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[2] = 0x17;
1484 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[3] = 0x0e;
1485 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[4] = 0x00;
1486 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[5] = 0x00;
1487 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[6] = 0x00;
1488 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[7] = 0x00;
1489
1490 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[0] = 0x1a;
1491 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[1] = 0x19;
1492 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[2] = 0x16;
1493 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[3] = 0x0d;
1494 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[4] = 0x00;
1495 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[5] = 0x00;
1496 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[6] = 0x00;
1497 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[7] = 0x00;
1498
1499 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[0] = 0x18;
1500 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[1] = 0x17;
1501 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[2] = 0x15;
1502 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[3] = 0x0c;
1503 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[4] = 0x00;
1504 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[5] = 0x00;
1505 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[6] = 0x00;
1506 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[7] = 0x00;
1507
1508 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[0] = 0x17;
1509 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[1] = 0x16;
1510 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[2] = 0x13;
1511 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[3] = 0x0b;
1512 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[4] = 0x00;
1513 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[5] = 0x00;
1514 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[6] = 0x00;
1515 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[7] = 0x00;
1516
1517 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[0] = 0x16;
1518 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[1] = 0x15;
1519 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[2] = 0x12;
1520 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[3] = 0x0b;
1521 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[4] = 0x00;
1522 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[5] = 0x00;
1523 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[6] = 0x00;
1524 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[7] = 0x00;
1525
1526 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[0] = 0x14;
1527 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[1] = 0x14;
1528 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[2] = 0x11;
1529 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[3] = 0x0a;
1530 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[4] = 0x00;
1531 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[5] = 0x00;
1532 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[6] = 0x00;
1533 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[7] = 0x00;
1534
1535 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[0] = 0x13;
1536 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[1] = 0x13;
1537 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[2] = 0x10;
1538 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[3] = 0x0a;
1539 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[4] = 0x00;
1540 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[5] = 0x00;
1541 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[6] = 0x00;
1542 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[7] = 0x00;
1543
1544 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[0] = 0x12;
1545 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[1] = 0x12;
1546 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[2] = 0x0f;
1547 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[3] = 0x09;
1548 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[4] = 0x00;
1549 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[5] = 0x00;
1550 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[6] = 0x00;
1551 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[7] = 0x00;
1552
1553 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[0] = 0x11;
1554 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[1] = 0x11;
1555 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[2] = 0x0f;
1556 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[3] = 0x09;
1557 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[4] = 0x00;
1558 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[5] = 0x00;
1559 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[6] = 0x00;
1560 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[7] = 0x00;
1561
1562 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[0] = 0x10;
1563 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[1] = 0x10;
1564 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[2] = 0x0e;
1565 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[3] = 0x08;
1566 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[4] = 0x00;
1567 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[5] = 0x00;
1568 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[6] = 0x00;
1569 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[7] = 0x00;
1570
1571 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[0] = 0x0f;
1572 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[1] = 0x0f;
1573 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[2] = 0x0d;
1574 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[3] = 0x08;
1575 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[4] = 0x00;
1576 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[5] = 0x00;
1577 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[6] = 0x00;
1578 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[7] = 0x00;
1579
1580 priv->btxpower_tracking = TRUE;
1581 priv->txpower_count = 0;
1582 priv->btxpower_trackingInit = FALSE;
1583
1584 }
1585 #ifndef RTL8190P
1586 static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
1587 {
1588 struct r8192_priv *priv = ieee80211_priv(dev);
1589
1590 // Tx Power tracking by Theremal Meter require Firmware R/W 3-wire. This mechanism
1591 // can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w
1592 // 3-wire by driver cause RF goes into wrong state.
1593 if(priv->ieee80211->FwRWRF)
1594 priv->btxpower_tracking = TRUE;
1595 else
1596 priv->btxpower_tracking = FALSE;
1597 priv->txpower_count = 0;
1598 priv->btxpower_trackingInit = FALSE;
1599 }
1600 #endif
1601
1602 void dm_initialize_txpower_tracking(struct net_device *dev)
1603 {
1604 #ifndef RTL8190P
1605 struct r8192_priv *priv = ieee80211_priv(dev);
1606 #endif
1607 #ifdef RTL8190P
1608 dm_InitializeTXPowerTracking_TSSI(dev);
1609 #else
1610 //if(priv->bDcut == TRUE)
1611 if(priv->IC_Cut >= IC_VersionCut_D)
1612 dm_InitializeTXPowerTracking_TSSI(dev);
1613 else
1614 dm_InitializeTXPowerTracking_ThermalMeter(dev);
1615 #endif
1616 } // dm_InitializeTXPowerTracking
1617
1618
1619 static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev)
1620 {
1621 struct r8192_priv *priv = ieee80211_priv(dev);
1622 static u32 tx_power_track_counter = 0;
1623 RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
1624 if(read_nic_byte(dev, 0x11e) ==1)
1625 return;
1626 if(!priv->btxpower_tracking)
1627 return;
1628 tx_power_track_counter++;
1629
1630
1631 if(tx_power_track_counter > 90)
1632 {
1633 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1634 queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0);
1635 #else
1636 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1637 schedule_task(&priv->txpower_tracking_wq);
1638 #else
1639 queue_work(priv->priv_wq,&priv->txpower_tracking_wq);
1640 #endif
1641 #endif
1642 tx_power_track_counter =0;
1643 }
1644
1645 }
1646
1647 #ifndef RTL8190P
1648 static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
1649 {
1650 struct r8192_priv *priv = ieee80211_priv(dev);
1651 static u8 TM_Trigger=0;
1652 #if 0
1653 u1Byte i;
1654 u4Byte tmpRegA;
1655 for(i=0; i<50; i++)
1656 {
1657 tmpRegA = PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7]
1658 PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1659 //delay_us(100);
1660 PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1661 //delay_us(100);
1662 }
1663 DbgPrint("Trigger and readback ThermalMeter, write RF reg0x2 = 0x4d to 0x4f for 50 times\n");
1664 #else
1665 //DbgPrint("dm_CheckTXPowerTracking() \n");
1666 if(!priv->btxpower_tracking)
1667 return;
1668 else
1669 {
1670 if(priv->txpower_count <= 2)
1671 {
1672 priv->txpower_count++;
1673 return;
1674 }
1675 }
1676
1677 if(!TM_Trigger)
1678 {
1679 //Attention!! You have to wirte all 12bits data to RF, or it may cause RF to crash
1680 //actually write reg0x02 bit1=0, then bit1=1.
1681 //DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n");
1682 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1683 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1684 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1685 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1686 TM_Trigger = 1;
1687 return;
1688 }
1689 else
1690 {
1691 //DbgPrint("Schedule TxPowerTrackingWorkItem\n");
1692 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1693 queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0);
1694 #else
1695 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1696 schedule_task(&priv->txpower_tracking_wq);
1697 #else
1698 queue_work(priv->priv_wq,&priv->txpower_tracking_wq);
1699 #endif
1700 #endif
1701 TM_Trigger = 0;
1702 }
1703 #endif
1704 }
1705 #endif
1706
1707 static void dm_check_txpower_tracking(struct net_device *dev)
1708 {
1709 #ifndef RTL8190P
1710 struct r8192_priv *priv = ieee80211_priv(dev);
1711 //static u32 tx_power_track_counter = 0;
1712 #endif
1713 #ifdef RTL8190P
1714 dm_CheckTXPowerTracking_TSSI(dev);
1715 #else
1716 //if(priv->bDcut == TRUE)
1717 if(priv->IC_Cut >= IC_VersionCut_D)
1718 dm_CheckTXPowerTracking_TSSI(dev);
1719 else
1720 dm_CheckTXPowerTracking_ThermalMeter(dev);
1721 #endif
1722
1723 } // dm_CheckTXPowerTracking
1724
1725
1726 static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14)
1727 {
1728 u32 TempVal;
1729 struct r8192_priv *priv = ieee80211_priv(dev);
1730 //Write 0xa22 0xa23
1731 TempVal = 0;
1732 if(!bInCH14){
1733 //Write 0xa22 0xa23
1734 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] +
1735 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ;
1736
1737 rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal);
1738 //Write 0xa24 ~ 0xa27
1739 TempVal = 0;
1740 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] +
1741 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) +
1742 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+
1743 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24));
1744 rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal);
1745 //Write 0xa28 0xa29
1746 TempVal = 0;
1747 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] +
1748 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ;
1749
1750 rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal);
1751 }
1752 else
1753 {
1754 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] +
1755 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ;
1756
1757 rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal);
1758 //Write 0xa24 ~ 0xa27
1759 TempVal = 0;
1760 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] +
1761 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) +
1762 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+
1763 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24));
1764 rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal);
1765 //Write 0xa28 0xa29
1766 TempVal = 0;
1767 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] +
1768 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ;
1769
1770 rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal);
1771 }
1772
1773
1774 }
1775 #ifndef RTL8190P
1776 static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14)
1777 {
1778 u32 TempVal;
1779 struct r8192_priv *priv = ieee80211_priv(dev);
1780
1781 TempVal = 0;
1782 if(!bInCH14)
1783 {
1784 //Write 0xa22 0xa23
1785 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] +
1786 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8) ;
1787 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1788 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1789 rCCK0_TxFilter1, TempVal);
1790 //Write 0xa24 ~ 0xa27
1791 TempVal = 0;
1792 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] +
1793 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) +
1794 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16 )+
1795 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24);
1796 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1797 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1798 rCCK0_TxFilter2, TempVal);
1799 //Write 0xa28 0xa29
1800 TempVal = 0;
1801 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] +
1802 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8) ;
1803
1804 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1805 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1806 rCCK0_DebugPort, TempVal);
1807 }
1808 else
1809 {
1810 // priv->CCKTxPowerAdjustCntNotCh14++; //cosa add for debug.
1811 //Write 0xa22 0xa23
1812 TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] +
1813 (CCKSwingTable_Ch14[priv->CCK_index][1]<<8) ;
1814
1815 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1816 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1817 rCCK0_TxFilter1, TempVal);
1818 //Write 0xa24 ~ 0xa27
1819 TempVal = 0;
1820 TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] +
1821 (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) +
1822 (CCKSwingTable_Ch14[priv->CCK_index][4]<<16 )+
1823 (CCKSwingTable_Ch14[priv->CCK_index][5]<<24);
1824 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1825 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1826 rCCK0_TxFilter2, TempVal);
1827 //Write 0xa28 0xa29
1828 TempVal = 0;
1829 TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] +
1830 (CCKSwingTable_Ch14[priv->CCK_index][7]<<8) ;
1831
1832 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1833 RT_TRACE(COMP_POWER_TRACKING,"CCK chnl 14, reg 0x%x = 0x%x\n",
1834 rCCK0_DebugPort, TempVal);
1835 }
1836 }
1837 #endif
1838
1839
1840 extern void dm_cck_txpower_adjust(
1841 struct net_device *dev,
1842 bool binch14
1843 )
1844 { // dm_CCKTxPowerAdjust
1845 #ifndef RTL8190P
1846 struct r8192_priv *priv = ieee80211_priv(dev);
1847 #endif
1848 #ifdef RTL8190P
1849 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1850 #else
1851 //if(priv->bDcut == TRUE)
1852 if(priv->IC_Cut >= IC_VersionCut_D)
1853 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1854 else
1855 dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14);
1856 #endif
1857 }
1858
1859
1860 #ifndef RTL8192U
1861 static void dm_txpower_reset_recovery(
1862 struct net_device *dev
1863 )
1864 {
1865 struct r8192_priv *priv = ieee80211_priv(dev);
1866
1867 RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
1868 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1869 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1870 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n",priv->rfa_txpowertrackingindex);
1871 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain);
1872 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n",priv->CCKPresentAttentuation);
1873 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1874
1875 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1876 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1877 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",priv->rfc_txpowertrackingindex);
1878 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain);
1879
1880 } // dm_TXPowerResetRecovery
1881
1882 extern void dm_restore_dynamic_mechanism_state(struct net_device *dev)
1883 {
1884 struct r8192_priv *priv = ieee80211_priv(dev);
1885 u32 reg_ratr = priv->rate_adaptive.last_ratr;
1886
1887 if(!priv->up)
1888 {
1889 RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
1890 return;
1891 }
1892
1893 //
1894 // Restore previous state for rate adaptive
1895 //
1896 if(priv->rate_adaptive.rate_adaptive_disabled)
1897 return;
1898 // TODO: Only 11n mode is implemented currently,
1899 if( !(priv->ieee80211->mode==WIRELESS_MODE_N_24G ||
1900 priv->ieee80211->mode==WIRELESS_MODE_N_5G))
1901 return;
1902 {
1903 /* 2007/11/15 MH Copy from 8190PCI. */
1904 u32 ratr_value;
1905 ratr_value = reg_ratr;
1906 if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled
1907 {
1908 ratr_value &=~ (RATE_ALL_OFDM_2SS);
1909 //DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value);
1910 }
1911 //DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value);
1912 //cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]);
1913 write_nic_dword(dev, RATR0, ratr_value);
1914 write_nic_byte(dev, UFWP, 1);
1915 #if 0 // Disable old code.
1916 u1Byte index;
1917 u4Byte input_value;
1918 index = (u1Byte)((((pu4Byte)(val))[0]) >> 28);
1919 input_value = (((pu4Byte)(val))[0]) & 0x0fffffff;
1920 // TODO: Correct it. Emily 2007.01.11
1921 PlatformEFIOWrite4Byte(Adapter, RATR0+index*4, input_value);
1922 #endif
1923 }
1924 //Resore TX Power Tracking Index
1925 if(priv->btxpower_trackingInit && priv->btxpower_tracking){
1926 dm_txpower_reset_recovery(dev);
1927 }
1928
1929 //
1930 //Restore BB Initial Gain
1931 //
1932 dm_bb_initialgain_restore(dev);
1933
1934 } // DM_RestoreDynamicMechanismState
1935
1936 static void dm_bb_initialgain_restore(struct net_device *dev)
1937 {
1938 struct r8192_priv *priv = ieee80211_priv(dev);
1939 u32 bit_mask = 0x7f; //Bit0~ Bit6
1940
1941 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1942 return;
1943
1944 //Disable Initial Gain
1945 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1946 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1947 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);
1948 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1949 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1);
1950 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
1951 bit_mask = bMaskByte2;
1952 rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca);
1953
1954 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1955 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1956 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1957 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1958 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
1959 //Enable Initial Gain
1960 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);
1961 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1962
1963 } // dm_BBInitialGainRestore
1964
1965
1966 extern void dm_backup_dynamic_mechanism_state(struct net_device *dev)
1967 {
1968 struct r8192_priv *priv = ieee80211_priv(dev);
1969
1970 // Fsync to avoid reset
1971 priv->bswitch_fsync = false;
1972 priv->bfsync_processing = false;
1973 //Backup BB InitialGain
1974 dm_bb_initialgain_backup(dev);
1975
1976 } // DM_BackupDynamicMechanismState
1977
1978
1979 static void dm_bb_initialgain_backup(struct net_device *dev)
1980 {
1981 struct r8192_priv *priv = ieee80211_priv(dev);
1982 u32 bit_mask = bMaskByte0; //Bit0~ Bit6
1983
1984 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1985 return;
1986
1987 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1988 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1989 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);
1990 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
1991 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask);
1992 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
1993 bit_mask = bMaskByte2;
1994 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask);
1995
1996 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1997 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1998 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1999 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
2000 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
2001
2002 } // dm_BBInitialGainBakcup
2003
2004 #endif
2005 /*-----------------------------------------------------------------------------
2006 * Function: dm_change_dynamic_initgain_thresh()
2007 *
2008 * Overview:
2009 *
2010 * Input: NONE
2011 *
2012 * Output: NONE
2013 *
2014 * Return: NONE
2015 *
2016 * Revised History:
2017 * When Who Remark
2018 * 05/29/2008 amy Create Version 0 porting from windows code.
2019 *
2020 *---------------------------------------------------------------------------*/
2021 extern void dm_change_dynamic_initgain_thresh(struct net_device *dev,
2022 u32 dm_type,
2023 u32 dm_value)
2024 {
2025 if (dm_type == DIG_TYPE_THRESH_HIGH)
2026 {
2027 dm_digtable.rssi_high_thresh = dm_value;
2028 }
2029 else if (dm_type == DIG_TYPE_THRESH_LOW)
2030 {
2031 dm_digtable.rssi_low_thresh = dm_value;
2032 }
2033 else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
2034 {
2035 dm_digtable.rssi_high_power_highthresh = dm_value;
2036 }
2037 else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
2038 {
2039 dm_digtable.rssi_high_power_highthresh = dm_value;
2040 }
2041 else if (dm_type == DIG_TYPE_ENABLE)
2042 {
2043 dm_digtable.dig_state = DM_STA_DIG_MAX;
2044 dm_digtable.dig_enable_flag = true;
2045 }
2046 else if (dm_type == DIG_TYPE_DISABLE)
2047 {
2048 dm_digtable.dig_state = DM_STA_DIG_MAX;
2049 dm_digtable.dig_enable_flag = false;
2050 }
2051 else if (dm_type == DIG_TYPE_DBG_MODE)
2052 {
2053 if(dm_value >= DM_DBG_MAX)
2054 dm_value = DM_DBG_OFF;
2055 dm_digtable.dbg_mode = (u8)dm_value;
2056 }
2057 else if (dm_type == DIG_TYPE_RSSI)
2058 {
2059 if(dm_value > 100)
2060 dm_value = 30;
2061 dm_digtable.rssi_val = (long)dm_value;
2062 }
2063 else if (dm_type == DIG_TYPE_ALGORITHM)
2064 {
2065 if (dm_value >= DIG_ALGO_MAX)
2066 dm_value = DIG_ALGO_BY_FALSE_ALARM;
2067 if(dm_digtable.dig_algorithm != (u8)dm_value)
2068 dm_digtable.dig_algorithm_switch = 1;
2069 dm_digtable.dig_algorithm = (u8)dm_value;
2070 }
2071 else if (dm_type == DIG_TYPE_BACKOFF)
2072 {
2073 if(dm_value > 30)
2074 dm_value = 30;
2075 dm_digtable.backoff_val = (u8)dm_value;
2076 }
2077 else if(dm_type == DIG_TYPE_RX_GAIN_MIN)
2078 {
2079 if(dm_value == 0)
2080 dm_value = 0x1;
2081 dm_digtable.rx_gain_range_min = (u8)dm_value;
2082 }
2083 else if(dm_type == DIG_TYPE_RX_GAIN_MAX)
2084 {
2085 if(dm_value > 0x50)
2086 dm_value = 0x50;
2087 dm_digtable.rx_gain_range_max = (u8)dm_value;
2088 }
2089 } /* DM_ChangeDynamicInitGainThresh */
2090 extern void
2091 dm_change_fsync_setting(
2092 struct net_device *dev,
2093 s32 DM_Type,
2094 s32 DM_Value)
2095 {
2096 struct r8192_priv *priv = ieee80211_priv(dev);
2097
2098 if (DM_Type == 0) // monitor 0xc38 register
2099 {
2100 if(DM_Value > 1)
2101 DM_Value = 1;
2102 priv->framesyncMonitor = (u8)DM_Value;
2103 //DbgPrint("pHalData->framesyncMonitor = %d", pHalData->framesyncMonitor);
2104 }
2105 }
2106
2107 extern void
2108 dm_change_rxpath_selection_setting(
2109 struct net_device *dev,
2110 s32 DM_Type,
2111 s32 DM_Value)
2112 {
2113 struct r8192_priv *priv = ieee80211_priv(dev);
2114 prate_adaptive pRA = (prate_adaptive)&(priv->rate_adaptive);
2115
2116
2117 if(DM_Type == 0)
2118 {
2119 if(DM_Value > 1)
2120 DM_Value = 1;
2121 DM_RxPathSelTable.Enable = (u8)DM_Value;
2122 }
2123 else if(DM_Type == 1)
2124 {
2125 if(DM_Value > 1)
2126 DM_Value = 1;
2127 DM_RxPathSelTable.DbgMode = (u8)DM_Value;
2128 }
2129 else if(DM_Type == 2)
2130 {
2131 if(DM_Value > 40)
2132 DM_Value = 40;
2133 DM_RxPathSelTable.SS_TH_low = (u8)DM_Value;
2134 }
2135 else if(DM_Type == 3)
2136 {
2137 if(DM_Value > 25)
2138 DM_Value = 25;
2139 DM_RxPathSelTable.diff_TH = (u8)DM_Value;
2140 }
2141 else if(DM_Type == 4)
2142 {
2143 if(DM_Value >= CCK_Rx_Version_MAX)
2144 DM_Value = CCK_Rx_Version_1;
2145 DM_RxPathSelTable.cck_method= (u8)DM_Value;
2146 }
2147 else if(DM_Type == 10)
2148 {
2149 if(DM_Value > 100)
2150 DM_Value = 50;
2151 DM_RxPathSelTable.rf_rssi[0] = (u8)DM_Value;
2152 }
2153 else if(DM_Type == 11)
2154 {
2155 if(DM_Value > 100)
2156 DM_Value = 50;
2157 DM_RxPathSelTable.rf_rssi[1] = (u8)DM_Value;
2158 }
2159 else if(DM_Type == 12)
2160 {
2161 if(DM_Value > 100)
2162 DM_Value = 50;
2163 DM_RxPathSelTable.rf_rssi[2] = (u8)DM_Value;
2164 }
2165 else if(DM_Type == 13)
2166 {
2167 if(DM_Value > 100)
2168 DM_Value = 50;
2169 DM_RxPathSelTable.rf_rssi[3] = (u8)DM_Value;
2170 }
2171 else if(DM_Type == 20)
2172 {
2173 if(DM_Value > 1)
2174 DM_Value = 1;
2175 pRA->ping_rssi_enable = (u8)DM_Value;
2176 }
2177 else if(DM_Type == 21)
2178 {
2179 if(DM_Value > 30)
2180 DM_Value = 30;
2181 pRA->ping_rssi_thresh_for_ra = DM_Value;
2182 }
2183 }
2184
2185 #if 0
2186 extern void dm_force_tx_fw_info(struct net_device *dev,
2187 u32 force_type,
2188 u32 force_value)
2189 {
2190 struct r8192_priv *priv = ieee80211_priv(dev);
2191
2192 if (force_type == 0) // don't force TxSC
2193 {
2194 //DbgPrint("Set Force SubCarrier Off\n");
2195 priv->tx_fwinfo_force_subcarriermode = 0;
2196 }
2197 else if(force_type == 1) //force
2198 {
2199 //DbgPrint("Set Force SubCarrier On\n");
2200 priv->tx_fwinfo_force_subcarriermode = 1;
2201 if(force_value > 3)
2202 force_value = 3;
2203 priv->tx_fwinfo_force_subcarrierval = (u8)force_value;
2204 }
2205 }
2206 #endif
2207
2208 /*-----------------------------------------------------------------------------
2209 * Function: dm_dig_init()
2210 *
2211 * Overview: Set DIG scheme init value.
2212 *
2213 * Input: NONE
2214 *
2215 * Output: NONE
2216 *
2217 * Return: NONE
2218 *
2219 * Revised History:
2220 * When Who Remark
2221 * 05/15/2008 amy Create Version 0 porting from windows code.
2222 *
2223 *---------------------------------------------------------------------------*/
2224 static void dm_dig_init(struct net_device *dev)
2225 {
2226 struct r8192_priv *priv = ieee80211_priv(dev);
2227 /* 2007/10/05 MH Disable DIG scheme now. Not tested. */
2228 dm_digtable.dig_enable_flag = true;
2229 dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI;
2230 dm_digtable.dbg_mode = DM_DBG_OFF; //off=by real rssi value, on=by DM_DigTable.Rssi_val for new dig
2231 dm_digtable.dig_algorithm_switch = 0;
2232
2233 /* 2007/10/04 MH Define init gain threshol. */
2234 dm_digtable.dig_state = DM_STA_DIG_MAX;
2235 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
2236 dm_digtable.initialgain_lowerbound_state = false;
2237
2238 dm_digtable.rssi_low_thresh = DM_DIG_THRESH_LOW;
2239 dm_digtable.rssi_high_thresh = DM_DIG_THRESH_HIGH;
2240
2241 dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
2242 dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
2243
2244 dm_digtable.rssi_val = 50; //for new dig debug rssi value
2245 dm_digtable.backoff_val = DM_DIG_BACKOFF;
2246 dm_digtable.rx_gain_range_max = DM_DIG_MAX;
2247 if(priv->CustomerID == RT_CID_819x_Netcore)
2248 dm_digtable.rx_gain_range_min = DM_DIG_MIN_Netcore;
2249 else
2250 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
2251
2252 } /* dm_dig_init */
2253
2254
2255 /*-----------------------------------------------------------------------------
2256 * Function: dm_ctrl_initgain_byrssi()
2257 *
2258 * Overview: Driver must monitor RSSI and notify firmware to change initial
2259 * gain according to different threshold. BB team provide the
2260 * suggested solution.
2261 *
2262 * Input: struct net_device *dev
2263 *
2264 * Output: NONE
2265 *
2266 * Return: NONE
2267 *
2268 * Revised History:
2269 * When Who Remark
2270 * 05/27/2008 amy Create Version 0 porting from windows code.
2271 *---------------------------------------------------------------------------*/
2272 static void dm_ctrl_initgain_byrssi(struct net_device *dev)
2273 {
2274
2275 if (dm_digtable.dig_enable_flag == false)
2276 return;
2277
2278 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2279 dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev);
2280 else if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
2281 dm_ctrl_initgain_byrssi_by_driverrssi(dev);
2282 else
2283 return;
2284 }
2285
2286
2287 static void dm_ctrl_initgain_byrssi_by_driverrssi(
2288 struct net_device *dev)
2289 {
2290 struct r8192_priv *priv = ieee80211_priv(dev);
2291 u8 i;
2292 static u8 fw_dig=0;
2293
2294 if (dm_digtable.dig_enable_flag == false)
2295 return;
2296
2297 //DbgPrint("Dig by Sw Rssi \n");
2298 if(dm_digtable.dig_algorithm_switch) // if swithed algorithm, we have to disable FW Dig.
2299 fw_dig = 0;
2300 if(fw_dig <= 3) // execute several times to make sure the FW Dig is disabled
2301 {// FW DIG Off
2302 for(i=0; i<3; i++)
2303 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2304 fw_dig++;
2305 dm_digtable.dig_state = DM_STA_DIG_OFF; //fw dig off.
2306 }
2307
2308 if(priv->ieee80211->state == IEEE80211_LINKED)
2309 dm_digtable.cur_connect_state = DIG_CONNECT;
2310 else
2311 dm_digtable.cur_connect_state = DIG_DISCONNECT;
2312
2313 //DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d \n",
2314 //DM_DigTable.PreConnectState, DM_DigTable.CurConnectState);
2315
2316 if(dm_digtable.dbg_mode == DM_DBG_OFF)
2317 dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb;
2318 //DbgPrint("DM_DigTable.Rssi_val = %d \n", DM_DigTable.Rssi_val);
2319 dm_initial_gain(dev);
2320 dm_pd_th(dev);
2321 dm_cs_ratio(dev);
2322 if(dm_digtable.dig_algorithm_switch)
2323 dm_digtable.dig_algorithm_switch = 0;
2324 dm_digtable.pre_connect_state = dm_digtable.cur_connect_state;
2325
2326 } /* dm_CtrlInitGainByRssi */
2327
2328 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
2329 struct net_device *dev)
2330 {
2331 struct r8192_priv *priv = ieee80211_priv(dev);
2332 static u32 reset_cnt = 0;
2333 u8 i;
2334
2335 if (dm_digtable.dig_enable_flag == false)
2336 return;
2337
2338 if(dm_digtable.dig_algorithm_switch)
2339 {
2340 dm_digtable.dig_state = DM_STA_DIG_MAX;
2341 // Fw DIG On.
2342 for(i=0; i<3; i++)
2343 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2344 dm_digtable.dig_algorithm_switch = 0;
2345 }
2346
2347 if (priv->ieee80211->state != IEEE80211_LINKED)
2348 return;
2349
2350 // For smooth, we can not change DIG state.
2351 if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) &&
2352 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh))
2353 {
2354 return;
2355 }
2356 //DbgPrint("Dig by Fw False Alarm\n");
2357 //if (DM_DigTable.Dig_State == DM_STA_DIG_OFF)
2358 /*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d",
2359 pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh,
2360 DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/
2361 /* 1. When RSSI decrease, We have to judge if it is smaller than a treshold
2362 and then execute below step. */
2363 if ((priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh))
2364 {
2365 /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters
2366 will be reset to init value. We must prevent the condition. */
2367 if (dm_digtable.dig_state == DM_STA_DIG_OFF &&
2368 (priv->reset_count == reset_cnt))
2369 {
2370 return;
2371 }
2372 else
2373 {
2374 reset_cnt = priv->reset_count;
2375 }
2376
2377 // If DIG is off, DIG high power state must reset.
2378 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
2379 dm_digtable.dig_state = DM_STA_DIG_OFF;
2380
2381 // 1.1 DIG Off.
2382 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2383
2384 // 1.2 Set initial gain.
2385 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17);
2386 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
2387 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17);
2388 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);
2389
2390 // 1.3 Lower PD_TH for OFDM.
2391 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2392 {
2393 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2394 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2395 #ifdef RTL8190P
2396 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2397 #else
2398 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
2399 #endif
2400 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2401 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
2402 */
2403 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
2404
2405
2406 //else
2407 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
2408 }
2409 else
2410 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2411
2412 // 1.4 Lower CS ratio for CCK.
2413 write_nic_byte(dev, 0xa0a, 0x08);
2414
2415 // 1.5 Higher EDCCA.
2416 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);
2417 return;
2418
2419 }
2420
2421 /* 2. When RSSI increase, We have to judge if it is larger than a treshold
2422 and then execute below step. */
2423 if ((priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) )
2424 {
2425 u8 reset_flag = 0;
2426
2427 if (dm_digtable.dig_state == DM_STA_DIG_ON &&
2428 (priv->reset_count == reset_cnt))
2429 {
2430 dm_ctrl_initgain_byrssi_highpwr(dev);
2431 return;
2432 }
2433 else
2434 {
2435 if (priv->reset_count != reset_cnt)
2436 reset_flag = 1;
2437
2438 reset_cnt = priv->reset_count;
2439 }
2440
2441 dm_digtable.dig_state = DM_STA_DIG_ON;
2442 //DbgPrint("DIG ON\n\r");
2443
2444 // 2.1 Set initial gain.
2445 // 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
2446 if (reset_flag == 1)
2447 {
2448 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c);
2449 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
2450 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c);
2451 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);
2452 }
2453 else
2454 {
2455 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20);
2456 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
2457 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20);
2458 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);
2459 }
2460
2461 // 2.2 Higher PD_TH for OFDM.
2462 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2463 {
2464 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2465 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2466 #ifdef RTL8190P
2467 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2468 #else
2469 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2470 #endif
2471 /*
2472 else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2473 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2474 */
2475 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
2476
2477 //else
2478 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
2479 }
2480 else
2481 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2482
2483 // 2.3 Higher CS ratio for CCK.
2484 write_nic_byte(dev, 0xa0a, 0xcd);
2485
2486 // 2.4 Lower EDCCA.
2487 /* 2008/01/11 MH 90/92 series are the same. */
2488 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);
2489
2490 // 2.5 DIG On.
2491 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2492
2493 }
2494
2495 dm_ctrl_initgain_byrssi_highpwr(dev);
2496
2497 } /* dm_CtrlInitGainByRssi */
2498
2499
2500 /*-----------------------------------------------------------------------------
2501 * Function: dm_ctrl_initgain_byrssi_highpwr()
2502 *
2503 * Overview:
2504 *
2505 * Input: NONE
2506 *
2507 * Output: NONE
2508 *
2509 * Return: NONE
2510 *
2511 * Revised History:
2512 * When Who Remark
2513 * 05/28/2008 amy Create Version 0 porting from windows code.
2514 *
2515 *---------------------------------------------------------------------------*/
2516 static void dm_ctrl_initgain_byrssi_highpwr(
2517 struct net_device * dev)
2518 {
2519 struct r8192_priv *priv = ieee80211_priv(dev);
2520 static u32 reset_cnt_highpwr = 0;
2521
2522 // For smooth, we can not change high power DIG state in the range.
2523 if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) &&
2524 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh))
2525 {
2526 return;
2527 }
2528
2529 /* 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if
2530 it is larger than a treshold and then execute below step. */
2531 // 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue.
2532 if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh)
2533 {
2534 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON &&
2535 (priv->reset_count == reset_cnt_highpwr))
2536 return;
2537 else
2538 dm_digtable.dig_highpwr_state = DM_STA_DIG_ON;
2539
2540 // 3.1 Higher PD_TH for OFDM for high power state.
2541 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2542 {
2543 #ifdef RTL8190P
2544 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2545 #else
2546 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2547 #endif
2548
2549 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2550 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2551 */
2552
2553 }
2554 else
2555 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2556 }
2557 else
2558 {
2559 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF&&
2560 (priv->reset_count == reset_cnt_highpwr))
2561 return;
2562 else
2563 dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF;
2564
2565 if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh &&
2566 priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh)
2567 {
2568 // 3.2 Recover PD_TH for OFDM for normal power region.
2569 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2570 {
2571 #ifdef RTL8190P
2572 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2573 #else
2574 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2575 #endif
2576 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2577 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2578 */
2579
2580 }
2581 else
2582 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2583 }
2584 }
2585
2586 reset_cnt_highpwr = priv->reset_count;
2587
2588 } /* dm_CtrlInitGainByRssiHighPwr */
2589
2590
2591 static void dm_initial_gain(
2592 struct net_device * dev)
2593 {
2594 struct r8192_priv *priv = ieee80211_priv(dev);
2595 u8 initial_gain=0;
2596 static u8 initialized=0, force_write=0;
2597 static u32 reset_cnt=0;
2598
2599 if(dm_digtable.dig_algorithm_switch)
2600 {
2601 initialized = 0;
2602 reset_cnt = 0;
2603 }
2604
2605 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2606 {
2607 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2608 {
2609 if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) > dm_digtable.rx_gain_range_max)
2610 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_max;
2611 else if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
2612 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min;
2613 else
2614 dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val;
2615 }
2616 else //current state is disconnected
2617 {
2618 if(dm_digtable.cur_ig_value == 0)
2619 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
2620 else
2621 dm_digtable.cur_ig_value = dm_digtable.pre_ig_value;
2622 }
2623 }
2624 else // disconnected -> connected or connected -> disconnected
2625 {
2626 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
2627 dm_digtable.pre_ig_value = 0;
2628 }
2629 //DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue);
2630
2631 // if silent reset happened, we should rewrite the values back
2632 if(priv->reset_count != reset_cnt)
2633 {
2634 force_write = 1;
2635 reset_cnt = priv->reset_count;
2636 }
2637
2638 if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1))
2639 force_write = 1;
2640
2641 {
2642 if((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value)
2643 || !initialized || force_write)
2644 {
2645 initial_gain = (u8)dm_digtable.cur_ig_value;
2646 //DbgPrint("Write initial gain = 0x%x\n", initial_gain);
2647 // Set initial gain.
2648 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
2649 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
2650 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
2651 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
2652 dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;
2653 initialized = 1;
2654 force_write = 0;
2655 }
2656 }
2657 }
2658
2659 static void dm_pd_th(
2660 struct net_device * dev)
2661 {
2662 struct r8192_priv *priv = ieee80211_priv(dev);
2663 static u8 initialized=0, force_write=0;
2664 static u32 reset_cnt = 0;
2665
2666 if(dm_digtable.dig_algorithm_switch)
2667 {
2668 initialized = 0;
2669 reset_cnt = 0;
2670 }
2671
2672 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2673 {
2674 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2675 {
2676 if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh)
2677 dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER;
2678 else if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh))
2679 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2680 else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) &&
2681 (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh))
2682 dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER;
2683 else
2684 dm_digtable.curpd_thstate = dm_digtable.prepd_thstate;
2685 }
2686 else
2687 {
2688 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2689 }
2690 }
2691 else // disconnected -> connected or connected -> disconnected
2692 {
2693 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2694 }
2695
2696 // if silent reset happened, we should rewrite the values back
2697 if(priv->reset_count != reset_cnt)
2698 {
2699 force_write = 1;
2700 reset_cnt = priv->reset_count;
2701 }
2702
2703 {
2704 if((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) ||
2705 (initialized<=3) || force_write)
2706 {
2707 //DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState);
2708 if(dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER)
2709 {
2710 // Lower PD_TH for OFDM.
2711 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2712 {
2713 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2714 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2715 #ifdef RTL8190P
2716 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2717 #else
2718 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
2719 #endif
2720 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2721 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2722 */
2723 }
2724 else
2725 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2726 }
2727 else if(dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER)
2728 {
2729 // Higher PD_TH for OFDM.
2730 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2731 {
2732 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2733 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2734 #ifdef RTL8190P
2735 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2736 #else
2737 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2738 #endif
2739 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2740 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2741 */
2742 }
2743 else
2744 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2745 }
2746 else if(dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER)
2747 {
2748 // Higher PD_TH for OFDM for high power state.
2749 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2750 {
2751 #ifdef RTL8190P
2752 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2753 #else
2754 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2755 #endif
2756 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2757 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2758 */
2759 }
2760 else
2761 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2762 }
2763 dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;
2764 if(initialized <= 3)
2765 initialized++;
2766 force_write = 0;
2767 }
2768 }
2769 }
2770
2771 static void dm_cs_ratio(
2772 struct net_device * dev)
2773 {
2774 struct r8192_priv *priv = ieee80211_priv(dev);
2775 static u8 initialized=0,force_write=0;
2776 static u32 reset_cnt = 0;
2777
2778 if(dm_digtable.dig_algorithm_switch)
2779 {
2780 initialized = 0;
2781 reset_cnt = 0;
2782 }
2783
2784 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2785 {
2786 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2787 {
2788 if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh))
2789 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2790 else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) )
2791 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER;
2792 else
2793 dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state;
2794 }
2795 else
2796 {
2797 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2798 }
2799 }
2800 else // disconnected -> connected or connected -> disconnected
2801 {
2802 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2803 }
2804
2805 // if silent reset happened, we should rewrite the values back
2806 if(priv->reset_count != reset_cnt)
2807 {
2808 force_write = 1;
2809 reset_cnt = priv->reset_count;
2810 }
2811
2812
2813 {
2814 if((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) ||
2815 !initialized || force_write)
2816 {
2817 //DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState);
2818 if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER)
2819 {
2820 // Lower CS ratio for CCK.
2821 write_nic_byte(dev, 0xa0a, 0x08);
2822 }
2823 else if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER)
2824 {
2825 // Higher CS ratio for CCK.
2826 write_nic_byte(dev, 0xa0a, 0xcd);
2827 }
2828 dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;
2829 initialized = 1;
2830 force_write = 0;
2831 }
2832 }
2833 }
2834
2835 extern void dm_init_edca_turbo(struct net_device * dev)
2836 {
2837 struct r8192_priv *priv = ieee80211_priv(dev);
2838
2839 priv->bcurrent_turbo_EDCA = false;
2840 priv->ieee80211->bis_any_nonbepkts = false;
2841 priv->bis_cur_rdlstate = false;
2842 } // dm_init_edca_turbo
2843
2844 #if 1
2845 static void dm_check_edca_turbo(
2846 struct net_device * dev)
2847 {
2848 struct r8192_priv *priv = ieee80211_priv(dev);
2849 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
2850 //PSTA_QOS pStaQos = pMgntInfo->pStaQos;
2851
2852 // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.
2853 static unsigned long lastTxOkCnt = 0;
2854 static unsigned long lastRxOkCnt = 0;
2855 unsigned long curTxOkCnt = 0;
2856 unsigned long curRxOkCnt = 0;
2857
2858 //
2859 // Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters
2860 // should follow the settings from QAP. By Bruce, 2007-12-07.
2861 //
2862 #if 1
2863 if(priv->ieee80211->state != IEEE80211_LINKED)
2864 goto dm_CheckEdcaTurbo_EXIT;
2865 #endif
2866 // We do not turn on EDCA turbo mode for some AP that has IOT issue
2867 if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO)
2868 goto dm_CheckEdcaTurbo_EXIT;
2869
2870 // printk("========>%s():bis_any_nonbepkts is %d\n",__FUNCTION__,priv->bis_any_nonbepkts);
2871 // Check the status for current condition.
2872 if(!priv->ieee80211->bis_any_nonbepkts)
2873 {
2874 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2875 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2876 // For RT-AP, we needs to turn it on when Rx>Tx
2877 if(curRxOkCnt > 4*curTxOkCnt)
2878 {
2879 //printk("%s():curRxOkCnt > 4*curTxOkCnt\n");
2880 if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
2881 {
2882 write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
2883 priv->bis_cur_rdlstate = true;
2884 }
2885 }
2886 else
2887 {
2888
2889 //printk("%s():curRxOkCnt < 4*curTxOkCnt\n");
2890 if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
2891 {
2892 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
2893 priv->bis_cur_rdlstate = false;
2894 }
2895
2896 }
2897
2898 priv->bcurrent_turbo_EDCA = true;
2899 }
2900 else
2901 {
2902 //
2903 // Turn Off EDCA turbo here.
2904 // Restore original EDCA according to the declaration of AP.
2905 //
2906 if(priv->bcurrent_turbo_EDCA)
2907 {
2908
2909 {
2910 u8 u1bAIFS;
2911 u32 u4bAcParam;
2912 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
2913 u8 mode = priv->ieee80211->mode;
2914
2915 // For Each time updating EDCA parameter, reset EDCA turbo mode status.
2916 dm_init_edca_turbo(dev);
2917 u1bAIFS = qos_parameters->aifs[0] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime;
2918 u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[0]))<< AC_PARAM_TXOP_LIMIT_OFFSET)|
2919 (((u32)(qos_parameters->cw_max[0]))<< AC_PARAM_ECW_MAX_OFFSET)|
2920 (((u32)(qos_parameters->cw_min[0]))<< AC_PARAM_ECW_MIN_OFFSET)|
2921 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
2922 printk("===>u4bAcParam:%x, ", u4bAcParam);
2923 //write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
2924 write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
2925
2926 // Check ACM bit.
2927 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2928 {
2929 // TODO: Modified this part and try to set acm control in only 1 IO processing!!
2930
2931 PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]);
2932 u8 AcmCtrl = read_nic_byte( dev, AcmHwCtrl );
2933 if( pAciAifsn->f.ACM )
2934 { // ACM bit is 1.
2935 AcmCtrl |= AcmHw_BeqEn;
2936 }
2937 else
2938 { // ACM bit is 0.
2939 AcmCtrl &= (~AcmHw_BeqEn);
2940 }
2941
2942 RT_TRACE( COMP_QOS,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl ) ;
2943 write_nic_byte(dev, AcmHwCtrl, AcmCtrl );
2944 }
2945 }
2946 priv->bcurrent_turbo_EDCA = false;
2947 }
2948 }
2949
2950
2951 dm_CheckEdcaTurbo_EXIT:
2952 // Set variables for next time.
2953 priv->ieee80211->bis_any_nonbepkts = false;
2954 lastTxOkCnt = priv->stats.txbytesunicast;
2955 lastRxOkCnt = priv->stats.rxbytesunicast;
2956 } // dm_CheckEdcaTurbo
2957 #endif
2958
2959 extern void DM_CTSToSelfSetting(struct net_device * dev,u32 DM_Type, u32 DM_Value)
2960 {
2961 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2962
2963 if (DM_Type == 0) // CTS to self disable/enable
2964 {
2965 if(DM_Value > 1)
2966 DM_Value = 1;
2967 priv->ieee80211->bCTSToSelfEnable = (bool)DM_Value;
2968 //DbgPrint("pMgntInfo->bCTSToSelfEnable = %d\n", pMgntInfo->bCTSToSelfEnable);
2969 }
2970 else if(DM_Type == 1) //CTS to self Th
2971 {
2972 if(DM_Value >= 50)
2973 DM_Value = 50;
2974 priv->ieee80211->CTSToSelfTH = (u8)DM_Value;
2975 //DbgPrint("pMgntInfo->CTSToSelfTH = %d\n", pMgntInfo->CTSToSelfTH);
2976 }
2977 }
2978
2979 static void dm_init_ctstoself(struct net_device * dev)
2980 {
2981 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2982
2983 priv->ieee80211->bCTSToSelfEnable = TRUE;
2984 priv->ieee80211->CTSToSelfTH = CTSToSelfTHVal;
2985 }
2986
2987 static void dm_ctstoself(struct net_device *dev)
2988 {
2989 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2990 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
2991 static unsigned long lastTxOkCnt = 0;
2992 static unsigned long lastRxOkCnt = 0;
2993 unsigned long curTxOkCnt = 0;
2994 unsigned long curRxOkCnt = 0;
2995
2996 if(priv->ieee80211->bCTSToSelfEnable != TRUE)
2997 {
2998 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2999 return;
3000 }
3001 /*
3002 1. Uplink
3003 2. Linksys350/Linksys300N
3004 3. <50 disable, >55 enable
3005 */
3006
3007 if(pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM)
3008 {
3009 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
3010 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
3011 if(curRxOkCnt > 4*curTxOkCnt) //downlink, disable CTS to self
3012 {
3013 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
3014 //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n");
3015 }
3016 else //uplink
3017 {
3018 #if 1
3019 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
3020 #else
3021 if(priv->undecorated_smoothed_pwdb < priv->ieee80211->CTSToSelfTH) // disable CTS to self
3022 {
3023 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
3024 //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled\n");
3025 }
3026 else if(priv->undecorated_smoothed_pwdb >= (priv->ieee80211->CTSToSelfTH+5)) // enable CTS to self
3027 {
3028 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
3029 //DbgPrint("dm_CTSToSelf() ==> CTS to self enabled\n");
3030 }
3031 #endif
3032 }
3033
3034 lastTxOkCnt = priv->stats.txbytesunicast;
3035 lastRxOkCnt = priv->stats.rxbytesunicast;
3036 }
3037 }
3038
3039
3040 #if 0
3041 /*-----------------------------------------------------------------------------
3042 * Function: dm_rf_operation_test_callback()
3043 *
3044 * Overview: Only for RF operation test now.
3045 *
3046 * Input: NONE
3047 *
3048 * Output: NONE
3049 *
3050 * Return: NONE
3051 *
3052 * Revised History:
3053 * When Who Remark
3054 * 05/29/2008 amy Create Version 0 porting from windows code.
3055 *
3056 *---------------------------------------------------------------------------*/
3057 extern void dm_rf_operation_test_callback(unsigned long dev)
3058 {
3059 // struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
3060 u8 erfpath;
3061
3062
3063 for(erfpath=0; erfpath<4; erfpath++)
3064 {
3065 //DbgPrint("Set RF-%d\n\r", eRFPath);
3066 //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);
3067 udelay(100);
3068 }
3069
3070 {
3071 //PlatformSetPeriodicTimer(Adapter, &pHalData->RfTest1Timer, 500);
3072 }
3073
3074 // For test
3075 {
3076 //u8 i;
3077 //PlatformSetPeriodicTimer(Adapter, &pHalData->RfTest1Timer, 500);
3078 #if 0
3079 for(i=0; i<50; i++)
3080 {
3081 // Write Test
3082 PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
3083 //delay_us(100);
3084 PHY_SetRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
3085 //delay_us(100);
3086 PHY_SetRFReg(Adapter, RF90_PATH_C, 0x02, bMask12Bits, 0x4d);
3087 //delay_us(100);
3088 PHY_SetRFReg(Adapter, RF90_PATH_C, 0x02, bMask12Bits, 0x4f);
3089 //delay_us(100);
3090
3091 #if 0
3092 // Read test
3093 PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits);
3094 //delay_us(100);
3095 PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x02, bMask12Bits);
3096 //delay_us(100);
3097 PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, bMask12Bits);
3098 //delay_us(100);
3099 PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x12, bMask12Bits);
3100 //delay_us(100);
3101 PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x21, bMask12Bits);
3102 //delay_us(100);
3103 PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x21, bMask12Bits);
3104 //delay_us(100);
3105 #endif
3106 }
3107 #endif
3108 }
3109
3110 } /* DM_RfOperationTestCallBack */
3111 #endif
3112
3113 /*-----------------------------------------------------------------------------
3114 * Function: dm_check_rfctrl_gpio()
3115 *
3116 * Overview: Copy 8187B template for 9xseries.
3117 *
3118 * Input: NONE
3119 *
3120 * Output: NONE
3121 *
3122 * Return: NONE
3123 *
3124 * Revised History:
3125 * When Who Remark
3126 * 05/28/2008 amy Create Version 0 porting from windows code.
3127 *
3128 *---------------------------------------------------------------------------*/
3129 #if 1
3130 static void dm_check_rfctrl_gpio(struct net_device * dev)
3131 {
3132 #ifdef RTL8192E
3133 struct r8192_priv *priv = ieee80211_priv(dev);
3134 #endif
3135
3136 // Walk around for DTM test, we will not enable HW - radio on/off because r/w
3137 // page 1 register before Lextra bus is enabled cause system fails when resuming
3138 // from S4. 20080218, Emily
3139
3140 // Stop to execute workitem to prevent S3/S4 bug.
3141 #ifdef RTL8190P
3142 return;
3143 #endif
3144 #ifdef RTL8192U
3145 return;
3146 #endif
3147 #ifdef RTL8192E
3148 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
3149 queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0);
3150 #else
3151 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3152 schedule_task(&priv->gpio_change_rf_wq);
3153 #else
3154 queue_work(priv->priv_wq,&priv->gpio_change_rf_wq);
3155 #endif
3156 #endif
3157 #endif
3158
3159 } /* dm_CheckRfCtrlGPIO */
3160
3161 #endif
3162 /*-----------------------------------------------------------------------------
3163 * Function: dm_check_pbc_gpio()
3164 *
3165 * Overview: Check if PBC button is pressed.
3166 *
3167 * Input: NONE
3168 *
3169 * Output: NONE
3170 *
3171 * Return: NONE
3172 *
3173 * Revised History:
3174 * When Who Remark
3175 * 05/28/2008 amy Create Version 0 porting from windows code.
3176 *
3177 *---------------------------------------------------------------------------*/
3178 static void dm_check_pbc_gpio(struct net_device *dev)
3179 {
3180 #ifdef RTL8192U
3181 struct r8192_priv *priv = ieee80211_priv(dev);
3182 u8 tmp1byte;
3183
3184
3185 tmp1byte = read_nic_byte(dev,GPI);
3186 if(tmp1byte == 0xff)
3187 return;
3188
3189 if (tmp1byte&BIT6 || tmp1byte&BIT0)
3190 {
3191 // Here we only set bPbcPressed to TRUE
3192 // After trigger PBC, the variable will be set to FALSE
3193 RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");
3194 priv->bpbc_pressed = true;
3195 }
3196 #endif
3197
3198 }
3199
3200 #ifdef RTL8192E
3201
3202 /*-----------------------------------------------------------------------------
3203 * Function: dm_GPIOChangeRF
3204 * Overview: PCI will not support workitem call back HW radio on-off control.
3205 *
3206 * Input: NONE
3207 *
3208 * Output: NONE
3209 *
3210 * Return: NONE
3211 *
3212 * Revised History:
3213 * When Who Remark
3214 * 02/21/2008 MHC Create Version 0.
3215 *
3216 *---------------------------------------------------------------------------*/
3217 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
3218 extern void dm_gpio_change_rf_callback(struct work_struct *work)
3219 {
3220 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
3221 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,gpio_change_rf_wq);
3222 struct net_device *dev = priv->ieee80211->dev;
3223 #else
3224 extern void dm_gpio_change_rf_callback(struct net_device *dev)
3225 {
3226 struct r8192_priv *priv = ieee80211_priv(dev);
3227 #endif
3228 u8 tmp1byte;
3229 RT_RF_POWER_STATE eRfPowerStateToSet;
3230 bool bActuallySet = false;
3231
3232 bActuallySet=false;
3233
3234 if(!priv->up)
3235 {
3236 RT_TRACE((COMP_INIT | COMP_POWER | COMP_RF),"dm_gpio_change_rf_callback(): Callback function breaks out!!\n");
3237 }
3238 else
3239 {
3240 // 0x108 GPIO input register is read only
3241 //set 0x108 B1= 1: RF-ON; 0: RF-OFF.
3242 tmp1byte = read_nic_byte(dev,GPI);
3243
3244 eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff;
3245
3246 if( (priv->bHwRadioOff == true) && (eRfPowerStateToSet == eRfOn))
3247 {
3248 RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio ON\n");
3249
3250 priv->bHwRadioOff = false;
3251 bActuallySet = true;
3252 }
3253 else if ( (priv->bHwRadioOff == false) && (eRfPowerStateToSet == eRfOff))
3254 {
3255 RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio OFF\n");
3256 priv->bHwRadioOff = true;
3257 bActuallySet = true;
3258 }
3259
3260 if(bActuallySet)
3261 {
3262 priv->bHwRfOffAction = 1;
3263 MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW);
3264 //DrvIFIndicateCurrentPhyStatus(pAdapter);
3265
3266 }
3267 else
3268 {
3269 msleep(2000);
3270 }
3271
3272 }
3273
3274 } /* dm_GPIOChangeRF */
3275
3276 #endif
3277 /*-----------------------------------------------------------------------------
3278 * Function: DM_RFPathCheckWorkItemCallBack()
3279 *
3280 * Overview: Check if Current RF RX path is enabled
3281 *
3282 * Input: NONE
3283 *
3284 * Output: NONE
3285 *
3286 * Return: NONE
3287 *
3288 * Revised History:
3289 * When Who Remark
3290 * 01/30/2008 MHC Create Version 0.
3291 *
3292 *---------------------------------------------------------------------------*/
3293 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
3294 extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
3295 {
3296 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
3297 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,rfpath_check_wq);
3298 struct net_device *dev =priv->ieee80211->dev;
3299 #else
3300 extern void dm_rf_pathcheck_workitemcallback(struct net_device *dev)
3301 {
3302 struct r8192_priv *priv = ieee80211_priv(dev);
3303 #endif
3304 //bool bactually_set = false;
3305 u8 rfpath = 0, i;
3306
3307
3308 /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
3309 always be the same. We only read 0xc04 now. */
3310 rfpath = read_nic_byte(dev, 0xc04);
3311
3312 // Check Bit 0-3, it means if RF A-D is enabled.
3313 for (i = 0; i < RF90_PATH_MAX; i++)
3314 {
3315 if (rfpath & (0x01<<i))
3316 priv->brfpath_rxenable[i] = 1;
3317 else
3318 priv->brfpath_rxenable[i] = 0;
3319 }
3320 if(!DM_RxPathSelTable.Enable)
3321 return;
3322
3323 dm_rxpath_sel_byrssi(dev);
3324 } /* DM_RFPathCheckWorkItemCallBack */
3325
3326 static void dm_init_rxpath_selection(struct net_device * dev)
3327 {
3328 u8 i;
3329 struct r8192_priv *priv = ieee80211_priv(dev);
3330 DM_RxPathSelTable.Enable = 1; //default enabled
3331 DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low;
3332 DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH;
3333 if(priv->CustomerID == RT_CID_819x_Netcore)
3334 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2;
3335 else
3336 DM_RxPathSelTable.cck_method = CCK_Rx_Version_1;
3337 DM_RxPathSelTable.DbgMode = DM_DBG_OFF;
3338 DM_RxPathSelTable.disabledRF = 0;
3339 for(i=0; i<4; i++)
3340 {
3341 DM_RxPathSelTable.rf_rssi[i] = 50;
3342 DM_RxPathSelTable.cck_pwdb_sta[i] = -64;
3343 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
3344 }
3345 }
3346
3347 static void dm_rxpath_sel_byrssi(struct net_device * dev)
3348 {
3349 struct r8192_priv *priv = ieee80211_priv(dev);
3350 u8 i, max_rssi_index=0, min_rssi_index=0, sec_rssi_index=0, rf_num=0;
3351 u8 tmp_max_rssi=0, tmp_min_rssi=0, tmp_sec_rssi=0;
3352 u8 cck_default_Rx=0x2; //RF-C
3353 u8 cck_optional_Rx=0x3;//RF-D
3354 long tmp_cck_max_pwdb=0, tmp_cck_min_pwdb=0, tmp_cck_sec_pwdb=0;
3355 u8 cck_rx_ver2_max_index=0, cck_rx_ver2_min_index=0, cck_rx_ver2_sec_index=0;
3356 u8 cur_rf_rssi;
3357 long cur_cck_pwdb;
3358 static u8 disabled_rf_cnt=0, cck_Rx_Path_initialized=0;
3359 u8 update_cck_rx_path;
3360
3361 if(priv->rf_type != RF_2T4R)
3362 return;
3363
3364 if(!cck_Rx_Path_initialized)
3365 {
3366 DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(dev, 0xa07)&0xf);
3367 cck_Rx_Path_initialized = 1;
3368 }
3369
3370 DM_RxPathSelTable.disabledRF = 0xf;
3371 DM_RxPathSelTable.disabledRF &=~ (read_nic_byte(dev, 0xc04));
3372
3373 if(priv->ieee80211->mode == WIRELESS_MODE_B)
3374 {
3375 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; //pure B mode, fixed cck version2
3376 //DbgPrint("Pure B mode, use cck rx version2 \n");
3377 }
3378
3379 //decide max/sec/min rssi index
3380 for (i=0; i<RF90_PATH_MAX; i++)
3381 {
3382 if(!DM_RxPathSelTable.DbgMode)
3383 DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i];
3384
3385 if(priv->brfpath_rxenable[i])
3386 {
3387 rf_num++;
3388 cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i];
3389
3390 if(rf_num == 1) // find first enabled rf path and the rssi values
3391 { //initialize, set all rssi index to the same one
3392 max_rssi_index = min_rssi_index = sec_rssi_index = i;
3393 tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi;
3394 }
3395 else if(rf_num == 2)
3396 { // we pick up the max index first, and let sec and min to be the same one
3397 if(cur_rf_rssi >= tmp_max_rssi)
3398 {
3399 tmp_max_rssi = cur_rf_rssi;
3400 max_rssi_index = i;
3401 }
3402 else
3403 {
3404 tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi;
3405 sec_rssi_index = min_rssi_index = i;
3406 }
3407 }
3408 else
3409 {
3410 if(cur_rf_rssi > tmp_max_rssi)
3411 {
3412 tmp_sec_rssi = tmp_max_rssi;
3413 sec_rssi_index = max_rssi_index;
3414 tmp_max_rssi = cur_rf_rssi;
3415 max_rssi_index = i;
3416 }
3417 else if(cur_rf_rssi == tmp_max_rssi)
3418 { // let sec and min point to the different index
3419 tmp_sec_rssi = cur_rf_rssi;
3420 sec_rssi_index = i;
3421 }
3422 else if((cur_rf_rssi < tmp_max_rssi) &&(cur_rf_rssi > tmp_sec_rssi))
3423 {
3424 tmp_sec_rssi = cur_rf_rssi;
3425 sec_rssi_index = i;
3426 }
3427 else if(cur_rf_rssi == tmp_sec_rssi)
3428 {
3429 if(tmp_sec_rssi == tmp_min_rssi)
3430 { // let sec and min point to the different index
3431 tmp_sec_rssi = cur_rf_rssi;
3432 sec_rssi_index = i;
3433 }
3434 else
3435 {
3436 // This case we don't need to set any index
3437 }
3438 }
3439 else if((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi))
3440 {
3441 // This case we don't need to set any index
3442 }
3443 else if(cur_rf_rssi == tmp_min_rssi)
3444 {
3445 if(tmp_sec_rssi == tmp_min_rssi)
3446 { // let sec and min point to the different index
3447 tmp_min_rssi = cur_rf_rssi;
3448 min_rssi_index = i;
3449 }
3450 else
3451 {
3452 // This case we don't need to set any index
3453 }
3454 }
3455 else if(cur_rf_rssi < tmp_min_rssi)
3456 {
3457 tmp_min_rssi = cur_rf_rssi;
3458 min_rssi_index = i;
3459 }
3460 }
3461 }
3462 }
3463
3464 rf_num = 0;
3465 // decide max/sec/min cck pwdb index
3466 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2)
3467 {
3468 for (i=0; i<RF90_PATH_MAX; i++)
3469 {
3470 if(priv->brfpath_rxenable[i])
3471 {
3472 rf_num++;
3473 cur_cck_pwdb = DM_RxPathSelTable.cck_pwdb_sta[i];
3474
3475 if(rf_num == 1) // find first enabled rf path and the rssi values
3476 { //initialize, set all rssi index to the same one
3477 cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i;
3478 tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb;
3479 }
3480 else if(rf_num == 2)
3481 { // we pick up the max index first, and let sec and min to be the same one
3482 if(cur_cck_pwdb >= tmp_cck_max_pwdb)
3483 {
3484 tmp_cck_max_pwdb = cur_cck_pwdb;
3485 cck_rx_ver2_max_index = i;
3486 }
3487 else
3488 {
3489 tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb;
3490 cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i;
3491 }
3492 }
3493 else
3494 {
3495 if(cur_cck_pwdb > tmp_cck_max_pwdb)
3496 {
3497 tmp_cck_sec_pwdb = tmp_cck_max_pwdb;
3498 cck_rx_ver2_sec_index = cck_rx_ver2_max_index;
3499 tmp_cck_max_pwdb = cur_cck_pwdb;
3500 cck_rx_ver2_max_index = i;
3501 }
3502 else if(cur_cck_pwdb == tmp_cck_max_pwdb)
3503 { // let sec and min point to the different index
3504 tmp_cck_sec_pwdb = cur_cck_pwdb;
3505 cck_rx_ver2_sec_index = i;
3506 }
3507 else if((cur_cck_pwdb < tmp_cck_max_pwdb) &&(cur_cck_pwdb > tmp_cck_sec_pwdb))
3508 {
3509 tmp_cck_sec_pwdb = cur_cck_pwdb;
3510 cck_rx_ver2_sec_index = i;
3511 }
3512 else if(cur_cck_pwdb == tmp_cck_sec_pwdb)
3513 {
3514 if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb)
3515 { // let sec and min point to the different index
3516 tmp_cck_sec_pwdb = cur_cck_pwdb;
3517 cck_rx_ver2_sec_index = i;
3518 }
3519 else
3520 {
3521 // This case we don't need to set any index
3522 }
3523 }
3524 else if((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb))
3525 {
3526 // This case we don't need to set any index
3527 }
3528 else if(cur_cck_pwdb == tmp_cck_min_pwdb)
3529 {
3530 if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb)
3531 { // let sec and min point to the different index
3532 tmp_cck_min_pwdb = cur_cck_pwdb;
3533 cck_rx_ver2_min_index = i;
3534 }
3535 else
3536 {
3537 // This case we don't need to set any index
3538 }
3539 }
3540 else if(cur_cck_pwdb < tmp_cck_min_pwdb)
3541 {
3542 tmp_cck_min_pwdb = cur_cck_pwdb;
3543 cck_rx_ver2_min_index = i;
3544 }
3545 }
3546
3547 }
3548 }
3549 }
3550
3551
3552 // Set CCK Rx path
3553 // reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path.
3554 update_cck_rx_path = 0;
3555 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2)
3556 {
3557 cck_default_Rx = cck_rx_ver2_max_index;
3558 cck_optional_Rx = cck_rx_ver2_sec_index;
3559 if(tmp_cck_max_pwdb != -64)
3560 update_cck_rx_path = 1;
3561 }
3562
3563 if(tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2)
3564 {
3565 if((tmp_max_rssi - tmp_min_rssi) >= DM_RxPathSelTable.diff_TH)
3566 {
3567 //record the enabled rssi threshold
3568 DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5;
3569 //disable the BB Rx path, OFDM
3570 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xc04[3:0]
3571 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xd04[3:0]
3572 disabled_rf_cnt++;
3573 }
3574 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_1)
3575 {
3576 cck_default_Rx = max_rssi_index;
3577 cck_optional_Rx = sec_rssi_index;
3578 if(tmp_max_rssi)
3579 update_cck_rx_path = 1;
3580 }
3581 }
3582
3583 if(update_cck_rx_path)
3584 {
3585 DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2)|(cck_optional_Rx);
3586 rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path);
3587 }
3588
3589 if(DM_RxPathSelTable.disabledRF)
3590 {
3591 for(i=0; i<4; i++)
3592 {
3593 if((DM_RxPathSelTable.disabledRF>>i) & 0x1) //disabled rf
3594 {
3595 if(tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i])
3596 {
3597 //enable the BB Rx path
3598 //DbgPrint("RF-%d is enabled. \n", 0x1<<i);
3599 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); // 0xc04[3:0]
3600 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); // 0xd04[3:0]
3601 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
3602 disabled_rf_cnt--;
3603 }
3604 }
3605 }
3606 }
3607 }
3608
3609 /*-----------------------------------------------------------------------------
3610 * Function: dm_check_rx_path_selection()
3611 *
3612 * Overview: Call a workitem to check current RXRF path and Rx Path selection by RSSI.
3613 *
3614 * Input: NONE
3615 *
3616 * Output: NONE
3617 *
3618 * Return: NONE
3619 *
3620 * Revised History:
3621 * When Who Remark
3622 * 05/28/2008 amy Create Version 0 porting from windows code.
3623 *
3624 *---------------------------------------------------------------------------*/
3625 static void dm_check_rx_path_selection(struct net_device *dev)
3626 {
3627 struct r8192_priv *priv = ieee80211_priv(dev);
3628 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
3629 queue_delayed_work(priv->priv_wq,&priv->rfpath_check_wq,0);
3630 #else
3631 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3632 schedule_task(&priv->rfpath_check_wq);
3633 #else
3634 queue_work(priv->priv_wq,&priv->rfpath_check_wq);
3635 #endif
3636 #endif
3637 } /* dm_CheckRxRFPath */
3638
3639
3640 static void dm_init_fsync (struct net_device *dev)
3641 {
3642 struct r8192_priv *priv = ieee80211_priv(dev);
3643
3644 priv->ieee80211->fsync_time_interval = 500;
3645 priv->ieee80211->fsync_rate_bitmap = 0x0f000800;
3646 priv->ieee80211->fsync_rssi_threshold = 30;
3647 #ifdef RTL8190P
3648 priv->ieee80211->bfsync_enable = true;
3649 #else
3650 priv->ieee80211->bfsync_enable = false;
3651 #endif
3652 priv->ieee80211->fsync_multiple_timeinterval = 3;
3653 priv->ieee80211->fsync_firstdiff_ratethreshold= 100;
3654 priv->ieee80211->fsync_seconddiff_ratethreshold= 200;
3655 priv->ieee80211->fsync_state = Default_Fsync;
3656 priv->framesyncMonitor = 1; // current default 0xc38 monitor on
3657
3658 init_timer(&priv->fsync_timer);
3659 priv->fsync_timer.data = (unsigned long)dev;
3660 priv->fsync_timer.function = dm_fsync_timer_callback;
3661 }
3662
3663
3664 static void dm_deInit_fsync(struct net_device *dev)
3665 {
3666 struct r8192_priv *priv = ieee80211_priv(dev);
3667 del_timer_sync(&priv->fsync_timer);
3668 }
3669
3670 extern void dm_fsync_timer_callback(unsigned long data)
3671 {
3672 struct net_device *dev = (struct net_device *)data;
3673 struct r8192_priv *priv = ieee80211_priv((struct net_device *)data);
3674 u32 rate_index, rate_count = 0, rate_count_diff=0;
3675 bool bSwitchFromCountDiff = false;
3676 bool bDoubleTimeInterval = false;
3677
3678 if( priv->ieee80211->state == IEEE80211_LINKED &&
3679 priv->ieee80211->bfsync_enable &&
3680 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC))
3681 {
3682 // Count rate 54, MCS [7], [12, 13, 14, 15]
3683 u32 rate_bitmap;
3684 for(rate_index = 0; rate_index <= 27; rate_index++)
3685 {
3686 rate_bitmap = 1 << rate_index;
3687 if(priv->ieee80211->fsync_rate_bitmap & rate_bitmap)
3688 rate_count+= priv->stats.received_rate_histogram[1][rate_index];
3689 }
3690
3691 if(rate_count < priv->rate_record)
3692 rate_count_diff = 0xffffffff - rate_count + priv->rate_record;
3693 else
3694 rate_count_diff = rate_count - priv->rate_record;
3695 if(rate_count_diff < priv->rateCountDiffRecord)
3696 {
3697
3698 u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff;
3699 // Contiune count
3700 if(DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold)
3701 priv->ContiuneDiffCount++;
3702 else
3703 priv->ContiuneDiffCount = 0;
3704
3705 // Contiune count over
3706 if(priv->ContiuneDiffCount >=2)
3707 {
3708 bSwitchFromCountDiff = true;
3709 priv->ContiuneDiffCount = 0;
3710 }
3711 }
3712 else
3713 {
3714 // Stop contiune count
3715 priv->ContiuneDiffCount = 0;
3716 }
3717
3718 //If Count diff <= FsyncRateCountThreshold
3719 if(rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold)
3720 {
3721 bSwitchFromCountDiff = true;
3722 priv->ContiuneDiffCount = 0;
3723 }
3724 priv->rate_record = rate_count;
3725 priv->rateCountDiffRecord = rate_count_diff;
3726 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
3727 // if we never receive those mcs rate and rssi > 30 % then switch fsyn
3728 if(priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff)
3729 {
3730 bDoubleTimeInterval = true;
3731 priv->bswitch_fsync = !priv->bswitch_fsync;
3732 if(priv->bswitch_fsync)
3733 {
3734 #ifdef RTL8190P
3735 write_nic_byte(dev,0xC36, 0x00);
3736 #else
3737 write_nic_byte(dev,0xC36, 0x1c);
3738 #endif
3739 write_nic_byte(dev, 0xC3e, 0x90);
3740 }
3741 else
3742 {
3743 #ifdef RTL8190P
3744 write_nic_byte(dev, 0xC36, 0x40);
3745 #else
3746 write_nic_byte(dev, 0xC36, 0x5c);
3747 #endif
3748 write_nic_byte(dev, 0xC3e, 0x96);
3749 }
3750 }
3751 else if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold)
3752 {
3753 if(priv->bswitch_fsync)
3754 {
3755 priv->bswitch_fsync = false;
3756 #ifdef RTL8190P
3757 write_nic_byte(dev, 0xC36, 0x40);
3758 #else
3759 write_nic_byte(dev, 0xC36, 0x5c);
3760 #endif
3761 write_nic_byte(dev, 0xC3e, 0x96);
3762 }
3763 }
3764 if(bDoubleTimeInterval){
3765 if(timer_pending(&priv->fsync_timer))
3766 del_timer_sync(&priv->fsync_timer);
3767 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval*priv->ieee80211->fsync_multiple_timeinterval);
3768 add_timer(&priv->fsync_timer);
3769 }
3770 else{
3771 if(timer_pending(&priv->fsync_timer))
3772 del_timer_sync(&priv->fsync_timer);
3773 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
3774 add_timer(&priv->fsync_timer);
3775 }
3776 }
3777 else
3778 {
3779 // Let Register return to default value;
3780 if(priv->bswitch_fsync)
3781 {
3782 priv->bswitch_fsync = false;
3783 #ifdef RTL8190P
3784 write_nic_byte(dev, 0xC36, 0x40);
3785 #else
3786 write_nic_byte(dev, 0xC36, 0x5c);
3787 #endif
3788 write_nic_byte(dev, 0xC3e, 0x96);
3789 }
3790 priv->ContiuneDiffCount = 0;
3791 #ifdef RTL8190P
3792 write_nic_dword(dev, rOFDM0_RxDetector2, 0x164052cd);
3793 #else
3794 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
3795 #endif
3796 }
3797 RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount);
3798 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
3799 }
3800
3801 static void dm_StartHWFsync(struct net_device *dev)
3802 {
3803 RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);
3804 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf);
3805 write_nic_byte(dev, 0xc3b, 0x41);
3806 }
3807
3808 static void dm_EndSWFsync(struct net_device *dev)
3809 {
3810 struct r8192_priv *priv = ieee80211_priv(dev);
3811
3812 RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);
3813 del_timer_sync(&(priv->fsync_timer));
3814
3815 // Let Register return to default value;
3816 if(priv->bswitch_fsync)
3817 {
3818 priv->bswitch_fsync = false;
3819
3820 #ifdef RTL8190P
3821 write_nic_byte(dev, 0xC36, 0x40);
3822 #else
3823 write_nic_byte(dev, 0xC36, 0x5c);
3824 #endif
3825
3826 write_nic_byte(dev, 0xC3e, 0x96);
3827 }
3828
3829 priv->ContiuneDiffCount = 0;
3830 #ifndef RTL8190P
3831 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
3832 #endif
3833
3834 }
3835
3836 static void dm_StartSWFsync(struct net_device *dev)
3837 {
3838 struct r8192_priv *priv = ieee80211_priv(dev);
3839 u32 rateIndex;
3840 u32 rateBitmap;
3841
3842 RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
3843 // Initial rate record to zero, start to record.
3844 priv->rate_record = 0;
3845 // Initial contiune diff count to zero, start to record.
3846 priv->ContiuneDiffCount = 0;
3847 priv->rateCountDiffRecord = 0;
3848 priv->bswitch_fsync = false;
3849
3850 if(priv->ieee80211->mode == WIRELESS_MODE_N_24G)
3851 {
3852 priv->ieee80211->fsync_firstdiff_ratethreshold= 600;
3853 priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff;
3854 }
3855 else
3856 {
3857 priv->ieee80211->fsync_firstdiff_ratethreshold= 200;
3858 priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
3859 }
3860 for(rateIndex = 0; rateIndex <= 27; rateIndex++)
3861 {
3862 rateBitmap = 1 << rateIndex;
3863 if(priv->ieee80211->fsync_rate_bitmap & rateBitmap)
3864 priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex];
3865 }
3866 if(timer_pending(&priv->fsync_timer))
3867 del_timer_sync(&priv->fsync_timer);
3868 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
3869 add_timer(&priv->fsync_timer);
3870
3871 #ifndef RTL8190P
3872 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd);
3873 #endif
3874
3875 }
3876
3877 static void dm_EndHWFsync(struct net_device *dev)
3878 {
3879 RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
3880 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
3881 write_nic_byte(dev, 0xc3b, 0x49);
3882
3883 }
3884
3885 void dm_check_fsync(struct net_device *dev)
3886 {
3887 #define RegC38_Default 0
3888 #define RegC38_NonFsync_Other_AP 1
3889 #define RegC38_Fsync_AP_BCM 2
3890 struct r8192_priv *priv = ieee80211_priv(dev);
3891 //u32 framesyncC34;
3892 static u8 reg_c38_State=RegC38_Default;
3893 static u32 reset_cnt=0;
3894
3895 RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval);
3896 RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold);
3897
3898 if( priv->ieee80211->state == IEEE80211_LINKED &&
3899 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC))
3900 {
3901 if(priv->ieee80211->bfsync_enable == 0)
3902 {
3903 switch(priv->ieee80211->fsync_state)
3904 {
3905 case Default_Fsync:
3906 dm_StartHWFsync(dev);
3907 priv->ieee80211->fsync_state = HW_Fsync;
3908 break;
3909 case SW_Fsync:
3910 dm_EndSWFsync(dev);
3911 dm_StartHWFsync(dev);
3912 priv->ieee80211->fsync_state = HW_Fsync;
3913 break;
3914 case HW_Fsync:
3915 default:
3916 break;
3917 }
3918 }
3919 else
3920 {
3921 switch(priv->ieee80211->fsync_state)
3922 {
3923 case Default_Fsync:
3924 dm_StartSWFsync(dev);
3925 priv->ieee80211->fsync_state = SW_Fsync;
3926 break;
3927 case HW_Fsync:
3928 dm_EndHWFsync(dev);
3929 dm_StartSWFsync(dev);
3930 priv->ieee80211->fsync_state = SW_Fsync;
3931 break;
3932 case SW_Fsync:
3933 default:
3934 break;
3935
3936 }
3937 }
3938 if(priv->framesyncMonitor)
3939 {
3940 if(reg_c38_State != RegC38_Fsync_AP_BCM)
3941 { //For broadcom AP we write different default value
3942 #ifdef RTL8190P
3943 write_nic_byte(dev, rOFDM0_RxDetector3, 0x15);
3944 #else
3945 write_nic_byte(dev, rOFDM0_RxDetector3, 0x95);
3946 #endif
3947
3948 reg_c38_State = RegC38_Fsync_AP_BCM;
3949 }
3950 }
3951 }
3952 else
3953 {
3954 switch(priv->ieee80211->fsync_state)
3955 {
3956 case HW_Fsync:
3957 dm_EndHWFsync(dev);
3958 priv->ieee80211->fsync_state = Default_Fsync;
3959 break;
3960 case SW_Fsync:
3961 dm_EndSWFsync(dev);
3962 priv->ieee80211->fsync_state = Default_Fsync;
3963 break;
3964 case Default_Fsync:
3965 default:
3966 break;
3967 }
3968
3969 if(priv->framesyncMonitor)
3970 {
3971 if(priv->ieee80211->state == IEEE80211_LINKED)
3972 {
3973 if(priv->undecorated_smoothed_pwdb <= RegC38_TH)
3974 {
3975 if(reg_c38_State != RegC38_NonFsync_Other_AP)
3976 {
3977 #ifdef RTL8190P
3978 write_nic_byte(dev, rOFDM0_RxDetector3, 0x10);
3979 #else
3980 write_nic_byte(dev, rOFDM0_RxDetector3, 0x90);
3981 #endif
3982
3983 reg_c38_State = RegC38_NonFsync_Other_AP;
3984 #if 0//cosa
3985 if (Adapter->HardwareType == HARDWARE_TYPE_RTL8190P)
3986 DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x10);
3987 else
3988 DbgPrint("Fsync is idle, rssi<=35, write 0xc38 = 0x%x \n", 0x90);
3989 #endif
3990 }
3991 }
3992 else if(priv->undecorated_smoothed_pwdb >= (RegC38_TH+5))
3993 {
3994 if(reg_c38_State)
3995 {
3996 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3997 reg_c38_State = RegC38_Default;
3998 //DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x \n", pHalData->framesync);
3999 }
4000 }
4001 }
4002 else
4003 {
4004 if(reg_c38_State)
4005 {
4006 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
4007 reg_c38_State = RegC38_Default;
4008 //DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x \n", pHalData->framesync);
4009 }
4010 }
4011 }
4012 }
4013 if(priv->framesyncMonitor)
4014 {
4015 if(priv->reset_count != reset_cnt)
4016 { //After silent reset, the reg_c38_State will be returned to default value
4017 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
4018 reg_c38_State = RegC38_Default;
4019 reset_cnt = priv->reset_count;
4020 //DbgPrint("reg_c38_State = 0 for silent reset. \n");
4021 }
4022 }
4023 else
4024 {
4025 if(reg_c38_State)
4026 {
4027 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
4028 reg_c38_State = RegC38_Default;
4029 //DbgPrint("framesync no monitor, write 0xc38 = 0x%x \n", pHalData->framesync);
4030 }
4031 }
4032 }
4033
4034 #if 0
4035 /*-----------------------------------------------------------------------------
4036 * Function: DM_CheckLBusStatus()
4037 *
4038 * Overview: For 9x series, we must make sure LBUS is active for IO.
4039 *
4040 * Input: NONE
4041 *
4042 * Output: NONE
4043 *
4044 * Return: NONE
4045 *
4046 * Revised History:
4047 * When Who Remark
4048 * 02/22/2008 MHC Create Version 0.
4049 *
4050 *---------------------------------------------------------------------------*/
4051 extern s1Byte DM_CheckLBusStatus(IN PADAPTER Adapter)
4052 {
4053 PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
4054
4055 #if (HAL_CODE_BASE & RTL819X)
4056
4057 #if (HAL_CODE_BASE == RTL8192)
4058
4059 #if( DEV_BUS_TYPE==PCI_INTERFACE)
4060 //return (pMgntInfo->bLbusEnable); // For debug only
4061 return TRUE;
4062 #endif
4063
4064 #if( DEV_BUS_TYPE==USB_INTERFACE)
4065 return TRUE;
4066 #endif
4067
4068 #endif // #if (HAL_CODE_BASE == RTL8192)
4069
4070 #if (HAL_CODE_BASE == RTL8190)
4071 return TRUE;
4072 #endif // #if (HAL_CODE_BASE == RTL8190)
4073
4074 #endif // #if (HAL_CODE_BASE & RTL819X)
4075 } /* DM_CheckLBusStatus */
4076
4077 #endif
4078
4079 /*-----------------------------------------------------------------------------
4080 * Function: dm_shadow_init()
4081 *
4082 * Overview: Store all NIC MAC/BB register content.
4083 *
4084 * Input: NONE
4085 *
4086 * Output: NONE
4087 *
4088 * Return: NONE
4089 *
4090 * Revised History:
4091 * When Who Remark
4092 * 05/29/2008 amy Create Version 0 porting from windows code.
4093 *
4094 *---------------------------------------------------------------------------*/
4095 extern void dm_shadow_init(struct net_device *dev)
4096 {
4097 u8 page;
4098 u16 offset;
4099
4100 for (page = 0; page < 5; page++)
4101 for (offset = 0; offset < 256; offset++)
4102 {
4103 dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
4104 //DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]);
4105 }
4106
4107 for (page = 8; page < 11; page++)
4108 for (offset = 0; offset < 256; offset++)
4109 dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
4110
4111 for (page = 12; page < 15; page++)
4112 for (offset = 0; offset < 256; offset++)
4113 dm_shadow[page][offset] = read_nic_byte(dev, offset+page*256);
4114
4115 } /* dm_shadow_init */
4116
4117 /*---------------------------Define function prototype------------------------*/
4118 /*-----------------------------------------------------------------------------
4119 * Function: DM_DynamicTxPower()
4120 *
4121 * Overview: Detect Signal strength to control TX Registry
4122 Tx Power Control For Near/Far Range
4123 *
4124 * Input: NONE
4125 *
4126 * Output: NONE
4127 *
4128 * Return: NONE
4129 *
4130 * Revised History:
4131 * When Who Remark
4132 * 03/06/2008 Jacken Create Version 0.
4133 *
4134 *---------------------------------------------------------------------------*/
4135 static void dm_init_dynamic_txpower(struct net_device *dev)
4136 {
4137 struct r8192_priv *priv = ieee80211_priv(dev);
4138
4139 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
4140 priv->ieee80211->bdynamic_txpower_enable = true; //Default to enable Tx Power Control
4141 priv->bLastDTPFlag_High = false;
4142 priv->bLastDTPFlag_Low = false;
4143 priv->bDynamicTxHighPower = false;
4144 priv->bDynamicTxLowPower = false;
4145 }
4146
4147 static void dm_dynamic_txpower(struct net_device *dev)
4148 {
4149 struct r8192_priv *priv = ieee80211_priv(dev);
4150 unsigned int txhipower_threshhold=0;
4151 unsigned int txlowpower_threshold=0;
4152 if(priv->ieee80211->bdynamic_txpower_enable != true)
4153 {
4154 priv->bDynamicTxHighPower = false;
4155 priv->bDynamicTxLowPower = false;
4156 return;
4157 }
4158 //printk("priv->ieee80211->current_network.unknown_cap_exist is %d ,priv->ieee80211->current_network.broadcom_cap_exist is %d\n",priv->ieee80211->current_network.unknown_cap_exist,priv->ieee80211->current_network.broadcom_cap_exist);
4159 if((priv->ieee80211->current_network.atheros_cap_exist ) && (priv->ieee80211->mode == IEEE_G)){
4160 txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH;
4161 txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW;
4162 }
4163 else
4164 {
4165 txhipower_threshhold = TX_POWER_NEAR_FIELD_THRESH_HIGH;
4166 txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW;
4167 }
4168
4169 // printk("=======>%s(): txhipower_threshhold is %d,txlowpower_threshold is %d\n",__FUNCTION__,txhipower_threshhold,txlowpower_threshold);
4170
4171 RT_TRACE(COMP_TXAGC,"priv->undecorated_smoothed_pwdb = %ld \n" , priv->undecorated_smoothed_pwdb);
4172
4173 if(priv->ieee80211->state == IEEE80211_LINKED)
4174 {
4175 if(priv->undecorated_smoothed_pwdb >= txhipower_threshhold)
4176 {
4177 priv->bDynamicTxHighPower = true;
4178 priv->bDynamicTxLowPower = false;
4179 }
4180 else
4181 {
4182 // high power state check
4183 if(priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower == true)
4184 {
4185 priv->bDynamicTxHighPower = false;
4186 }
4187 // low power state check
4188 if(priv->undecorated_smoothed_pwdb < 35)
4189 {
4190 priv->bDynamicTxLowPower = true;
4191 }
4192 else if(priv->undecorated_smoothed_pwdb >= 40)
4193 {
4194 priv->bDynamicTxLowPower = false;
4195 }
4196 }
4197 }
4198 else
4199 {
4200 //pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;
4201 priv->bDynamicTxHighPower = false;
4202 priv->bDynamicTxLowPower = false;
4203 }
4204
4205 if( (priv->bDynamicTxHighPower != priv->bLastDTPFlag_High ) ||
4206 (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low ) )
4207 {
4208 RT_TRACE(COMP_TXAGC,"SetTxPowerLevel8190() channel = %d \n" , priv->ieee80211->current_network.channel);
4209
4210
4211 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
4212
4213 }
4214 priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;
4215 priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower;
4216
4217 } /* dm_dynamic_txpower */
4218
4219 //added by vivi, for read tx rate and retrycount
4220 static void dm_check_txrateandretrycount(struct net_device * dev)
4221 {
4222 struct r8192_priv *priv = ieee80211_priv(dev);
4223 struct ieee80211_device* ieee = priv->ieee80211;
4224 //for 11n tx rate
4225 // priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
4226 ieee->softmac_stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
4227 //printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);
4228 //for initial tx rate
4229 // priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg);
4230 ieee->softmac_stats.last_packet_rate = read_nic_byte(dev ,Initial_Tx_Rate_Reg);
4231 //for tx tx retry count
4232 // priv->stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
4233 ieee->softmac_stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
4234 }
4235
4236 static void dm_send_rssi_tofw(struct net_device *dev)
4237 {
4238 DCMD_TXCMD_T tx_cmd;
4239 struct r8192_priv *priv = ieee80211_priv(dev);
4240
4241 // If we test chariot, we should stop the TX command ?
4242 // Because 92E will always silent reset when we send tx command. We use register
4243 // 0x1e0(byte) to botify driver.
4244 write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
4245 return;
4246 #if 1
4247 tx_cmd.Op = TXCMD_SET_RX_RSSI;
4248 tx_cmd.Length = 4;
4249 tx_cmd.Value = priv->undecorated_smoothed_pwdb;
4250
4251 cmpk_message_handle_tx(dev, (u8*)&tx_cmd,
4252 DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
4253 #endif
4254 }
4255
4256 /*---------------------------Define function prototype------------------------*/
4257
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