1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
9 * You should have received a copy of the GNU General Public License along with
10 * this program; if not, write to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
13 * The full GNU General Public License is included in this distribution in the
14 * file called LICENSE.
16 * Contact Information:
17 * wlanfae <wlanfae@realtek.com>
18 ******************************************************************************/
21 #include "r8192E_phyreg.h"
22 #include "r8192E_phy.h"
23 #include "r8190P_rtl8256.h"
25 void rtl92e_set_bandwidth(struct net_device
*dev
,
26 enum ht_channel_width Bandwidth
)
29 struct r8192_priv
*priv
= rtllib_priv(dev
);
31 if (priv
->card_8192_version
!= VERSION_8190_BD
&&
32 priv
->card_8192_version
!= VERSION_8190_BE
) {
33 netdev_warn(dev
, "%s(): Unknown HW version.\n", __func__
);
37 for (eRFPath
= 0; eRFPath
< priv
->NumTotalRFPath
; eRFPath
++) {
38 if (!rtl92e_is_legal_rf_path(dev
, eRFPath
))
42 case HT_CHANNEL_WIDTH_20
:
43 rtl92e_set_rf_reg(dev
, (enum rf90_radio_path
)eRFPath
,
44 0x0b, bMask12Bits
, 0x100);
45 rtl92e_set_rf_reg(dev
, (enum rf90_radio_path
)eRFPath
,
46 0x2c, bMask12Bits
, 0x3d7);
47 rtl92e_set_rf_reg(dev
, (enum rf90_radio_path
)eRFPath
,
48 0x0e, bMask12Bits
, 0x021);
50 case HT_CHANNEL_WIDTH_20_40
:
51 rtl92e_set_rf_reg(dev
, (enum rf90_radio_path
)eRFPath
,
52 0x0b, bMask12Bits
, 0x300);
53 rtl92e_set_rf_reg(dev
, (enum rf90_radio_path
)eRFPath
,
54 0x2c, bMask12Bits
, 0x3ff);
55 rtl92e_set_rf_reg(dev
, (enum rf90_radio_path
)eRFPath
,
56 0x0e, bMask12Bits
, 0x0e1);
59 netdev_err(dev
, "%s(): Unknown bandwidth: %#X\n",
67 bool rtl92e_config_rf(struct net_device
*dev
)
72 struct bb_reg_definition
*pPhyReg
;
73 struct r8192_priv
*priv
= rtllib_priv(dev
);
74 u32 RegOffSetToBeCheck
= 0x3;
75 u32 RegValueToBeCheck
= 0x7f1;
76 u32 RF3_Final_Value
= 0;
77 u8 ConstRetryTimes
= 5, RetryTimes
= 5;
80 priv
->NumTotalRFPath
= RTL819X_TOTAL_RF_PATH
;
82 for (eRFPath
= (enum rf90_radio_path
)RF90_PATH_A
;
83 eRFPath
< priv
->NumTotalRFPath
; eRFPath
++) {
84 if (!rtl92e_is_legal_rf_path(dev
, eRFPath
))
87 pPhyReg
= &priv
->PHYRegDef
[eRFPath
];
93 u4RegValue
= rtl92e_get_bb_reg(dev
, pPhyReg
->rfintfs
,
98 u4RegValue
= rtl92e_get_bb_reg(dev
, pPhyReg
->rfintfs
,
103 rtl92e_set_bb_reg(dev
, pPhyReg
->rfintfe
, bRFSI_RFENV
<<16, 0x1);
105 rtl92e_set_bb_reg(dev
, pPhyReg
->rfintfo
, bRFSI_RFENV
, 0x1);
107 rtl92e_set_bb_reg(dev
, pPhyReg
->rfHSSIPara2
,
108 b3WireAddressLength
, 0x0);
109 rtl92e_set_bb_reg(dev
, pPhyReg
->rfHSSIPara2
,
110 b3WireDataLength
, 0x0);
112 rtl92e_set_rf_reg(dev
, (enum rf90_radio_path
)eRFPath
, 0x0,
115 rtStatus
= rtl92e_check_bb_and_rf(dev
, HW90_BLOCK_RF
,
116 (enum rf90_radio_path
)eRFPath
);
118 netdev_err(dev
, "%s(): Failed to check RF Path %d.\n",
123 RetryTimes
= ConstRetryTimes
;
125 while (RF3_Final_Value
!= RegValueToBeCheck
&&
127 ret
= rtl92e_config_rf_path(dev
,
128 (enum rf90_radio_path
)eRFPath
);
129 RF3_Final_Value
= rtl92e_get_rf_reg(dev
,
130 (enum rf90_radio_path
)eRFPath
,
134 "RF %d %d register final value: %x\n",
135 eRFPath
, RegOffSetToBeCheck
,
143 rtl92e_set_bb_reg(dev
, pPhyReg
->rfintfs
, bRFSI_RFENV
,
148 rtl92e_set_bb_reg(dev
, pPhyReg
->rfintfs
,
149 bRFSI_RFENV
<<16, u4RegValue
);
155 "%s(): Failed to initialize RF Path %d.\n",
162 RT_TRACE(COMP_PHY
, "PHY Initialization Success\n");
169 void rtl92e_set_cck_tx_power(struct net_device
*dev
, u8 powerlevel
)
172 struct r8192_priv
*priv
= rtllib_priv(dev
);
175 if (priv
->bDynamicTxLowPower
) {
176 if (priv
->CustomerID
== RT_CID_819x_Netcore
)
179 TxAGC
+= priv
->CckPwEnl
;
183 rtl92e_set_bb_reg(dev
, rTxAGC_CCK_Mcs32
, bTxAGCRateCCK
, TxAGC
);
187 void rtl92e_set_ofdm_tx_power(struct net_device
*dev
, u8 powerlevel
)
189 struct r8192_priv
*priv
= rtllib_priv(dev
);
190 u32 writeVal
, powerBase0
, powerBase1
, writeVal_tmp
;
192 u16 RegOffset
[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
193 u8 byte0
, byte1
, byte2
, byte3
;
195 powerBase0
= powerlevel
+ priv
->LegacyHTTxPowerDiff
;
196 powerBase0
= (powerBase0
<< 24) | (powerBase0
<< 16) |
197 (powerBase0
<< 8) | powerBase0
;
198 powerBase1
= powerlevel
;
199 powerBase1
= (powerBase1
<< 24) | (powerBase1
<< 16) |
200 (powerBase1
<< 8) | powerBase1
;
202 for (index
= 0; index
< 6; index
++) {
203 writeVal
= (u32
)(priv
->MCSTxPowerLevelOriginalOffset
[index
] +
204 ((index
< 2) ? powerBase0
: powerBase1
));
205 byte0
= (u8
)(writeVal
& 0x7f);
206 byte1
= (u8
)((writeVal
& 0x7f00)>>8);
207 byte2
= (u8
)((writeVal
& 0x7f0000)>>16);
208 byte3
= (u8
)((writeVal
& 0x7f000000)>>24);
219 writeVal_tmp
= (byte3
<< 24) | (byte2
<< 16) |
220 (byte1
<< 8) | byte0
;
221 priv
->Pwr_Track
= writeVal_tmp
;
224 if (priv
->bDynamicTxHighPower
)
225 writeVal
= 0x03030303;
227 writeVal
= (byte3
<< 24) | (byte2
<< 16) |
228 (byte1
<< 8) | byte0
;
229 rtl92e_set_bb_reg(dev
, RegOffset
[index
], 0x7f7f7f7f, writeVal
);