]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
MAINTAINERS: Update MAX77802 PMIC entry
[mirror_ubuntu-artful-kernel.git] / drivers / staging / rtl8192e / rtl8192e / r8192E_dev.c
1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 *
4 * Based on the r8180 driver, which is:
5 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * The full GNU General Public License is included in this distribution in the
16 * file called LICENSE.
17 *
18 * Contact Information:
19 * wlanfae <wlanfae@realtek.com>
20 *****************************************************************************/
21 #include "rtl_core.h"
22 #include "r8192E_phy.h"
23 #include "r8192E_phyreg.h"
24 #include "r8190P_rtl8256.h"
25 #include "r8192E_cmdpkt.h"
26 #include "rtl_dm.h"
27 #include "rtl_wx.h"
28
29 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI,
30 EDCAPARA_VO};
31
32 void rtl92e_start_beacon(struct net_device *dev)
33 {
34 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
35 struct rtllib_network *net = &priv->rtllib->current_network;
36 u16 BcnTimeCfg = 0;
37 u16 BcnCW = 6;
38 u16 BcnIFS = 0xf;
39
40 rtl92e_irq_disable(dev);
41
42 rtl92e_writew(dev, ATIMWND, 2);
43
44 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
45 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
46 rtl92e_writew(dev, BCN_DMATIME, 256);
47
48 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
49
50 BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
51 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
52 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
53 rtl92e_irq_enable(dev);
54 }
55
56 static void _rtl92e_update_msr(struct net_device *dev)
57 {
58 struct r8192_priv *priv = rtllib_priv(dev);
59 u8 msr;
60 enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
61
62 msr = rtl92e_readb(dev, MSR);
63 msr &= ~MSR_LINK_MASK;
64
65 switch (priv->rtllib->iw_mode) {
66 case IW_MODE_INFRA:
67 if (priv->rtllib->state == RTLLIB_LINKED)
68 msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
69 else
70 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
71 LedAction = LED_CTL_LINK;
72 break;
73 case IW_MODE_ADHOC:
74 if (priv->rtllib->state == RTLLIB_LINKED)
75 msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
76 else
77 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
78 break;
79 case IW_MODE_MASTER:
80 if (priv->rtllib->state == RTLLIB_LINKED)
81 msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
82 else
83 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
84 break;
85 default:
86 break;
87 }
88
89 rtl92e_writeb(dev, MSR, msr);
90 if (priv->rtllib->LedControlHandler)
91 priv->rtllib->LedControlHandler(dev, LedAction);
92 }
93
94 void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val)
95 {
96 struct r8192_priv *priv = rtllib_priv(dev);
97
98 switch (variable) {
99 case HW_VAR_BSSID:
100 rtl92e_writel(dev, BSSIDR, ((u32 *)(val))[0]);
101 rtl92e_writew(dev, BSSIDR+2, ((u16 *)(val+2))[0]);
102 break;
103
104 case HW_VAR_MEDIA_STATUS:
105 {
106 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
107 u8 btMsr = rtl92e_readb(dev, MSR);
108
109 btMsr &= 0xfc;
110
111 switch (OpMode) {
112 case RT_OP_MODE_INFRASTRUCTURE:
113 btMsr |= MSR_INFRA;
114 break;
115
116 case RT_OP_MODE_IBSS:
117 btMsr |= MSR_ADHOC;
118 break;
119
120 case RT_OP_MODE_AP:
121 btMsr |= MSR_AP;
122 break;
123
124 default:
125 btMsr |= MSR_NOLINK;
126 break;
127 }
128
129 rtl92e_writeb(dev, MSR, btMsr);
130
131 }
132 break;
133
134 case HW_VAR_CECHK_BSSID:
135 {
136 u32 RegRCR, Type;
137
138 Type = val[0];
139 RegRCR = rtl92e_readl(dev, RCR);
140 priv->ReceiveConfig = RegRCR;
141
142 if (Type == true)
143 RegRCR |= (RCR_CBSSID);
144 else if (Type == false)
145 RegRCR &= (~RCR_CBSSID);
146
147 rtl92e_writel(dev, RCR, RegRCR);
148 priv->ReceiveConfig = RegRCR;
149
150 }
151 break;
152
153 case HW_VAR_SLOT_TIME:
154
155 priv->slot_time = val[0];
156 rtl92e_writeb(dev, SLOT_TIME, val[0]);
157
158 break;
159
160 case HW_VAR_ACK_PREAMBLE:
161 {
162 u32 regTmp;
163
164 priv->short_preamble = (bool)*val;
165 regTmp = priv->basic_rate;
166 if (priv->short_preamble)
167 regTmp |= BRSR_AckShortPmb;
168 rtl92e_writel(dev, RRSR, regTmp);
169 break;
170 }
171
172 case HW_VAR_CPU_RST:
173 rtl92e_writel(dev, CPU_GEN, ((u32 *)(val))[0]);
174 break;
175
176 case HW_VAR_AC_PARAM:
177 {
178 u8 pAcParam = *val;
179 u32 eACI = pAcParam;
180 u8 u1bAIFS;
181 u32 u4bAcParam;
182 u8 mode = priv->rtllib->mode;
183 struct rtllib_qos_parameters *qop =
184 &priv->rtllib->current_network.qos_data.parameters;
185
186 u1bAIFS = qop->aifs[pAcParam] *
187 ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
188
189 rtl92e_dm_init_edca_turbo(dev);
190
191 u4bAcParam = (le16_to_cpu(qop->tx_op_limit[pAcParam]) <<
192 AC_PARAM_TXOP_LIMIT_OFFSET) |
193 ((le16_to_cpu(qop->cw_max[pAcParam])) <<
194 AC_PARAM_ECW_MAX_OFFSET) |
195 ((le16_to_cpu(qop->cw_min[pAcParam])) <<
196 AC_PARAM_ECW_MIN_OFFSET) |
197 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET);
198
199 RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n",
200 __func__, eACI, u4bAcParam);
201 switch (eACI) {
202 case AC1_BK:
203 rtl92e_writel(dev, EDCAPARA_BK, u4bAcParam);
204 break;
205
206 case AC0_BE:
207 rtl92e_writel(dev, EDCAPARA_BE, u4bAcParam);
208 break;
209
210 case AC2_VI:
211 rtl92e_writel(dev, EDCAPARA_VI, u4bAcParam);
212 break;
213
214 case AC3_VO:
215 rtl92e_writel(dev, EDCAPARA_VO, u4bAcParam);
216 break;
217
218 default:
219 netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n",
220 eACI);
221 break;
222 }
223 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
224 &pAcParam);
225 break;
226 }
227
228 case HW_VAR_ACM_CTRL:
229 {
230 struct rtllib_qos_parameters *qos_parameters =
231 &priv->rtllib->current_network.qos_data.parameters;
232 u8 pAcParam = *val;
233 u32 eACI = pAcParam;
234 union aci_aifsn *pAciAifsn = (union aci_aifsn *) &
235 (qos_parameters->aifs[0]);
236 u8 acm = pAciAifsn->f.acm;
237 u8 AcmCtrl = rtl92e_readb(dev, AcmHwCtrl);
238
239 RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n",
240 __func__, eACI);
241 AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1);
242
243 if (acm) {
244 switch (eACI) {
245 case AC0_BE:
246 AcmCtrl |= AcmHw_BeqEn;
247 break;
248
249 case AC2_VI:
250 AcmCtrl |= AcmHw_ViqEn;
251 break;
252
253 case AC3_VO:
254 AcmCtrl |= AcmHw_VoqEn;
255 break;
256
257 default:
258 RT_TRACE(COMP_QOS,
259 "SetHwReg8185(): [HW_VAR_ACM_CTRL] acm set failed: eACI is %d\n",
260 eACI);
261 break;
262 }
263 } else {
264 switch (eACI) {
265 case AC0_BE:
266 AcmCtrl &= (~AcmHw_BeqEn);
267 break;
268
269 case AC2_VI:
270 AcmCtrl &= (~AcmHw_ViqEn);
271 break;
272
273 case AC3_VO:
274 AcmCtrl &= (~AcmHw_BeqEn);
275 break;
276
277 default:
278 break;
279 }
280 }
281
282 RT_TRACE(COMP_QOS,
283 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
284 AcmCtrl);
285 rtl92e_writeb(dev, AcmHwCtrl, AcmCtrl);
286 break;
287 }
288
289 case HW_VAR_SIFS:
290 rtl92e_writeb(dev, SIFS, val[0]);
291 rtl92e_writeb(dev, SIFS+1, val[0]);
292 break;
293
294 case HW_VAR_RF_TIMING:
295 {
296 u8 Rf_Timing = *val;
297
298 rtl92e_writeb(dev, rFPGA0_RFTiming1, Rf_Timing);
299 break;
300 }
301
302 default:
303 break;
304 }
305
306 }
307
308 static void _rtl92e_read_eeprom_info(struct net_device *dev)
309 {
310 struct r8192_priv *priv = rtllib_priv(dev);
311 const u8 bMac_Tmp_Addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
312 u8 tempval;
313 u8 ICVer8192, ICVer8256;
314 u16 i, usValue, IC_Version;
315 u16 EEPROMId;
316
317 RT_TRACE(COMP_INIT, "====> _rtl92e_read_eeprom_info\n");
318
319 EEPROMId = rtl92e_eeprom_read(dev, 0);
320 if (EEPROMId != RTL8190_EEPROM_ID) {
321 netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__,
322 EEPROMId);
323 priv->AutoloadFailFlag = true;
324 } else {
325 priv->AutoloadFailFlag = false;
326 }
327
328 if (!priv->AutoloadFailFlag) {
329 priv->eeprom_vid = rtl92e_eeprom_read(dev, EEPROM_VID >> 1);
330 priv->eeprom_did = rtl92e_eeprom_read(dev, EEPROM_DID >> 1);
331
332 usValue = rtl92e_eeprom_read(dev,
333 (u16)(EEPROM_Customer_ID>>1)) >> 8;
334 priv->eeprom_CustomerID = (u8)(usValue & 0xff);
335 usValue = rtl92e_eeprom_read(dev,
336 EEPROM_ICVersion_ChannelPlan>>1);
337 priv->eeprom_ChannelPlan = usValue&0xff;
338 IC_Version = (usValue & 0xff00)>>8;
339
340 ICVer8192 = (IC_Version&0xf);
341 ICVer8256 = (IC_Version & 0xf0)>>4;
342 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
343 RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256);
344 if (ICVer8192 == 0x2) {
345 if (ICVer8256 == 0x5)
346 priv->card_8192_version = VERSION_8190_BE;
347 }
348 switch (priv->card_8192_version) {
349 case VERSION_8190_BD:
350 case VERSION_8190_BE:
351 break;
352 default:
353 priv->card_8192_version = VERSION_8190_BD;
354 break;
355 }
356 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n",
357 priv->card_8192_version);
358 } else {
359 priv->card_8192_version = VERSION_8190_BD;
360 priv->eeprom_vid = 0;
361 priv->eeprom_did = 0;
362 priv->eeprom_CustomerID = 0;
363 priv->eeprom_ChannelPlan = 0;
364 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff);
365 }
366
367 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
368 RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did);
369 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n",
370 priv->eeprom_CustomerID);
371
372 if (!priv->AutoloadFailFlag) {
373 for (i = 0; i < 6; i += 2) {
374 usValue = rtl92e_eeprom_read(dev,
375 (EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1);
376 *(u16 *)(&dev->dev_addr[i]) = usValue;
377 }
378 } else {
379 ether_addr_copy(dev->dev_addr, bMac_Tmp_Addr);
380 }
381
382 RT_TRACE(COMP_INIT, "Permanent Address = %pM\n",
383 dev->dev_addr);
384
385 if (priv->card_8192_version > VERSION_8190_BD)
386 priv->bTXPowerDataReadFromEEPORM = true;
387 else
388 priv->bTXPowerDataReadFromEEPORM = false;
389
390 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
391
392 if (priv->card_8192_version > VERSION_8190_BD) {
393 if (!priv->AutoloadFailFlag) {
394 tempval = (rtl92e_eeprom_read(dev,
395 (EEPROM_RFInd_PowerDiff >> 1))) & 0xff;
396 priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf;
397
398 if (tempval&0x80)
399 priv->rf_type = RF_1T2R;
400 else
401 priv->rf_type = RF_2T4R;
402 } else {
403 priv->EEPROMLegacyHTTxPowerDiff = 0x04;
404 }
405 RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n",
406 priv->EEPROMLegacyHTTxPowerDiff);
407
408 if (!priv->AutoloadFailFlag)
409 priv->EEPROMThermalMeter = (u8)(((rtl92e_eeprom_read(dev,
410 (EEPROM_ThermalMeter>>1))) &
411 0xff00)>>8);
412 else
413 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
414 RT_TRACE(COMP_INIT, "ThermalMeter = %d\n",
415 priv->EEPROMThermalMeter);
416 priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100;
417
418 if (priv->epromtype == EEPROM_93C46) {
419 if (!priv->AutoloadFailFlag) {
420 usValue = rtl92e_eeprom_read(dev,
421 EEPROM_TxPwDiff_CrystalCap >> 1);
422 priv->EEPROMAntPwDiff = (usValue&0x0fff);
423 priv->EEPROMCrystalCap = (u8)((usValue & 0xf000)
424 >> 12);
425 } else {
426 priv->EEPROMAntPwDiff =
427 EEPROM_Default_AntTxPowerDiff;
428 priv->EEPROMCrystalCap =
429 EEPROM_Default_TxPwDiff_CrystalCap;
430 }
431 RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n",
432 priv->EEPROMAntPwDiff);
433 RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n",
434 priv->EEPROMCrystalCap);
435
436 for (i = 0; i < 14; i += 2) {
437 if (!priv->AutoloadFailFlag)
438 usValue = rtl92e_eeprom_read(dev,
439 (EEPROM_TxPwIndex_CCK + i) >> 1);
440 else
441 usValue = EEPROM_Default_TxPower;
442 *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) =
443 usValue;
444 RT_TRACE(COMP_INIT,
445 "CCK Tx Power Level, Index %d = 0x%02x\n",
446 i, priv->EEPROMTxPowerLevelCCK[i]);
447 RT_TRACE(COMP_INIT,
448 "CCK Tx Power Level, Index %d = 0x%02x\n",
449 i+1, priv->EEPROMTxPowerLevelCCK[i+1]);
450 }
451 for (i = 0; i < 14; i += 2) {
452 if (!priv->AutoloadFailFlag)
453 usValue = rtl92e_eeprom_read(dev,
454 (EEPROM_TxPwIndex_OFDM_24G + i) >> 1);
455 else
456 usValue = EEPROM_Default_TxPower;
457 *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i]))
458 = usValue;
459 RT_TRACE(COMP_INIT,
460 "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
461 i, priv->EEPROMTxPowerLevelOFDM24G[i]);
462 RT_TRACE(COMP_INIT,
463 "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
464 i + 1,
465 priv->EEPROMTxPowerLevelOFDM24G[i+1]);
466 }
467 }
468 if (priv->epromtype == EEPROM_93C46) {
469 for (i = 0; i < 14; i++) {
470 priv->TxPowerLevelCCK[i] =
471 priv->EEPROMTxPowerLevelCCK[i];
472 priv->TxPowerLevelOFDM24G[i] =
473 priv->EEPROMTxPowerLevelOFDM24G[i];
474 }
475 priv->LegacyHTTxPowerDiff =
476 priv->EEPROMLegacyHTTxPowerDiff;
477 priv->AntennaTxPwDiff[0] = (priv->EEPROMAntPwDiff &
478 0xf);
479 priv->AntennaTxPwDiff[1] = (priv->EEPROMAntPwDiff &
480 0xf0) >> 4;
481 priv->AntennaTxPwDiff[2] = (priv->EEPROMAntPwDiff &
482 0xf00) >> 8;
483 priv->CrystalCap = priv->EEPROMCrystalCap;
484 priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
485 0xf);
486 priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
487 0xf0) >> 4;
488 } else if (priv->epromtype == EEPROM_93C56) {
489
490 for (i = 0; i < 3; i++) {
491 priv->TxPowerLevelCCK_A[i] =
492 priv->EEPROMRfACCKChnl1TxPwLevel[0];
493 priv->TxPowerLevelOFDM24G_A[i] =
494 priv->EEPROMRfAOfdmChnlTxPwLevel[0];
495 priv->TxPowerLevelCCK_C[i] =
496 priv->EEPROMRfCCCKChnl1TxPwLevel[0];
497 priv->TxPowerLevelOFDM24G_C[i] =
498 priv->EEPROMRfCOfdmChnlTxPwLevel[0];
499 }
500 for (i = 3; i < 9; i++) {
501 priv->TxPowerLevelCCK_A[i] =
502 priv->EEPROMRfACCKChnl1TxPwLevel[1];
503 priv->TxPowerLevelOFDM24G_A[i] =
504 priv->EEPROMRfAOfdmChnlTxPwLevel[1];
505 priv->TxPowerLevelCCK_C[i] =
506 priv->EEPROMRfCCCKChnl1TxPwLevel[1];
507 priv->TxPowerLevelOFDM24G_C[i] =
508 priv->EEPROMRfCOfdmChnlTxPwLevel[1];
509 }
510 for (i = 9; i < 14; i++) {
511 priv->TxPowerLevelCCK_A[i] =
512 priv->EEPROMRfACCKChnl1TxPwLevel[2];
513 priv->TxPowerLevelOFDM24G_A[i] =
514 priv->EEPROMRfAOfdmChnlTxPwLevel[2];
515 priv->TxPowerLevelCCK_C[i] =
516 priv->EEPROMRfCCCKChnl1TxPwLevel[2];
517 priv->TxPowerLevelOFDM24G_C[i] =
518 priv->EEPROMRfCOfdmChnlTxPwLevel[2];
519 }
520 for (i = 0; i < 14; i++)
521 RT_TRACE(COMP_INIT,
522 "priv->TxPowerLevelCCK_A[%d] = 0x%x\n",
523 i, priv->TxPowerLevelCCK_A[i]);
524 for (i = 0; i < 14; i++)
525 RT_TRACE(COMP_INIT,
526 "priv->TxPowerLevelOFDM24G_A[%d] = 0x%x\n",
527 i, priv->TxPowerLevelOFDM24G_A[i]);
528 for (i = 0; i < 14; i++)
529 RT_TRACE(COMP_INIT,
530 "priv->TxPowerLevelCCK_C[%d] = 0x%x\n",
531 i, priv->TxPowerLevelCCK_C[i]);
532 for (i = 0; i < 14; i++)
533 RT_TRACE(COMP_INIT,
534 "priv->TxPowerLevelOFDM24G_C[%d] = 0x%x\n",
535 i, priv->TxPowerLevelOFDM24G_C[i]);
536 priv->LegacyHTTxPowerDiff =
537 priv->EEPROMLegacyHTTxPowerDiff;
538 priv->AntennaTxPwDiff[0] = 0;
539 priv->AntennaTxPwDiff[1] = 0;
540 priv->AntennaTxPwDiff[2] = 0;
541 priv->CrystalCap = priv->EEPROMCrystalCap;
542 priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
543 0xf);
544 priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
545 0xf0) >> 4;
546 }
547 }
548
549 if (priv->rf_type == RF_1T2R) {
550 /* no matter what checkpatch says, the braces are needed */
551 RT_TRACE(COMP_INIT, "\n1T2R config\n");
552 } else if (priv->rf_type == RF_2T4R) {
553 RT_TRACE(COMP_INIT, "\n2T4R config\n");
554 }
555
556 rtl92e_init_adaptive_rate(dev);
557
558 priv->rf_chip = RF_8256;
559
560 if (priv->RegChannelPlan == 0xf)
561 priv->ChannelPlan = priv->eeprom_ChannelPlan;
562 else
563 priv->ChannelPlan = priv->RegChannelPlan;
564
565 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
566 priv->CustomerID = RT_CID_DLINK;
567
568 switch (priv->eeprom_CustomerID) {
569 case EEPROM_CID_DEFAULT:
570 priv->CustomerID = RT_CID_DEFAULT;
571 break;
572 case EEPROM_CID_CAMEO:
573 priv->CustomerID = RT_CID_819x_CAMEO;
574 break;
575 case EEPROM_CID_RUNTOP:
576 priv->CustomerID = RT_CID_819x_RUNTOP;
577 break;
578 case EEPROM_CID_NetCore:
579 priv->CustomerID = RT_CID_819x_Netcore;
580 break;
581 case EEPROM_CID_TOSHIBA:
582 priv->CustomerID = RT_CID_TOSHIBA;
583 if (priv->eeprom_ChannelPlan&0x80)
584 priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f;
585 else
586 priv->ChannelPlan = 0x0;
587 RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n",
588 priv->ChannelPlan);
589 break;
590 case EEPROM_CID_Nettronix:
591 priv->ScanDelay = 100;
592 priv->CustomerID = RT_CID_Nettronix;
593 break;
594 case EEPROM_CID_Pronet:
595 priv->CustomerID = RT_CID_PRONET;
596 break;
597 case EEPROM_CID_DLINK:
598 priv->CustomerID = RT_CID_DLINK;
599 break;
600
601 case EEPROM_CID_WHQL:
602 break;
603 default:
604 break;
605 }
606
607 if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1)
608 priv->ChannelPlan = 0;
609 priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13;
610
611 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
612 priv->rtllib->bSupportRemoteWakeUp = true;
613 else
614 priv->rtllib->bSupportRemoteWakeUp = false;
615
616 RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan);
617 RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan);
618 RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n");
619 }
620
621 void rtl92e_get_eeprom_size(struct net_device *dev)
622 {
623 u16 curCR;
624 struct r8192_priv *priv = rtllib_priv(dev);
625
626 RT_TRACE(COMP_INIT, "===========>%s()\n", __func__);
627 curCR = rtl92e_readl(dev, EPROM_CMD);
628 RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD,
629 curCR);
630 priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
631 EEPROM_93C46;
632 RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__,
633 priv->epromtype);
634 _rtl92e_read_eeprom_info(dev);
635 }
636
637 static void _rtl92e_hwconfig(struct net_device *dev)
638 {
639 u32 regRATR = 0, regRRSR = 0;
640 u8 regBwOpMode = 0, regTmp = 0;
641 struct r8192_priv *priv = rtllib_priv(dev);
642
643 switch (priv->rtllib->mode) {
644 case WIRELESS_MODE_B:
645 regBwOpMode = BW_OPMODE_20MHZ;
646 regRATR = RATE_ALL_CCK;
647 regRRSR = RATE_ALL_CCK;
648 break;
649 case WIRELESS_MODE_A:
650 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
651 regRATR = RATE_ALL_OFDM_AG;
652 regRRSR = RATE_ALL_OFDM_AG;
653 break;
654 case WIRELESS_MODE_G:
655 regBwOpMode = BW_OPMODE_20MHZ;
656 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
657 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
658 break;
659 case WIRELESS_MODE_AUTO:
660 case WIRELESS_MODE_N_24G:
661 regBwOpMode = BW_OPMODE_20MHZ;
662 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
663 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
664 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
665 break;
666 case WIRELESS_MODE_N_5G:
667 regBwOpMode = BW_OPMODE_5G;
668 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
669 RATE_ALL_OFDM_2SS;
670 regRRSR = RATE_ALL_OFDM_AG;
671 break;
672 default:
673 regBwOpMode = BW_OPMODE_20MHZ;
674 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
675 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
676 break;
677 }
678
679 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
680 {
681 u32 ratr_value;
682
683 ratr_value = regRATR;
684 if (priv->rf_type == RF_1T2R)
685 ratr_value &= ~(RATE_ALL_OFDM_2SS);
686 rtl92e_writel(dev, RATR0, ratr_value);
687 rtl92e_writeb(dev, UFWP, 1);
688 }
689 regTmp = rtl92e_readb(dev, 0x313);
690 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
691 rtl92e_writel(dev, RRSR, regRRSR);
692
693 rtl92e_writew(dev, RETRY_LIMIT,
694 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
695 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
696 }
697
698 bool rtl92e_start_adapter(struct net_device *dev)
699 {
700 struct r8192_priv *priv = rtllib_priv(dev);
701 u32 ulRegRead;
702 bool rtStatus = true;
703 u8 tmpvalue;
704 u8 ICVersion, SwitchingRegulatorOutput;
705 bool bfirmwareok = true;
706 u32 tmpRegA, tmpRegC, TempCCk;
707 int i = 0;
708 u32 retry_times = 0;
709
710 RT_TRACE(COMP_INIT, "====>%s()\n", __func__);
711 priv->being_init_adapter = true;
712
713 start:
714 rtl92e_reset_desc_ring(dev);
715 priv->Rf_Mode = RF_OP_By_SW_3wire;
716 if (priv->ResetProgress == RESET_TYPE_NORESET) {
717 rtl92e_writeb(dev, ANAPAR, 0x37);
718 mdelay(500);
719 }
720 priv->pFirmware->status = FW_STATUS_0_INIT;
721
722 if (priv->RegRfOff)
723 priv->rtllib->eRFPowerState = eRfOff;
724
725 ulRegRead = rtl92e_readl(dev, CPU_GEN);
726 if (priv->pFirmware->status == FW_STATUS_0_INIT)
727 ulRegRead |= CPU_GEN_SYSTEM_RESET;
728 else if (priv->pFirmware->status == FW_STATUS_5_READY)
729 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
730 else
731 netdev_err(dev, "%s(): undefined firmware state: %d.\n",
732 __func__, priv->pFirmware->status);
733
734 rtl92e_writel(dev, CPU_GEN, ulRegRead);
735
736 ICVersion = rtl92e_readb(dev, IC_VERRSION);
737 if (ICVersion >= 0x4) {
738 SwitchingRegulatorOutput = rtl92e_readb(dev, SWREGULATOR);
739 if (SwitchingRegulatorOutput != 0xb8) {
740 rtl92e_writeb(dev, SWREGULATOR, 0xa8);
741 mdelay(1);
742 rtl92e_writeb(dev, SWREGULATOR, 0xb8);
743 }
744 }
745 RT_TRACE(COMP_INIT, "BB Config Start!\n");
746 rtStatus = rtl92e_config_bb(dev);
747 if (!rtStatus) {
748 netdev_warn(dev, "%s(): Failed to configure BB\n", __func__);
749 return rtStatus;
750 }
751 RT_TRACE(COMP_INIT, "BB Config Finished!\n");
752
753 priv->LoopbackMode = RTL819X_NO_LOOPBACK;
754 if (priv->ResetProgress == RESET_TYPE_NORESET) {
755 ulRegRead = rtl92e_readl(dev, CPU_GEN);
756 if (priv->LoopbackMode == RTL819X_NO_LOOPBACK)
757 ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
758 CPU_GEN_NO_LOOPBACK_SET);
759 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK)
760 ulRegRead |= CPU_CCK_LOOPBACK;
761 else
762 netdev_err(dev, "%s: Invalid loopback mode setting.\n",
763 __func__);
764
765 rtl92e_writel(dev, CPU_GEN, ulRegRead);
766
767 udelay(500);
768 }
769 _rtl92e_hwconfig(dev);
770 rtl92e_writeb(dev, CMDR, CR_RE | CR_TE);
771
772 rtl92e_writeb(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
773 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT)));
774 rtl92e_writel(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
775 rtl92e_writew(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
776 rtl92e_writel(dev, RCR, priv->ReceiveConfig);
777
778 rtl92e_writel(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK <<
779 RSVD_FW_QUEUE_PAGE_BK_SHIFT |
780 NUM_OF_PAGE_IN_FW_QUEUE_BE <<
781 RSVD_FW_QUEUE_PAGE_BE_SHIFT |
782 NUM_OF_PAGE_IN_FW_QUEUE_VI <<
783 RSVD_FW_QUEUE_PAGE_VI_SHIFT |
784 NUM_OF_PAGE_IN_FW_QUEUE_VO <<
785 RSVD_FW_QUEUE_PAGE_VO_SHIFT);
786 rtl92e_writel(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
787 RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
788 rtl92e_writel(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
789 NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
790 RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
791 NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
792 RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
793
794 rtl92e_tx_enable(dev);
795 rtl92e_rx_enable(dev);
796 ulRegRead = (0xFFF00000 & rtl92e_readl(dev, RRSR)) |
797 RATE_ALL_OFDM_AG | RATE_ALL_CCK;
798 rtl92e_writel(dev, RRSR, ulRegRead);
799 rtl92e_writel(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
800
801 rtl92e_writeb(dev, ACK_TIMEOUT, 0x30);
802
803 if (priv->ResetProgress == RESET_TYPE_NORESET)
804 rtl92e_set_wireless_mode(dev, priv->rtllib->mode);
805 rtl92e_cam_reset(dev);
806 {
807 u8 SECR_value = 0x0;
808
809 SECR_value |= SCR_TxEncEnable;
810 SECR_value |= SCR_RxDecEnable;
811 SECR_value |= SCR_NoSKMC;
812 rtl92e_writeb(dev, SECR, SECR_value);
813 }
814 rtl92e_writew(dev, ATIMWND, 2);
815 rtl92e_writew(dev, BCN_INTERVAL, 100);
816 {
817 int i;
818
819 for (i = 0; i < QOS_QUEUE_NUM; i++)
820 rtl92e_writel(dev, WDCAPARA_ADD[i], 0x005e4332);
821 }
822 rtl92e_writeb(dev, 0xbe, 0xc0);
823
824 rtl92e_config_mac(dev);
825
826 if (priv->card_8192_version > (u8) VERSION_8190_BD) {
827 rtl92e_get_tx_power(dev);
828 rtl92e_set_tx_power(dev, priv->chan);
829 }
830
831 tmpvalue = rtl92e_readb(dev, IC_VERRSION);
832 priv->IC_Cut = tmpvalue;
833 RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut);
834 if (priv->IC_Cut >= IC_VersionCut_D) {
835 if (priv->IC_Cut == IC_VersionCut_D) {
836 /* no matter what checkpatch says, braces are needed */
837 RT_TRACE(COMP_INIT, "D-cut\n");
838 } else if (priv->IC_Cut == IC_VersionCut_E) {
839 RT_TRACE(COMP_INIT, "E-cut\n");
840 }
841 } else {
842 RT_TRACE(COMP_INIT, "Before C-cut\n");
843 }
844
845 RT_TRACE(COMP_INIT, "Load Firmware!\n");
846 bfirmwareok = rtl92e_init_fw(dev);
847 if (!bfirmwareok) {
848 if (retry_times < 10) {
849 retry_times++;
850 goto start;
851 } else {
852 rtStatus = false;
853 goto end;
854 }
855 }
856 RT_TRACE(COMP_INIT, "Load Firmware finished!\n");
857 if (priv->ResetProgress == RESET_TYPE_NORESET) {
858 RT_TRACE(COMP_INIT, "RF Config Started!\n");
859 rtStatus = rtl92e_config_phy(dev);
860 if (!rtStatus) {
861 netdev_info(dev, "RF Config failed\n");
862 return rtStatus;
863 }
864 RT_TRACE(COMP_INIT, "RF Config Finished!\n");
865 }
866
867 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
868 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
869
870 rtl92e_writeb(dev, 0x87, 0x0);
871
872 if (priv->RegRfOff) {
873 RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER),
874 "%s(): Turn off RF for RegRfOff ----------\n",
875 __func__);
876 rtl92e_set_rf_state(dev, eRfOff, RF_CHANGE_BY_SW);
877 } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) {
878 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
879 "%s(): Turn off RF for RfOffReason(%d) ----------\n",
880 __func__, priv->rtllib->RfOffReason);
881 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason);
882 } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) {
883 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
884 "%s(): Turn off RF for RfOffReason(%d) ----------\n",
885 __func__, priv->rtllib->RfOffReason);
886 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason);
887 } else {
888 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n",
889 __func__);
890 priv->rtllib->eRFPowerState = eRfOn;
891 priv->rtllib->RfOffReason = 0;
892 }
893
894 if (priv->rtllib->FwRWRF)
895 priv->Rf_Mode = RF_OP_By_FW;
896 else
897 priv->Rf_Mode = RF_OP_By_SW_3wire;
898
899 if (priv->ResetProgress == RESET_TYPE_NORESET) {
900 rtl92e_dm_init_txpower_tracking(dev);
901
902 if (priv->IC_Cut >= IC_VersionCut_D) {
903 tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance,
904 bMaskDWord);
905 tmpRegC = rtl92e_get_bb_reg(dev, rOFDM0_XCTxIQImbalance,
906 bMaskDWord);
907 for (i = 0; i < TxBBGainTableLength; i++) {
908 if (tmpRegA == dm_tx_bb_gain[i]) {
909 priv->rfa_txpowertrackingindex = (u8)i;
910 priv->rfa_txpowertrackingindex_real =
911 (u8)i;
912 priv->rfa_txpowertracking_default =
913 priv->rfa_txpowertrackingindex;
914 break;
915 }
916 }
917
918 TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1,
919 bMaskByte2);
920
921 for (i = 0; i < CCKTxBBGainTableLength; i++) {
922 if (TempCCk == dm_cck_tx_bb_gain[i][0]) {
923 priv->CCKPresentAttentuation_20Mdefault = (u8)i;
924 break;
925 }
926 }
927 priv->CCKPresentAttentuation_40Mdefault = 0;
928 priv->CCKPresentAttentuation_difference = 0;
929 priv->CCKPresentAttentuation =
930 priv->CCKPresentAttentuation_20Mdefault;
931 RT_TRACE(COMP_POWER_TRACKING,
932 "priv->rfa_txpowertrackingindex_initial = %d\n",
933 priv->rfa_txpowertrackingindex);
934 RT_TRACE(COMP_POWER_TRACKING,
935 "priv->rfa_txpowertrackingindex_real__initial = %d\n",
936 priv->rfa_txpowertrackingindex_real);
937 RT_TRACE(COMP_POWER_TRACKING,
938 "priv->CCKPresentAttentuation_difference_initial = %d\n",
939 priv->CCKPresentAttentuation_difference);
940 RT_TRACE(COMP_POWER_TRACKING,
941 "priv->CCKPresentAttentuation_initial = %d\n",
942 priv->CCKPresentAttentuation);
943 priv->btxpower_tracking = false;
944 }
945 }
946 rtl92e_irq_enable(dev);
947 end:
948 priv->being_init_adapter = false;
949 return rtStatus;
950 }
951
952 static void _rtl92e_net_update(struct net_device *dev)
953 {
954
955 struct r8192_priv *priv = rtllib_priv(dev);
956 struct rtllib_network *net;
957 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
958 u16 rate_config = 0;
959
960 net = &priv->rtllib->current_network;
961 rtl92e_config_rate(dev, &rate_config);
962 priv->dot11CurrentPreambleMode = PREAMBLE_AUTO;
963 priv->basic_rate = rate_config &= 0x15f;
964 rtl92e_writel(dev, BSSIDR, ((u32 *)net->bssid)[0]);
965 rtl92e_writew(dev, BSSIDR+4, ((u16 *)net->bssid)[2]);
966
967 if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
968 rtl92e_writew(dev, ATIMWND, 2);
969 rtl92e_writew(dev, BCN_DMATIME, 256);
970 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
971 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
972 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
973
974 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
975 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
976
977 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
978 }
979 }
980
981 void rtl92e_link_change(struct net_device *dev)
982 {
983 struct r8192_priv *priv = rtllib_priv(dev);
984 struct rtllib_device *ieee = priv->rtllib;
985
986 if (!priv->up)
987 return;
988
989 if (ieee->state == RTLLIB_LINKED) {
990 _rtl92e_net_update(dev);
991 priv->ops->update_ratr_table(dev);
992 if ((ieee->pairwise_key_type == KEY_TYPE_WEP40) ||
993 (ieee->pairwise_key_type == KEY_TYPE_WEP104))
994 rtl92e_enable_hw_security_config(dev);
995 } else {
996 rtl92e_writeb(dev, 0x173, 0);
997 }
998 _rtl92e_update_msr(dev);
999
1000 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
1001 u32 reg;
1002
1003 reg = rtl92e_readl(dev, RCR);
1004 if (priv->rtllib->state == RTLLIB_LINKED) {
1005 if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn)
1006 ;
1007 else
1008 priv->ReceiveConfig = reg |= RCR_CBSSID;
1009 } else
1010 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
1011
1012 rtl92e_writel(dev, RCR, reg);
1013 }
1014 }
1015
1016 void rtl92e_set_monitor_mode(struct net_device *dev, bool bAllowAllDA,
1017 bool WriteIntoReg)
1018 {
1019 struct r8192_priv *priv = rtllib_priv(dev);
1020
1021 if (bAllowAllDA)
1022 priv->ReceiveConfig |= RCR_AAP;
1023 else
1024 priv->ReceiveConfig &= ~RCR_AAP;
1025
1026 if (WriteIntoReg)
1027 rtl92e_writel(dev, RCR, priv->ReceiveConfig);
1028 }
1029
1030 static u8 _rtl92e_rate_mgn_to_hw(u8 rate)
1031 {
1032 u8 ret = DESC90_RATE1M;
1033
1034 switch (rate) {
1035 case MGN_1M:
1036 ret = DESC90_RATE1M;
1037 break;
1038 case MGN_2M:
1039 ret = DESC90_RATE2M;
1040 break;
1041 case MGN_5_5M:
1042 ret = DESC90_RATE5_5M;
1043 break;
1044 case MGN_11M:
1045 ret = DESC90_RATE11M;
1046 break;
1047 case MGN_6M:
1048 ret = DESC90_RATE6M;
1049 break;
1050 case MGN_9M:
1051 ret = DESC90_RATE9M;
1052 break;
1053 case MGN_12M:
1054 ret = DESC90_RATE12M;
1055 break;
1056 case MGN_18M:
1057 ret = DESC90_RATE18M;
1058 break;
1059 case MGN_24M:
1060 ret = DESC90_RATE24M;
1061 break;
1062 case MGN_36M:
1063 ret = DESC90_RATE36M;
1064 break;
1065 case MGN_48M:
1066 ret = DESC90_RATE48M;
1067 break;
1068 case MGN_54M:
1069 ret = DESC90_RATE54M;
1070 break;
1071 case MGN_MCS0:
1072 ret = DESC90_RATEMCS0;
1073 break;
1074 case MGN_MCS1:
1075 ret = DESC90_RATEMCS1;
1076 break;
1077 case MGN_MCS2:
1078 ret = DESC90_RATEMCS2;
1079 break;
1080 case MGN_MCS3:
1081 ret = DESC90_RATEMCS3;
1082 break;
1083 case MGN_MCS4:
1084 ret = DESC90_RATEMCS4;
1085 break;
1086 case MGN_MCS5:
1087 ret = DESC90_RATEMCS5;
1088 break;
1089 case MGN_MCS6:
1090 ret = DESC90_RATEMCS6;
1091 break;
1092 case MGN_MCS7:
1093 ret = DESC90_RATEMCS7;
1094 break;
1095 case MGN_MCS8:
1096 ret = DESC90_RATEMCS8;
1097 break;
1098 case MGN_MCS9:
1099 ret = DESC90_RATEMCS9;
1100 break;
1101 case MGN_MCS10:
1102 ret = DESC90_RATEMCS10;
1103 break;
1104 case MGN_MCS11:
1105 ret = DESC90_RATEMCS11;
1106 break;
1107 case MGN_MCS12:
1108 ret = DESC90_RATEMCS12;
1109 break;
1110 case MGN_MCS13:
1111 ret = DESC90_RATEMCS13;
1112 break;
1113 case MGN_MCS14:
1114 ret = DESC90_RATEMCS14;
1115 break;
1116 case MGN_MCS15:
1117 ret = DESC90_RATEMCS15;
1118 break;
1119 case (0x80|0x20):
1120 ret = DESC90_RATEMCS32;
1121 break;
1122 default:
1123 break;
1124 }
1125 return ret;
1126 }
1127
1128 static u8 _rtl92e_hw_queue_to_fw_queue(struct net_device *dev, u8 QueueID,
1129 u8 priority)
1130 {
1131 u8 QueueSelect = 0x0;
1132
1133 switch (QueueID) {
1134 case BE_QUEUE:
1135 QueueSelect = QSLT_BE;
1136 break;
1137
1138 case BK_QUEUE:
1139 QueueSelect = QSLT_BK;
1140 break;
1141
1142 case VO_QUEUE:
1143 QueueSelect = QSLT_VO;
1144 break;
1145
1146 case VI_QUEUE:
1147 QueueSelect = QSLT_VI;
1148 break;
1149 case MGNT_QUEUE:
1150 QueueSelect = QSLT_MGNT;
1151 break;
1152 case BEACON_QUEUE:
1153 QueueSelect = QSLT_BEACON;
1154 break;
1155 case TXCMD_QUEUE:
1156 QueueSelect = QSLT_CMD;
1157 break;
1158 case HIGH_QUEUE:
1159 QueueSelect = QSLT_HIGH;
1160 break;
1161 default:
1162 netdev_warn(dev, "%s(): Impossible Queue Selection: %d\n",
1163 __func__, QueueID);
1164 break;
1165 }
1166 return QueueSelect;
1167 }
1168
1169 static u8 _rtl92e_query_is_short(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
1170 {
1171 u8 tmp_Short;
1172
1173 tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
1174 ((tcb_desc->bUseShortPreamble) ? 1 : 0);
1175 if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
1176 tmp_Short = 0;
1177
1178 return tmp_Short;
1179 }
1180
1181 void rtl92e_fill_tx_desc(struct net_device *dev, struct tx_desc *pdesc,
1182 struct cb_desc *cb_desc, struct sk_buff *skb)
1183 {
1184 struct r8192_priv *priv = rtllib_priv(dev);
1185 dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1186 PCI_DMA_TODEVICE);
1187 struct tx_fwinfo_8190pci *pTxFwInfo;
1188
1189 pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
1190 memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
1191 pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
1192 pTxFwInfo->TxRate = _rtl92e_rate_mgn_to_hw((u8)cb_desc->data_rate);
1193 pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
1194 pTxFwInfo->Short = _rtl92e_query_is_short(pTxFwInfo->TxHT,
1195 pTxFwInfo->TxRate, cb_desc);
1196
1197 if (pci_dma_mapping_error(priv->pdev, mapping))
1198 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1199 if (cb_desc->bAMPDUEnable) {
1200 pTxFwInfo->AllowAggregation = 1;
1201 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
1202 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
1203 } else {
1204 pTxFwInfo->AllowAggregation = 0;
1205 pTxFwInfo->RxMF = 0;
1206 pTxFwInfo->RxAMD = 0;
1207 }
1208
1209 pTxFwInfo->RtsEnable = (cb_desc->bRTSEnable) ? 1 : 0;
1210 pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
1211 pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
1212 pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0;
1213 pTxFwInfo->RtsRate = _rtl92e_rate_mgn_to_hw((u8)cb_desc->rts_rate);
1214 pTxFwInfo->RtsBandwidth = 0;
1215 pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
1216 pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
1217 (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
1218 (cb_desc->bRTSUseShortGI ? 1 : 0);
1219 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1220 if (cb_desc->bPacketBW) {
1221 pTxFwInfo->TxBandwidth = 1;
1222 pTxFwInfo->TxSubCarrier = 0;
1223 } else {
1224 pTxFwInfo->TxBandwidth = 0;
1225 pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
1226 }
1227 } else {
1228 pTxFwInfo->TxBandwidth = 0;
1229 pTxFwInfo->TxSubCarrier = 0;
1230 }
1231
1232 memset((u8 *)pdesc, 0, 12);
1233 pdesc->LINIP = 0;
1234 pdesc->CmdInit = 1;
1235 pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1236 pdesc->PktSize = (u16)skb->len-sizeof(struct tx_fwinfo_8190pci);
1237
1238 pdesc->SecCAMID = 0;
1239 pdesc->RATid = cb_desc->RATRIndex;
1240
1241
1242 pdesc->NoEnc = 1;
1243 pdesc->SecType = 0x0;
1244 if (cb_desc->bHwSec) {
1245 static u8 tmp;
1246
1247 if (!tmp) {
1248 RT_TRACE(COMP_DBG, "==>================hw sec\n");
1249 tmp = 1;
1250 }
1251 switch (priv->rtllib->pairwise_key_type) {
1252 case KEY_TYPE_WEP40:
1253 case KEY_TYPE_WEP104:
1254 pdesc->SecType = 0x1;
1255 pdesc->NoEnc = 0;
1256 break;
1257 case KEY_TYPE_TKIP:
1258 pdesc->SecType = 0x2;
1259 pdesc->NoEnc = 0;
1260 break;
1261 case KEY_TYPE_CCMP:
1262 pdesc->SecType = 0x3;
1263 pdesc->NoEnc = 0;
1264 break;
1265 case KEY_TYPE_NA:
1266 pdesc->SecType = 0x0;
1267 pdesc->NoEnc = 1;
1268 break;
1269 }
1270 }
1271
1272 pdesc->PktId = 0x0;
1273
1274 pdesc->QueueSelect = _rtl92e_hw_queue_to_fw_queue(dev,
1275 cb_desc->queue_index,
1276 cb_desc->priority);
1277 pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1278
1279 pdesc->DISFB = cb_desc->bTxDisableRateFallBack;
1280 pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate;
1281
1282 pdesc->FirstSeg = 1;
1283 pdesc->LastSeg = 1;
1284 pdesc->TxBufferSize = skb->len;
1285
1286 pdesc->TxBuffAddr = mapping;
1287 }
1288
1289 void rtl92e_fill_tx_cmd_desc(struct net_device *dev, struct tx_desc_cmd *entry,
1290 struct cb_desc *cb_desc, struct sk_buff *skb)
1291 {
1292 struct r8192_priv *priv = rtllib_priv(dev);
1293 dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1294 PCI_DMA_TODEVICE);
1295
1296 if (pci_dma_mapping_error(priv->pdev, mapping))
1297 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1298 memset(entry, 0, 12);
1299 entry->LINIP = cb_desc->bLastIniPkt;
1300 entry->FirstSeg = 1;
1301 entry->LastSeg = 1;
1302 if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1303 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1304 } else {
1305 struct tx_desc *entry_tmp = (struct tx_desc *)entry;
1306
1307 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1308 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1309 entry_tmp->PktSize = (u16)(cb_desc->pkt_size +
1310 entry_tmp->Offset);
1311 entry_tmp->QueueSelect = QSLT_CMD;
1312 entry_tmp->TxFWInfoSize = 0x08;
1313 entry_tmp->RATid = (u8)DESC_PACKET_TYPE_INIT;
1314 }
1315 entry->TxBufferSize = skb->len;
1316 entry->TxBuffAddr = mapping;
1317 entry->OWN = 1;
1318 }
1319
1320 static u8 _rtl92e_rate_hw_to_mgn(bool bIsHT, u8 rate)
1321 {
1322 u8 ret_rate = 0x02;
1323
1324 if (!bIsHT) {
1325 switch (rate) {
1326 case DESC90_RATE1M:
1327 ret_rate = MGN_1M;
1328 break;
1329 case DESC90_RATE2M:
1330 ret_rate = MGN_2M;
1331 break;
1332 case DESC90_RATE5_5M:
1333 ret_rate = MGN_5_5M;
1334 break;
1335 case DESC90_RATE11M:
1336 ret_rate = MGN_11M;
1337 break;
1338 case DESC90_RATE6M:
1339 ret_rate = MGN_6M;
1340 break;
1341 case DESC90_RATE9M:
1342 ret_rate = MGN_9M;
1343 break;
1344 case DESC90_RATE12M:
1345 ret_rate = MGN_12M;
1346 break;
1347 case DESC90_RATE18M:
1348 ret_rate = MGN_18M;
1349 break;
1350 case DESC90_RATE24M:
1351 ret_rate = MGN_24M;
1352 break;
1353 case DESC90_RATE36M:
1354 ret_rate = MGN_36M;
1355 break;
1356 case DESC90_RATE48M:
1357 ret_rate = MGN_48M;
1358 break;
1359 case DESC90_RATE54M:
1360 ret_rate = MGN_54M;
1361 break;
1362
1363 default:
1364 RT_TRACE(COMP_RECV,
1365 "_rtl92e_rate_hw_to_mgn(): Non supportedRate [%x], bIsHT = %d!!!\n",
1366 rate, bIsHT);
1367 break;
1368 }
1369
1370 } else {
1371 switch (rate) {
1372 case DESC90_RATEMCS0:
1373 ret_rate = MGN_MCS0;
1374 break;
1375 case DESC90_RATEMCS1:
1376 ret_rate = MGN_MCS1;
1377 break;
1378 case DESC90_RATEMCS2:
1379 ret_rate = MGN_MCS2;
1380 break;
1381 case DESC90_RATEMCS3:
1382 ret_rate = MGN_MCS3;
1383 break;
1384 case DESC90_RATEMCS4:
1385 ret_rate = MGN_MCS4;
1386 break;
1387 case DESC90_RATEMCS5:
1388 ret_rate = MGN_MCS5;
1389 break;
1390 case DESC90_RATEMCS6:
1391 ret_rate = MGN_MCS6;
1392 break;
1393 case DESC90_RATEMCS7:
1394 ret_rate = MGN_MCS7;
1395 break;
1396 case DESC90_RATEMCS8:
1397 ret_rate = MGN_MCS8;
1398 break;
1399 case DESC90_RATEMCS9:
1400 ret_rate = MGN_MCS9;
1401 break;
1402 case DESC90_RATEMCS10:
1403 ret_rate = MGN_MCS10;
1404 break;
1405 case DESC90_RATEMCS11:
1406 ret_rate = MGN_MCS11;
1407 break;
1408 case DESC90_RATEMCS12:
1409 ret_rate = MGN_MCS12;
1410 break;
1411 case DESC90_RATEMCS13:
1412 ret_rate = MGN_MCS13;
1413 break;
1414 case DESC90_RATEMCS14:
1415 ret_rate = MGN_MCS14;
1416 break;
1417 case DESC90_RATEMCS15:
1418 ret_rate = MGN_MCS15;
1419 break;
1420 case DESC90_RATEMCS32:
1421 ret_rate = (0x80|0x20);
1422 break;
1423
1424 default:
1425 RT_TRACE(COMP_RECV,
1426 "_rtl92e_rate_hw_to_mgn(): Non supported Rate [%x], bIsHT = %d!!!\n",
1427 rate, bIsHT);
1428 break;
1429 }
1430 }
1431
1432 return ret_rate;
1433 }
1434
1435 static long _rtl92e_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1436 {
1437 long retsig;
1438
1439 if (currsig >= 61 && currsig <= 100)
1440 retsig = 90 + ((currsig - 60) / 4);
1441 else if (currsig >= 41 && currsig <= 60)
1442 retsig = 78 + ((currsig - 40) / 2);
1443 else if (currsig >= 31 && currsig <= 40)
1444 retsig = 66 + (currsig - 30);
1445 else if (currsig >= 21 && currsig <= 30)
1446 retsig = 54 + (currsig - 20);
1447 else if (currsig >= 5 && currsig <= 20)
1448 retsig = 42 + (((currsig - 5) * 2) / 3);
1449 else if (currsig == 4)
1450 retsig = 36;
1451 else if (currsig == 3)
1452 retsig = 27;
1453 else if (currsig == 2)
1454 retsig = 18;
1455 else if (currsig == 1)
1456 retsig = 9;
1457 else
1458 retsig = currsig;
1459
1460 return retsig;
1461 }
1462
1463
1464 #define rx_hal_is_cck_rate(_pdrvinfo)\
1465 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1466 _pdrvinfo->RxRate == DESC90_RATE2M ||\
1467 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1468 _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1469 !_pdrvinfo->RxHT)
1470
1471 static void _rtl92e_query_rxphystatus(
1472 struct r8192_priv *priv,
1473 struct rtllib_rx_stats *pstats,
1474 struct rx_desc *pdesc,
1475 struct rx_fwinfo *pdrvinfo,
1476 struct rtllib_rx_stats *precord_stats,
1477 bool bpacket_match_bssid,
1478 bool bpacket_toself,
1479 bool bPacketBeacon,
1480 bool bToSelfBA
1481 )
1482 {
1483 struct phy_sts_ofdm_819xpci *pofdm_buf;
1484 struct phy_sts_cck_819xpci *pcck_buf;
1485 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc;
1486 u8 *prxpkt;
1487 u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
1488 s8 rx_pwr[4], rx_pwr_all = 0;
1489 s8 rx_snrX, rx_evmX;
1490 u8 evm, pwdb_all;
1491 u32 RSSI, total_rssi = 0;
1492 u8 is_cck_rate = 0;
1493 u8 rf_rx_num = 0;
1494 static u8 check_reg824;
1495 static u32 reg824_bit9;
1496
1497 priv->stats.numqry_phystatus++;
1498
1499 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1500 memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1501 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1502 bpacket_match_bssid;
1503 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1504 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1505 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1506 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1507 if (check_reg824 == 0) {
1508 reg824_bit9 = rtl92e_get_bb_reg(priv->rtllib->dev,
1509 rFPGA0_XA_HSSIParameter2,
1510 0x200);
1511 check_reg824 = 1;
1512 }
1513
1514
1515 prxpkt = (u8 *)pdrvinfo;
1516
1517 prxpkt += sizeof(struct rx_fwinfo);
1518
1519 pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1520 pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1521
1522 pstats->RxMIMOSignalQuality[0] = -1;
1523 pstats->RxMIMOSignalQuality[1] = -1;
1524 precord_stats->RxMIMOSignalQuality[0] = -1;
1525 precord_stats->RxMIMOSignalQuality[1] = -1;
1526
1527 if (is_cck_rate) {
1528 u8 report;
1529
1530 priv->stats.numqry_phystatusCCK++;
1531 if (!reg824_bit9) {
1532 report = pcck_buf->cck_agc_rpt & 0xc0;
1533 report >>= 6;
1534 switch (report) {
1535 case 0x3:
1536 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1537 0x3e);
1538 break;
1539 case 0x2:
1540 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1541 0x3e);
1542 break;
1543 case 0x1:
1544 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1545 0x3e);
1546 break;
1547 case 0x0:
1548 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1549 break;
1550 }
1551 } else {
1552 report = pcck_buf->cck_agc_rpt & 0x60;
1553 report >>= 5;
1554 switch (report) {
1555 case 0x3:
1556 rx_pwr_all = -35 -
1557 ((pcck_buf->cck_agc_rpt &
1558 0x1f) << 1);
1559 break;
1560 case 0x2:
1561 rx_pwr_all = -23 -
1562 ((pcck_buf->cck_agc_rpt &
1563 0x1f) << 1);
1564 break;
1565 case 0x1:
1566 rx_pwr_all = -11 -
1567 ((pcck_buf->cck_agc_rpt &
1568 0x1f) << 1);
1569 break;
1570 case 0x0:
1571 rx_pwr_all = -8 -
1572 ((pcck_buf->cck_agc_rpt &
1573 0x1f) << 1);
1574 break;
1575 }
1576 }
1577
1578 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1579 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1580 pstats->RecvSignalPower = rx_pwr_all;
1581
1582 if (bpacket_match_bssid) {
1583 u8 sq;
1584
1585 if (pstats->RxPWDBAll > 40) {
1586 sq = 100;
1587 } else {
1588 sq = pcck_buf->sq_rpt;
1589
1590 if (pcck_buf->sq_rpt > 64)
1591 sq = 0;
1592 else if (pcck_buf->sq_rpt < 20)
1593 sq = 100;
1594 else
1595 sq = ((64-sq) * 100) / 44;
1596 }
1597 pstats->SignalQuality = sq;
1598 precord_stats->SignalQuality = sq;
1599 pstats->RxMIMOSignalQuality[0] = sq;
1600 precord_stats->RxMIMOSignalQuality[0] = sq;
1601 pstats->RxMIMOSignalQuality[1] = -1;
1602 precord_stats->RxMIMOSignalQuality[1] = -1;
1603 }
1604 } else {
1605 priv->stats.numqry_phystatusHT++;
1606 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1607 if (priv->brfpath_rxenable[i])
1608 rf_rx_num++;
1609
1610 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1611 2) - 110;
1612
1613 tmp_rxsnr = pofdm_buf->rxsnr_X[i];
1614 rx_snrX = (s8)(tmp_rxsnr);
1615 rx_snrX /= 2;
1616 priv->stats.rxSNRdB[i] = (long)rx_snrX;
1617
1618 RSSI = rtl92e_rx_db_to_percent(rx_pwr[i]);
1619 if (priv->brfpath_rxenable[i])
1620 total_rssi += RSSI;
1621
1622 if (bpacket_match_bssid) {
1623 pstats->RxMIMOSignalStrength[i] = (u8) RSSI;
1624 precord_stats->RxMIMOSignalStrength[i] =
1625 (u8) RSSI;
1626 }
1627 }
1628
1629
1630 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1631 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1632
1633 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1634 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
1635 pstats->RecvSignalPower = rx_pwr_all;
1636 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1637 pdrvinfo->RxRate <= DESC90_RATEMCS15)
1638 max_spatial_stream = 2;
1639 else
1640 max_spatial_stream = 1;
1641
1642 for (i = 0; i < max_spatial_stream; i++) {
1643 tmp_rxevm = pofdm_buf->rxevm_X[i];
1644 rx_evmX = (s8)(tmp_rxevm);
1645
1646 rx_evmX /= 2;
1647
1648 evm = rtl92e_evm_db_to_percent(rx_evmX);
1649 if (bpacket_match_bssid) {
1650 if (i == 0) {
1651 pstats->SignalQuality = evm & 0xff;
1652 precord_stats->SignalQuality = evm & 0xff;
1653 }
1654 pstats->RxMIMOSignalQuality[i] = evm & 0xff;
1655 precord_stats->RxMIMOSignalQuality[i] = evm & 0xff;
1656 }
1657 }
1658
1659
1660 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
1661 prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *)
1662 &rxsc_sgien_exflg;
1663 if (pdrvinfo->BW)
1664 priv->stats.received_bwtype[1+prxsc->rxsc]++;
1665 else
1666 priv->stats.received_bwtype[0]++;
1667 }
1668
1669 if (is_cck_rate) {
1670 pstats->SignalStrength = precord_stats->SignalStrength =
1671 (u8)(_rtl92e_signal_scale_mapping(priv,
1672 (long)pwdb_all));
1673
1674 } else {
1675 if (rf_rx_num != 0)
1676 pstats->SignalStrength = precord_stats->SignalStrength =
1677 (u8)(_rtl92e_signal_scale_mapping(priv,
1678 (long)(total_rssi /= rf_rx_num)));
1679 }
1680 }
1681
1682 static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1683 struct rtllib_rx_stats *prev_st,
1684 struct rtllib_rx_stats *curr_st)
1685 {
1686 bool bcheck = false;
1687 u8 rfpath;
1688 u32 ij, tmp_val;
1689 static u32 slide_rssi_index, slide_rssi_statistics;
1690 static u32 slide_evm_index, slide_evm_statistics;
1691 static u32 last_rssi, last_evm;
1692 static u32 slide_beacon_adc_pwdb_index;
1693 static u32 slide_beacon_adc_pwdb_statistics;
1694 static u32 last_beacon_adc_pwdb;
1695 struct rtllib_hdr_3addr *hdr;
1696 u16 sc;
1697 unsigned int frag, seq;
1698
1699 hdr = (struct rtllib_hdr_3addr *)buffer;
1700 sc = le16_to_cpu(hdr->seq_ctl);
1701 frag = WLAN_GET_SEQ_FRAG(sc);
1702 seq = WLAN_GET_SEQ_SEQ(sc);
1703 curr_st->Seq_Num = seq;
1704 if (!prev_st->bIsAMPDU)
1705 bcheck = true;
1706
1707 if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1708 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1709 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1710 priv->stats.slide_rssi_total -= last_rssi;
1711 }
1712 priv->stats.slide_rssi_total += prev_st->SignalStrength;
1713
1714 priv->stats.slide_signal_strength[slide_rssi_index++] =
1715 prev_st->SignalStrength;
1716 if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1717 slide_rssi_index = 0;
1718
1719 tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
1720 priv->stats.signal_strength = rtl92e_translate_to_dbm(priv,
1721 (u8)tmp_val);
1722 curr_st->rssi = priv->stats.signal_strength;
1723 if (!prev_st->bPacketMatchBSSID) {
1724 if (!prev_st->bToSelfBA)
1725 return;
1726 }
1727
1728 if (!bcheck)
1729 return;
1730
1731 priv->stats.num_process_phyinfo++;
1732 if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1733 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
1734 if (!rtl92e_is_legal_rf_path(priv->rtllib->dev, rfpath))
1735 continue;
1736 RT_TRACE(COMP_DBG,
1737 "Jacken -> pPreviousstats->RxMIMOSignalStrength[rfpath] = %d\n",
1738 prev_st->RxMIMOSignalStrength[rfpath]);
1739 if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1740 priv->stats.rx_rssi_percentage[rfpath] =
1741 prev_st->RxMIMOSignalStrength[rfpath];
1742 }
1743 if (prev_st->RxMIMOSignalStrength[rfpath] >
1744 priv->stats.rx_rssi_percentage[rfpath]) {
1745 priv->stats.rx_rssi_percentage[rfpath] =
1746 ((priv->stats.rx_rssi_percentage[rfpath]
1747 * (RX_SMOOTH - 1)) +
1748 (prev_st->RxMIMOSignalStrength
1749 [rfpath])) / (RX_SMOOTH);
1750 priv->stats.rx_rssi_percentage[rfpath] =
1751 priv->stats.rx_rssi_percentage[rfpath]
1752 + 1;
1753 } else {
1754 priv->stats.rx_rssi_percentage[rfpath] =
1755 ((priv->stats.rx_rssi_percentage[rfpath] *
1756 (RX_SMOOTH-1)) +
1757 (prev_st->RxMIMOSignalStrength[rfpath])) /
1758 (RX_SMOOTH);
1759 }
1760 RT_TRACE(COMP_DBG,
1761 "Jacken -> priv->RxStats.RxRSSIPercentage[rfPath] = %d\n",
1762 priv->stats.rx_rssi_percentage[rfpath]);
1763 }
1764 }
1765
1766
1767 if (prev_st->bPacketBeacon) {
1768 if (slide_beacon_adc_pwdb_statistics++ >=
1769 PHY_Beacon_RSSI_SLID_WIN_MAX) {
1770 slide_beacon_adc_pwdb_statistics =
1771 PHY_Beacon_RSSI_SLID_WIN_MAX;
1772 last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb
1773 [slide_beacon_adc_pwdb_index];
1774 priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
1775 }
1776 priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll;
1777 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] =
1778 prev_st->RxPWDBAll;
1779 slide_beacon_adc_pwdb_index++;
1780 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1781 slide_beacon_adc_pwdb_index = 0;
1782 prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total /
1783 slide_beacon_adc_pwdb_statistics;
1784 if (prev_st->RxPWDBAll >= 3)
1785 prev_st->RxPWDBAll -= 3;
1786 }
1787
1788 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
1789 prev_st->bIsCCK ? "CCK" : "OFDM",
1790 prev_st->RxPWDBAll);
1791
1792 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1793 prev_st->bToSelfBA) {
1794 if (priv->undecorated_smoothed_pwdb < 0)
1795 priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1796 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1797 priv->undecorated_smoothed_pwdb =
1798 (((priv->undecorated_smoothed_pwdb) *
1799 (RX_SMOOTH-1)) +
1800 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1801 priv->undecorated_smoothed_pwdb =
1802 priv->undecorated_smoothed_pwdb + 1;
1803 } else {
1804 priv->undecorated_smoothed_pwdb =
1805 (((priv->undecorated_smoothed_pwdb) *
1806 (RX_SMOOTH-1)) +
1807 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1808 }
1809 rtl92e_update_rx_statistics(priv, prev_st);
1810 }
1811
1812 if (prev_st->SignalQuality != 0) {
1813 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1814 prev_st->bToSelfBA) {
1815 if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1816 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1817 last_evm =
1818 priv->stats.slide_evm[slide_evm_index];
1819 priv->stats.slide_evm_total -= last_evm;
1820 }
1821
1822 priv->stats.slide_evm_total += prev_st->SignalQuality;
1823
1824 priv->stats.slide_evm[slide_evm_index++] =
1825 prev_st->SignalQuality;
1826 if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1827 slide_evm_index = 0;
1828
1829 tmp_val = priv->stats.slide_evm_total /
1830 slide_evm_statistics;
1831 priv->stats.signal_quality = tmp_val;
1832 priv->stats.last_signal_strength_inpercent = tmp_val;
1833 }
1834
1835 if (prev_st->bPacketToSelf ||
1836 prev_st->bPacketBeacon ||
1837 prev_st->bToSelfBA) {
1838 for (ij = 0; ij < 2; ij++) {
1839 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1840 if (priv->stats.rx_evm_percentage[ij] == 0)
1841 priv->stats.rx_evm_percentage[ij] =
1842 prev_st->RxMIMOSignalQuality[ij];
1843 priv->stats.rx_evm_percentage[ij] =
1844 ((priv->stats.rx_evm_percentage[ij] *
1845 (RX_SMOOTH - 1)) +
1846 (prev_st->RxMIMOSignalQuality[ij])) /
1847 (RX_SMOOTH);
1848 }
1849 }
1850 }
1851 }
1852 }
1853
1854 static void _rtl92e_translate_rx_signal_stats(struct net_device *dev,
1855 struct sk_buff *skb,
1856 struct rtllib_rx_stats *pstats,
1857 struct rx_desc *pdesc,
1858 struct rx_fwinfo *pdrvinfo)
1859 {
1860 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1861 bool bpacket_match_bssid, bpacket_toself;
1862 bool bPacketBeacon = false;
1863 struct rtllib_hdr_3addr *hdr;
1864 bool bToSelfBA = false;
1865 static struct rtllib_rx_stats previous_stats;
1866 u16 fc, type;
1867 u8 *tmp_buf;
1868 u8 *praddr;
1869
1870 tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1871
1872 hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1873 fc = le16_to_cpu(hdr->frame_ctl);
1874 type = WLAN_FC_GET_TYPE(fc);
1875 praddr = hdr->addr1;
1876
1877 bpacket_match_bssid =
1878 ((type != RTLLIB_FTYPE_CTL) &&
1879 ether_addr_equal(priv->rtllib->current_network.bssid,
1880 (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1881 (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 :
1882 hdr->addr3) &&
1883 (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1884 bpacket_toself = bpacket_match_bssid && /* check this */
1885 ether_addr_equal(praddr, priv->rtllib->dev->dev_addr);
1886 if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1887 bPacketBeacon = true;
1888 if (bpacket_match_bssid)
1889 priv->stats.numpacket_matchbssid++;
1890 if (bpacket_toself)
1891 priv->stats.numpacket_toself++;
1892 _rtl92e_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1893 _rtl92e_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1894 &previous_stats, bpacket_match_bssid,
1895 bpacket_toself, bPacketBeacon, bToSelfBA);
1896 rtl92e_copy_mpdu_stats(pstats, &previous_stats);
1897 }
1898
1899 static void _rtl92e_update_received_rate_histogram_stats(
1900 struct net_device *dev,
1901 struct rtllib_rx_stats *pstats)
1902 {
1903 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1904 u32 rcvType = 1;
1905 u32 rateIndex;
1906 u32 preamble_guardinterval;
1907
1908 if (pstats->bCRC)
1909 rcvType = 2;
1910 else if (pstats->bICV)
1911 rcvType = 3;
1912
1913 if (pstats->bShortPreamble)
1914 preamble_guardinterval = 1;
1915 else
1916 preamble_guardinterval = 0;
1917
1918 switch (pstats->rate) {
1919 case MGN_1M:
1920 rateIndex = 0;
1921 break;
1922 case MGN_2M:
1923 rateIndex = 1;
1924 break;
1925 case MGN_5_5M:
1926 rateIndex = 2;
1927 break;
1928 case MGN_11M:
1929 rateIndex = 3;
1930 break;
1931 case MGN_6M:
1932 rateIndex = 4;
1933 break;
1934 case MGN_9M:
1935 rateIndex = 5;
1936 break;
1937 case MGN_12M:
1938 rateIndex = 6;
1939 break;
1940 case MGN_18M:
1941 rateIndex = 7;
1942 break;
1943 case MGN_24M:
1944 rateIndex = 8;
1945 break;
1946 case MGN_36M:
1947 rateIndex = 9;
1948 break;
1949 case MGN_48M:
1950 rateIndex = 10;
1951 break;
1952 case MGN_54M:
1953 rateIndex = 11;
1954 break;
1955 case MGN_MCS0:
1956 rateIndex = 12;
1957 break;
1958 case MGN_MCS1:
1959 rateIndex = 13;
1960 break;
1961 case MGN_MCS2:
1962 rateIndex = 14;
1963 break;
1964 case MGN_MCS3:
1965 rateIndex = 15;
1966 break;
1967 case MGN_MCS4:
1968 rateIndex = 16;
1969 break;
1970 case MGN_MCS5:
1971 rateIndex = 17;
1972 break;
1973 case MGN_MCS6:
1974 rateIndex = 18;
1975 break;
1976 case MGN_MCS7:
1977 rateIndex = 19;
1978 break;
1979 case MGN_MCS8:
1980 rateIndex = 20;
1981 break;
1982 case MGN_MCS9:
1983 rateIndex = 21;
1984 break;
1985 case MGN_MCS10:
1986 rateIndex = 22;
1987 break;
1988 case MGN_MCS11:
1989 rateIndex = 23;
1990 break;
1991 case MGN_MCS12:
1992 rateIndex = 24;
1993 break;
1994 case MGN_MCS13:
1995 rateIndex = 25;
1996 break;
1997 case MGN_MCS14:
1998 rateIndex = 26;
1999 break;
2000 case MGN_MCS15:
2001 rateIndex = 27;
2002 break;
2003 default:
2004 rateIndex = 28;
2005 break;
2006 }
2007 priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
2008 priv->stats.received_rate_histogram[0][rateIndex]++;
2009 priv->stats.received_rate_histogram[rcvType][rateIndex]++;
2010 }
2011
2012 bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats,
2013 struct rx_desc *pdesc, struct sk_buff *skb)
2014 {
2015 struct r8192_priv *priv = rtllib_priv(dev);
2016 struct rx_fwinfo *pDrvInfo = NULL;
2017
2018 stats->bICV = pdesc->ICV;
2019 stats->bCRC = pdesc->CRC32;
2020 stats->bHwError = pdesc->CRC32 | pdesc->ICV;
2021
2022 stats->Length = pdesc->Length;
2023 if (stats->Length < 24)
2024 stats->bHwError |= 1;
2025
2026 if (stats->bHwError) {
2027 stats->bShift = false;
2028
2029 if (pdesc->CRC32) {
2030 if (pdesc->Length < 500)
2031 priv->stats.rxcrcerrmin++;
2032 else if (pdesc->Length > 1000)
2033 priv->stats.rxcrcerrmax++;
2034 else
2035 priv->stats.rxcrcerrmid++;
2036 }
2037 return false;
2038 }
2039
2040 stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
2041 stats->RxBufShift = ((pdesc->Shift)&0x03);
2042 stats->Decrypted = !pdesc->SWDec;
2043
2044 pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
2045
2046 stats->rate = _rtl92e_rate_hw_to_mgn((bool)pDrvInfo->RxHT,
2047 (u8)pDrvInfo->RxRate);
2048 stats->bShortPreamble = pDrvInfo->SPLCP;
2049
2050 _rtl92e_update_received_rate_histogram_stats(dev, stats);
2051
2052 stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
2053 stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
2054 (pDrvInfo->FirstAGGR == 1);
2055
2056 stats->TimeStampLow = pDrvInfo->TSFL;
2057 stats->TimeStampHigh = rtl92e_readl(dev, TSFR+4);
2058
2059 rtl92e_update_rx_pkt_timestamp(dev, stats);
2060
2061 if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
2062 stats->bShift = 1;
2063
2064 stats->RxIs40MHzPacket = pDrvInfo->BW;
2065
2066 _rtl92e_translate_rx_signal_stats(dev, skb, stats, pdesc, pDrvInfo);
2067
2068 if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1)
2069 RT_TRACE(COMP_RXDESC,
2070 "pDrvInfo->FirstAGGR = %d, pDrvInfo->PartAggr = %d\n",
2071 pDrvInfo->FirstAGGR, pDrvInfo->PartAggr);
2072 skb_trim(skb, skb->len - 4/*sCrcLng*/);
2073
2074
2075 stats->packetlength = stats->Length-4;
2076 stats->fraglength = stats->packetlength;
2077 stats->fragoffset = 0;
2078 stats->ntotalfrag = 1;
2079 return true;
2080 }
2081
2082 void rtl92e_stop_adapter(struct net_device *dev, bool reset)
2083 {
2084 struct r8192_priv *priv = rtllib_priv(dev);
2085 int i;
2086 u8 OpMode;
2087 u8 u1bTmp;
2088 u32 ulRegRead;
2089
2090 OpMode = RT_OP_MODE_NO_LINK;
2091 priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
2092
2093 if (!priv->rtllib->bSupportRemoteWakeUp) {
2094 u1bTmp = 0x0;
2095 rtl92e_writeb(dev, CMDR, u1bTmp);
2096 }
2097
2098 mdelay(20);
2099
2100 if (!reset) {
2101 mdelay(150);
2102
2103 priv->bHwRfOffAction = 2;
2104
2105 if (!priv->rtllib->bSupportRemoteWakeUp) {
2106 rtl92e_set_rf_off(dev);
2107 ulRegRead = rtl92e_readl(dev, CPU_GEN);
2108 ulRegRead |= CPU_GEN_SYSTEM_RESET;
2109 rtl92e_writel(dev, CPU_GEN, ulRegRead);
2110 } else {
2111 rtl92e_writel(dev, WFCRC0, 0xffffffff);
2112 rtl92e_writel(dev, WFCRC1, 0xffffffff);
2113 rtl92e_writel(dev, WFCRC2, 0xffffffff);
2114
2115
2116 rtl92e_writeb(dev, PMR, 0x5);
2117 rtl92e_writeb(dev, MacBlkCtrl, 0xa);
2118 }
2119 }
2120
2121 for (i = 0; i < MAX_QUEUE_SIZE; i++)
2122 skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
2123 for (i = 0; i < MAX_QUEUE_SIZE; i++)
2124 skb_queue_purge(&priv->rtllib->skb_aggQ[i]);
2125
2126 skb_queue_purge(&priv->skb_queue);
2127 }
2128
2129 void rtl92e_update_ratr_table(struct net_device *dev)
2130 {
2131 struct r8192_priv *priv = rtllib_priv(dev);
2132 struct rtllib_device *ieee = priv->rtllib;
2133 u8 *pMcsRate = ieee->dot11HTOperationalRateSet;
2134 u32 ratr_value = 0;
2135 u16 rate_config = 0;
2136 u8 rate_index = 0;
2137
2138 rtl92e_config_rate(dev, &rate_config);
2139 ratr_value = rate_config | *pMcsRate << 12;
2140 switch (ieee->mode) {
2141 case IEEE_A:
2142 ratr_value &= 0x00000FF0;
2143 break;
2144 case IEEE_B:
2145 ratr_value &= 0x0000000F;
2146 break;
2147 case IEEE_G:
2148 case IEEE_G|IEEE_B:
2149 ratr_value &= 0x00000FF7;
2150 break;
2151 case IEEE_N_24G:
2152 case IEEE_N_5G:
2153 if (ieee->pHTInfo->PeerMimoPs == 0) {
2154 ratr_value &= 0x0007F007;
2155 } else {
2156 if (priv->rf_type == RF_1T2R)
2157 ratr_value &= 0x000FF007;
2158 else
2159 ratr_value &= 0x0F81F007;
2160 }
2161 break;
2162 default:
2163 break;
2164 }
2165 ratr_value &= 0x0FFFFFFF;
2166 if (ieee->pHTInfo->bCurTxBW40MHz &&
2167 ieee->pHTInfo->bCurShortGI40MHz)
2168 ratr_value |= 0x80000000;
2169 else if (!ieee->pHTInfo->bCurTxBW40MHz &&
2170 ieee->pHTInfo->bCurShortGI20MHz)
2171 ratr_value |= 0x80000000;
2172 rtl92e_writel(dev, RATR0+rate_index*4, ratr_value);
2173 rtl92e_writeb(dev, UFWP, 1);
2174 }
2175
2176 void
2177 rtl92e_init_variables(struct net_device *dev)
2178 {
2179 struct r8192_priv *priv = rtllib_priv(dev);
2180
2181 strcpy(priv->nick, "rtl8192E");
2182
2183 priv->rtllib->softmac_features = IEEE_SOFTMAC_SCAN |
2184 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2185 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
2186
2187 priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
2188
2189 priv->ShortRetryLimit = 0x30;
2190 priv->LongRetryLimit = 0x30;
2191
2192 priv->ReceiveConfig = RCR_ADD3 |
2193 RCR_AMF | RCR_ADF |
2194 RCR_AICV |
2195 RCR_AB | RCR_AM | RCR_APM |
2196 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
2197 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
2198
2199 priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
2200 IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
2201 IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
2202 IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
2203 IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
2204 IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
2205
2206 priv->PwrDomainProtect = false;
2207
2208 priv->bfirst_after_down = false;
2209 }
2210
2211 void rtl92e_enable_irq(struct net_device *dev)
2212 {
2213 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2214
2215 priv->irq_enabled = 1;
2216
2217 rtl92e_writel(dev, INTA_MASK, priv->irq_mask[0]);
2218
2219 }
2220
2221 void rtl92e_disable_irq(struct net_device *dev)
2222 {
2223 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2224
2225 rtl92e_writel(dev, INTA_MASK, 0);
2226
2227 priv->irq_enabled = 0;
2228 }
2229
2230 void rtl92e_clear_irq(struct net_device *dev)
2231 {
2232 u32 tmp;
2233
2234 tmp = rtl92e_readl(dev, ISR);
2235 rtl92e_writel(dev, ISR, tmp);
2236 }
2237
2238
2239 void rtl92e_enable_rx(struct net_device *dev)
2240 {
2241 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2242
2243 rtl92e_writel(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
2244 }
2245
2246 static const u32 TX_DESC_BASE[] = {
2247 BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
2248 };
2249
2250 void rtl92e_enable_tx(struct net_device *dev)
2251 {
2252 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2253 u32 i;
2254
2255 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
2256 rtl92e_writel(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
2257 }
2258
2259
2260 void rtl92e_ack_irq(struct net_device *dev, u32 *p_inta, u32 *p_intb)
2261 {
2262 *p_inta = rtl92e_readl(dev, ISR);
2263 rtl92e_writel(dev, ISR, *p_inta);
2264 }
2265
2266 bool rtl92e_is_rx_stuck(struct net_device *dev)
2267 {
2268 struct r8192_priv *priv = rtllib_priv(dev);
2269 u16 RegRxCounter = rtl92e_readw(dev, 0x130);
2270 bool bStuck = false;
2271 static u8 rx_chk_cnt;
2272 u32 SlotIndex = 0, TotalRxStuckCount = 0;
2273 u8 i;
2274 u8 SilentResetRxSoltNum = 4;
2275
2276 RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n",
2277 __func__, RegRxCounter, priv->RxCounter);
2278
2279 rx_chk_cnt++;
2280 if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) {
2281 rx_chk_cnt = 0;
2282 } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5))
2283 && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2284 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M))
2285 || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2286 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) {
2287 if (rx_chk_cnt < 2)
2288 return bStuck;
2289 rx_chk_cnt = 0;
2290 } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2291 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) ||
2292 ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2293 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) &&
2294 priv->undecorated_smoothed_pwdb >= VeryLowRSSI) {
2295 if (rx_chk_cnt < 4)
2296 return bStuck;
2297 rx_chk_cnt = 0;
2298 } else {
2299 if (rx_chk_cnt < 8)
2300 return bStuck;
2301 rx_chk_cnt = 0;
2302 }
2303
2304
2305 SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum;
2306
2307 if (priv->RxCounter == RegRxCounter) {
2308 priv->SilentResetRxStuckEvent[SlotIndex] = 1;
2309
2310 for (i = 0; i < SilentResetRxSoltNum; i++)
2311 TotalRxStuckCount += priv->SilentResetRxStuckEvent[i];
2312
2313 if (TotalRxStuckCount == SilentResetRxSoltNum) {
2314 bStuck = true;
2315 for (i = 0; i < SilentResetRxSoltNum; i++)
2316 TotalRxStuckCount +=
2317 priv->SilentResetRxStuckEvent[i];
2318 }
2319
2320
2321 } else {
2322 priv->SilentResetRxStuckEvent[SlotIndex] = 0;
2323 }
2324
2325 priv->RxCounter = RegRxCounter;
2326
2327 return bStuck;
2328 }
2329
2330 bool rtl92e_is_tx_stuck(struct net_device *dev)
2331 {
2332 struct r8192_priv *priv = rtllib_priv(dev);
2333 bool bStuck = false;
2334 u16 RegTxCounter = rtl92e_readw(dev, 0x128);
2335
2336 RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n",
2337 __func__, RegTxCounter, priv->TxCounter);
2338
2339 if (priv->TxCounter == RegTxCounter)
2340 bStuck = true;
2341
2342 priv->TxCounter = RegTxCounter;
2343
2344 return bStuck;
2345 }
2346
2347 bool rtl92e_get_nmode_support_by_sec(struct net_device *dev)
2348 {
2349 struct r8192_priv *priv = rtllib_priv(dev);
2350 struct rtllib_device *ieee = priv->rtllib;
2351
2352 if (ieee->rtllib_ap_sec_type &&
2353 (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP |
2354 SEC_ALG_TKIP))) {
2355 return false;
2356 } else {
2357 return true;
2358 }
2359 }
2360
2361 bool rtl92e_is_halfn_supported_by_ap(struct net_device *dev)
2362 {
2363 struct r8192_priv *priv = rtllib_priv(dev);
2364 struct rtllib_device *ieee = priv->rtllib;
2365
2366 return ieee->bHalfWirelessN24GMode;
2367 }
Ubuntu Artful kernel mirror