1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
9 * You should have received a copy of the GNU General Public License along with
10 * this program; if not, write to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
13 * The full GNU General Public License is included in this distribution in the
14 * file called LICENSE.
16 * Contact Information:
17 * wlanfae <wlanfae@realtek.com>
18 ******************************************************************************/
21 #include "r8192E_hw.h"
22 #include "r8192E_phyreg.h"
23 #include "r8190P_rtl8256.h"
24 #include "r8192E_phy.h"
27 #include "r8192E_hwimg.h"
29 static u32 RF_CHANNEL_TABLE_ZEBRA
[] = {
47 /*************************Define local function prototype**********************/
49 static u32
phy_FwRFSerialRead(struct net_device
*dev
,
50 enum rf90_radio_path eRFPath
,
52 static void phy_FwRFSerialWrite(struct net_device
*dev
,
53 enum rf90_radio_path eRFPath
,
54 u32 Offset
, u32 Data
);
56 static u32
rtl8192_CalculateBitShift(u32 dwBitMask
)
60 for (i
= 0; i
<= 31; i
++) {
61 if (((dwBitMask
>> i
) & 0x1) == 1)
67 u8
rtl92e_is_legal_rf_path(struct net_device
*dev
, u32 eRFPath
)
70 struct r8192_priv
*priv
= rtllib_priv(dev
);
72 if (priv
->rf_type
== RF_2T4R
)
74 else if (priv
->rf_type
== RF_1T2R
) {
75 if (eRFPath
== RF90_PATH_A
|| eRFPath
== RF90_PATH_B
)
77 else if (eRFPath
== RF90_PATH_C
|| eRFPath
== RF90_PATH_D
)
83 void rtl92e_set_bb_reg(struct net_device
*dev
, u32 dwRegAddr
, u32 dwBitMask
,
87 u32 OriginalValue
, BitShift
, NewValue
;
89 if (dwBitMask
!= bMaskDWord
) {
90 OriginalValue
= rtl92e_readl(dev
, dwRegAddr
);
91 BitShift
= rtl8192_CalculateBitShift(dwBitMask
);
92 NewValue
= (((OriginalValue
) & (~dwBitMask
)) |
93 (dwData
<< BitShift
));
94 rtl92e_writel(dev
, dwRegAddr
, NewValue
);
96 rtl92e_writel(dev
, dwRegAddr
, dwData
);
99 u32
rtl92e_get_bb_reg(struct net_device
*dev
, u32 dwRegAddr
, u32 dwBitMask
)
101 u32 Ret
= 0, OriginalValue
, BitShift
;
103 OriginalValue
= rtl92e_readl(dev
, dwRegAddr
);
104 BitShift
= rtl8192_CalculateBitShift(dwBitMask
);
105 Ret
= (OriginalValue
& dwBitMask
) >> BitShift
;
109 static u32
rtl8192_phy_RFSerialRead(struct net_device
*dev
,
110 enum rf90_radio_path eRFPath
, u32 Offset
)
112 struct r8192_priv
*priv
= rtllib_priv(dev
);
115 struct bb_reg_definition
*pPhyReg
= &priv
->PHYRegDef
[eRFPath
];
119 if (priv
->rf_chip
== RF_8256
) {
120 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter4
, 0xf00, 0x0);
122 priv
->RfReg0Value
[eRFPath
] |= 0x140;
123 rtl92e_set_bb_reg(dev
, pPhyReg
->rf3wireOffset
,
125 (priv
->RfReg0Value
[eRFPath
]<<16));
126 NewOffset
= Offset
- 30;
127 } else if (Offset
>= 16) {
128 priv
->RfReg0Value
[eRFPath
] |= 0x100;
129 priv
->RfReg0Value
[eRFPath
] &= (~0x40);
130 rtl92e_set_bb_reg(dev
, pPhyReg
->rf3wireOffset
,
132 (priv
->RfReg0Value
[eRFPath
]<<16));
134 NewOffset
= Offset
- 15;
138 RT_TRACE((COMP_PHY
|COMP_ERR
),
139 "check RF type here, need to be 8256\n");
142 rtl92e_set_bb_reg(dev
, pPhyReg
->rfHSSIPara2
, bLSSIReadAddress
,
144 rtl92e_set_bb_reg(dev
, pPhyReg
->rfHSSIPara2
, bLSSIReadEdge
, 0x0);
145 rtl92e_set_bb_reg(dev
, pPhyReg
->rfHSSIPara2
, bLSSIReadEdge
, 0x1);
149 ret
= rtl92e_get_bb_reg(dev
, pPhyReg
->rfLSSIReadBack
,
152 if (priv
->rf_chip
== RF_8256
) {
153 priv
->RfReg0Value
[eRFPath
] &= 0xebf;
155 rtl92e_set_bb_reg(dev
, pPhyReg
->rf3wireOffset
, bMaskDWord
,
156 (priv
->RfReg0Value
[eRFPath
] << 16));
158 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter4
, 0x300, 0x3);
166 static void rtl8192_phy_RFSerialWrite(struct net_device
*dev
,
167 enum rf90_radio_path eRFPath
, u32 Offset
,
170 struct r8192_priv
*priv
= rtllib_priv(dev
);
171 u32 DataAndAddr
= 0, NewOffset
= 0;
172 struct bb_reg_definition
*pPhyReg
= &priv
->PHYRegDef
[eRFPath
];
175 if (priv
->rf_chip
== RF_8256
) {
176 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter4
, 0xf00, 0x0);
179 priv
->RfReg0Value
[eRFPath
] |= 0x140;
180 rtl92e_set_bb_reg(dev
, pPhyReg
->rf3wireOffset
,
182 (priv
->RfReg0Value
[eRFPath
] << 16));
183 NewOffset
= Offset
- 30;
184 } else if (Offset
>= 16) {
185 priv
->RfReg0Value
[eRFPath
] |= 0x100;
186 priv
->RfReg0Value
[eRFPath
] &= (~0x40);
187 rtl92e_set_bb_reg(dev
, pPhyReg
->rf3wireOffset
,
189 (priv
->RfReg0Value
[eRFPath
] << 16));
190 NewOffset
= Offset
- 15;
194 RT_TRACE((COMP_PHY
|COMP_ERR
),
195 "check RF type here, need to be 8256\n");
199 DataAndAddr
= (Data
<<16) | (NewOffset
&0x3f);
201 rtl92e_set_bb_reg(dev
, pPhyReg
->rf3wireOffset
, bMaskDWord
, DataAndAddr
);
204 priv
->RfReg0Value
[eRFPath
] = Data
;
206 if (priv
->rf_chip
== RF_8256
) {
208 priv
->RfReg0Value
[eRFPath
] &= 0xebf;
209 rtl92e_set_bb_reg(dev
, pPhyReg
->rf3wireOffset
,
211 (priv
->RfReg0Value
[eRFPath
] << 16));
213 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter4
, 0x300, 0x3);
217 void rtl92e_set_rf_reg(struct net_device
*dev
, enum rf90_radio_path eRFPath
,
218 u32 RegAddr
, u32 BitMask
, u32 Data
)
220 struct r8192_priv
*priv
= rtllib_priv(dev
);
221 u32 Original_Value
, BitShift
, New_Value
;
223 if (!rtl92e_is_legal_rf_path(dev
, eRFPath
))
225 if (priv
->rtllib
->eRFPowerState
!= eRfOn
&& !priv
->being_init_adapter
)
228 RT_TRACE(COMP_PHY
, "FW RF CTRL is not ready now\n");
229 if (priv
->Rf_Mode
== RF_OP_By_FW
) {
230 if (BitMask
!= bMask12Bits
) {
231 Original_Value
= phy_FwRFSerialRead(dev
, eRFPath
,
233 BitShift
= rtl8192_CalculateBitShift(BitMask
);
234 New_Value
= (((Original_Value
) & (~BitMask
)) |
237 phy_FwRFSerialWrite(dev
, eRFPath
, RegAddr
, New_Value
);
239 phy_FwRFSerialWrite(dev
, eRFPath
, RegAddr
, Data
);
243 if (BitMask
!= bMask12Bits
) {
244 Original_Value
= rtl8192_phy_RFSerialRead(dev
, eRFPath
,
246 BitShift
= rtl8192_CalculateBitShift(BitMask
);
247 New_Value
= (((Original_Value
) & (~BitMask
)) |
250 rtl8192_phy_RFSerialWrite(dev
, eRFPath
, RegAddr
,
253 rtl8192_phy_RFSerialWrite(dev
, eRFPath
, RegAddr
, Data
);
257 u32
rtl92e_get_rf_reg(struct net_device
*dev
, enum rf90_radio_path eRFPath
,
258 u32 RegAddr
, u32 BitMask
)
260 u32 Original_Value
, Readback_Value
, BitShift
;
261 struct r8192_priv
*priv
= rtllib_priv(dev
);
263 if (!rtl92e_is_legal_rf_path(dev
, eRFPath
))
265 if (priv
->rtllib
->eRFPowerState
!= eRfOn
&& !priv
->being_init_adapter
)
268 if (priv
->Rf_Mode
== RF_OP_By_FW
) {
269 Original_Value
= phy_FwRFSerialRead(dev
, eRFPath
, RegAddr
);
272 Original_Value
= rtl8192_phy_RFSerialRead(dev
, eRFPath
,
275 BitShift
= rtl8192_CalculateBitShift(BitMask
);
276 Readback_Value
= (Original_Value
& BitMask
) >> BitShift
;
278 return Readback_Value
;
281 static u32
phy_FwRFSerialRead(struct net_device
*dev
,
282 enum rf90_radio_path eRFPath
, u32 Offset
)
287 Data
|= ((Offset
& 0xFF) << 12);
288 Data
|= ((eRFPath
& 0x3) << 20);
290 while (rtl92e_readl(dev
, QPNR
) & 0x80000000) {
296 rtl92e_writel(dev
, QPNR
, Data
);
297 while (rtl92e_readl(dev
, QPNR
) & 0x80000000) {
303 return rtl92e_readl(dev
, RF_DATA
);
307 static void phy_FwRFSerialWrite(struct net_device
*dev
,
308 enum rf90_radio_path eRFPath
,
309 u32 Offset
, u32 Data
)
313 Data
|= ((Offset
& 0xFF) << 12);
314 Data
|= ((eRFPath
& 0x3) << 20);
318 while (rtl92e_readl(dev
, QPNR
) & 0x80000000) {
324 rtl92e_writel(dev
, QPNR
, Data
);
329 void rtl92e_config_mac(struct net_device
*dev
)
331 u32 dwArrayLen
= 0, i
= 0;
332 u32
*pdwArray
= NULL
;
333 struct r8192_priv
*priv
= rtllib_priv(dev
);
335 if (priv
->bTXPowerDataReadFromEEPORM
) {
336 RT_TRACE(COMP_PHY
, "Rtl819XMACPHY_Array_PG\n");
337 dwArrayLen
= MACPHY_Array_PGLength
;
338 pdwArray
= Rtl819XMACPHY_Array_PG
;
341 RT_TRACE(COMP_PHY
, "Read rtl819XMACPHY_Array\n");
342 dwArrayLen
= MACPHY_ArrayLength
;
343 pdwArray
= Rtl819XMACPHY_Array
;
345 for (i
= 0; i
< dwArrayLen
; i
+= 3) {
347 "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
348 pdwArray
[i
], pdwArray
[i
+1], pdwArray
[i
+2]);
349 if (pdwArray
[i
] == 0x318)
350 pdwArray
[i
+2] = 0x00000800;
351 rtl92e_set_bb_reg(dev
, pdwArray
[i
], pdwArray
[i
+1],
358 static void rtl8192_phyConfigBB(struct net_device
*dev
, u8 ConfigType
)
361 u32
*Rtl819XPHY_REGArray_Table
= NULL
;
362 u32
*Rtl819XAGCTAB_Array_Table
= NULL
;
363 u16 AGCTAB_ArrayLen
, PHY_REGArrayLen
= 0;
364 struct r8192_priv
*priv
= rtllib_priv(dev
);
366 AGCTAB_ArrayLen
= AGCTAB_ArrayLength
;
367 Rtl819XAGCTAB_Array_Table
= Rtl819XAGCTAB_Array
;
368 if (priv
->rf_type
== RF_2T4R
) {
369 PHY_REGArrayLen
= PHY_REGArrayLength
;
370 Rtl819XPHY_REGArray_Table
= Rtl819XPHY_REGArray
;
371 } else if (priv
->rf_type
== RF_1T2R
) {
372 PHY_REGArrayLen
= PHY_REG_1T2RArrayLength
;
373 Rtl819XPHY_REGArray_Table
= Rtl819XPHY_REG_1T2RArray
;
376 if (ConfigType
== BaseBand_Config_PHY_REG
) {
377 for (i
= 0; i
< PHY_REGArrayLen
; i
+= 2) {
378 rtl92e_set_bb_reg(dev
, Rtl819XPHY_REGArray_Table
[i
],
380 Rtl819XPHY_REGArray_Table
[i
+1]);
382 "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",
383 i
, Rtl819XPHY_REGArray_Table
[i
],
384 Rtl819XPHY_REGArray_Table
[i
+1]);
386 } else if (ConfigType
== BaseBand_Config_AGC_TAB
) {
387 for (i
= 0; i
< AGCTAB_ArrayLen
; i
+= 2) {
388 rtl92e_set_bb_reg(dev
, Rtl819XAGCTAB_Array_Table
[i
],
390 Rtl819XAGCTAB_Array_Table
[i
+1]);
392 "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n",
393 i
, Rtl819XAGCTAB_Array_Table
[i
],
394 Rtl819XAGCTAB_Array_Table
[i
+1]);
399 static void rtl8192_InitBBRFRegDef(struct net_device
*dev
)
401 struct r8192_priv
*priv
= rtllib_priv(dev
);
403 priv
->PHYRegDef
[RF90_PATH_A
].rfintfs
= rFPGA0_XAB_RFInterfaceSW
;
404 priv
->PHYRegDef
[RF90_PATH_B
].rfintfs
= rFPGA0_XAB_RFInterfaceSW
;
405 priv
->PHYRegDef
[RF90_PATH_C
].rfintfs
= rFPGA0_XCD_RFInterfaceSW
;
406 priv
->PHYRegDef
[RF90_PATH_D
].rfintfs
= rFPGA0_XCD_RFInterfaceSW
;
408 priv
->PHYRegDef
[RF90_PATH_A
].rfintfi
= rFPGA0_XAB_RFInterfaceRB
;
409 priv
->PHYRegDef
[RF90_PATH_B
].rfintfi
= rFPGA0_XAB_RFInterfaceRB
;
410 priv
->PHYRegDef
[RF90_PATH_C
].rfintfi
= rFPGA0_XCD_RFInterfaceRB
;
411 priv
->PHYRegDef
[RF90_PATH_D
].rfintfi
= rFPGA0_XCD_RFInterfaceRB
;
413 priv
->PHYRegDef
[RF90_PATH_A
].rfintfo
= rFPGA0_XA_RFInterfaceOE
;
414 priv
->PHYRegDef
[RF90_PATH_B
].rfintfo
= rFPGA0_XB_RFInterfaceOE
;
415 priv
->PHYRegDef
[RF90_PATH_C
].rfintfo
= rFPGA0_XC_RFInterfaceOE
;
416 priv
->PHYRegDef
[RF90_PATH_D
].rfintfo
= rFPGA0_XD_RFInterfaceOE
;
418 priv
->PHYRegDef
[RF90_PATH_A
].rfintfe
= rFPGA0_XA_RFInterfaceOE
;
419 priv
->PHYRegDef
[RF90_PATH_B
].rfintfe
= rFPGA0_XB_RFInterfaceOE
;
420 priv
->PHYRegDef
[RF90_PATH_C
].rfintfe
= rFPGA0_XC_RFInterfaceOE
;
421 priv
->PHYRegDef
[RF90_PATH_D
].rfintfe
= rFPGA0_XD_RFInterfaceOE
;
423 priv
->PHYRegDef
[RF90_PATH_A
].rf3wireOffset
= rFPGA0_XA_LSSIParameter
;
424 priv
->PHYRegDef
[RF90_PATH_B
].rf3wireOffset
= rFPGA0_XB_LSSIParameter
;
425 priv
->PHYRegDef
[RF90_PATH_C
].rf3wireOffset
= rFPGA0_XC_LSSIParameter
;
426 priv
->PHYRegDef
[RF90_PATH_D
].rf3wireOffset
= rFPGA0_XD_LSSIParameter
;
428 priv
->PHYRegDef
[RF90_PATH_A
].rfLSSI_Select
= rFPGA0_XAB_RFParameter
;
429 priv
->PHYRegDef
[RF90_PATH_B
].rfLSSI_Select
= rFPGA0_XAB_RFParameter
;
430 priv
->PHYRegDef
[RF90_PATH_C
].rfLSSI_Select
= rFPGA0_XCD_RFParameter
;
431 priv
->PHYRegDef
[RF90_PATH_D
].rfLSSI_Select
= rFPGA0_XCD_RFParameter
;
433 priv
->PHYRegDef
[RF90_PATH_A
].rfTxGainStage
= rFPGA0_TxGainStage
;
434 priv
->PHYRegDef
[RF90_PATH_B
].rfTxGainStage
= rFPGA0_TxGainStage
;
435 priv
->PHYRegDef
[RF90_PATH_C
].rfTxGainStage
= rFPGA0_TxGainStage
;
436 priv
->PHYRegDef
[RF90_PATH_D
].rfTxGainStage
= rFPGA0_TxGainStage
;
438 priv
->PHYRegDef
[RF90_PATH_A
].rfHSSIPara1
= rFPGA0_XA_HSSIParameter1
;
439 priv
->PHYRegDef
[RF90_PATH_B
].rfHSSIPara1
= rFPGA0_XB_HSSIParameter1
;
440 priv
->PHYRegDef
[RF90_PATH_C
].rfHSSIPara1
= rFPGA0_XC_HSSIParameter1
;
441 priv
->PHYRegDef
[RF90_PATH_D
].rfHSSIPara1
= rFPGA0_XD_HSSIParameter1
;
443 priv
->PHYRegDef
[RF90_PATH_A
].rfHSSIPara2
= rFPGA0_XA_HSSIParameter2
;
444 priv
->PHYRegDef
[RF90_PATH_B
].rfHSSIPara2
= rFPGA0_XB_HSSIParameter2
;
445 priv
->PHYRegDef
[RF90_PATH_C
].rfHSSIPara2
= rFPGA0_XC_HSSIParameter2
;
446 priv
->PHYRegDef
[RF90_PATH_D
].rfHSSIPara2
= rFPGA0_XD_HSSIParameter2
;
448 priv
->PHYRegDef
[RF90_PATH_A
].rfSwitchControl
= rFPGA0_XAB_SwitchControl
;
449 priv
->PHYRegDef
[RF90_PATH_B
].rfSwitchControl
= rFPGA0_XAB_SwitchControl
;
450 priv
->PHYRegDef
[RF90_PATH_C
].rfSwitchControl
= rFPGA0_XCD_SwitchControl
;
451 priv
->PHYRegDef
[RF90_PATH_D
].rfSwitchControl
= rFPGA0_XCD_SwitchControl
;
453 priv
->PHYRegDef
[RF90_PATH_A
].rfAGCControl1
= rOFDM0_XAAGCCore1
;
454 priv
->PHYRegDef
[RF90_PATH_B
].rfAGCControl1
= rOFDM0_XBAGCCore1
;
455 priv
->PHYRegDef
[RF90_PATH_C
].rfAGCControl1
= rOFDM0_XCAGCCore1
;
456 priv
->PHYRegDef
[RF90_PATH_D
].rfAGCControl1
= rOFDM0_XDAGCCore1
;
458 priv
->PHYRegDef
[RF90_PATH_A
].rfAGCControl2
= rOFDM0_XAAGCCore2
;
459 priv
->PHYRegDef
[RF90_PATH_B
].rfAGCControl2
= rOFDM0_XBAGCCore2
;
460 priv
->PHYRegDef
[RF90_PATH_C
].rfAGCControl2
= rOFDM0_XCAGCCore2
;
461 priv
->PHYRegDef
[RF90_PATH_D
].rfAGCControl2
= rOFDM0_XDAGCCore2
;
463 priv
->PHYRegDef
[RF90_PATH_A
].rfRxIQImbalance
= rOFDM0_XARxIQImbalance
;
464 priv
->PHYRegDef
[RF90_PATH_B
].rfRxIQImbalance
= rOFDM0_XBRxIQImbalance
;
465 priv
->PHYRegDef
[RF90_PATH_C
].rfRxIQImbalance
= rOFDM0_XCRxIQImbalance
;
466 priv
->PHYRegDef
[RF90_PATH_D
].rfRxIQImbalance
= rOFDM0_XDRxIQImbalance
;
468 priv
->PHYRegDef
[RF90_PATH_A
].rfRxAFE
= rOFDM0_XARxAFE
;
469 priv
->PHYRegDef
[RF90_PATH_B
].rfRxAFE
= rOFDM0_XBRxAFE
;
470 priv
->PHYRegDef
[RF90_PATH_C
].rfRxAFE
= rOFDM0_XCRxAFE
;
471 priv
->PHYRegDef
[RF90_PATH_D
].rfRxAFE
= rOFDM0_XDRxAFE
;
473 priv
->PHYRegDef
[RF90_PATH_A
].rfTxIQImbalance
= rOFDM0_XATxIQImbalance
;
474 priv
->PHYRegDef
[RF90_PATH_B
].rfTxIQImbalance
= rOFDM0_XBTxIQImbalance
;
475 priv
->PHYRegDef
[RF90_PATH_C
].rfTxIQImbalance
= rOFDM0_XCTxIQImbalance
;
476 priv
->PHYRegDef
[RF90_PATH_D
].rfTxIQImbalance
= rOFDM0_XDTxIQImbalance
;
478 priv
->PHYRegDef
[RF90_PATH_A
].rfTxAFE
= rOFDM0_XATxAFE
;
479 priv
->PHYRegDef
[RF90_PATH_B
].rfTxAFE
= rOFDM0_XBTxAFE
;
480 priv
->PHYRegDef
[RF90_PATH_C
].rfTxAFE
= rOFDM0_XCTxAFE
;
481 priv
->PHYRegDef
[RF90_PATH_D
].rfTxAFE
= rOFDM0_XDTxAFE
;
483 priv
->PHYRegDef
[RF90_PATH_A
].rfLSSIReadBack
= rFPGA0_XA_LSSIReadBack
;
484 priv
->PHYRegDef
[RF90_PATH_B
].rfLSSIReadBack
= rFPGA0_XB_LSSIReadBack
;
485 priv
->PHYRegDef
[RF90_PATH_C
].rfLSSIReadBack
= rFPGA0_XC_LSSIReadBack
;
486 priv
->PHYRegDef
[RF90_PATH_D
].rfLSSIReadBack
= rFPGA0_XD_LSSIReadBack
;
490 bool rtl92e_check_bb_and_rf(struct net_device
*dev
, enum hw90_block CheckBlock
,
491 enum rf90_radio_path eRFPath
)
494 u32 i
, CheckTimes
= 4, dwRegRead
= 0;
496 u32 WriteData
[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
498 WriteAddr
[HW90_BLOCK_MAC
] = 0x100;
499 WriteAddr
[HW90_BLOCK_PHY0
] = 0x900;
500 WriteAddr
[HW90_BLOCK_PHY1
] = 0x800;
501 WriteAddr
[HW90_BLOCK_RF
] = 0x3;
502 RT_TRACE(COMP_PHY
, "=======>%s(), CheckBlock:%d\n", __func__
,
505 if (CheckBlock
== HW90_BLOCK_MAC
) {
506 netdev_warn(dev
, "%s(): No checks available for MAC block.\n",
511 for (i
= 0; i
< CheckTimes
; i
++) {
512 switch (CheckBlock
) {
513 case HW90_BLOCK_PHY0
:
514 case HW90_BLOCK_PHY1
:
515 rtl92e_writel(dev
, WriteAddr
[CheckBlock
],
517 dwRegRead
= rtl92e_readl(dev
, WriteAddr
[CheckBlock
]);
521 WriteData
[i
] &= 0xfff;
522 rtl92e_set_rf_reg(dev
, eRFPath
,
523 WriteAddr
[HW90_BLOCK_RF
],
524 bMask12Bits
, WriteData
[i
]);
526 dwRegRead
= rtl92e_get_rf_reg(dev
, eRFPath
,
527 WriteAddr
[HW90_BLOCK_RF
],
538 if (dwRegRead
!= WriteData
[i
]) {
539 netdev_warn(dev
, "%s(): Check failed.\n", __func__
);
548 static bool rtl8192_BB_Config_ParaFile(struct net_device
*dev
)
550 struct r8192_priv
*priv
= rtllib_priv(dev
);
551 bool rtStatus
= true;
552 u8 bRegValue
= 0, eCheckItem
= 0;
555 bRegValue
= rtl92e_readb(dev
, BB_GLOBAL_RESET
);
556 rtl92e_writeb(dev
, BB_GLOBAL_RESET
, (bRegValue
|BB_GLOBAL_RESET_BIT
));
558 dwRegValue
= rtl92e_readl(dev
, CPU_GEN
);
559 rtl92e_writel(dev
, CPU_GEN
, (dwRegValue
&(~CPU_GEN_BB_RST
)));
561 for (eCheckItem
= (enum hw90_block
)HW90_BLOCK_PHY0
;
562 eCheckItem
<= HW90_BLOCK_PHY1
; eCheckItem
++) {
563 rtStatus
= rtl92e_check_bb_and_rf(dev
,
564 (enum hw90_block
)eCheckItem
,
565 (enum rf90_radio_path
)0);
567 RT_TRACE((COMP_ERR
| COMP_PHY
),
568 "rtl92e_config_rf():Check PHY%d Fail!!\n",
573 rtl92e_set_bb_reg(dev
, rFPGA0_RFMOD
, bCCKEn
|bOFDMEn
, 0x0);
574 rtl8192_phyConfigBB(dev
, BaseBand_Config_PHY_REG
);
576 dwRegValue
= rtl92e_readl(dev
, CPU_GEN
);
577 rtl92e_writel(dev
, CPU_GEN
, (dwRegValue
|CPU_GEN_BB_RST
));
579 rtl8192_phyConfigBB(dev
, BaseBand_Config_AGC_TAB
);
581 if (priv
->IC_Cut
> VERSION_8190_BD
) {
582 if (priv
->rf_type
== RF_2T4R
)
583 dwRegValue
= (priv
->AntennaTxPwDiff
[2]<<8 |
584 priv
->AntennaTxPwDiff
[1]<<4 |
585 priv
->AntennaTxPwDiff
[0]);
588 rtl92e_set_bb_reg(dev
, rFPGA0_TxGainStage
,
589 (bXBTxAGC
|bXCTxAGC
|bXDTxAGC
), dwRegValue
);
592 dwRegValue
= priv
->CrystalCap
;
593 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter1
, bXtalCap92x
,
599 bool rtl92e_config_bb(struct net_device
*dev
)
601 rtl8192_InitBBRFRegDef(dev
);
602 return rtl8192_BB_Config_ParaFile(dev
);
605 void rtl92e_get_tx_power(struct net_device
*dev
)
607 struct r8192_priv
*priv
= rtllib_priv(dev
);
609 priv
->MCSTxPowerLevelOriginalOffset
[0] =
610 rtl92e_readl(dev
, rTxAGC_Rate18_06
);
611 priv
->MCSTxPowerLevelOriginalOffset
[1] =
612 rtl92e_readl(dev
, rTxAGC_Rate54_24
);
613 priv
->MCSTxPowerLevelOriginalOffset
[2] =
614 rtl92e_readl(dev
, rTxAGC_Mcs03_Mcs00
);
615 priv
->MCSTxPowerLevelOriginalOffset
[3] =
616 rtl92e_readl(dev
, rTxAGC_Mcs07_Mcs04
);
617 priv
->MCSTxPowerLevelOriginalOffset
[4] =
618 rtl92e_readl(dev
, rTxAGC_Mcs11_Mcs08
);
619 priv
->MCSTxPowerLevelOriginalOffset
[5] =
620 rtl92e_readl(dev
, rTxAGC_Mcs15_Mcs12
);
622 priv
->DefaultInitialGain
[0] = rtl92e_readb(dev
, rOFDM0_XAAGCCore1
);
623 priv
->DefaultInitialGain
[1] = rtl92e_readb(dev
, rOFDM0_XBAGCCore1
);
624 priv
->DefaultInitialGain
[2] = rtl92e_readb(dev
, rOFDM0_XCAGCCore1
);
625 priv
->DefaultInitialGain
[3] = rtl92e_readb(dev
, rOFDM0_XDAGCCore1
);
627 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
628 priv
->DefaultInitialGain
[0], priv
->DefaultInitialGain
[1],
629 priv
->DefaultInitialGain
[2], priv
->DefaultInitialGain
[3]);
631 priv
->framesync
= rtl92e_readb(dev
, rOFDM0_RxDetector3
);
632 priv
->framesyncC34
= rtl92e_readl(dev
, rOFDM0_RxDetector2
);
633 RT_TRACE(COMP_INIT
, "Default framesync (0x%x) = 0x%x\n",
634 rOFDM0_RxDetector3
, priv
->framesync
);
635 priv
->SifsTime
= rtl92e_readw(dev
, SIFS
);
638 void rtl92e_set_tx_power(struct net_device
*dev
, u8 channel
)
640 struct r8192_priv
*priv
= rtllib_priv(dev
);
641 u8 powerlevel
= 0, powerlevelOFDM24G
= 0;
645 if (priv
->epromtype
== EEPROM_93C46
) {
646 powerlevel
= priv
->TxPowerLevelCCK
[channel
-1];
647 powerlevelOFDM24G
= priv
->TxPowerLevelOFDM24G
[channel
-1];
648 } else if (priv
->epromtype
== EEPROM_93C56
) {
649 if (priv
->rf_type
== RF_1T2R
) {
650 powerlevel
= priv
->TxPowerLevelCCK_C
[channel
-1];
651 powerlevelOFDM24G
= priv
->TxPowerLevelOFDM24G_C
[channel
-1];
652 } else if (priv
->rf_type
== RF_2T4R
) {
653 powerlevel
= priv
->TxPowerLevelCCK_A
[channel
-1];
654 powerlevelOFDM24G
= priv
->TxPowerLevelOFDM24G_A
[channel
-1];
656 ant_pwr_diff
= priv
->TxPowerLevelOFDM24G_C
[channel
-1]
657 - priv
->TxPowerLevelOFDM24G_A
[channel
-1];
659 priv
->RF_C_TxPwDiff
= ant_pwr_diff
;
663 priv
->AntennaTxPwDiff
[2] = 0;
664 priv
->AntennaTxPwDiff
[1] = (u8
)(ant_pwr_diff
);
665 priv
->AntennaTxPwDiff
[0] = 0;
667 u4RegValue
= (priv
->AntennaTxPwDiff
[2]<<8 |
668 priv
->AntennaTxPwDiff
[1]<<4 |
669 priv
->AntennaTxPwDiff
[0]);
671 rtl92e_set_bb_reg(dev
, rFPGA0_TxGainStage
,
672 (bXBTxAGC
|bXCTxAGC
|bXDTxAGC
),
676 switch (priv
->rf_chip
) {
680 rtl92e_set_cck_tx_power(dev
, powerlevel
);
681 rtl92e_set_ofdm_tx_power(dev
, powerlevelOFDM24G
);
686 netdev_err(dev
, "Invalid RF Chip ID.\n");
691 bool rtl92e_config_phy(struct net_device
*dev
)
693 struct r8192_priv
*priv
= rtllib_priv(dev
);
694 bool rtStatus
= true;
696 switch (priv
->rf_chip
) {
700 rtStatus
= rtl92e_config_rf(dev
);
709 netdev_err(dev
, "Invalid RF Chip ID.\n");
715 u8
rtl92e_config_rf_path(struct net_device
*dev
, enum rf90_radio_path eRFPath
)
722 for (i
= 0; i
< RadioA_ArrayLength
; i
+= 2) {
723 if (Rtl819XRadioA_Array
[i
] == 0xfe) {
727 rtl92e_set_rf_reg(dev
, eRFPath
, Rtl819XRadioA_Array
[i
],
729 Rtl819XRadioA_Array
[i
+1]);
734 for (i
= 0; i
< RadioB_ArrayLength
; i
+= 2) {
735 if (Rtl819XRadioB_Array
[i
] == 0xfe) {
739 rtl92e_set_rf_reg(dev
, eRFPath
, Rtl819XRadioB_Array
[i
],
741 Rtl819XRadioB_Array
[i
+1]);
746 for (i
= 0; i
< RadioC_ArrayLength
; i
+= 2) {
747 if (Rtl819XRadioC_Array
[i
] == 0xfe) {
751 rtl92e_set_rf_reg(dev
, eRFPath
, Rtl819XRadioC_Array
[i
],
753 Rtl819XRadioC_Array
[i
+1]);
758 for (i
= 0; i
< RadioD_ArrayLength
; i
+= 2) {
759 if (Rtl819XRadioD_Array
[i
] == 0xfe) {
763 rtl92e_set_rf_reg(dev
, eRFPath
, Rtl819XRadioD_Array
[i
],
765 Rtl819XRadioD_Array
[i
+1]);
776 static void rtl8192_SetTxPowerLevel(struct net_device
*dev
, u8 channel
)
778 struct r8192_priv
*priv
= rtllib_priv(dev
);
779 u8 powerlevel
= priv
->TxPowerLevelCCK
[channel
-1];
780 u8 powerlevelOFDM24G
= priv
->TxPowerLevelOFDM24G
[channel
-1];
782 switch (priv
->rf_chip
) {
787 rtl92e_set_cck_tx_power(dev
, powerlevel
);
788 rtl92e_set_ofdm_tx_power(dev
, powerlevelOFDM24G
);
794 netdev_warn(dev
, "%s(): Invalid RF Chip ID\n", __func__
);
799 static u8
rtl8192_phy_SetSwChnlCmdArray(struct net_device
*dev
,
800 struct sw_chnl_cmd
*CmdTable
,
801 u32 CmdTableIdx
, u32 CmdTableSz
,
802 enum sw_chnl_cmd_id CmdID
,
803 u32 Para1
, u32 Para2
, u32 msDelay
)
805 struct sw_chnl_cmd
*pCmd
;
807 if (CmdTable
== NULL
) {
808 netdev_err(dev
, "%s(): CmdTable cannot be NULL.\n", __func__
);
811 if (CmdTableIdx
>= CmdTableSz
) {
812 netdev_err(dev
, "%s(): Invalid index requested.\n", __func__
);
816 pCmd
= CmdTable
+ CmdTableIdx
;
820 pCmd
->msDelay
= msDelay
;
825 static u8
rtl8192_phy_SwChnlStepByStep(struct net_device
*dev
, u8 channel
,
826 u8
*stage
, u8
*step
, u32
*delay
)
828 struct r8192_priv
*priv
= rtllib_priv(dev
);
829 struct rtllib_device
*ieee
= priv
->rtllib
;
831 u32 PostCommonCmdCnt
;
833 struct sw_chnl_cmd
*CurrentCmd
= NULL
;
836 RT_TRACE(COMP_TRACE
, "====>%s()====stage:%d, step:%d, channel:%d\n",
837 __func__
, *stage
, *step
, channel
);
839 if (!rtllib_legal_channel(priv
->rtllib
, channel
)) {
840 netdev_err(dev
, "Invalid channel requested: %d\n", channel
);
846 rtl8192_phy_SetSwChnlCmdArray(dev
, ieee
->PreCommonCmd
,
848 MAX_PRECMD_CNT
, CmdID_SetTxPowerLevel
,
850 rtl8192_phy_SetSwChnlCmdArray(dev
, ieee
->PreCommonCmd
,
852 MAX_PRECMD_CNT
, CmdID_End
, 0, 0, 0);
854 PostCommonCmdCnt
= 0;
856 rtl8192_phy_SetSwChnlCmdArray(dev
, ieee
->PostCommonCmd
,
858 MAX_POSTCMD_CNT
, CmdID_End
, 0, 0, 0);
861 switch (priv
->rf_chip
) {
863 if (!(channel
>= 1 && channel
<= 14)) {
865 "Invalid channel requested for 8225: %d\n",
869 rtl8192_phy_SetSwChnlCmdArray(dev
, ieee
->RfDependCmd
,
870 RfDependCmdCnt
++, MAX_RFDEPENDCMD_CNT
,
871 CmdID_RF_WriteReg
, rZebra1_Channel
,
872 RF_CHANNEL_TABLE_ZEBRA
[channel
], 10);
873 rtl8192_phy_SetSwChnlCmdArray(dev
, ieee
->RfDependCmd
,
874 RfDependCmdCnt
++, MAX_RFDEPENDCMD_CNT
,
879 if (!(channel
>= 1 && channel
<= 14)) {
881 "Invalid channel requested for 8256: %d\n",
885 rtl8192_phy_SetSwChnlCmdArray(dev
, ieee
->RfDependCmd
,
886 RfDependCmdCnt
++, MAX_RFDEPENDCMD_CNT
,
887 CmdID_RF_WriteReg
, rZebra1_Channel
, channel
,
889 rtl8192_phy_SetSwChnlCmdArray(dev
, ieee
->RfDependCmd
,
900 netdev_warn(dev
, "Unknown RF Chip ID\n");
908 CurrentCmd
= &ieee
->PreCommonCmd
[*step
];
911 CurrentCmd
= &ieee
->RfDependCmd
[*step
];
914 CurrentCmd
= &ieee
->PostCommonCmd
[*step
];
918 if (CurrentCmd
&& CurrentCmd
->CmdID
== CmdID_End
) {
928 switch (CurrentCmd
->CmdID
) {
929 case CmdID_SetTxPowerLevel
:
930 if (priv
->IC_Cut
> (u8
)VERSION_8190_BD
)
931 rtl8192_SetTxPowerLevel(dev
, channel
);
933 case CmdID_WritePortUlong
:
934 rtl92e_writel(dev
, CurrentCmd
->Para1
,
937 case CmdID_WritePortUshort
:
938 rtl92e_writew(dev
, CurrentCmd
->Para1
,
939 (u16
)CurrentCmd
->Para2
);
941 case CmdID_WritePortUchar
:
942 rtl92e_writeb(dev
, CurrentCmd
->Para1
,
943 (u8
)CurrentCmd
->Para2
);
945 case CmdID_RF_WriteReg
:
946 for (eRFPath
= 0; eRFPath
<
947 priv
->NumTotalRFPath
; eRFPath
++)
948 rtl92e_set_rf_reg(dev
,
949 (enum rf90_radio_path
)eRFPath
,
950 CurrentCmd
->Para1
, bMask12Bits
,
951 CurrentCmd
->Para2
<<7);
959 } /*for (Number of RF paths)*/
961 (*delay
) = CurrentCmd
->msDelay
;
966 static void rtl8192_phy_FinishSwChnlNow(struct net_device
*dev
, u8 channel
)
968 struct r8192_priv
*priv
= rtllib_priv(dev
);
971 while (!rtl8192_phy_SwChnlStepByStep(dev
, channel
, &priv
->SwChnlStage
,
972 &priv
->SwChnlStep
, &delay
)) {
979 static void rtl8192_SwChnl_WorkItem(struct net_device
*dev
)
982 struct r8192_priv
*priv
= rtllib_priv(dev
);
984 RT_TRACE(COMP_TRACE
, "==> SwChnlCallback819xUsbWorkItem()\n");
986 RT_TRACE(COMP_TRACE
, "=====>--%s(), set chan:%d, priv:%p\n", __func__
,
989 rtl8192_phy_FinishSwChnlNow(dev
, priv
->chan
);
991 RT_TRACE(COMP_TRACE
, "<== SwChnlCallback819xUsbWorkItem()\n");
994 u8
rtl92e_set_channel(struct net_device
*dev
, u8 channel
)
996 struct r8192_priv
*priv
= rtllib_priv(dev
);
998 RT_TRACE(COMP_PHY
, "=====>%s()\n", __func__
);
1000 netdev_err(dev
, "%s(): Driver is not initialized\n", __func__
);
1003 if (priv
->SwChnlInProgress
)
1007 switch (priv
->rtllib
->mode
) {
1008 case WIRELESS_MODE_A
:
1009 case WIRELESS_MODE_N_5G
:
1010 if (channel
<= 14) {
1012 "Channel %d not available in 802.11a.\n",
1017 case WIRELESS_MODE_B
:
1020 "Channel %d not available in 802.11b.\n",
1025 case WIRELESS_MODE_G
:
1026 case WIRELESS_MODE_N_24G
:
1029 "Channel %d not available in 802.11g.\n",
1036 priv
->SwChnlInProgress
= true;
1040 priv
->chan
= channel
;
1042 priv
->SwChnlStage
= 0;
1043 priv
->SwChnlStep
= 0;
1046 rtl8192_SwChnl_WorkItem(dev
);
1047 priv
->SwChnlInProgress
= false;
1051 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device
*dev
)
1053 struct r8192_priv
*priv
= rtllib_priv(dev
);
1055 switch (priv
->CurrentChannelBW
) {
1056 case HT_CHANNEL_WIDTH_20
:
1057 priv
->CCKPresentAttentuation
=
1058 priv
->CCKPresentAttentuation_20Mdefault
+
1059 priv
->CCKPresentAttentuation_difference
;
1061 if (priv
->CCKPresentAttentuation
>
1062 (CCKTxBBGainTableLength
-1))
1063 priv
->CCKPresentAttentuation
=
1064 CCKTxBBGainTableLength
-1;
1065 if (priv
->CCKPresentAttentuation
< 0)
1066 priv
->CCKPresentAttentuation
= 0;
1068 RT_TRACE(COMP_POWER_TRACKING
,
1069 "20M, priv->CCKPresentAttentuation = %d\n",
1070 priv
->CCKPresentAttentuation
);
1072 if (priv
->rtllib
->current_network
.channel
== 14 &&
1073 !priv
->bcck_in_ch14
) {
1074 priv
->bcck_in_ch14
= true;
1075 rtl92e_dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
1076 } else if (priv
->rtllib
->current_network
.channel
!=
1077 14 && priv
->bcck_in_ch14
) {
1078 priv
->bcck_in_ch14
= false;
1079 rtl92e_dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
1081 rtl92e_dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
1085 case HT_CHANNEL_WIDTH_20_40
:
1086 priv
->CCKPresentAttentuation
=
1087 priv
->CCKPresentAttentuation_40Mdefault
+
1088 priv
->CCKPresentAttentuation_difference
;
1090 RT_TRACE(COMP_POWER_TRACKING
,
1091 "40M, priv->CCKPresentAttentuation = %d\n",
1092 priv
->CCKPresentAttentuation
);
1093 if (priv
->CCKPresentAttentuation
>
1094 (CCKTxBBGainTableLength
- 1))
1095 priv
->CCKPresentAttentuation
=
1096 CCKTxBBGainTableLength
-1;
1097 if (priv
->CCKPresentAttentuation
< 0)
1098 priv
->CCKPresentAttentuation
= 0;
1100 if (priv
->rtllib
->current_network
.channel
== 14 &&
1101 !priv
->bcck_in_ch14
) {
1102 priv
->bcck_in_ch14
= true;
1103 rtl92e_dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
1104 } else if (priv
->rtllib
->current_network
.channel
!= 14
1105 && priv
->bcck_in_ch14
) {
1106 priv
->bcck_in_ch14
= false;
1107 rtl92e_dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
1109 rtl92e_dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
1115 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device
*dev
)
1117 struct r8192_priv
*priv
= rtllib_priv(dev
);
1119 if (priv
->rtllib
->current_network
.channel
== 14 &&
1120 !priv
->bcck_in_ch14
)
1121 priv
->bcck_in_ch14
= true;
1122 else if (priv
->rtllib
->current_network
.channel
!= 14 &&
1124 priv
->bcck_in_ch14
= false;
1126 switch (priv
->CurrentChannelBW
) {
1127 case HT_CHANNEL_WIDTH_20
:
1128 if (priv
->Record_CCK_20Mindex
== 0)
1129 priv
->Record_CCK_20Mindex
= 6;
1130 priv
->CCK_index
= priv
->Record_CCK_20Mindex
;
1131 RT_TRACE(COMP_POWER_TRACKING
,
1132 "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n",
1136 case HT_CHANNEL_WIDTH_20_40
:
1137 priv
->CCK_index
= priv
->Record_CCK_40Mindex
;
1138 RT_TRACE(COMP_POWER_TRACKING
,
1139 "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n",
1143 rtl92e_dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
1146 static void CCK_Tx_Power_Track_BW_Switch(struct net_device
*dev
)
1148 struct r8192_priv
*priv
= rtllib_priv(dev
);
1150 if (priv
->IC_Cut
>= IC_VersionCut_D
)
1151 CCK_Tx_Power_Track_BW_Switch_TSSI(dev
);
1153 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev
);
1156 static void rtl8192_SetBWModeWorkItem(struct net_device
*dev
)
1159 struct r8192_priv
*priv
= rtllib_priv(dev
);
1163 "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n",
1164 priv
->CurrentChannelBW
== HT_CHANNEL_WIDTH_20
?
1168 if (priv
->rf_chip
== RF_PSEUDO_11N
) {
1169 priv
->SetBWModeInProgress
= false;
1173 netdev_err(dev
, "%s(): Driver is not initialized\n", __func__
);
1176 regBwOpMode
= rtl92e_readb(dev
, BW_OPMODE
);
1178 switch (priv
->CurrentChannelBW
) {
1179 case HT_CHANNEL_WIDTH_20
:
1180 regBwOpMode
|= BW_OPMODE_20MHZ
;
1181 rtl92e_writeb(dev
, BW_OPMODE
, regBwOpMode
);
1184 case HT_CHANNEL_WIDTH_20_40
:
1185 regBwOpMode
&= ~BW_OPMODE_20MHZ
;
1186 rtl92e_writeb(dev
, BW_OPMODE
, regBwOpMode
);
1190 netdev_err(dev
, "%s(): unknown Bandwidth: %#X\n", __func__
,
1191 priv
->CurrentChannelBW
);
1195 switch (priv
->CurrentChannelBW
) {
1196 case HT_CHANNEL_WIDTH_20
:
1197 rtl92e_set_bb_reg(dev
, rFPGA0_RFMOD
, bRFMOD
, 0x0);
1198 rtl92e_set_bb_reg(dev
, rFPGA1_RFMOD
, bRFMOD
, 0x0);
1200 if (!priv
->btxpower_tracking
) {
1201 rtl92e_writel(dev
, rCCK0_TxFilter1
, 0x1a1b0000);
1202 rtl92e_writel(dev
, rCCK0_TxFilter2
, 0x090e1317);
1203 rtl92e_writel(dev
, rCCK0_DebugPort
, 0x00000204);
1205 CCK_Tx_Power_Track_BW_Switch(dev
);
1208 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter1
, 0x00100000, 1);
1211 case HT_CHANNEL_WIDTH_20_40
:
1212 rtl92e_set_bb_reg(dev
, rFPGA0_RFMOD
, bRFMOD
, 0x1);
1213 rtl92e_set_bb_reg(dev
, rFPGA1_RFMOD
, bRFMOD
, 0x1);
1215 if (!priv
->btxpower_tracking
) {
1216 rtl92e_writel(dev
, rCCK0_TxFilter1
, 0x35360000);
1217 rtl92e_writel(dev
, rCCK0_TxFilter2
, 0x121c252e);
1218 rtl92e_writel(dev
, rCCK0_DebugPort
, 0x00000409);
1220 CCK_Tx_Power_Track_BW_Switch(dev
);
1223 rtl92e_set_bb_reg(dev
, rCCK0_System
, bCCKSideBand
,
1224 (priv
->nCur40MhzPrimeSC
>>1));
1225 rtl92e_set_bb_reg(dev
, rOFDM1_LSTF
, 0xC00,
1226 priv
->nCur40MhzPrimeSC
);
1228 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter1
, 0x00100000, 0);
1231 netdev_err(dev
, "%s(): unknown Bandwidth: %#X\n", __func__
,
1232 priv
->CurrentChannelBW
);
1237 switch (priv
->rf_chip
) {
1242 rtl92e_set_bandwidth(dev
, priv
->CurrentChannelBW
);
1252 netdev_info(dev
, "%s(): Unknown RFChipID: %d\n", __func__
,
1257 atomic_dec(&(priv
->rtllib
->atm_swbw
));
1258 priv
->SetBWModeInProgress
= false;
1260 RT_TRACE(COMP_SWBW
, "<==SetBWMode819xUsb()");
1263 void rtl92e_set_bw_mode(struct net_device
*dev
, enum ht_channel_width Bandwidth
,
1264 enum ht_extchnl_offset Offset
)
1266 struct r8192_priv
*priv
= rtllib_priv(dev
);
1269 if (priv
->SetBWModeInProgress
)
1272 atomic_inc(&(priv
->rtllib
->atm_swbw
));
1273 priv
->SetBWModeInProgress
= true;
1275 priv
->CurrentChannelBW
= Bandwidth
;
1277 if (Offset
== HT_EXTCHNL_OFFSET_LOWER
)
1278 priv
->nCur40MhzPrimeSC
= HAL_PRIME_CHNL_OFFSET_UPPER
;
1279 else if (Offset
== HT_EXTCHNL_OFFSET_UPPER
)
1280 priv
->nCur40MhzPrimeSC
= HAL_PRIME_CHNL_OFFSET_LOWER
;
1282 priv
->nCur40MhzPrimeSC
= HAL_PRIME_CHNL_OFFSET_DONT_CARE
;
1284 rtl8192_SetBWModeWorkItem(dev
);
1288 void rtl92e_init_gain(struct net_device
*dev
, u8 Operation
)
1290 #define SCAN_RX_INITIAL_GAIN 0x17
1291 #define POWER_DETECTION_TH 0x08
1292 struct r8192_priv
*priv
= rtllib_priv(dev
);
1297 switch (Operation
) {
1300 "IG_Backup, backup the initial gain.\n");
1301 initial_gain
= SCAN_RX_INITIAL_GAIN
;
1302 BitMask
= bMaskByte0
;
1303 if (dm_digtable
.dig_algorithm
==
1304 DIG_ALGO_BY_FALSE_ALARM
)
1305 rtl92e_set_bb_reg(dev
, UFWP
, bMaskByte1
, 0x8);
1306 priv
->initgain_backup
.xaagccore1
=
1307 (u8
)rtl92e_get_bb_reg(dev
, rOFDM0_XAAGCCore1
,
1309 priv
->initgain_backup
.xbagccore1
=
1310 (u8
)rtl92e_get_bb_reg(dev
, rOFDM0_XBAGCCore1
,
1312 priv
->initgain_backup
.xcagccore1
=
1313 (u8
)rtl92e_get_bb_reg(dev
, rOFDM0_XCAGCCore1
,
1315 priv
->initgain_backup
.xdagccore1
=
1316 (u8
)rtl92e_get_bb_reg(dev
, rOFDM0_XDAGCCore1
,
1318 BitMask
= bMaskByte2
;
1319 priv
->initgain_backup
.cca
= (u8
)rtl92e_get_bb_reg(dev
,
1320 rCCK0_CCA
, BitMask
);
1323 "Scan InitialGainBackup 0xc50 is %x\n",
1324 priv
->initgain_backup
.xaagccore1
);
1326 "Scan InitialGainBackup 0xc58 is %x\n",
1327 priv
->initgain_backup
.xbagccore1
);
1329 "Scan InitialGainBackup 0xc60 is %x\n",
1330 priv
->initgain_backup
.xcagccore1
);
1332 "Scan InitialGainBackup 0xc68 is %x\n",
1333 priv
->initgain_backup
.xdagccore1
);
1335 "Scan InitialGainBackup 0xa0a is %x\n",
1336 priv
->initgain_backup
.cca
);
1338 RT_TRACE(COMP_SCAN
, "Write scan initial gain = 0x%x\n",
1340 rtl92e_writeb(dev
, rOFDM0_XAAGCCore1
, initial_gain
);
1341 rtl92e_writeb(dev
, rOFDM0_XBAGCCore1
, initial_gain
);
1342 rtl92e_writeb(dev
, rOFDM0_XCAGCCore1
, initial_gain
);
1343 rtl92e_writeb(dev
, rOFDM0_XDAGCCore1
, initial_gain
);
1344 RT_TRACE(COMP_SCAN
, "Write scan 0xa0a = 0x%x\n",
1345 POWER_DETECTION_TH
);
1346 rtl92e_writeb(dev
, 0xa0a, POWER_DETECTION_TH
);
1350 "IG_Restore, restore the initial gain.\n");
1352 if (dm_digtable
.dig_algorithm
==
1353 DIG_ALGO_BY_FALSE_ALARM
)
1354 rtl92e_set_bb_reg(dev
, UFWP
, bMaskByte1
, 0x8);
1356 rtl92e_set_bb_reg(dev
, rOFDM0_XAAGCCore1
, BitMask
,
1357 (u32
)priv
->initgain_backup
.xaagccore1
);
1358 rtl92e_set_bb_reg(dev
, rOFDM0_XBAGCCore1
, BitMask
,
1359 (u32
)priv
->initgain_backup
.xbagccore1
);
1360 rtl92e_set_bb_reg(dev
, rOFDM0_XCAGCCore1
, BitMask
,
1361 (u32
)priv
->initgain_backup
.xcagccore1
);
1362 rtl92e_set_bb_reg(dev
, rOFDM0_XDAGCCore1
, BitMask
,
1363 (u32
)priv
->initgain_backup
.xdagccore1
);
1364 BitMask
= bMaskByte2
;
1365 rtl92e_set_bb_reg(dev
, rCCK0_CCA
, BitMask
,
1366 (u32
)priv
->initgain_backup
.cca
);
1369 "Scan BBInitialGainRestore 0xc50 is %x\n",
1370 priv
->initgain_backup
.xaagccore1
);
1372 "Scan BBInitialGainRestore 0xc58 is %x\n",
1373 priv
->initgain_backup
.xbagccore1
);
1375 "Scan BBInitialGainRestore 0xc60 is %x\n",
1376 priv
->initgain_backup
.xcagccore1
);
1378 "Scan BBInitialGainRestore 0xc68 is %x\n",
1379 priv
->initgain_backup
.xdagccore1
);
1381 "Scan BBInitialGainRestore 0xa0a is %x\n",
1382 priv
->initgain_backup
.cca
);
1384 rtl92e_set_tx_power(dev
,
1385 priv
->rtllib
->current_network
.channel
);
1387 if (dm_digtable
.dig_algorithm
==
1388 DIG_ALGO_BY_FALSE_ALARM
)
1389 rtl92e_set_bb_reg(dev
, UFWP
, bMaskByte1
, 0x1);
1392 RT_TRACE(COMP_SCAN
, "Unknown IG Operation.\n");
1398 void rtl92e_set_rf_off(struct net_device
*dev
)
1401 rtl92e_set_bb_reg(dev
, rFPGA0_XA_RFInterfaceOE
, BIT4
, 0x0);
1402 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter4
, 0x300, 0x0);
1403 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter1
, 0x18, 0x0);
1404 rtl92e_set_bb_reg(dev
, rOFDM0_TRxPathEnable
, 0xf, 0x0);
1405 rtl92e_set_bb_reg(dev
, rOFDM1_TRxPathEnable
, 0xf, 0x0);
1406 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter1
, 0x60, 0x0);
1407 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter1
, 0x4, 0x0);
1408 rtl92e_writeb(dev
, ANAPAR_FOR_8192PciE
, 0x07);
1412 static bool SetRFPowerState8190(struct net_device
*dev
,
1413 enum rt_rf_power_state eRFPowerState
)
1415 struct r8192_priv
*priv
= rtllib_priv(dev
);
1416 struct rt_pwr_save_ctrl
*pPSC
= (struct rt_pwr_save_ctrl
*)
1417 (&(priv
->rtllib
->PowerSaveControl
));
1418 bool bResult
= true;
1419 u8 i
= 0, QueueID
= 0;
1420 struct rtl8192_tx_ring
*ring
= NULL
;
1422 if (priv
->SetRFPowerStateInProgress
)
1424 RT_TRACE(COMP_PS
, "===========> SetRFPowerState8190()!\n");
1425 priv
->SetRFPowerStateInProgress
= true;
1427 switch (priv
->rf_chip
) {
1429 switch (eRFPowerState
) {
1431 RT_TRACE(COMP_PS
, "SetRFPowerState8190() eRfOn!\n");
1432 if ((priv
->rtllib
->eRFPowerState
== eRfOff
) &&
1433 RT_IN_PS_LEVEL(pPSC
, RT_RF_OFF_LEVL_HALT_NIC
)) {
1434 bool rtstatus
= true;
1435 u32 InitilizeCount
= 3;
1439 priv
->RegRfOff
= false;
1440 rtstatus
= rtl92e_enable_nic(dev
);
1441 } while (!rtstatus
&& (InitilizeCount
> 0));
1445 "%s(): Failed to initialize Adapter.\n",
1447 priv
->SetRFPowerStateInProgress
= false;
1451 RT_CLEAR_PS_LEVEL(pPSC
,
1452 RT_RF_OFF_LEVL_HALT_NIC
);
1454 rtl92e_writeb(dev
, ANAPAR
, 0x37);
1456 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter1
,
1458 priv
->bHwRfOffAction
= 0;
1460 rtl92e_set_bb_reg(dev
, rFPGA0_XA_RFInterfaceOE
,
1462 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter4
,
1464 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter1
,
1466 rtl92e_set_bb_reg(dev
, rOFDM0_TRxPathEnable
,
1468 rtl92e_set_bb_reg(dev
, rOFDM1_TRxPathEnable
,
1470 rtl92e_set_bb_reg(dev
, rFPGA0_AnalogParameter1
,
1478 if (priv
->rtllib
->eRFPowerState
== eRfOff
)
1482 for (QueueID
= 0, i
= 0; QueueID
< MAX_TX_QUEUE
; ) {
1483 ring
= &priv
->tx_ring
[QueueID
];
1485 if (skb_queue_len(&ring
->queue
) == 0) {
1489 RT_TRACE((COMP_POWER
|COMP_RF
),
1490 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n",
1496 if (i
>= MAX_DOZE_WAITING_TIMES_9x
) {
1497 RT_TRACE(COMP_POWER
,
1498 "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n",
1499 MAX_DOZE_WAITING_TIMES_9x
,
1504 rtl92e_set_rf_off(dev
);
1509 "SetRFPowerState8190() eRfOff/Sleep !\n");
1511 for (QueueID
= 0, i
= 0; QueueID
< MAX_TX_QUEUE
; ) {
1512 ring
= &priv
->tx_ring
[QueueID
];
1514 if (skb_queue_len(&ring
->queue
) == 0) {
1518 RT_TRACE(COMP_POWER
,
1519 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n",
1525 if (i
>= MAX_DOZE_WAITING_TIMES_9x
) {
1526 RT_TRACE(COMP_POWER
,
1527 "\n\n\n SetZebra: RFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n",
1528 MAX_DOZE_WAITING_TIMES_9x
,
1534 if (pPSC
->RegRfPsLevel
& RT_RF_OFF_LEVL_HALT_NIC
&&
1535 !RT_IN_PS_LEVEL(pPSC
, RT_RF_OFF_LEVL_HALT_NIC
)) {
1536 rtl92e_disable_nic(dev
);
1537 RT_SET_PS_LEVEL(pPSC
, RT_RF_OFF_LEVL_HALT_NIC
);
1538 } else if (!(pPSC
->RegRfPsLevel
&
1539 RT_RF_OFF_LEVL_HALT_NIC
)) {
1540 rtl92e_set_rf_off(dev
);
1548 "%s(): Unknown state requested: 0x%X.\n",
1549 __func__
, eRFPowerState
);
1556 netdev_warn(dev
, "%s(): Unknown RF type\n", __func__
);
1561 priv
->rtllib
->eRFPowerState
= eRFPowerState
;
1563 switch (priv
->rf_chip
) {
1568 netdev_warn(dev
, "%s(): Unknown RF type\n", __func__
);
1573 priv
->SetRFPowerStateInProgress
= false;
1574 RT_TRACE(COMP_PS
, "<=========== SetRFPowerState8190() bResult = %d!\n",
1579 bool rtl92e_set_rf_power_state(struct net_device
*dev
,
1580 enum rt_rf_power_state eRFPowerState
)
1582 struct r8192_priv
*priv
= rtllib_priv(dev
);
1584 bool bResult
= false;
1587 "---------> rtl92e_set_rf_power_state(): eRFPowerState(%d)\n",
1589 if (eRFPowerState
== priv
->rtllib
->eRFPowerState
&&
1590 priv
->bHwRfOffAction
== 0) {
1592 "<--------- rtl92e_set_rf_power_state(): discard the request for eRFPowerState(%d) is the same.\n",
1597 bResult
= SetRFPowerState8190(dev
, eRFPowerState
);
1600 "<--------- rtl92e_set_rf_power_state(): bResult(%d)\n",
1606 void rtl92e_scan_op_backup(struct net_device
*dev
, u8 Operation
)
1608 struct r8192_priv
*priv
= rtllib_priv(dev
);
1611 switch (Operation
) {
1612 case SCAN_OPT_BACKUP
:
1613 priv
->rtllib
->InitialGainHandler(dev
, IG_Backup
);
1616 case SCAN_OPT_RESTORE
:
1617 priv
->rtllib
->InitialGainHandler(dev
, IG_Restore
);
1621 RT_TRACE(COMP_SCAN
, "Unknown Scan Backup Operation.\n");