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Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[mirror_ubuntu-eoan-kernel.git] / drivers / staging / rtl8192e / rtl8192e / r8192E_phy.c
1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 *
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
7 * more details.
8 *
9 * You should have received a copy of the GNU General Public License along with
10 * this program; if not, write to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
12 *
13 * The full GNU General Public License is included in this distribution in the
14 * file called LICENSE.
15 *
16 * Contact Information:
17 * wlanfae <wlanfae@realtek.com>
18 ******************************************************************************/
19
20 #include "rtl_core.h"
21 #include "r8192E_hw.h"
22 #include "r8192E_phyreg.h"
23 #include "r8190P_rtl8256.h"
24 #include "r8192E_phy.h"
25 #include "rtl_dm.h"
26
27 #include "r8192E_hwimg.h"
28
29 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
30 0,
31 0x085c,
32 0x08dc,
33 0x095c,
34 0x09dc,
35 0x0a5c,
36 0x0adc,
37 0x0b5c,
38 0x0bdc,
39 0x0c5c,
40 0x0cdc,
41 0x0d5c,
42 0x0ddc,
43 0x0e5c,
44 0x0f72,
45 };
46
47 /*************************Define local function prototype**********************/
48
49 static u32 phy_FwRFSerialRead(struct net_device *dev,
50 enum rf90_radio_path eRFPath,
51 u32 Offset);
52 static void phy_FwRFSerialWrite(struct net_device *dev,
53 enum rf90_radio_path eRFPath,
54 u32 Offset, u32 Data);
55
56 static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
57 {
58 u32 i;
59
60 for (i = 0; i <= 31; i++) {
61 if (((dwBitMask >> i) & 0x1) == 1)
62 break;
63 }
64 return i;
65 }
66
67 u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath)
68 {
69 u8 ret = 1;
70 struct r8192_priv *priv = rtllib_priv(dev);
71
72 if (priv->rf_type == RF_2T4R)
73 ret = 0;
74 else if (priv->rf_type == RF_1T2R) {
75 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
76 ret = 1;
77 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
78 ret = 0;
79 }
80 return ret;
81 }
82
83 void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
84 u32 dwData)
85 {
86
87 u32 OriginalValue, BitShift, NewValue;
88
89 if (dwBitMask != bMaskDWord) {
90 OriginalValue = rtl92e_readl(dev, dwRegAddr);
91 BitShift = rtl8192_CalculateBitShift(dwBitMask);
92 NewValue = (((OriginalValue) & (~dwBitMask)) |
93 (dwData << BitShift));
94 rtl92e_writel(dev, dwRegAddr, NewValue);
95 } else
96 rtl92e_writel(dev, dwRegAddr, dwData);
97 }
98
99 u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
100 {
101 u32 Ret = 0, OriginalValue, BitShift;
102
103 OriginalValue = rtl92e_readl(dev, dwRegAddr);
104 BitShift = rtl8192_CalculateBitShift(dwBitMask);
105 Ret = (OriginalValue & dwBitMask) >> BitShift;
106
107 return Ret;
108 }
109 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
110 enum rf90_radio_path eRFPath, u32 Offset)
111 {
112 struct r8192_priv *priv = rtllib_priv(dev);
113 u32 ret = 0;
114 u32 NewOffset = 0;
115 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
116
117 Offset &= 0x3f;
118
119 if (priv->rf_chip == RF_8256) {
120 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
121 if (Offset >= 31) {
122 priv->RfReg0Value[eRFPath] |= 0x140;
123 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
124 bMaskDWord,
125 (priv->RfReg0Value[eRFPath]<<16));
126 NewOffset = Offset - 30;
127 } else if (Offset >= 16) {
128 priv->RfReg0Value[eRFPath] |= 0x100;
129 priv->RfReg0Value[eRFPath] &= (~0x40);
130 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
131 bMaskDWord,
132 (priv->RfReg0Value[eRFPath]<<16));
133
134 NewOffset = Offset - 15;
135 } else
136 NewOffset = Offset;
137 } else {
138 RT_TRACE((COMP_PHY|COMP_ERR),
139 "check RF type here, need to be 8256\n");
140 NewOffset = Offset;
141 }
142 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
143 NewOffset);
144 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
145 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
146
147 mdelay(1);
148
149 ret = rtl92e_get_bb_reg(dev, pPhyReg->rfLSSIReadBack,
150 bLSSIReadBackData);
151
152 if (priv->rf_chip == RF_8256) {
153 priv->RfReg0Value[eRFPath] &= 0xebf;
154
155 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
156 (priv->RfReg0Value[eRFPath] << 16));
157
158 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
159 }
160
161
162 return ret;
163
164 }
165
166 static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
167 enum rf90_radio_path eRFPath, u32 Offset,
168 u32 Data)
169 {
170 struct r8192_priv *priv = rtllib_priv(dev);
171 u32 DataAndAddr = 0, NewOffset = 0;
172 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
173
174 Offset &= 0x3f;
175 if (priv->rf_chip == RF_8256) {
176 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
177
178 if (Offset >= 31) {
179 priv->RfReg0Value[eRFPath] |= 0x140;
180 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
181 bMaskDWord,
182 (priv->RfReg0Value[eRFPath] << 16));
183 NewOffset = Offset - 30;
184 } else if (Offset >= 16) {
185 priv->RfReg0Value[eRFPath] |= 0x100;
186 priv->RfReg0Value[eRFPath] &= (~0x40);
187 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
188 bMaskDWord,
189 (priv->RfReg0Value[eRFPath] << 16));
190 NewOffset = Offset - 15;
191 } else
192 NewOffset = Offset;
193 } else {
194 RT_TRACE((COMP_PHY|COMP_ERR),
195 "check RF type here, need to be 8256\n");
196 NewOffset = Offset;
197 }
198
199 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
200
201 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
202
203 if (Offset == 0x0)
204 priv->RfReg0Value[eRFPath] = Data;
205
206 if (priv->rf_chip == RF_8256) {
207 if (Offset != 0) {
208 priv->RfReg0Value[eRFPath] &= 0xebf;
209 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
210 bMaskDWord,
211 (priv->RfReg0Value[eRFPath] << 16));
212 }
213 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
214 }
215 }
216
217 void rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
218 u32 RegAddr, u32 BitMask, u32 Data)
219 {
220 struct r8192_priv *priv = rtllib_priv(dev);
221 u32 Original_Value, BitShift, New_Value;
222
223 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
224 return;
225 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
226 return;
227
228 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
229 if (priv->Rf_Mode == RF_OP_By_FW) {
230 if (BitMask != bMask12Bits) {
231 Original_Value = phy_FwRFSerialRead(dev, eRFPath,
232 RegAddr);
233 BitShift = rtl8192_CalculateBitShift(BitMask);
234 New_Value = (((Original_Value) & (~BitMask)) |
235 (Data << BitShift));
236
237 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
238 } else
239 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
240 udelay(200);
241
242 } else {
243 if (BitMask != bMask12Bits) {
244 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
245 RegAddr);
246 BitShift = rtl8192_CalculateBitShift(BitMask);
247 New_Value = (((Original_Value) & (~BitMask)) |
248 (Data << BitShift));
249
250 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr,
251 New_Value);
252 } else
253 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
254 }
255 }
256
257 u32 rtl92e_get_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
258 u32 RegAddr, u32 BitMask)
259 {
260 u32 Original_Value, Readback_Value, BitShift;
261 struct r8192_priv *priv = rtllib_priv(dev);
262
263 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
264 return 0;
265 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
266 return 0;
267 down(&priv->rf_sem);
268 if (priv->Rf_Mode == RF_OP_By_FW) {
269 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
270 udelay(200);
271 } else {
272 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
273 RegAddr);
274 }
275 BitShift = rtl8192_CalculateBitShift(BitMask);
276 Readback_Value = (Original_Value & BitMask) >> BitShift;
277 up(&priv->rf_sem);
278 return Readback_Value;
279 }
280
281 static u32 phy_FwRFSerialRead(struct net_device *dev,
282 enum rf90_radio_path eRFPath, u32 Offset)
283 {
284 u32 Data = 0;
285 u8 time = 0;
286
287 Data |= ((Offset & 0xFF) << 12);
288 Data |= ((eRFPath & 0x3) << 20);
289 Data |= 0x80000000;
290 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
291 if (time++ < 100)
292 udelay(10);
293 else
294 break;
295 }
296 rtl92e_writel(dev, QPNR, Data);
297 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
298 if (time++ < 100)
299 udelay(10);
300 else
301 return 0;
302 }
303 return rtl92e_readl(dev, RF_DATA);
304
305 }
306
307 static void phy_FwRFSerialWrite(struct net_device *dev,
308 enum rf90_radio_path eRFPath,
309 u32 Offset, u32 Data)
310 {
311 u8 time = 0;
312
313 Data |= ((Offset & 0xFF) << 12);
314 Data |= ((eRFPath & 0x3) << 20);
315 Data |= 0x400000;
316 Data |= 0x80000000;
317
318 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
319 if (time++ < 100)
320 udelay(10);
321 else
322 break;
323 }
324 rtl92e_writel(dev, QPNR, Data);
325
326 }
327
328
329 void rtl92e_config_mac(struct net_device *dev)
330 {
331 u32 dwArrayLen = 0, i = 0;
332 u32 *pdwArray = NULL;
333 struct r8192_priv *priv = rtllib_priv(dev);
334
335 if (priv->bTXPowerDataReadFromEEPORM) {
336 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
337 dwArrayLen = MACPHY_Array_PGLength;
338 pdwArray = Rtl819XMACPHY_Array_PG;
339
340 } else {
341 RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n");
342 dwArrayLen = MACPHY_ArrayLength;
343 pdwArray = Rtl819XMACPHY_Array;
344 }
345 for (i = 0; i < dwArrayLen; i += 3) {
346 RT_TRACE(COMP_DBG,
347 "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
348 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
349 if (pdwArray[i] == 0x318)
350 pdwArray[i+2] = 0x00000800;
351 rtl92e_set_bb_reg(dev, pdwArray[i], pdwArray[i+1],
352 pdwArray[i+2]);
353 }
354 return;
355
356 }
357
358 static void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
359 {
360 int i;
361 u32 *Rtl819XPHY_REGArray_Table = NULL;
362 u32 *Rtl819XAGCTAB_Array_Table = NULL;
363 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
364 struct r8192_priv *priv = rtllib_priv(dev);
365
366 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
367 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
368 if (priv->rf_type == RF_2T4R) {
369 PHY_REGArrayLen = PHY_REGArrayLength;
370 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
371 } else if (priv->rf_type == RF_1T2R) {
372 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
373 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
374 }
375
376 if (ConfigType == BaseBand_Config_PHY_REG) {
377 for (i = 0; i < PHY_REGArrayLen; i += 2) {
378 rtl92e_set_bb_reg(dev, Rtl819XPHY_REGArray_Table[i],
379 bMaskDWord,
380 Rtl819XPHY_REGArray_Table[i+1]);
381 RT_TRACE(COMP_DBG,
382 "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",
383 i, Rtl819XPHY_REGArray_Table[i],
384 Rtl819XPHY_REGArray_Table[i+1]);
385 }
386 } else if (ConfigType == BaseBand_Config_AGC_TAB) {
387 for (i = 0; i < AGCTAB_ArrayLen; i += 2) {
388 rtl92e_set_bb_reg(dev, Rtl819XAGCTAB_Array_Table[i],
389 bMaskDWord,
390 Rtl819XAGCTAB_Array_Table[i+1]);
391 RT_TRACE(COMP_DBG,
392 "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n",
393 i, Rtl819XAGCTAB_Array_Table[i],
394 Rtl819XAGCTAB_Array_Table[i+1]);
395 }
396 }
397 }
398
399 static void rtl8192_InitBBRFRegDef(struct net_device *dev)
400 {
401 struct r8192_priv *priv = rtllib_priv(dev);
402
403 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
404 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
405 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
406 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
407
408 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
409 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
410 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
411 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
412
413 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
414 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
415 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
416 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
417
418 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
419 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
420 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
421 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
422
423 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
424 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
425 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
426 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
427
428 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
429 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
430 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
431 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
432
433 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
434 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
435 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
436 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
437
438 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
439 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
440 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
441 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
442
443 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
444 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
445 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
446 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
447
448 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
449 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
450 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
451 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
452
453 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
454 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
455 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
456 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
457
458 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
459 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
460 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
461 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
462
463 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
464 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
465 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
466 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
467
468 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
469 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
470 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
471 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
472
473 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
474 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
475 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
476 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
477
478 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
479 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
480 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
481 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
482
483 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
484 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
485 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
486 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
487
488 }
489
490 bool rtl92e_check_bb_and_rf(struct net_device *dev, enum hw90_block CheckBlock,
491 enum rf90_radio_path eRFPath)
492 {
493 bool ret = true;
494 u32 i, CheckTimes = 4, dwRegRead = 0;
495 u32 WriteAddr[4];
496 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
497
498 WriteAddr[HW90_BLOCK_MAC] = 0x100;
499 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
500 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
501 WriteAddr[HW90_BLOCK_RF] = 0x3;
502 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__,
503 CheckBlock);
504
505 if (CheckBlock == HW90_BLOCK_MAC) {
506 netdev_warn(dev, "%s(): No checks available for MAC block.\n",
507 __func__);
508 return ret;
509 }
510
511 for (i = 0; i < CheckTimes; i++) {
512 switch (CheckBlock) {
513 case HW90_BLOCK_PHY0:
514 case HW90_BLOCK_PHY1:
515 rtl92e_writel(dev, WriteAddr[CheckBlock],
516 WriteData[i]);
517 dwRegRead = rtl92e_readl(dev, WriteAddr[CheckBlock]);
518 break;
519
520 case HW90_BLOCK_RF:
521 WriteData[i] &= 0xfff;
522 rtl92e_set_rf_reg(dev, eRFPath,
523 WriteAddr[HW90_BLOCK_RF],
524 bMask12Bits, WriteData[i]);
525 mdelay(10);
526 dwRegRead = rtl92e_get_rf_reg(dev, eRFPath,
527 WriteAddr[HW90_BLOCK_RF],
528 bMaskDWord);
529 mdelay(10);
530 break;
531
532 default:
533 ret = false;
534 break;
535 }
536
537
538 if (dwRegRead != WriteData[i]) {
539 netdev_warn(dev, "%s(): Check failed.\n", __func__);
540 ret = false;
541 break;
542 }
543 }
544
545 return ret;
546 }
547
548 static bool rtl8192_BB_Config_ParaFile(struct net_device *dev)
549 {
550 struct r8192_priv *priv = rtllib_priv(dev);
551 bool rtStatus = true;
552 u8 bRegValue = 0, eCheckItem = 0;
553 u32 dwRegValue = 0;
554
555 bRegValue = rtl92e_readb(dev, BB_GLOBAL_RESET);
556 rtl92e_writeb(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT));
557
558 dwRegValue = rtl92e_readl(dev, CPU_GEN);
559 rtl92e_writel(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
560
561 for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0;
562 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
563 rtStatus = rtl92e_check_bb_and_rf(dev,
564 (enum hw90_block)eCheckItem,
565 (enum rf90_radio_path)0);
566 if (!rtStatus) {
567 RT_TRACE((COMP_ERR | COMP_PHY),
568 "rtl92e_config_rf():Check PHY%d Fail!!\n",
569 eCheckItem-1);
570 return rtStatus;
571 }
572 }
573 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
574 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
575
576 dwRegValue = rtl92e_readl(dev, CPU_GEN);
577 rtl92e_writel(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
578
579 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
580
581 if (priv->IC_Cut > VERSION_8190_BD) {
582 if (priv->rf_type == RF_2T4R)
583 dwRegValue = (priv->AntennaTxPwDiff[2]<<8 |
584 priv->AntennaTxPwDiff[1]<<4 |
585 priv->AntennaTxPwDiff[0]);
586 else
587 dwRegValue = 0x0;
588 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
589 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
590
591
592 dwRegValue = priv->CrystalCap;
593 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, bXtalCap92x,
594 dwRegValue);
595 }
596
597 return rtStatus;
598 }
599 bool rtl92e_config_bb(struct net_device *dev)
600 {
601 rtl8192_InitBBRFRegDef(dev);
602 return rtl8192_BB_Config_ParaFile(dev);
603 }
604
605 void rtl92e_get_tx_power(struct net_device *dev)
606 {
607 struct r8192_priv *priv = rtllib_priv(dev);
608
609 priv->MCSTxPowerLevelOriginalOffset[0] =
610 rtl92e_readl(dev, rTxAGC_Rate18_06);
611 priv->MCSTxPowerLevelOriginalOffset[1] =
612 rtl92e_readl(dev, rTxAGC_Rate54_24);
613 priv->MCSTxPowerLevelOriginalOffset[2] =
614 rtl92e_readl(dev, rTxAGC_Mcs03_Mcs00);
615 priv->MCSTxPowerLevelOriginalOffset[3] =
616 rtl92e_readl(dev, rTxAGC_Mcs07_Mcs04);
617 priv->MCSTxPowerLevelOriginalOffset[4] =
618 rtl92e_readl(dev, rTxAGC_Mcs11_Mcs08);
619 priv->MCSTxPowerLevelOriginalOffset[5] =
620 rtl92e_readl(dev, rTxAGC_Mcs15_Mcs12);
621
622 priv->DefaultInitialGain[0] = rtl92e_readb(dev, rOFDM0_XAAGCCore1);
623 priv->DefaultInitialGain[1] = rtl92e_readb(dev, rOFDM0_XBAGCCore1);
624 priv->DefaultInitialGain[2] = rtl92e_readb(dev, rOFDM0_XCAGCCore1);
625 priv->DefaultInitialGain[3] = rtl92e_readb(dev, rOFDM0_XDAGCCore1);
626 RT_TRACE(COMP_INIT,
627 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
628 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
629 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
630
631 priv->framesync = rtl92e_readb(dev, rOFDM0_RxDetector3);
632 priv->framesyncC34 = rtl92e_readl(dev, rOFDM0_RxDetector2);
633 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
634 rOFDM0_RxDetector3, priv->framesync);
635 priv->SifsTime = rtl92e_readw(dev, SIFS);
636 }
637
638 void rtl92e_set_tx_power(struct net_device *dev, u8 channel)
639 {
640 struct r8192_priv *priv = rtllib_priv(dev);
641 u8 powerlevel = 0, powerlevelOFDM24G = 0;
642 char ant_pwr_diff;
643 u32 u4RegValue;
644
645 if (priv->epromtype == EEPROM_93C46) {
646 powerlevel = priv->TxPowerLevelCCK[channel-1];
647 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
648 } else if (priv->epromtype == EEPROM_93C56) {
649 if (priv->rf_type == RF_1T2R) {
650 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
651 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
652 } else if (priv->rf_type == RF_2T4R) {
653 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
654 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
655
656 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
657 - priv->TxPowerLevelOFDM24G_A[channel-1];
658
659 priv->RF_C_TxPwDiff = ant_pwr_diff;
660
661 ant_pwr_diff &= 0xf;
662
663 priv->AntennaTxPwDiff[2] = 0;
664 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);
665 priv->AntennaTxPwDiff[0] = 0;
666
667 u4RegValue = (priv->AntennaTxPwDiff[2]<<8 |
668 priv->AntennaTxPwDiff[1]<<4 |
669 priv->AntennaTxPwDiff[0]);
670
671 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
672 (bXBTxAGC|bXCTxAGC|bXDTxAGC),
673 u4RegValue);
674 }
675 }
676 switch (priv->rf_chip) {
677 case RF_8225:
678 break;
679 case RF_8256:
680 rtl92e_set_cck_tx_power(dev, powerlevel);
681 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G);
682 break;
683 case RF_8258:
684 break;
685 default:
686 netdev_err(dev, "Invalid RF Chip ID.\n");
687 break;
688 }
689 }
690
691 bool rtl92e_config_phy(struct net_device *dev)
692 {
693 struct r8192_priv *priv = rtllib_priv(dev);
694 bool rtStatus = true;
695
696 switch (priv->rf_chip) {
697 case RF_8225:
698 break;
699 case RF_8256:
700 rtStatus = rtl92e_config_rf(dev);
701 break;
702
703 case RF_8258:
704 break;
705 case RF_PSEUDO_11N:
706 break;
707
708 default:
709 netdev_err(dev, "Invalid RF Chip ID.\n");
710 break;
711 }
712 return rtStatus;
713 }
714
715 u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath)
716 {
717
718 int i;
719
720 switch (eRFPath) {
721 case RF90_PATH_A:
722 for (i = 0; i < RadioA_ArrayLength; i += 2) {
723 if (Rtl819XRadioA_Array[i] == 0xfe) {
724 msleep(100);
725 continue;
726 }
727 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioA_Array[i],
728 bMask12Bits,
729 Rtl819XRadioA_Array[i+1]);
730
731 }
732 break;
733 case RF90_PATH_B:
734 for (i = 0; i < RadioB_ArrayLength; i += 2) {
735 if (Rtl819XRadioB_Array[i] == 0xfe) {
736 msleep(100);
737 continue;
738 }
739 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioB_Array[i],
740 bMask12Bits,
741 Rtl819XRadioB_Array[i+1]);
742
743 }
744 break;
745 case RF90_PATH_C:
746 for (i = 0; i < RadioC_ArrayLength; i += 2) {
747 if (Rtl819XRadioC_Array[i] == 0xfe) {
748 msleep(100);
749 continue;
750 }
751 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioC_Array[i],
752 bMask12Bits,
753 Rtl819XRadioC_Array[i+1]);
754
755 }
756 break;
757 case RF90_PATH_D:
758 for (i = 0; i < RadioD_ArrayLength; i += 2) {
759 if (Rtl819XRadioD_Array[i] == 0xfe) {
760 msleep(100);
761 continue;
762 }
763 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioD_Array[i],
764 bMask12Bits,
765 Rtl819XRadioD_Array[i+1]);
766
767 }
768 break;
769 default:
770 break;
771 }
772
773 return 0;
774
775 }
776 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
777 {
778 struct r8192_priv *priv = rtllib_priv(dev);
779 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
780 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
781
782 switch (priv->rf_chip) {
783 case RF_8225:
784 break;
785
786 case RF_8256:
787 rtl92e_set_cck_tx_power(dev, powerlevel);
788 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G);
789 break;
790
791 case RF_8258:
792 break;
793 default:
794 netdev_warn(dev, "%s(): Invalid RF Chip ID\n", __func__);
795 break;
796 }
797 }
798
799 static u8 rtl8192_phy_SetSwChnlCmdArray(struct net_device *dev,
800 struct sw_chnl_cmd *CmdTable,
801 u32 CmdTableIdx, u32 CmdTableSz,
802 enum sw_chnl_cmd_id CmdID,
803 u32 Para1, u32 Para2, u32 msDelay)
804 {
805 struct sw_chnl_cmd *pCmd;
806
807 if (CmdTable == NULL) {
808 netdev_err(dev, "%s(): CmdTable cannot be NULL.\n", __func__);
809 return false;
810 }
811 if (CmdTableIdx >= CmdTableSz) {
812 netdev_err(dev, "%s(): Invalid index requested.\n", __func__);
813 return false;
814 }
815
816 pCmd = CmdTable + CmdTableIdx;
817 pCmd->CmdID = CmdID;
818 pCmd->Para1 = Para1;
819 pCmd->Para2 = Para2;
820 pCmd->msDelay = msDelay;
821
822 return true;
823 }
824
825 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
826 u8 *stage, u8 *step, u32 *delay)
827 {
828 struct r8192_priv *priv = rtllib_priv(dev);
829 struct rtllib_device *ieee = priv->rtllib;
830 u32 PreCommonCmdCnt;
831 u32 PostCommonCmdCnt;
832 u32 RfDependCmdCnt;
833 struct sw_chnl_cmd *CurrentCmd = NULL;
834 u8 eRFPath;
835
836 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n",
837 __func__, *stage, *step, channel);
838
839 if (!rtllib_legal_channel(priv->rtllib, channel)) {
840 netdev_err(dev, "Invalid channel requested: %d\n", channel);
841 return true;
842 }
843
844 {
845 PreCommonCmdCnt = 0;
846 rtl8192_phy_SetSwChnlCmdArray(dev, ieee->PreCommonCmd,
847 PreCommonCmdCnt++,
848 MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
849 0, 0, 0);
850 rtl8192_phy_SetSwChnlCmdArray(dev, ieee->PreCommonCmd,
851 PreCommonCmdCnt++,
852 MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
853
854 PostCommonCmdCnt = 0;
855
856 rtl8192_phy_SetSwChnlCmdArray(dev, ieee->PostCommonCmd,
857 PostCommonCmdCnt++,
858 MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
859
860 RfDependCmdCnt = 0;
861 switch (priv->rf_chip) {
862 case RF_8225:
863 if (!(channel >= 1 && channel <= 14)) {
864 netdev_err(dev,
865 "Invalid channel requested for 8225: %d\n",
866 channel);
867 return false;
868 }
869 rtl8192_phy_SetSwChnlCmdArray(dev, ieee->RfDependCmd,
870 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
871 CmdID_RF_WriteReg, rZebra1_Channel,
872 RF_CHANNEL_TABLE_ZEBRA[channel], 10);
873 rtl8192_phy_SetSwChnlCmdArray(dev, ieee->RfDependCmd,
874 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
875 CmdID_End, 0, 0, 0);
876 break;
877
878 case RF_8256:
879 if (!(channel >= 1 && channel <= 14)) {
880 netdev_err(dev,
881 "Invalid channel requested for 8256: %d\n",
882 channel);
883 return false;
884 }
885 rtl8192_phy_SetSwChnlCmdArray(dev, ieee->RfDependCmd,
886 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
887 CmdID_RF_WriteReg, rZebra1_Channel, channel,
888 10);
889 rtl8192_phy_SetSwChnlCmdArray(dev, ieee->RfDependCmd,
890
891 RfDependCmdCnt++,
892 MAX_RFDEPENDCMD_CNT,
893 CmdID_End, 0, 0, 0);
894 break;
895
896 case RF_8258:
897 break;
898
899 default:
900 netdev_warn(dev, "Unknown RF Chip ID\n");
901 return false;
902 }
903
904
905 do {
906 switch (*stage) {
907 case 0:
908 CurrentCmd = &ieee->PreCommonCmd[*step];
909 break;
910 case 1:
911 CurrentCmd = &ieee->RfDependCmd[*step];
912 break;
913 case 2:
914 CurrentCmd = &ieee->PostCommonCmd[*step];
915 break;
916 }
917
918 if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) {
919 if ((*stage) == 2)
920 return true;
921 (*stage)++;
922 (*step) = 0;
923 continue;
924 }
925
926 if (!CurrentCmd)
927 continue;
928 switch (CurrentCmd->CmdID) {
929 case CmdID_SetTxPowerLevel:
930 if (priv->IC_Cut > (u8)VERSION_8190_BD)
931 rtl8192_SetTxPowerLevel(dev, channel);
932 break;
933 case CmdID_WritePortUlong:
934 rtl92e_writel(dev, CurrentCmd->Para1,
935 CurrentCmd->Para2);
936 break;
937 case CmdID_WritePortUshort:
938 rtl92e_writew(dev, CurrentCmd->Para1,
939 (u16)CurrentCmd->Para2);
940 break;
941 case CmdID_WritePortUchar:
942 rtl92e_writeb(dev, CurrentCmd->Para1,
943 (u8)CurrentCmd->Para2);
944 break;
945 case CmdID_RF_WriteReg:
946 for (eRFPath = 0; eRFPath <
947 priv->NumTotalRFPath; eRFPath++)
948 rtl92e_set_rf_reg(dev,
949 (enum rf90_radio_path)eRFPath,
950 CurrentCmd->Para1, bMask12Bits,
951 CurrentCmd->Para2<<7);
952 break;
953 default:
954 break;
955 }
956
957 break;
958 } while (true);
959 } /*for (Number of RF paths)*/
960
961 (*delay) = CurrentCmd->msDelay;
962 (*step)++;
963 return false;
964 }
965
966 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
967 {
968 struct r8192_priv *priv = rtllib_priv(dev);
969 u32 delay = 0;
970
971 while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
972 &priv->SwChnlStep, &delay)) {
973 if (delay > 0)
974 msleep(delay);
975 if (!priv->up)
976 break;
977 }
978 }
979 static void rtl8192_SwChnl_WorkItem(struct net_device *dev)
980 {
981
982 struct r8192_priv *priv = rtllib_priv(dev);
983
984 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
985
986 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__,
987 priv->chan, priv);
988
989 rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
990
991 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
992 }
993
994 u8 rtl92e_set_channel(struct net_device *dev, u8 channel)
995 {
996 struct r8192_priv *priv = rtllib_priv(dev);
997
998 RT_TRACE(COMP_PHY, "=====>%s()\n", __func__);
999 if (!priv->up) {
1000 netdev_err(dev, "%s(): Driver is not initialized\n", __func__);
1001 return false;
1002 }
1003 if (priv->SwChnlInProgress)
1004 return false;
1005
1006
1007 switch (priv->rtllib->mode) {
1008 case WIRELESS_MODE_A:
1009 case WIRELESS_MODE_N_5G:
1010 if (channel <= 14) {
1011 netdev_warn(dev,
1012 "Channel %d not available in 802.11a.\n",
1013 channel);
1014 return false;
1015 }
1016 break;
1017 case WIRELESS_MODE_B:
1018 if (channel > 14) {
1019 netdev_warn(dev,
1020 "Channel %d not available in 802.11b.\n",
1021 channel);
1022 return false;
1023 }
1024 break;
1025 case WIRELESS_MODE_G:
1026 case WIRELESS_MODE_N_24G:
1027 if (channel > 14) {
1028 netdev_warn(dev,
1029 "Channel %d not available in 802.11g.\n",
1030 channel);
1031 return false;
1032 }
1033 break;
1034 }
1035
1036 priv->SwChnlInProgress = true;
1037 if (channel == 0)
1038 channel = 1;
1039
1040 priv->chan = channel;
1041
1042 priv->SwChnlStage = 0;
1043 priv->SwChnlStep = 0;
1044
1045 if (priv->up)
1046 rtl8192_SwChnl_WorkItem(dev);
1047 priv->SwChnlInProgress = false;
1048 return true;
1049 }
1050
1051 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev)
1052 {
1053 struct r8192_priv *priv = rtllib_priv(dev);
1054
1055 switch (priv->CurrentChannelBW) {
1056 case HT_CHANNEL_WIDTH_20:
1057 priv->CCKPresentAttentuation =
1058 priv->CCKPresentAttentuation_20Mdefault +
1059 priv->CCKPresentAttentuation_difference;
1060
1061 if (priv->CCKPresentAttentuation >
1062 (CCKTxBBGainTableLength-1))
1063 priv->CCKPresentAttentuation =
1064 CCKTxBBGainTableLength-1;
1065 if (priv->CCKPresentAttentuation < 0)
1066 priv->CCKPresentAttentuation = 0;
1067
1068 RT_TRACE(COMP_POWER_TRACKING,
1069 "20M, priv->CCKPresentAttentuation = %d\n",
1070 priv->CCKPresentAttentuation);
1071
1072 if (priv->rtllib->current_network.channel == 14 &&
1073 !priv->bcck_in_ch14) {
1074 priv->bcck_in_ch14 = true;
1075 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1076 } else if (priv->rtllib->current_network.channel !=
1077 14 && priv->bcck_in_ch14) {
1078 priv->bcck_in_ch14 = false;
1079 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1080 } else {
1081 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1082 }
1083 break;
1084
1085 case HT_CHANNEL_WIDTH_20_40:
1086 priv->CCKPresentAttentuation =
1087 priv->CCKPresentAttentuation_40Mdefault +
1088 priv->CCKPresentAttentuation_difference;
1089
1090 RT_TRACE(COMP_POWER_TRACKING,
1091 "40M, priv->CCKPresentAttentuation = %d\n",
1092 priv->CCKPresentAttentuation);
1093 if (priv->CCKPresentAttentuation >
1094 (CCKTxBBGainTableLength - 1))
1095 priv->CCKPresentAttentuation =
1096 CCKTxBBGainTableLength-1;
1097 if (priv->CCKPresentAttentuation < 0)
1098 priv->CCKPresentAttentuation = 0;
1099
1100 if (priv->rtllib->current_network.channel == 14 &&
1101 !priv->bcck_in_ch14) {
1102 priv->bcck_in_ch14 = true;
1103 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1104 } else if (priv->rtllib->current_network.channel != 14
1105 && priv->bcck_in_ch14) {
1106 priv->bcck_in_ch14 = false;
1107 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1108 } else {
1109 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1110 }
1111 break;
1112 }
1113 }
1114
1115 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
1116 {
1117 struct r8192_priv *priv = rtllib_priv(dev);
1118
1119 if (priv->rtllib->current_network.channel == 14 &&
1120 !priv->bcck_in_ch14)
1121 priv->bcck_in_ch14 = true;
1122 else if (priv->rtllib->current_network.channel != 14 &&
1123 priv->bcck_in_ch14)
1124 priv->bcck_in_ch14 = false;
1125
1126 switch (priv->CurrentChannelBW) {
1127 case HT_CHANNEL_WIDTH_20:
1128 if (priv->Record_CCK_20Mindex == 0)
1129 priv->Record_CCK_20Mindex = 6;
1130 priv->CCK_index = priv->Record_CCK_20Mindex;
1131 RT_TRACE(COMP_POWER_TRACKING,
1132 "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n",
1133 priv->CCK_index);
1134 break;
1135
1136 case HT_CHANNEL_WIDTH_20_40:
1137 priv->CCK_index = priv->Record_CCK_40Mindex;
1138 RT_TRACE(COMP_POWER_TRACKING,
1139 "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n",
1140 priv->CCK_index);
1141 break;
1142 }
1143 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1144 }
1145
1146 static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
1147 {
1148 struct r8192_priv *priv = rtllib_priv(dev);
1149
1150 if (priv->IC_Cut >= IC_VersionCut_D)
1151 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
1152 else
1153 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
1154 }
1155
1156 static void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1157 {
1158
1159 struct r8192_priv *priv = rtllib_priv(dev);
1160 u8 regBwOpMode;
1161
1162 RT_TRACE(COMP_SWBW,
1163 "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n",
1164 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ?
1165 "20MHz" : "40MHz");
1166
1167
1168 if (priv->rf_chip == RF_PSEUDO_11N) {
1169 priv->SetBWModeInProgress = false;
1170 return;
1171 }
1172 if (!priv->up) {
1173 netdev_err(dev, "%s(): Driver is not initialized\n", __func__);
1174 return;
1175 }
1176 regBwOpMode = rtl92e_readb(dev, BW_OPMODE);
1177
1178 switch (priv->CurrentChannelBW) {
1179 case HT_CHANNEL_WIDTH_20:
1180 regBwOpMode |= BW_OPMODE_20MHZ;
1181 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
1182 break;
1183
1184 case HT_CHANNEL_WIDTH_20_40:
1185 regBwOpMode &= ~BW_OPMODE_20MHZ;
1186 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
1187 break;
1188
1189 default:
1190 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__,
1191 priv->CurrentChannelBW);
1192 break;
1193 }
1194
1195 switch (priv->CurrentChannelBW) {
1196 case HT_CHANNEL_WIDTH_20:
1197 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1198 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1199
1200 if (!priv->btxpower_tracking) {
1201 rtl92e_writel(dev, rCCK0_TxFilter1, 0x1a1b0000);
1202 rtl92e_writel(dev, rCCK0_TxFilter2, 0x090e1317);
1203 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000204);
1204 } else {
1205 CCK_Tx_Power_Track_BW_Switch(dev);
1206 }
1207
1208 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1209
1210 break;
1211 case HT_CHANNEL_WIDTH_20_40:
1212 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1213 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1214
1215 if (!priv->btxpower_tracking) {
1216 rtl92e_writel(dev, rCCK0_TxFilter1, 0x35360000);
1217 rtl92e_writel(dev, rCCK0_TxFilter2, 0x121c252e);
1218 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000409);
1219 } else {
1220 CCK_Tx_Power_Track_BW_Switch(dev);
1221 }
1222
1223 rtl92e_set_bb_reg(dev, rCCK0_System, bCCKSideBand,
1224 (priv->nCur40MhzPrimeSC>>1));
1225 rtl92e_set_bb_reg(dev, rOFDM1_LSTF, 0xC00,
1226 priv->nCur40MhzPrimeSC);
1227
1228 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1229 break;
1230 default:
1231 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__,
1232 priv->CurrentChannelBW);
1233 break;
1234
1235 }
1236
1237 switch (priv->rf_chip) {
1238 case RF_8225:
1239 break;
1240
1241 case RF_8256:
1242 rtl92e_set_bandwidth(dev, priv->CurrentChannelBW);
1243 break;
1244
1245 case RF_8258:
1246 break;
1247
1248 case RF_PSEUDO_11N:
1249 break;
1250
1251 default:
1252 netdev_info(dev, "%s(): Unknown RFChipID: %d\n", __func__,
1253 priv->rf_chip);
1254 break;
1255 }
1256
1257 atomic_dec(&(priv->rtllib->atm_swbw));
1258 priv->SetBWModeInProgress = false;
1259
1260 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
1261 }
1262
1263 void rtl92e_set_bw_mode(struct net_device *dev, enum ht_channel_width Bandwidth,
1264 enum ht_extchnl_offset Offset)
1265 {
1266 struct r8192_priv *priv = rtllib_priv(dev);
1267
1268
1269 if (priv->SetBWModeInProgress)
1270 return;
1271
1272 atomic_inc(&(priv->rtllib->atm_swbw));
1273 priv->SetBWModeInProgress = true;
1274
1275 priv->CurrentChannelBW = Bandwidth;
1276
1277 if (Offset == HT_EXTCHNL_OFFSET_LOWER)
1278 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1279 else if (Offset == HT_EXTCHNL_OFFSET_UPPER)
1280 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1281 else
1282 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1283
1284 rtl8192_SetBWModeWorkItem(dev);
1285
1286 }
1287
1288 void rtl92e_init_gain(struct net_device *dev, u8 Operation)
1289 {
1290 #define SCAN_RX_INITIAL_GAIN 0x17
1291 #define POWER_DETECTION_TH 0x08
1292 struct r8192_priv *priv = rtllib_priv(dev);
1293 u32 BitMask;
1294 u8 initial_gain;
1295
1296 if (priv->up) {
1297 switch (Operation) {
1298 case IG_Backup:
1299 RT_TRACE(COMP_SCAN,
1300 "IG_Backup, backup the initial gain.\n");
1301 initial_gain = SCAN_RX_INITIAL_GAIN;
1302 BitMask = bMaskByte0;
1303 if (dm_digtable.dig_algorithm ==
1304 DIG_ALGO_BY_FALSE_ALARM)
1305 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
1306 priv->initgain_backup.xaagccore1 =
1307 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1,
1308 BitMask);
1309 priv->initgain_backup.xbagccore1 =
1310 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XBAGCCore1,
1311 BitMask);
1312 priv->initgain_backup.xcagccore1 =
1313 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XCAGCCore1,
1314 BitMask);
1315 priv->initgain_backup.xdagccore1 =
1316 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XDAGCCore1,
1317 BitMask);
1318 BitMask = bMaskByte2;
1319 priv->initgain_backup.cca = (u8)rtl92e_get_bb_reg(dev,
1320 rCCK0_CCA, BitMask);
1321
1322 RT_TRACE(COMP_SCAN,
1323 "Scan InitialGainBackup 0xc50 is %x\n",
1324 priv->initgain_backup.xaagccore1);
1325 RT_TRACE(COMP_SCAN,
1326 "Scan InitialGainBackup 0xc58 is %x\n",
1327 priv->initgain_backup.xbagccore1);
1328 RT_TRACE(COMP_SCAN,
1329 "Scan InitialGainBackup 0xc60 is %x\n",
1330 priv->initgain_backup.xcagccore1);
1331 RT_TRACE(COMP_SCAN,
1332 "Scan InitialGainBackup 0xc68 is %x\n",
1333 priv->initgain_backup.xdagccore1);
1334 RT_TRACE(COMP_SCAN,
1335 "Scan InitialGainBackup 0xa0a is %x\n",
1336 priv->initgain_backup.cca);
1337
1338 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1339 initial_gain);
1340 rtl92e_writeb(dev, rOFDM0_XAAGCCore1, initial_gain);
1341 rtl92e_writeb(dev, rOFDM0_XBAGCCore1, initial_gain);
1342 rtl92e_writeb(dev, rOFDM0_XCAGCCore1, initial_gain);
1343 rtl92e_writeb(dev, rOFDM0_XDAGCCore1, initial_gain);
1344 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1345 POWER_DETECTION_TH);
1346 rtl92e_writeb(dev, 0xa0a, POWER_DETECTION_TH);
1347 break;
1348 case IG_Restore:
1349 RT_TRACE(COMP_SCAN,
1350 "IG_Restore, restore the initial gain.\n");
1351 BitMask = 0x7f;
1352 if (dm_digtable.dig_algorithm ==
1353 DIG_ALGO_BY_FALSE_ALARM)
1354 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
1355
1356 rtl92e_set_bb_reg(dev, rOFDM0_XAAGCCore1, BitMask,
1357 (u32)priv->initgain_backup.xaagccore1);
1358 rtl92e_set_bb_reg(dev, rOFDM0_XBAGCCore1, BitMask,
1359 (u32)priv->initgain_backup.xbagccore1);
1360 rtl92e_set_bb_reg(dev, rOFDM0_XCAGCCore1, BitMask,
1361 (u32)priv->initgain_backup.xcagccore1);
1362 rtl92e_set_bb_reg(dev, rOFDM0_XDAGCCore1, BitMask,
1363 (u32)priv->initgain_backup.xdagccore1);
1364 BitMask = bMaskByte2;
1365 rtl92e_set_bb_reg(dev, rCCK0_CCA, BitMask,
1366 (u32)priv->initgain_backup.cca);
1367
1368 RT_TRACE(COMP_SCAN,
1369 "Scan BBInitialGainRestore 0xc50 is %x\n",
1370 priv->initgain_backup.xaagccore1);
1371 RT_TRACE(COMP_SCAN,
1372 "Scan BBInitialGainRestore 0xc58 is %x\n",
1373 priv->initgain_backup.xbagccore1);
1374 RT_TRACE(COMP_SCAN,
1375 "Scan BBInitialGainRestore 0xc60 is %x\n",
1376 priv->initgain_backup.xcagccore1);
1377 RT_TRACE(COMP_SCAN,
1378 "Scan BBInitialGainRestore 0xc68 is %x\n",
1379 priv->initgain_backup.xdagccore1);
1380 RT_TRACE(COMP_SCAN,
1381 "Scan BBInitialGainRestore 0xa0a is %x\n",
1382 priv->initgain_backup.cca);
1383
1384 rtl92e_set_tx_power(dev,
1385 priv->rtllib->current_network.channel);
1386
1387 if (dm_digtable.dig_algorithm ==
1388 DIG_ALGO_BY_FALSE_ALARM)
1389 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1);
1390 break;
1391 default:
1392 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
1393 break;
1394 }
1395 }
1396 }
1397
1398 void rtl92e_set_rf_off(struct net_device *dev)
1399 {
1400
1401 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
1402 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);
1403 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);
1404 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1405 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1406 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
1407 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
1408 rtl92e_writeb(dev, ANAPAR_FOR_8192PciE, 0x07);
1409
1410 }
1411
1412 static bool SetRFPowerState8190(struct net_device *dev,
1413 enum rt_rf_power_state eRFPowerState)
1414 {
1415 struct r8192_priv *priv = rtllib_priv(dev);
1416 struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)
1417 (&(priv->rtllib->PowerSaveControl));
1418 bool bResult = true;
1419 u8 i = 0, QueueID = 0;
1420 struct rtl8192_tx_ring *ring = NULL;
1421
1422 if (priv->SetRFPowerStateInProgress)
1423 return false;
1424 RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n");
1425 priv->SetRFPowerStateInProgress = true;
1426
1427 switch (priv->rf_chip) {
1428 case RF_8256:
1429 switch (eRFPowerState) {
1430 case eRfOn:
1431 RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn!\n");
1432 if ((priv->rtllib->eRFPowerState == eRfOff) &&
1433 RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1434 bool rtstatus = true;
1435 u32 InitilizeCount = 3;
1436
1437 do {
1438 InitilizeCount--;
1439 priv->RegRfOff = false;
1440 rtstatus = rtl92e_enable_nic(dev);
1441 } while (!rtstatus && (InitilizeCount > 0));
1442
1443 if (!rtstatus) {
1444 netdev_err(dev,
1445 "%s(): Failed to initialize Adapter.\n",
1446 __func__);
1447 priv->SetRFPowerStateInProgress = false;
1448 return false;
1449 }
1450
1451 RT_CLEAR_PS_LEVEL(pPSC,
1452 RT_RF_OFF_LEVL_HALT_NIC);
1453 } else {
1454 rtl92e_writeb(dev, ANAPAR, 0x37);
1455 mdelay(1);
1456 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1457 0x4, 0x1);
1458 priv->bHwRfOffAction = 0;
1459
1460 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE,
1461 BIT4, 0x1);
1462 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4,
1463 0x300, 0x3);
1464 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1465 0x18, 0x3);
1466 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable,
1467 0x3, 0x3);
1468 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable,
1469 0x3, 0x3);
1470 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1471 0x60, 0x3);
1472
1473 }
1474
1475 break;
1476
1477 case eRfSleep:
1478 if (priv->rtllib->eRFPowerState == eRfOff)
1479 break;
1480
1481
1482 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1483 ring = &priv->tx_ring[QueueID];
1484
1485 if (skb_queue_len(&ring->queue) == 0) {
1486 QueueID++;
1487 continue;
1488 } else {
1489 RT_TRACE((COMP_POWER|COMP_RF),
1490 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n",
1491 (i+1), QueueID);
1492 udelay(10);
1493 i++;
1494 }
1495
1496 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1497 RT_TRACE(COMP_POWER,
1498 "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n",
1499 MAX_DOZE_WAITING_TIMES_9x,
1500 QueueID);
1501 break;
1502 }
1503 }
1504 rtl92e_set_rf_off(dev);
1505 break;
1506
1507 case eRfOff:
1508 RT_TRACE(COMP_PS,
1509 "SetRFPowerState8190() eRfOff/Sleep !\n");
1510
1511 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1512 ring = &priv->tx_ring[QueueID];
1513
1514 if (skb_queue_len(&ring->queue) == 0) {
1515 QueueID++;
1516 continue;
1517 } else {
1518 RT_TRACE(COMP_POWER,
1519 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n",
1520 (i+1), QueueID);
1521 udelay(10);
1522 i++;
1523 }
1524
1525 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1526 RT_TRACE(COMP_POWER,
1527 "\n\n\n SetZebra: RFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n",
1528 MAX_DOZE_WAITING_TIMES_9x,
1529 QueueID);
1530 break;
1531 }
1532 }
1533
1534 if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC &&
1535 !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1536 rtl92e_disable_nic(dev);
1537 RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1538 } else if (!(pPSC->RegRfPsLevel &
1539 RT_RF_OFF_LEVL_HALT_NIC)) {
1540 rtl92e_set_rf_off(dev);
1541 }
1542
1543 break;
1544
1545 default:
1546 bResult = false;
1547 netdev_warn(dev,
1548 "%s(): Unknown state requested: 0x%X.\n",
1549 __func__, eRFPowerState);
1550 break;
1551 }
1552
1553 break;
1554
1555 default:
1556 netdev_warn(dev, "%s(): Unknown RF type\n", __func__);
1557 break;
1558 }
1559
1560 if (bResult) {
1561 priv->rtllib->eRFPowerState = eRFPowerState;
1562
1563 switch (priv->rf_chip) {
1564 case RF_8256:
1565 break;
1566
1567 default:
1568 netdev_warn(dev, "%s(): Unknown RF type\n", __func__);
1569 break;
1570 }
1571 }
1572
1573 priv->SetRFPowerStateInProgress = false;
1574 RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n",
1575 bResult);
1576 return bResult;
1577 }
1578
1579 bool rtl92e_set_rf_power_state(struct net_device *dev,
1580 enum rt_rf_power_state eRFPowerState)
1581 {
1582 struct r8192_priv *priv = rtllib_priv(dev);
1583
1584 bool bResult = false;
1585
1586 RT_TRACE(COMP_PS,
1587 "---------> rtl92e_set_rf_power_state(): eRFPowerState(%d)\n",
1588 eRFPowerState);
1589 if (eRFPowerState == priv->rtllib->eRFPowerState &&
1590 priv->bHwRfOffAction == 0) {
1591 RT_TRACE(COMP_PS,
1592 "<--------- rtl92e_set_rf_power_state(): discard the request for eRFPowerState(%d) is the same.\n",
1593 eRFPowerState);
1594 return bResult;
1595 }
1596
1597 bResult = SetRFPowerState8190(dev, eRFPowerState);
1598
1599 RT_TRACE(COMP_PS,
1600 "<--------- rtl92e_set_rf_power_state(): bResult(%d)\n",
1601 bResult);
1602
1603 return bResult;
1604 }
1605
1606 void rtl92e_scan_op_backup(struct net_device *dev, u8 Operation)
1607 {
1608 struct r8192_priv *priv = rtllib_priv(dev);
1609
1610 if (priv->up) {
1611 switch (Operation) {
1612 case SCAN_OPT_BACKUP:
1613 priv->rtllib->InitialGainHandler(dev, IG_Backup);
1614 break;
1615
1616 case SCAN_OPT_RESTORE:
1617 priv->rtllib->InitialGainHandler(dev, IG_Restore);
1618 break;
1619
1620 default:
1621 RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n");
1622 break;
1623 }
1624 }
1625
1626 }
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