drivers/staging/rtl8192e/rtl819x_HT.h

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * This program is distributed in the hope that it will be useful, but WITHOUT
   5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   7  * more details.
   8  *
   9  * You should have received a copy of the GNU General Public License along with
  10  * this program; if not, write to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  12  *
  13  * The full GNU General Public License is included in this distribution in the
  14  * file called LICENSE.
  15  *
  16  * Contact Information:
  17  * wlanfae <wlanfae@realtek.com>
  18 ******************************************************************************/
  19 #ifndef _RTL819XU_HTTYPE_H_
  20 #define _RTL819XU_HTTYPE_H_
  21
  22 #define MIMO_PS_STATIC                          0
  23 #define MIMO_PS_DYNAMIC                 1
  24 #define MIMO_PS_NOLIMIT                 3
  25
  26 #define sHTCLng 4
  27
  28 enum ht_channel_width {
  29         HT_CHANNEL_WIDTH_20 = 0,
  30         HT_CHANNEL_WIDTH_20_40 = 1,
  31 };
  32
  33 enum ht_extchnl_offset {
  34         HT_EXTCHNL_OFFSET_NO_EXT = 0,
  35         HT_EXTCHNL_OFFSET_UPPER = 1,
  36         HT_EXTCHNL_OFFSET_NO_DEF = 2,
  37         HT_EXTCHNL_OFFSET_LOWER = 3,
  38 };
  39
  40 struct ht_capab_ele {
  41
  42         u8      AdvCoding:1;
  43         u8      ChlWidth:1;
  44         u8      MimoPwrSave:2;
  45         u8      GreenField:1;
  46         u8      ShortGI20Mhz:1;
  47         u8      ShortGI40Mhz:1;
  48         u8      TxSTBC:1;
  49         u8      RxSTBC:2;
  50         u8      DelayBA:1;
  51         u8      MaxAMSDUSize:1;
  52         u8      DssCCk:1;
  53         u8      PSMP:1;
  54         u8      Rsvd1:1;
  55         u8      LSigTxopProtect:1;
  56
  57         u8      MaxRxAMPDUFactor:2;
  58         u8      MPDUDensity:3;
  59         u8      Rsvd2:3;
  60
  61         u8      MCS[16];
  62
  63
  64         u16     ExtHTCapInfo;
  65
  66         u8      TxBFCap[4];
  67
  68         u8      ASCap;
  69
  70 } __packed;
  71
  72
  73 struct ht_info_ele {
  74         u8      ControlChl;
  75
  76         u8      ExtChlOffset:2;
  77         u8      RecommemdedTxWidth:1;
  78         u8      RIFS:1;
  79         u8      PSMPAccessOnly:1;
  80         u8      SrvIntGranularity:3;
  81
  82         u8      OptMode:2;
  83         u8      NonGFDevPresent:1;
  84         u8      Revd1:5;
  85         u8      Revd2:8;
  86
  87         u8      Rsvd3:6;
  88         u8      DualBeacon:1;
  89         u8      DualCTSProtect:1;
  90
  91         u8      SecondaryBeacon:1;
  92         u8      LSigTxopProtectFull:1;
  93         u8      PcoActive:1;
  94         u8      PcoPhase:1;
  95         u8      Rsvd4:4;
  96
  97         u8      BasicMSC[16];
  98 } __packed;
  99
 100 enum ht_spec_ver {
 101         HT_SPEC_VER_IEEE = 0,
 102         HT_SPEC_VER_EWC = 1,
 103 };
 104
 105 enum ht_aggre_mode {
 106         HT_AGG_AUTO = 0,
 107         HT_AGG_FORCE_ENABLE = 1,
 108         HT_AGG_FORCE_DISABLE = 2,
 109 };
 110
 111
 112 struct rt_hi_throughput {
 113         u8                              bEnableHT;
 114         u8                              bCurrentHTSupport;
 115
 116         u8                              bRegBW40MHz;
 117         u8                              bCurBW40MHz;
 118
 119         u8                              bRegShortGI40MHz;
 120         u8                              bCurShortGI40MHz;
 121
 122         u8                              bRegShortGI20MHz;
 123         u8                              bCurShortGI20MHz;
 124
 125         u8                              bRegSuppCCK;
 126         u8                              bCurSuppCCK;
 127
 128         enum ht_spec_ver ePeerHTSpecVer;
 129
 130
 131         struct ht_capab_ele SelfHTCap;
 132         struct ht_info_ele SelfHTInfo;
 133
 134         u8                              PeerHTCapBuf[32];
 135         u8                              PeerHTInfoBuf[32];
 136
 137
 138         u8                              bAMSDU_Support;
 139         u16                             nAMSDU_MaxSize;
 140         u8                              bCurrent_AMSDU_Support;
 141         u16                             nCurrent_AMSDU_MaxSize;
 142
 143         u8                              bAMPDUEnable;
 144         u8                              bCurrentAMPDUEnable;
 145         u8                              AMPDU_Factor;
 146         u8                              CurrentAMPDUFactor;
 147         u8                              MPDU_Density;
 148         u8                              CurrentMPDUDensity;
 149
 150         enum ht_aggre_mode ForcedAMPDUMode;
 151         u8                              ForcedAMPDUFactor;
 152         u8                              ForcedMPDUDensity;
 153
 154         enum ht_aggre_mode ForcedAMSDUMode;
 155         u16                             ForcedAMSDUMaxSize;
 156
 157         u8                              bForcedShortGI;
 158
 159         u8                              CurrentOpMode;
 160
 161         u8                              SelfMimoPs;
 162         u8                              PeerMimoPs;
 163
 164         enum ht_extchnl_offset CurSTAExtChnlOffset;
 165         u8                              bCurTxBW40MHz;
 166         u8                              PeerBandwidth;
 167
 168         u8                              bSwBwInProgress;
 169         u8                              SwBwStep;
 170
 171         u8                              bRegRT2RTAggregation;
 172         u8                              RT2RT_HT_Mode;
 173         u8                              bCurrentRT2RTAggregation;
 174         u8                              bCurrentRT2RTLongSlotTime;
 175         u8                              szRT2RTAggBuffer[10];
 176
 177         u8                              bRegRxReorderEnable;
 178         u8                              bCurRxReorderEnable;
 179         u8                              RxReorderWinSize;
 180         u8                              RxReorderPendingTime;
 181         u16                             RxReorderDropCounter;
 182
 183         u8                              bIsPeerBcm;
 184
 185         u8                              IOTPeer;
 186         u32                             IOTAction;
 187         u8                              IOTRaFunc;
 188
 189         u8      bWAIotBroadcom;
 190         u8      WAIotTH;
 191
 192         u8                              bAcceptAddbaReq;
 193 } __packed;
 194
 195 struct bss_ht {
 196
 197         u8                              bdSupportHT;
 198
 199         u8                                      bdHTCapBuf[32];
 200         u16                                     bdHTCapLen;
 201         u8                                      bdHTInfoBuf[32];
 202         u16                                     bdHTInfoLen;
 203
 204         enum ht_spec_ver bdHTSpecVer;
 205         enum ht_channel_width bdBandWidth;
 206
 207         u8                                      bdRT2RTAggregation;
 208         u8                                      bdRT2RTLongSlotTime;
 209         u8                                      RT2RT_HT_Mode;
 210         u8                                      bdHT1R;
 211 };
 212
 213 extern u8 MCS_FILTER_ALL[16];
 214 extern u8 MCS_FILTER_1SS[16];
 215
 216 #define RATE_ADPT_1SS_MASK              0xFF
 217 #define RATE_ADPT_2SS_MASK              0xF0
 218 #define RATE_ADPT_MCS32_MASK            0x01
 219
 220 enum ht_aggre_size {
 221         HT_AGG_SIZE_8K = 0,
 222         HT_AGG_SIZE_16K = 1,
 223         HT_AGG_SIZE_32K = 2,
 224         HT_AGG_SIZE_64K = 3,
 225 };
 226
 227 enum ht_iot_peer {
 228         HT_IOT_PEER_UNKNOWN = 0,
 229         HT_IOT_PEER_REALTEK = 1,
 230         HT_IOT_PEER_REALTEK_92SE = 2,
 231         HT_IOT_PEER_BROADCOM = 3,
 232         HT_IOT_PEER_RALINK = 4,
 233         HT_IOT_PEER_ATHEROS = 5,
 234         HT_IOT_PEER_CISCO = 6,
 235         HT_IOT_PEER_MARVELL = 7,
 236         HT_IOT_PEER_92U_SOFTAP = 8,
 237         HT_IOT_PEER_SELF_SOFTAP = 9,
 238         HT_IOT_PEER_AIRGO = 10,
 239         HT_IOT_PEER_MAX = 11,
 240 };
 241
 242 enum ht_iot_action {
 243         HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
 244         HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
 245         HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
 246         HT_IOT_ACT_DISABLE_MCS15 = 0x00000008,
 247         HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010,
 248         HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020,
 249         HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040,
 250         HT_IOT_ACT_CDD_FSYNC = 0x00000080,
 251         HT_IOT_ACT_PURE_N_MODE = 0x00000100,
 252         HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200,
 253         HT_IOT_ACT_FORCED_RTS = 0x00000400,
 254         HT_IOT_ACT_AMSDU_ENABLE = 0x00000800,
 255         HT_IOT_ACT_REJECT_ADDBA_REQ = 0x00001000,
 256         HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT = 0x00002000,
 257         HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00004000,
 258
 259         HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000,
 260         HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000,
 261         HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000,
 262         HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000,
 263         HT_IOT_ACT_TX_NO_AGGREGATION = 0x00100000,
 264         HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000,
 265
 266         HT_IOT_ACT_MID_HIGHPOWER = 0x00400000,
 267         HT_IOT_ACT_NULL_DATA_POWER_SAVING = 0x00800000,
 268
 269         HT_IOT_ACT_DISABLE_CCK_RATE = 0x01000000,
 270         HT_IOT_ACT_FORCED_ENABLE_BE_TXOP = 0x02000000,
 271         HT_IOT_ACT_WA_IOT_Broadcom = 0x04000000,
 272
 273         HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI = 0x08000000,
 274
 275 };
 276
 277 enum ht_iot_rafunc {
 278         HT_IOT_RAFUNC_DISABLE_ALL = 0x00,
 279         HT_IOT_RAFUNC_PEER_1R = 0x01,
 280         HT_IOT_RAFUNC_TX_AMSDU = 0x02,
 281 };
 282
 283 enum rt_ht_capability {
 284         RT_HT_CAP_USE_TURBO_AGGR = 0x01,
 285         RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
 286         RT_HT_CAP_USE_AMPDU = 0x04,
 287         RT_HT_CAP_USE_WOW = 0x8,
 288         RT_HT_CAP_USE_SOFTAP = 0x10,
 289         RT_HT_CAP_USE_92SE = 0x20,
 290 };
 291
 292 #endif