1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
9 * The full GNU General Public License is included in this distribution in the
10 * file called LICENSE.
12 * Contact Information:
13 * wlanfae <wlanfae@realtek.com>
14 *****************************************************************************/
15 #ifndef _RTL819XU_HTTYPE_H_
16 #define _RTL819XU_HTTYPE_H_
18 #define MIMO_PS_STATIC 0
22 enum ht_channel_width
{
23 HT_CHANNEL_WIDTH_20
= 0,
24 HT_CHANNEL_WIDTH_20_40
= 1,
27 enum ht_extchnl_offset
{
28 HT_EXTCHNL_OFFSET_NO_EXT
= 0,
29 HT_EXTCHNL_OFFSET_UPPER
= 1,
30 HT_EXTCHNL_OFFSET_NO_DEF
= 2,
31 HT_EXTCHNL_OFFSET_LOWER
= 3,
51 u8 MaxRxAMPDUFactor
:2;
71 u8 RecommemdedTxWidth
:1;
74 u8 SrvIntGranularity
:3;
86 u8 LSigTxopProtectFull
:1;
101 HT_AGG_FORCE_ENABLE
= 1,
102 HT_AGG_FORCE_DISABLE
= 2,
106 struct rt_hi_throughput
{
108 u8 bCurrentHTSupport
;
122 enum ht_spec_ver ePeerHTSpecVer
;
125 struct ht_capab_ele SelfHTCap
;
126 struct ht_info_ele SelfHTInfo
;
129 u8 PeerHTInfoBuf
[32];
134 u8 bCurrent_AMSDU_Support
;
135 u16 nCurrent_AMSDU_MaxSize
;
138 u8 bCurrentAMPDUEnable
;
140 u8 CurrentAMPDUFactor
;
142 u8 CurrentMPDUDensity
;
144 enum ht_aggre_mode ForcedAMPDUMode
;
145 u8 ForcedAMPDUFactor
;
146 u8 ForcedMPDUDensity
;
148 enum ht_aggre_mode ForcedAMSDUMode
;
149 u16 ForcedAMSDUMaxSize
;
158 enum ht_extchnl_offset CurSTAExtChnlOffset
;
165 u8 bRegRT2RTAggregation
;
167 u8 bCurrentRT2RTAggregation
;
168 u8 bCurrentRT2RTLongSlotTime
;
169 u8 szRT2RTAggBuffer
[10];
171 u8 bRegRxReorderEnable
;
172 u8 bCurRxReorderEnable
;
174 u8 RxReorderPendingTime
;
175 u16 RxReorderDropCounter
;
198 enum ht_spec_ver bdHTSpecVer
;
199 enum ht_channel_width bdBandWidth
;
201 u8 bdRT2RTAggregation
;
202 u8 bdRT2RTLongSlotTime
;
207 extern u8 MCS_FILTER_ALL
[16];
208 extern u8 MCS_FILTER_1SS
[16];
210 #define RATE_ADPT_1SS_MASK 0xFF
211 #define RATE_ADPT_2SS_MASK 0xF0
212 #define RATE_ADPT_MCS32_MASK 0x01
222 HT_IOT_PEER_UNKNOWN
= 0,
223 HT_IOT_PEER_REALTEK
= 1,
224 HT_IOT_PEER_REALTEK_92SE
= 2,
225 HT_IOT_PEER_BROADCOM
= 3,
226 HT_IOT_PEER_RALINK
= 4,
227 HT_IOT_PEER_ATHEROS
= 5,
228 HT_IOT_PEER_CISCO
= 6,
229 HT_IOT_PEER_MARVELL
= 7,
230 HT_IOT_PEER_92U_SOFTAP
= 8,
231 HT_IOT_PEER_SELF_SOFTAP
= 9,
232 HT_IOT_PEER_AIRGO
= 10,
233 HT_IOT_PEER_MAX
= 11,
237 HT_IOT_ACT_TX_USE_AMSDU_4K
= 0x00000001,
238 HT_IOT_ACT_TX_USE_AMSDU_8K
= 0x00000002,
239 HT_IOT_ACT_DISABLE_MCS14
= 0x00000004,
240 HT_IOT_ACT_DISABLE_MCS15
= 0x00000008,
241 HT_IOT_ACT_DISABLE_ALL_2SS
= 0x00000010,
242 HT_IOT_ACT_DISABLE_EDCA_TURBO
= 0x00000020,
243 HT_IOT_ACT_MGNT_USE_CCK_6M
= 0x00000040,
244 HT_IOT_ACT_CDD_FSYNC
= 0x00000080,
245 HT_IOT_ACT_PURE_N_MODE
= 0x00000100,
246 HT_IOT_ACT_FORCED_CTS2SELF
= 0x00000200,
247 HT_IOT_ACT_FORCED_RTS
= 0x00000400,
248 HT_IOT_ACT_AMSDU_ENABLE
= 0x00000800,
249 HT_IOT_ACT_REJECT_ADDBA_REQ
= 0x00001000,
250 HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT
= 0x00002000,
251 HT_IOT_ACT_EDCA_BIAS_ON_RX
= 0x00004000,
253 HT_IOT_ACT_HYBRID_AGGREGATION
= 0x00010000,
254 HT_IOT_ACT_DISABLE_SHORT_GI
= 0x00020000,
255 HT_IOT_ACT_DISABLE_HIGH_POWER
= 0x00040000,
256 HT_IOT_ACT_DISABLE_TX_40_MHZ
= 0x00080000,
257 HT_IOT_ACT_TX_NO_AGGREGATION
= 0x00100000,
258 HT_IOT_ACT_DISABLE_TX_2SS
= 0x00200000,
260 HT_IOT_ACT_MID_HIGHPOWER
= 0x00400000,
261 HT_IOT_ACT_NULL_DATA_POWER_SAVING
= 0x00800000,
263 HT_IOT_ACT_DISABLE_CCK_RATE
= 0x01000000,
264 HT_IOT_ACT_FORCED_ENABLE_BE_TXOP
= 0x02000000,
265 HT_IOT_ACT_WA_IOT_Broadcom
= 0x04000000,
267 HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI
= 0x08000000,
272 HT_IOT_RAFUNC_DISABLE_ALL
= 0x00,
273 HT_IOT_RAFUNC_PEER_1R
= 0x01,
274 HT_IOT_RAFUNC_TX_AMSDU
= 0x02,
277 enum rt_ht_capability
{
278 RT_HT_CAP_USE_TURBO_AGGR
= 0x01,
279 RT_HT_CAP_USE_LONG_PREAMBLE
= 0x02,
280 RT_HT_CAP_USE_AMPDU
= 0x04,
281 RT_HT_CAP_USE_WOW
= 0x8,
282 RT_HT_CAP_USE_SOFTAP
= 0x10,
283 RT_HT_CAP_USE_92SE
= 0x20,