1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
9 * You should have received a copy of the GNU General Public License along with
10 * this program; if not, write to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
13 * The full GNU General Public License is included in this distribution in the
14 * file called LICENSE.
16 * Contact Information:
17 * wlanfae <wlanfae@realtek.com>
18 ******************************************************************************/
19 #ifndef _RTL819XU_HTTYPE_H_
20 #define _RTL819XU_HTTYPE_H_
23 #define HT_OPMODE_NO_PROTECT 0
24 #define HT_OPMODE_OPTIONAL 1
25 #define HT_OPMODE_40MHZ_PROTECT 2
26 #define HT_OPMODE_MIXED 3
28 #define MIMO_PS_STATIC 0
29 #define MIMO_PS_DYNAMIC 1
30 #define MIMO_PS_NOLIMIT 3
37 #define HT_SUPPORTED_MCS_1SS_BITMAP 0x000000ff
38 #define HT_SUPPORTED_MCS_2SS_BITMAP 0x0000ff00
39 #define HT_SUPPORTED_MCS_1SS_2SS_BITMAP \
40 (HT_MCS_1SS_BITMAP | HT_MCS_1SS_2SS_BITMAP)
53 HT_MCS10
= 0x00000400,
54 HT_MCS11
= 0x00000800,
55 HT_MCS12
= 0x00001000,
56 HT_MCS13
= 0x00002000,
57 HT_MCS14
= 0x00004000,
58 HT_MCS15
= 0x00008000,
61 enum ht_channel_width
{
62 HT_CHANNEL_WIDTH_20
= 0,
63 HT_CHANNEL_WIDTH_20_40
= 1,
66 enum ht_extchnl_offset
{
67 HT_EXTCHNL_OFFSET_NO_EXT
= 0,
68 HT_EXTCHNL_OFFSET_UPPER
= 1,
69 HT_EXTCHNL_OFFSET_NO_DEF
= 2,
70 HT_EXTCHNL_OFFSET_LOWER
= 3,
81 ACT_RECOMMAND_WIDTH
= 0,
82 ACT_MIMO_PWR_SAVE
= 1,
84 ACT_SET_PCO_PHASE
= 3,
85 ACT_MIMO_CHL_MEASURE
= 4,
86 ACT_RECIPROCITY_CORRECT
= 5,
87 ACT_MIMO_CSI_MATRICS
= 6,
88 ACT_MIMO_NOCOMPR_STEER
= 7,
89 ACT_MIMO_COMPR_STEER
= 8,
90 ACT_ANTENNA_SELECT
= 9,
95 SC_MODE_DUPLICATE
= 0,
98 SC_MODE_FULL40MHZ
= 3,
101 struct ht_capab_ele
{
116 u8 LSigTxopProtect
:1;
118 u8 MaxRxAMPDUFactor
:2;
138 u8 RecommemdedTxWidth
:1;
141 u8 SrvIntGranularity
:3;
144 u8 NonGFDevPresent
:1;
152 u8 SecondaryBeacon
:1;
153 u8 LSigTxopProtectFull
:1;
168 HT_SPEC_VER_IEEE
= 0,
174 HT_AGG_FORCE_ENABLE
= 1,
175 HT_AGG_FORCE_DISABLE
= 2,
179 struct rt_hi_throughput
{
181 u8 bCurrentHTSupport
;
195 enum ht_spec_ver ePeerHTSpecVer
;
198 struct ht_capab_ele SelfHTCap
;
199 struct ht_info_ele SelfHTInfo
;
202 u8 PeerHTInfoBuf
[32];
207 u8 bCurrent_AMSDU_Support
;
208 u16 nCurrent_AMSDU_MaxSize
;
211 u8 bCurrentAMPDUEnable
;
213 u8 CurrentAMPDUFactor
;
215 u8 CurrentMPDUDensity
;
217 enum ht_aggre_mode ForcedAMPDUMode
;
218 u8 ForcedAMPDUFactor
;
219 u8 ForcedMPDUDensity
;
221 enum ht_aggre_mode ForcedAMSDUMode
;
222 u16 ForcedAMSDUMaxSize
;
231 enum ht_extchnl_offset CurSTAExtChnlOffset
;
239 u8 bRegRT2RTAggregation
;
241 u8 bCurrentRT2RTAggregation
;
242 u8 bCurrentRT2RTLongSlotTime
;
243 u8 szRT2RTAggBuffer
[10];
245 u8 bRegRxReorderEnable
;
246 u8 bCurRxReorderEnable
;
248 u8 RxReorderPendingTime
;
249 u16 RxReorderDropCounter
;
265 struct rt_htinfo_sta_entry
{
275 u8 HTHighestOperaRate
;
289 u8 bCurRxReorderEnable
;
309 enum ht_spec_ver bdHTSpecVer
;
310 enum ht_channel_width bdBandWidth
;
312 u8 bdRT2RTAggregation
;
313 u8 bdRT2RTLongSlotTime
;
332 struct false_alarm_stats
{
334 u32 Cnt_Rate_Illegal
;
343 extern u8 MCS_FILTER_ALL
[16];
344 extern u8 MCS_FILTER_1SS
[16];
346 #define RATE_ADPT_1SS_MASK 0xFF
347 #define RATE_ADPT_2SS_MASK 0xF0
348 #define RATE_ADPT_MCS32_MASK 0x01
350 #define IS_11N_MCS_RATE(rate) (rate&0x80)
360 HT_IOT_PEER_UNKNOWN
= 0,
361 HT_IOT_PEER_REALTEK
= 1,
362 HT_IOT_PEER_REALTEK_92SE
= 2,
363 HT_IOT_PEER_BROADCOM
= 3,
364 HT_IOT_PEER_RALINK
= 4,
365 HT_IOT_PEER_ATHEROS
= 5,
366 HT_IOT_PEER_CISCO
= 6,
367 HT_IOT_PEER_MARVELL
= 7,
368 HT_IOT_PEER_92U_SOFTAP
= 8,
369 HT_IOT_PEER_SELF_SOFTAP
= 9,
370 HT_IOT_PEER_AIRGO
= 10,
371 HT_IOT_PEER_MAX
= 11,
374 enum ht_iot_peer_subtype
{
375 HT_IOT_PEER_ATHEROS_DIR635
= 0,
379 HT_IOT_ACT_TX_USE_AMSDU_4K
= 0x00000001,
380 HT_IOT_ACT_TX_USE_AMSDU_8K
= 0x00000002,
381 HT_IOT_ACT_DISABLE_MCS14
= 0x00000004,
382 HT_IOT_ACT_DISABLE_MCS15
= 0x00000008,
383 HT_IOT_ACT_DISABLE_ALL_2SS
= 0x00000010,
384 HT_IOT_ACT_DISABLE_EDCA_TURBO
= 0x00000020,
385 HT_IOT_ACT_MGNT_USE_CCK_6M
= 0x00000040,
386 HT_IOT_ACT_CDD_FSYNC
= 0x00000080,
387 HT_IOT_ACT_PURE_N_MODE
= 0x00000100,
388 HT_IOT_ACT_FORCED_CTS2SELF
= 0x00000200,
389 HT_IOT_ACT_FORCED_RTS
= 0x00000400,
390 HT_IOT_ACT_AMSDU_ENABLE
= 0x00000800,
391 HT_IOT_ACT_REJECT_ADDBA_REQ
= 0x00001000,
392 HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT
= 0x00002000,
393 HT_IOT_ACT_EDCA_BIAS_ON_RX
= 0x00004000,
395 HT_IOT_ACT_HYBRID_AGGREGATION
= 0x00010000,
396 HT_IOT_ACT_DISABLE_SHORT_GI
= 0x00020000,
397 HT_IOT_ACT_DISABLE_HIGH_POWER
= 0x00040000,
398 HT_IOT_ACT_DISABLE_TX_40_MHZ
= 0x00080000,
399 HT_IOT_ACT_TX_NO_AGGREGATION
= 0x00100000,
400 HT_IOT_ACT_DISABLE_TX_2SS
= 0x00200000,
402 HT_IOT_ACT_MID_HIGHPOWER
= 0x00400000,
403 HT_IOT_ACT_NULL_DATA_POWER_SAVING
= 0x00800000,
405 HT_IOT_ACT_DISABLE_CCK_RATE
= 0x01000000,
406 HT_IOT_ACT_FORCED_ENABLE_BE_TXOP
= 0x02000000,
407 HT_IOT_ACT_WA_IOT_Broadcom
= 0x04000000,
409 HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI
= 0x08000000,
414 HT_IOT_RAFUNC_DISABLE_ALL
= 0x00,
415 HT_IOT_RAFUNC_PEER_1R
= 0x01,
416 HT_IOT_RAFUNC_TX_AMSDU
= 0x02,
419 enum rt_ht_capability
{
420 RT_HT_CAP_USE_TURBO_AGGR
= 0x01,
421 RT_HT_CAP_USE_LONG_PREAMBLE
= 0x02,
422 RT_HT_CAP_USE_AMPDU
= 0x04,
423 RT_HT_CAP_USE_WOW
= 0x8,
424 RT_HT_CAP_USE_SOFTAP
= 0x10,
425 RT_HT_CAP_USE_92SE
= 0x20,