drivers/staging/rtl8192ee/rtl8192ee/sw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/vmalloc.h>
  27 #include <linux/module.h>
  28
  29 #include "../wifi.h"
  30 #include "../core.h"
  31 #include "../pci.h"
  32 #include "reg.h"
  33 #include "def.h"
  34 #include "phy.h"
  35 #include "dm.h"
  36 #include "hw.h"
  37 #include "sw.h"
  38 #include "fw.h"
  39 #include "trx.h"
  40 #include "led.h"
  41 #include "table.h"
  42
  43 #include "../btcoexist/rtl_btc.h"
  44
  45
  46 static void rtl92ee_init_aspm_vars(struct ieee80211_hw *hw)
  47 {
  48         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  49
  50         /*close ASPM for AMD defaultly */
  51         rtlpci->const_amdpci_aspm = 0;
  52
  53         /*
  54          * ASPM PS mode.
  55          * 0 - Disable ASPM,
  56          * 1 - Enable ASPM without Clock Req,
  57          * 2 - Enable ASPM with Clock Req,
  58          * 3 - Alwyas Enable ASPM with Clock Req,
  59          * 4 - Always Enable ASPM without Clock Req.
  60          * set defult to RTL8192CE:3 RTL8192E:2
  61          * */
  62         rtlpci->const_pci_aspm = 3;
  63
  64         /*Setting for PCI-E device */
  65         rtlpci->const_devicepci_aspm_setting = 0x03;
  66
  67         /*Setting for PCI-E bridge */
  68         rtlpci->const_hostpci_aspm_setting = 0x02;
  69
  70         /*
  71          * In Hw/Sw Radio Off situation.
  72          * 0 - Default,
  73          * 1 - From ASPM setting without low Mac Pwr,
  74          * 2 - From ASPM setting with low Mac Pwr,
  75          * 3 - Bus D3
  76          * set default to RTL8192CE:0 RTL8192SE:2
  77          */
  78         rtlpci->const_hwsw_rfoff_d3 = 0;
  79
  80         /*
  81          * This setting works for those device with
  82          * backdoor ASPM setting such as EPHY setting.
  83          * 0 - Not support ASPM,
  84          * 1 - Support ASPM,
  85          * 2 - According to chipset.
  86          */
  87         rtlpci->const_support_pciaspm = 1;
  88 }
  89
  90 int rtl92ee_init_sw_vars(struct ieee80211_hw *hw)
  91 {
  92         int err = 0;
  93         struct rtl_priv *rtlpriv = rtl_priv(hw);
  94         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  95         const struct firmware *firmware;
  96         char *fw_name = NULL;
  97
  98         rtl92ee_bt_reg_init(hw);
  99
 100         rtlpci->msi_support = true;
 101         rtlpriv->btcoexist.btc_ops = stg_rtl_btc_get_ops_pointer();
 102
 103         rtlpriv->dm.b_dm_initialgain_enable = 1;
 104         rtlpriv->dm.dm_flag = 0;
 105         rtlpriv->dm.b_disable_framebursting = 0;
 106         /*rtlpriv->dm.thermalvalue = 0;*/
 107         rtlpci->transmit_config = CFENDFORM | BIT(15);
 108
 109         /*just 2.4G band*/
 110         rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
 111         rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
 112         rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
 113
 114         rtlpci->receive_config = (RCR_APPFCS                    |
 115                                   RCR_APP_MIC                   |
 116                                   RCR_APP_ICV                   |
 117                                   RCR_APP_PHYST_RXFF            |
 118                                   RCR_HTC_LOC_CTRL              |
 119                                   RCR_AMF                       |
 120                                   RCR_ACF                       |
 121                                   RCR_ADF                       |
 122                                   RCR_AICV                      |
 123                                   RCR_ACRC32                    |
 124                                   RCR_AB                        |
 125                                   RCR_AM                        |
 126                                   RCR_APM                       |
 127                                   0);
 128
 129         rtlpci->irq_mask[0] = (u32) (IMR_PSTIMEOUT              |
 130                                 /*   IMR_TBDER                  |
 131                                      IMR_TBDOK                  |
 132                                      IMR_BCNDMAINT0             |*/
 133                                      IMR_C2HCMD                 |
 134                                      IMR_HIGHDOK                |
 135                                      IMR_MGNTDOK                |
 136                                      IMR_BKDOK                  |
 137                                      IMR_BEDOK                  |
 138                                      IMR_VIDOK                  |
 139                                      IMR_VODOK                  |
 140                                      IMR_RDU                    |
 141                                      IMR_ROK                    |
 142                                      0);
 143         rtlpci->irq_mask[1] = (u32) (IMR_RXFOVW | 0);
 144
 145         /* for debug level */
 146         rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
 147         /* for LPS & IPS */
 148         rtlpriv->psc.b_inactiveps = rtlpriv->cfg->mod_params->b_inactiveps;
 149         rtlpriv->psc.b_swctrl_lps = rtlpriv->cfg->mod_params->b_swctrl_lps;
 150         rtlpriv->psc.b_fwctrl_lps = rtlpriv->cfg->mod_params->b_fwctrl_lps;
 151         rtlpriv->psc.b_reg_fwctrl_lps = 3;
 152         rtlpriv->psc.reg_max_lps_awakeintvl = 5;
 153         /* for ASPM, you can close aspm through
 154          * set const_support_pciaspm = 0 */
 155         rtl92ee_init_aspm_vars(hw);
 156
 157         if (rtlpriv->psc.b_reg_fwctrl_lps == 1)
 158                 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
 159         else if (rtlpriv->psc.b_reg_fwctrl_lps == 2)
 160                 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
 161         else if (rtlpriv->psc.b_reg_fwctrl_lps == 3)
 162                 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
 163
 164         /* for early mode */
 165         rtlpriv->rtlhal.b_earlymode_enable = false;
 166
 167         /*low power */
 168         rtlpriv->psc.b_low_power_enable = false;
 169
 170
 171         /* for firmware buf */
 172         rtlpriv->rtlhal.pfirmware = vmalloc(0x8000);
 173         if (!rtlpriv->rtlhal.pfirmware) {
 174                 RT_TRACE(COMP_ERR, DBG_EMERG, "Can't alloc buffer for fw\n");
 175                 return 1;
 176         }
 177
 178         fw_name = "rtlwifi/rtl8192eefw.bin";
 179         err = request_firmware(&firmware, fw_name, rtlpriv->io.dev);
 180
 181         if (err) {
 182                 RT_TRACE(COMP_ERR, DBG_EMERG, "Failed to request firmware!\n");
 183                 return 1;
 184         }
 185         if (firmware->size > 0x8000) {
 186                 RT_TRACE(COMP_ERR, DBG_EMERG, "Firmware is too big!\n");
 187                 release_firmware(firmware);
 188                 return 1;
 189         }
 190         memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size);
 191         rtlpriv->rtlhal.fwsize = firmware->size;
 192         release_firmware(firmware);
 193
 194         return err;
 195 }
 196
 197 void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw)
 198 {
 199         struct rtl_priv *rtlpriv = rtl_priv(hw);
 200
 201         if (rtlpriv->rtlhal.pfirmware) {
 202                 vfree(rtlpriv->rtlhal.pfirmware);
 203                 rtlpriv->rtlhal.pfirmware = NULL;
 204         }
 205 }
 206
 207 /* get bt coexist status */
 208 bool rtl92ee_get_btc_status(void)
 209 {
 210         return true;
 211 }
 212
 213
 214 static struct rtl_hal_ops rtl8192ee_hal_ops = {
 215         .init_sw_vars = rtl92ee_init_sw_vars,
 216         .deinit_sw_vars = rtl92ee_deinit_sw_vars,
 217         .read_eeprom_info = rtl92ee_read_eeprom_info,
 218         .interrupt_recognized = rtl92ee_interrupt_recognized,/*need check*/
 219         .hw_init = rtl92ee_hw_init,
 220         .hw_disable = rtl92ee_card_disable,
 221         .hw_suspend = rtl92ee_suspend,
 222         .hw_resume = rtl92ee_resume,
 223         .enable_interrupt = rtl92ee_enable_interrupt,
 224         .disable_interrupt = rtl92ee_disable_interrupt,
 225         .set_network_type = rtl92ee_set_network_type,
 226         .set_chk_bssid = rtl92ee_set_check_bssid,
 227         .set_qos = rtl92ee_set_qos,
 228         .set_bcn_reg = rtl92ee_set_beacon_related_registers,
 229         .set_bcn_intv = rtl92ee_set_beacon_interval,
 230         .update_interrupt_mask = rtl92ee_update_interrupt_mask,
 231         .get_hw_reg = rtl92ee_get_hw_reg,
 232         .set_hw_reg = rtl92ee_set_hw_reg,
 233         .update_rate_tbl = rtl92ee_update_hal_rate_tbl,
 234         .pre_fill_tx_bd_desc = rtl92ee_pre_fill_tx_bd_desc,
 235         .rx_desc_buff_remained_cnt = rtl92ee_rx_desc_buff_remained_cnt,
 236         .rx_check_dma_ok = rtl92ee_rx_check_dma_ok,
 237         .fill_tx_desc = rtl92ee_tx_fill_desc,
 238         .fill_tx_cmddesc = rtl92ee_tx_fill_cmddesc,
 239         .query_rx_desc = rtl92ee_rx_query_desc,
 240         .set_channel_access = rtl92ee_update_channel_access_setting,
 241         .radio_onoff_checking = rtl92ee_gpio_radio_on_off_checking,
 242         .set_bw_mode = rtl92ee_phy_set_bw_mode,
 243         .switch_channel = rtl92ee_phy_sw_chnl,
 244         .dm_watchdog = rtl92ee_dm_watchdog,
 245         .scan_operation_backup = rtl92ee_phy_scan_operation_backup,
 246         .set_rf_power_state = rtl92ee_phy_set_rf_power_state,
 247         .led_control = rtl92ee_led_control,
 248         .set_desc = rtl92ee_set_desc,
 249         .get_desc = rtl92ee_get_desc,
 250         .is_tx_desc_closed = rtl92ee_is_tx_desc_closed,
 251         .enable_hw_sec = rtl92ee_enable_hw_security_config,
 252         .set_key = rtl92ee_set_key,
 253         .init_sw_leds = rtl92ee_init_sw_leds,
 254         .allow_all_destaddr = rtl92ee_allow_all_destaddr,
 255         .get_bbreg = rtl92ee_phy_query_bb_reg,
 256         .set_bbreg = rtl92ee_phy_set_bb_reg,
 257         .get_rfreg = rtl92ee_phy_query_rf_reg,
 258         .set_rfreg = rtl92ee_phy_set_rf_reg,
 259         .fill_h2c_cmd = rtl92ee_fill_h2c_cmd,
 260         .get_btc_status = rtl92ee_get_btc_status,
 261         .rx_command_packet = rtl92ee_rx_command_packet,
 262 };
 263
 264 static struct rtl_mod_params rtl92ee_mod_params = {
 265         .sw_crypto = false,
 266         .b_inactiveps = true,
 267         .b_swctrl_lps = false,
 268         .b_fwctrl_lps = true,
 269         .debug = DBG_EMERG,
 270 };
 271
 272 static struct rtl_hal_cfg rtl92ee_hal_cfg = {
 273         .bar_id = 2,
 274         .write_readback = true,
 275         .name = "rtl92ee_pci",
 276         .fw_name = "rtlwifi/rtl8192eefw.bin",
 277         .ops = &rtl8192ee_hal_ops,
 278         .mod_params = &rtl92ee_mod_params,
 279
 280         .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
 281         .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
 282         .maps[SYS_CLK] = REG_SYS_CLKR,
 283         .maps[MAC_RCR_AM] = AM,
 284         .maps[MAC_RCR_AB] = AB,
 285         .maps[MAC_RCR_ACRC32] = ACRC32,
 286         .maps[MAC_RCR_ACF] = ACF,
 287         .maps[MAC_RCR_AAP] = AAP,
 288         .maps[MAC_HIMR] = REG_HIMR,
 289         .maps[MAC_HIMRE] = REG_HIMRE,
 290
 291         .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
 292
 293         .maps[EFUSE_TEST] = REG_EFUSE_TEST,
 294         .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
 295         .maps[EFUSE_CLK] = 0,
 296         .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
 297         .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
 298         .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
 299         .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
 300         .maps[EFUSE_ANA8M] = ANA8M,
 301         .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
 302         .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
 303         .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
 304         .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
 305
 306         .maps[RWCAM] = REG_CAMCMD,
 307         .maps[WCAMI] = REG_CAMWRITE,
 308         .maps[RCAMO] = REG_CAMREAD,
 309         .maps[CAMDBG] = REG_CAMDBG,
 310         .maps[SECR] = REG_SECCFG,
 311         .maps[SEC_CAM_NONE] = CAM_NONE,
 312         .maps[SEC_CAM_WEP40] = CAM_WEP40,
 313         .maps[SEC_CAM_TKIP] = CAM_TKIP,
 314         .maps[SEC_CAM_AES] = CAM_AES,
 315         .maps[SEC_CAM_WEP104] = CAM_WEP104,
 316
 317         .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
 318         .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
 319         .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
 320         .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
 321         .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
 322         .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
 323 /*      .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,     */   /*need check*/
 324         .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
 325         .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
 326         .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
 327         .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
 328         .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
 329         .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
 330         .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
 331 /*      .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
 332 /*      .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
 333
 334         .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
 335         .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
 336         .maps[RTL_IMR_BcnInt] = IMR_BCNDMAINT0,
 337         .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
 338         .maps[RTL_IMR_RDU] = IMR_RDU,
 339         .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
 340         .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
 341         .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
 342         .maps[RTL_IMR_TBDER] = IMR_TBDER,
 343         .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
 344         .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
 345         .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
 346         .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
 347         .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
 348         .maps[RTL_IMR_VODOK] = IMR_VODOK,
 349         .maps[RTL_IMR_ROK] = IMR_ROK,
 350         .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
 351
 352         .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
 353         .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
 354         .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
 355         .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
 356         .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
 357         .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
 358         .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
 359         .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
 360         .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
 361         .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
 362         .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
 363         .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
 364
 365         .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
 366         .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
 367 };
 368
 369 static struct pci_device_id rtl92ee_pci_ids[] = {
 370         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x818B, rtl92ee_hal_cfg)},
 371         {},
 372 };
 373
 374 MODULE_DEVICE_TABLE(pci, rtl92ee_pci_ids);
 375
 376 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
 377 MODULE_AUTHOR("Larry Finger     <Larry.Finger@lwfinger.net>");
 378 MODULE_LICENSE("GPL");
 379 MODULE_DESCRIPTION("Realtek 8192E 802.11n PCI wireless");
 380 MODULE_FIRMWARE("rtlwifi/rtl8192eefw.bin");
 381
 382 module_param_named(swenc, rtl92ee_mod_params.sw_crypto, bool, 0444);
 383 module_param_named(debug, rtl92ee_mod_params.debug, int, 0444);
 384 module_param_named(ips, rtl92ee_mod_params.b_inactiveps, bool, 0444);
 385 module_param_named(swlps, rtl92ee_mod_params.b_swctrl_lps, bool, 0444);
 386 module_param_named(fwlps, rtl92ee_mod_params.b_fwctrl_lps, bool, 0444);
 387 MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n");
 388 MODULE_PARM_DESC(ips, "using no link power save (default 1 is open)\n");
 389 MODULE_PARM_DESC(fwlps, "using linked fw control power save (default 1 is open)\n");
 390 MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
 391
 392 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, stg_rtl_pci_suspend,
 393                          stg_rtl_pci_resume);
 394
 395 static struct pci_driver rtl92ee_driver = {
 396         .name = KBUILD_MODNAME,
 397         .id_table = rtl92ee_pci_ids,
 398         .probe = stg_rtl_pci_probe,
 399         .remove = stg_rtl_pci_disconnect,
 400
 401         .driver.pm = &rtlwifi_pm_ops,
 402 };
 403
 404 static int __init rtl92ee_module_init(void)
 405 {
 406         int ret;
 407         ret = rtl_core_module_init();
 408         if (ret)
 409                 return ret;
 410
 411         ret = pci_register_driver(&rtl92ee_driver);
 412         if (ret)
 413                 RT_ASSERT(false, (": No device found\n"));
 414
 415         return ret;
 416 }
 417
 418 static void __exit rtl92ee_module_exit(void)
 419 {
 420         pci_unregister_driver(&rtl92ee_driver);
 421         rtl_core_module_exit();
 422 }
 423
 424 module_init(rtl92ee_module_init);
 425 module_exit(rtl92ee_module_exit);