1 /* Driver for Realtek RTS51xx USB card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
22 * Edwin Rong (edwin_rong@realsil.com.cn)
23 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
26 #include <linux/blkdev.h>
27 #include <linux/kthread.h>
28 #include <linux/sched.h>
33 #include "rts51x_transport.h"
34 #include "rts51x_scsi.h"
35 #include "rts51x_card.h"
38 static inline void sd_set_reset_fail(struct rts51x_chip
*chip
, u8 err_code
)
40 struct sd_info
*sd_card
= &(chip
->sd_card
);
42 sd_card
->sd_reset_fail
|= err_code
;
45 static inline void sd_clear_reset_fail(struct rts51x_chip
*chip
)
47 struct sd_info
*sd_card
= &(chip
->sd_card
);
49 sd_card
->sd_reset_fail
= 0;
52 static inline int sd_check_reset_fail(struct rts51x_chip
*chip
, u8 err_code
)
54 struct sd_info
*sd_card
= &(chip
->sd_card
);
56 return sd_card
->sd_reset_fail
& err_code
;
59 static inline void sd_set_err_code(struct rts51x_chip
*chip
, u8 err_code
)
61 struct sd_info
*sd_card
= &(chip
->sd_card
);
63 sd_card
->err_code
|= err_code
;
66 static inline void sd_clr_err_code(struct rts51x_chip
*chip
)
68 struct sd_info
*sd_card
= &(chip
->sd_card
);
70 sd_card
->err_code
= 0;
73 static inline int sd_check_err_code(struct rts51x_chip
*chip
, u8 err_code
)
75 struct sd_info
*sd_card
= &(chip
->sd_card
);
77 return sd_card
->err_code
& err_code
;
80 static int sd_parse_err_code(struct rts51x_chip
*chip
)
82 TRACE_RET(chip
, STATUS_FAIL
);
85 int sd_check_data0_status(struct rts51x_chip
*chip
)
90 retval
= rts51x_ep0_read_register(chip
, SD_BUS_STAT
, &stat
);
91 if (retval
!= STATUS_SUCCESS
)
92 TRACE_RET(chip
, retval
);
93 if (!(stat
& SD_DAT0_STATUS
)) {
94 sd_set_err_code(chip
, SD_BUSY
);
95 TRACE_RET(chip
, STATUS_FAIL
);
98 return STATUS_SUCCESS
;
101 static int sd_send_cmd_get_rsp(struct rts51x_chip
*chip
, u8 cmd_idx
,
102 u32 arg
, u8 rsp_type
, u8
*rsp
, int rsp_len
)
104 struct sd_info
*sd_card
= &(chip
->sd_card
);
112 sd_clr_err_code(chip
);
114 RTS51X_DEBUGP("SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx
, arg
);
116 if (rsp_type
== SD_RSP_TYPE_R1b
)
121 rts51x_init_cmd(chip
);
123 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD0
, 0xFF, 0x40 | cmd_idx
);
124 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD1
, 0xFF, (u8
) (arg
>> 24));
125 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD2
, 0xFF, (u8
) (arg
>> 16));
126 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD3
, 0xFF, (u8
) (arg
>> 8));
127 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD4
, 0xFF, (u8
) arg
);
129 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG2
, 0xFF, rsp_type
);
130 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01,
132 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_TRANSFER
, 0xFF,
133 SD_TM_CMD_RSP
| SD_TRANSFER_START
);
134 rts51x_add_cmd(chip
, CHECK_REG_CMD
, SD_TRANSFER
,
135 SD_TRANSFER_END
| SD_STAT_IDLE
,
136 SD_TRANSFER_END
| SD_STAT_IDLE
);
138 rts51x_add_cmd(chip
, READ_REG_CMD
, SD_STAT1
, 0, 0);
140 if (CHECK_USB(chip
, USB_20
)) {
141 if (rsp_type
== SD_RSP_TYPE_R2
) {
142 /* Read data from ping-pong buffer */
143 for (reg_addr
= PPBUF_BASE2
;
144 reg_addr
< PPBUF_BASE2
+ 16; reg_addr
++) {
145 rts51x_add_cmd(chip
, READ_REG_CMD
, reg_addr
, 0,
149 } else if (rsp_type
!= SD_RSP_TYPE_R0
) {
150 /* Read data from SD_CMDx registers */
151 for (reg_addr
= SD_CMD0
; reg_addr
<= SD_CMD4
;
153 rts51x_add_cmd(chip
, READ_REG_CMD
, reg_addr
, 0,
164 retval
= rts51x_send_cmd(chip
, MODE_CR
, 100);
165 if (retval
!= STATUS_SUCCESS
)
166 TRACE_RET(chip
, retval
);
168 retval
= rts51x_get_rsp(chip
, len
, timeout
);
170 if (CHECK_SD_TRANS_FAIL(chip
, retval
)) {
173 rts51x_ep0_read_register(chip
, SD_STAT1
, &val
);
174 RTS51X_DEBUGP("SD_STAT1: 0x%x\n", val
);
176 rts51x_ep0_read_register(chip
, SD_STAT2
, &val
);
177 RTS51X_DEBUGP("SD_STAT2: 0x%x\n", val
);
179 if (val
& SD_RSP_80CLK_TIMEOUT
)
180 sd_set_err_code(chip
, SD_RSP_TIMEOUT
);
182 rts51x_ep0_read_register(chip
, SD_BUS_STAT
, &val
);
183 RTS51X_DEBUGP("SD_BUS_STAT: 0x%x\n", val
);
185 if (retval
== STATUS_TIMEDOUT
) {
186 if (rsp_type
& SD_WAIT_BUSY_END
) {
187 retval
= sd_check_data0_status(chip
);
188 if (retval
!= STATUS_SUCCESS
)
189 TRACE_RET(chip
, retval
);
191 sd_set_err_code(chip
, SD_TO_ERR
);
194 rts51x_clear_sd_error(chip
);
196 TRACE_RET(chip
, STATUS_FAIL
);
199 if (rsp_type
== SD_RSP_TYPE_R0
)
200 return STATUS_SUCCESS
;
202 if (CHECK_USB(chip
, USB_20
)) {
203 rts51x_read_rsp_buf(chip
, 2, buf
, len
- 2);
205 if (rsp_type
== SD_RSP_TYPE_R2
) {
206 reg_addr
= PPBUF_BASE2
;
212 retval
= rts51x_seq_read_register(chip
, reg_addr
,
213 (unsigned short)len
, buf
);
214 if (retval
!= STATUS_SUCCESS
)
215 TRACE_RET(chip
, retval
);
217 stat
= chip
->rsp_buf
[1];
219 /* Check (Start,Transmission) bit of Response */
220 if ((buf
[0] & 0xC0) != 0) {
221 sd_set_err_code(chip
, SD_STS_ERR
);
222 TRACE_RET(chip
, STATUS_FAIL
);
225 if (!(rsp_type
& SD_NO_CHECK_CRC7
)) {
226 if (stat
& SD_CRC7_ERR
) {
227 if (cmd_idx
== WRITE_MULTIPLE_BLOCK
) {
228 sd_set_err_code(chip
, SD_CRC_ERR
);
229 TRACE_RET(chip
, STATUS_FAIL
);
231 if (rty_cnt
< SD_MAX_RETRY_COUNT
) {
236 sd_set_err_code(chip
, SD_CRC_ERR
);
237 TRACE_RET(chip
, STATUS_FAIL
);
242 if ((rsp_type
== SD_RSP_TYPE_R1
) || (rsp_type
== SD_RSP_TYPE_R1b
)) {
243 if ((cmd_idx
!= SEND_RELATIVE_ADDR
)
244 && (cmd_idx
!= SEND_IF_COND
)) {
245 if (cmd_idx
!= STOP_TRANSMISSION
) {
247 TRACE_RET(chip
, STATUS_FAIL
);
250 RTS51X_DEBUGP("buf[1]: 0x%02x\n", buf
[1]);
251 TRACE_RET(chip
, STATUS_FAIL
);
254 RTS51X_DEBUGP("buf[2]: 0x%02x\n", buf
[2]);
255 TRACE_RET(chip
, STATUS_FAIL
);
258 RTS51X_DEBUGP("buf[3]: 0x%02x\n", buf
[3]);
259 TRACE_RET(chip
, STATUS_FAIL
);
262 /* Get "READY_FOR_DATA" bit */
263 sd_card
->sd_data_buf_ready
= 1;
265 sd_card
->sd_data_buf_ready
= 0;
271 memcpy(rsp
, buf
, rsp_len
);
273 return STATUS_SUCCESS
;
276 static inline void sd_print_debug_reg(struct rts51x_chip
*chip
)
278 #ifdef CONFIG_RTS5139_DEBUG
281 rts51x_ep0_read_register(chip
, SD_STAT1
, &val
);
282 RTS51X_DEBUGP("SD_STAT1: 0x%x\n", val
);
283 rts51x_ep0_read_register(chip
, SD_STAT2
, &val
);
284 RTS51X_DEBUGP("SD_STAT2: 0x%x\n", val
);
285 rts51x_ep0_read_register(chip
, SD_BUS_STAT
, &val
);
286 RTS51X_DEBUGP("SD_BUS_STAT: 0x%x\n", val
);
290 int sd_read_data(struct rts51x_chip
*chip
, u8 trans_mode
, u8
*cmd
, int cmd_len
,
291 u16 byte_cnt
, u16 blk_cnt
, u8 bus_width
, u8
*buf
, int buf_len
,
294 struct sd_info
*sd_card
= &(chip
->sd_card
);
298 sd_clr_err_code(chip
);
304 /* This function can't read data more than one page */
305 TRACE_RET(chip
, STATUS_FAIL
);
307 rts51x_init_cmd(chip
);
310 RTS51X_DEBUGP("SD/MMC CMD %d\n", cmd
[0] - 0x40);
311 for (i
= 0; i
< (cmd_len
< 6 ? cmd_len
: 6); i
++) {
312 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD0
+ i
, 0xFF,
316 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BYTE_CNT_L
, 0xFF, (u8
) byte_cnt
);
317 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BYTE_CNT_H
, 0xFF,
318 (u8
) (byte_cnt
>> 8));
319 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BLOCK_CNT_L
, 0xFF, (u8
) blk_cnt
);
320 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BLOCK_CNT_H
, 0xFF,
321 (u8
) (blk_cnt
>> 8));
323 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG1
, 0x03, bus_width
);
325 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG2
, 0xFF,
326 SD_CALCULATE_CRC7
| SD_CHECK_CRC16
| SD_NO_WAIT_BUSY_END
327 | SD_CHECK_CRC7
| SD_RSP_LEN_6
);
328 if (trans_mode
!= SD_TM_AUTO_TUNING
) {
329 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01,
332 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_TRANSFER
, 0xFF,
333 trans_mode
| SD_TRANSFER_START
);
334 rts51x_add_cmd(chip
, CHECK_REG_CMD
, SD_TRANSFER
, SD_TRANSFER_END
,
337 retval
= rts51x_send_cmd(chip
, MODE_CR
, 100);
338 if (retval
!= STATUS_SUCCESS
)
339 TRACE_RET(chip
, retval
);
341 retval
= rts51x_get_rsp(chip
, 1, timeout
);
343 if (CHECK_SD_TRANS_FAIL(chip
, retval
)) {
344 sd_print_debug_reg(chip
);
345 if (retval
== STATUS_TIMEDOUT
) {
346 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
347 SD_RSP_TYPE_R1
, NULL
, 0);
350 TRACE_RET(chip
, STATUS_FAIL
);
353 if (buf
&& buf_len
) {
354 retval
= rts51x_read_ppbuf(chip
, buf
, buf_len
);
355 if (retval
!= STATUS_SUCCESS
)
356 TRACE_RET(chip
, retval
);
359 return STATUS_SUCCESS
;
362 static int sd_write_data(struct rts51x_chip
*chip
, u8 trans_mode
,
363 u8
*cmd
, int cmd_len
, u16 byte_cnt
, u16 blk_cnt
,
364 u8 bus_width
, u8
*buf
, int buf_len
, int timeout
)
366 struct sd_info
*sd_card
= &(chip
->sd_card
);
370 sd_clr_err_code(chip
);
375 /* This function can't write data more than one page */
377 TRACE_RET(chip
, STATUS_FAIL
);
379 if (buf
&& buf_len
) {
380 retval
= rts51x_write_ppbuf(chip
, buf
, buf_len
);
381 if (retval
!= STATUS_SUCCESS
)
382 TRACE_RET(chip
, retval
);
385 rts51x_init_cmd(chip
);
388 RTS51X_DEBUGP("SD/MMC CMD %d\n", cmd
[0] - 0x40);
389 for (i
= 0; i
< (cmd_len
< 6 ? cmd_len
: 6); i
++) {
390 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD0
+ i
, 0xFF,
394 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BYTE_CNT_L
, 0xFF, (u8
) byte_cnt
);
395 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BYTE_CNT_H
, 0xFF,
396 (u8
) (byte_cnt
>> 8));
397 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BLOCK_CNT_L
, 0xFF, (u8
) blk_cnt
);
398 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BLOCK_CNT_H
, 0xFF,
399 (u8
) (blk_cnt
>> 8));
401 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG1
, 0x03, bus_width
);
404 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG2
, 0xFF,
405 SD_CALCULATE_CRC7
| SD_CHECK_CRC16
|
406 SD_WAIT_BUSY_END
| SD_CHECK_CRC7
| SD_RSP_LEN_6
);
409 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG2
, 0xFF,
410 SD_CALCULATE_CRC7
| SD_CHECK_CRC16
|
411 SD_NO_WAIT_BUSY_END
| SD_CHECK_CRC7
|
415 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_TRANSFER
, 0xFF,
416 trans_mode
| SD_TRANSFER_START
);
417 rts51x_add_cmd(chip
, CHECK_REG_CMD
, SD_TRANSFER
, SD_TRANSFER_END
,
420 retval
= rts51x_send_cmd(chip
, MODE_CR
, 100);
421 if (retval
!= STATUS_SUCCESS
)
422 TRACE_RET(chip
, retval
);
424 retval
= rts51x_get_rsp(chip
, 1, timeout
);
426 if (CHECK_SD_TRANS_FAIL(chip
, retval
)) {
427 sd_print_debug_reg(chip
);
429 if (retval
== STATUS_TIMEDOUT
)
430 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
431 SD_RSP_TYPE_R1
, NULL
, 0);
433 TRACE_RET(chip
, STATUS_FAIL
);
436 return STATUS_SUCCESS
;
439 static int sd_check_csd(struct rts51x_chip
*chip
, char check_wp
)
441 struct sd_info
*sd_card
= &(chip
->sd_card
);
444 u8 csd_ver
, trans_speed
;
447 for (i
= 0; i
< 6; i
++) {
448 if (monitor_card_cd(chip
, SD_CARD
) == CD_NOT_EXIST
) {
449 sd_set_reset_fail(chip
, SD_RESET_FAIL
);
450 TRACE_RET(chip
, STATUS_FAIL
);
454 sd_send_cmd_get_rsp(chip
, SEND_CSD
, sd_card
->sd_addr
,
455 SD_RSP_TYPE_R2
, rsp
, 16);
456 if (retval
== STATUS_SUCCESS
)
461 TRACE_RET(chip
, STATUS_FAIL
);
462 memcpy(sd_card
->raw_csd
, rsp
+ 1, 15);
464 RTS51X_READ_REG(chip
, SD_CMD5
, sd_card
->raw_csd
+ 15);
466 RTS51X_DEBUGP("CSD Response:\n");
467 RTS51X_DUMP(rsp
, 16);
469 /* Get CSD Version */
470 csd_ver
= (rsp
[1] & 0xc0) >> 6;
471 RTS51X_DEBUGP("csd_ver = %d\n", csd_ver
);
473 trans_speed
= rsp
[4];
474 if ((trans_speed
& 0x07) == 0x02) { /* 10Mbits/s */
475 if ((trans_speed
& 0xf8) >= 0x30) { /* >25Mbits/s */
477 sd_card
->sd_clock
= 46;
479 sd_card
->sd_clock
= CLK_50
;
480 } else if ((trans_speed
& 0xf8) == 0x28) { /* 20Mbits/s */
482 sd_card
->sd_clock
= 39;
484 sd_card
->sd_clock
= CLK_40
;
485 } else if ((trans_speed
& 0xf8) == 0x20) { /* 15Mbits/s */
487 sd_card
->sd_clock
= 29;
489 sd_card
->sd_clock
= CLK_30
;
490 } else if ((trans_speed
& 0xf8) >= 0x10) { /* 12Mbits/s */
492 sd_card
->sd_clock
= 23;
494 sd_card
->sd_clock
= CLK_20
;
495 } else if ((trans_speed
& 0x08) >= 0x08) { /* 10Mbits/s */
497 sd_card
->sd_clock
= 19;
499 sd_card
->sd_clock
= CLK_20
;
501 /*If this ,then slow card will use 30M clock */
502 /* TRACE_RET(chip, STATUS_FAIL); */
506 TRACE_RET(chip, STATUS_FAIL);
508 if (CHK_MMC_SECTOR_MODE(sd_card
)) {
509 sd_card
->capacity
= 0;
511 /* For High-Capacity Card, CSD_STRUCTURE always be "0x1" */
512 if ((!CHK_SD_HCXC(sd_card
)) || (csd_ver
== 0)) {
513 /* Calculate total sector according to C_SIZE,
514 * C_SIZE_MULT & READ_BL_LEN */
515 u8 blk_size
, c_size_mult
;
517 /* Get READ_BL_LEN */
518 blk_size
= rsp
[6] & 0x0F;
520 c_size
= ((u16
) (rsp
[7] & 0x03) << 10)
521 + ((u16
) rsp
[8] << 2)
522 + ((u16
) (rsp
[9] & 0xC0) >> 6);
524 c_size_mult
= (u8
) ((rsp
[10] & 0x03) << 1);
525 c_size_mult
+= (rsp
[11] & 0x80) >> 7;
526 /* Calculate total Capacity */
528 (((u32
) (c_size
+ 1)) *
529 (1 << (c_size_mult
+ 2))) << (blk_size
- 9);
531 /* High Capacity Card and Use CSD2.0 Version */
532 u32 total_sector
= 0;
533 total_sector
= (((u32
) rsp
[8] & 0x3f) << 16) |
534 ((u32
) rsp
[9] << 8) | (u32
) rsp
[10];
535 /* Total Capacity= (C_SIZE+1) *
536 * 512K Byte = (C_SIZE+1)K Sector,1K = 1024 Bytes */
537 sd_card
->capacity
= (total_sector
+ 1) << 10;
541 /* We need check Write-Protected Status by Field PERM WP or TEMP WP */
544 chip
->card_wp
|= SD_CARD
;
545 RTS51X_DEBUGP("CSD WP Status: 0x%x\n", rsp
[15]);
548 return STATUS_SUCCESS
;
551 static int sd_set_sample_push_timing(struct rts51x_chip
*chip
)
553 struct sd_info
*sd_card
= &(chip
->sd_card
);
556 rts51x_init_cmd(chip
);
558 if (CHK_SD_SDR104(sd_card
) || CHK_SD_SDR50(sd_card
)) {
559 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG1
,
560 0x0C | SD_ASYNC_FIFO_RST
,
561 SD_30_MODE
| SD_ASYNC_FIFO_RST
);
562 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_CLK_SOURCE
, 0xFF,
563 CRC_VAR_CLK0
| SD30_FIX_CLK
| SAMPLE_VAR_CLK1
);
564 } else if (CHK_SD_DDR50(sd_card
) || CHK_MMC_DDR52(sd_card
)) {
565 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG1
,
566 0x0C | SD_ASYNC_FIFO_RST
,
567 SD_DDR_MODE
| SD_ASYNC_FIFO_RST
);
568 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_CLK_SOURCE
, 0xFF,
569 CRC_VAR_CLK0
| SD30_FIX_CLK
| SAMPLE_VAR_CLK1
);
570 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_PUSH_POINT_CTL
,
571 DDR_VAR_TX_CMD_DAT
, DDR_VAR_TX_CMD_DAT
);
572 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_SAMPLE_POINT_CTL
,
573 DDR_VAR_RX_DAT
| DDR_VAR_RX_CMD
,
574 DDR_VAR_RX_DAT
| DDR_VAR_RX_CMD
);
578 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG1
, 0x0C, SD_20_MODE
);
579 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_CLK_SOURCE
, 0xFF,
580 CRC_FIX_CLK
| SD30_VAR_CLK0
| SAMPLE_VAR_CLK1
);
582 if ((chip
->option
.sd_ctl
& SD_PUSH_POINT_CTL_MASK
) ==
583 SD_PUSH_POINT_AUTO
) {
584 val
= SD20_TX_NEG_EDGE
;
585 } else if ((chip
->option
.sd_ctl
& SD_PUSH_POINT_CTL_MASK
) ==
586 SD_PUSH_POINT_DELAY
) {
587 val
= SD20_TX_14_AHEAD
;
589 val
= SD20_TX_NEG_EDGE
;
591 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_PUSH_POINT_CTL
,
592 SD20_TX_SEL_MASK
, val
);
594 if ((chip
->option
.sd_ctl
& SD_SAMPLE_POINT_CTL_MASK
) ==
595 SD_SAMPLE_POINT_AUTO
) {
596 if (chip
->asic_code
) {
597 if (CHK_SD_HS(sd_card
) || CHK_MMC_52M(sd_card
))
598 val
= SD20_RX_14_DELAY
;
600 val
= SD20_RX_POS_EDGE
;
602 val
= SD20_RX_14_DELAY
;
604 } else if ((chip
->option
.sd_ctl
& SD_SAMPLE_POINT_CTL_MASK
) ==
605 SD_SAMPLE_POINT_DELAY
) {
606 val
= SD20_RX_14_DELAY
;
608 val
= SD20_RX_POS_EDGE
;
610 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_SAMPLE_POINT_CTL
,
611 SD20_RX_SEL_MASK
, val
);
614 if (CHK_MMC_DDR52(sd_card
) && CHK_MMC_8BIT(sd_card
)) {
615 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_DMA1_CTL
,
616 EXTEND_DMA1_ASYNC_SIGNAL
, 0);
619 retval
= rts51x_send_cmd(chip
, MODE_C
, 100);
620 if (retval
!= STATUS_SUCCESS
)
621 TRACE_RET(chip
, retval
);
623 return STATUS_SUCCESS
;
626 static void sd_choose_proper_clock(struct rts51x_chip
*chip
)
628 struct sd_info
*sd_card
= &(chip
->sd_card
);
630 if (CHK_SD_SDR104(sd_card
)) {
632 sd_card
->sd_clock
= chip
->option
.asic_sd_sdr104_clk
;
634 sd_card
->sd_clock
= chip
->option
.fpga_sd_sdr104_clk
;
635 } else if (CHK_SD_DDR50(sd_card
)) {
637 sd_card
->sd_clock
= chip
->option
.asic_sd_ddr50_clk
;
639 sd_card
->sd_clock
= chip
->option
.fpga_sd_ddr50_clk
;
640 } else if (CHK_SD_SDR50(sd_card
)) {
642 sd_card
->sd_clock
= chip
->option
.asic_sd_sdr50_clk
;
644 sd_card
->sd_clock
= chip
->option
.fpga_sd_sdr50_clk
;
645 } else if (CHK_SD_HS(sd_card
)) {
647 sd_card
->sd_clock
= chip
->option
.asic_sd_hs_clk
;
649 sd_card
->sd_clock
= chip
->option
.fpga_sd_hs_clk
;
650 } else if (CHK_MMC_52M(sd_card
) || CHK_MMC_DDR52(sd_card
)) {
652 sd_card
->sd_clock
= chip
->option
.asic_mmc_52m_clk
;
654 sd_card
->sd_clock
= chip
->option
.fpga_mmc_52m_clk
;
655 } else if (CHK_MMC_26M(sd_card
)) {
656 if (chip
->asic_code
) {
657 sd_card
->sd_clock
= 46;
658 RTS51X_DEBUGP("Set MMC clock to 22.5MHz\n");
660 sd_card
->sd_clock
= CLK_50
;
665 static int sd_set_init_para(struct rts51x_chip
*chip
)
667 struct sd_info
*sd_card
= &(chip
->sd_card
);
670 retval
= sd_set_sample_push_timing(chip
);
671 if (retval
!= STATUS_SUCCESS
)
672 TRACE_RET(chip
, retval
);
674 sd_choose_proper_clock(chip
);
676 retval
= switch_clock(chip
, sd_card
->sd_clock
);
677 if (retval
!= STATUS_SUCCESS
)
678 TRACE_RET(chip
, retval
);
680 return STATUS_SUCCESS
;
683 int rts51x_sd_select_card(struct rts51x_chip
*chip
, int select
)
685 struct sd_info
*sd_card
= &(chip
->sd_card
);
687 u8 cmd_idx
, cmd_type
;
691 cmd_idx
= SELECT_CARD
;
692 cmd_type
= SD_RSP_TYPE_R1
;
693 addr
= sd_card
->sd_addr
;
695 cmd_idx
= DESELECT_CARD
;
696 cmd_type
= SD_RSP_TYPE_R0
;
700 retval
= sd_send_cmd_get_rsp(chip
, cmd_idx
, addr
, cmd_type
, NULL
, 0);
701 if (retval
!= STATUS_SUCCESS
)
702 TRACE_RET(chip
, retval
);
704 return STATUS_SUCCESS
;
707 static int sd_wait_currentstate_dataready(struct rts51x_chip
*chip
, u8 statechk
,
708 u8 rdychk
, u16 pollingcnt
)
710 struct sd_info
*sd_card
= &(chip
->sd_card
);
715 for (i
= 0; i
< pollingcnt
; i
++) {
718 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
719 SD_RSP_TYPE_R1
, rsp
, 5);
720 if (retval
== STATUS_SUCCESS
) {
721 if (((rsp
[3] & 0x1E) == statechk
)
722 && ((rsp
[3] & 0x01) == rdychk
)) {
723 return STATUS_SUCCESS
;
726 rts51x_clear_sd_error(chip
);
727 TRACE_RET(chip
, STATUS_FAIL
);
731 return STATUS_TIMEDOUT
;
734 static int sd_voltage_switch(struct rts51x_chip
*chip
)
739 RTS51X_WRITE_REG(chip
, SD_BUS_STAT
,
740 SD_CLK_TOGGLE_EN
| SD_CLK_FORCE_STOP
,
744 sd_send_cmd_get_rsp(chip
, VOLTAGE_SWITCH
, 0, SD_RSP_TYPE_R1
, NULL
,
746 if (retval
!= STATUS_SUCCESS
)
747 TRACE_RET(chip
, retval
);
749 RTS51X_READ_REG(chip
, SD_BUS_STAT
, &stat
);
750 if (stat
& (SD_CMD_STATUS
| SD_DAT3_STATUS
| SD_DAT2_STATUS
|
751 SD_DAT1_STATUS
| SD_DAT0_STATUS
))
752 TRACE_RET(chip
, STATUS_FAIL
);
754 rts51x_init_cmd(chip
);
755 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BUS_STAT
, 0xFF,
757 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_PAD_CTL
, SD_IO_USING_1V8
,
760 rts51x_add_cmd(chip
, WRITE_REG_CMD
, LDO_POWER_CFG
,
761 TUNE_SD18_MASK
, TUNE_SD18_1V8
);
762 retval
= rts51x_send_cmd(chip
, MODE_C
, 100);
763 if (retval
!= STATUS_SUCCESS
)
764 TRACE_RET(chip
, retval
);
766 wait_timeout(chip
->option
.D3318_off_delay
);
768 RTS51X_WRITE_REG(chip
, SD_BUS_STAT
, 0xFF, SD_CLK_TOGGLE_EN
);
771 RTS51X_READ_REG(chip
, SD_BUS_STAT
, &stat
);
772 if ((stat
& (SD_CMD_STATUS
| SD_DAT3_STATUS
| SD_DAT2_STATUS
|
773 SD_DAT1_STATUS
| SD_DAT0_STATUS
)) !=
774 (SD_CMD_STATUS
| SD_DAT3_STATUS
| SD_DAT2_STATUS
|
775 SD_DAT1_STATUS
| SD_DAT0_STATUS
)) {
776 rts51x_init_cmd(chip
);
777 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BUS_STAT
, 0xFF,
779 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_CLK_EN
, 0xFF, 0);
780 rts51x_send_cmd(chip
, MODE_C
, 100);
781 TRACE_RET(chip
, STATUS_FAIL
);
783 RTS51X_WRITE_REG(chip
, SD_BUS_STAT
,
784 SD_CLK_TOGGLE_EN
| SD_CLK_FORCE_STOP
, 0);
786 return STATUS_SUCCESS
;
789 static int sd_change_phase(struct rts51x_chip
*chip
, u8 sample_point
,
792 u16 SD_VP_CTL
, SD_DCMPS_CTL
;
796 RTS51X_DEBUGP("sd_change_phase (sample_point = %d, tune_dir = %d)\n",
797 sample_point
, tune_dir
);
799 if (tune_dir
== TUNE_RX
) {
800 SD_VP_CTL
= SD_VPCLK1_CTL
;
801 SD_DCMPS_CTL
= SD_DCMPS1_CTL
;
803 SD_VP_CTL
= SD_VPCLK0_CTL
;
804 SD_DCMPS_CTL
= SD_DCMPS0_CTL
;
807 if (chip
->asic_code
) {
808 RTS51X_WRITE_REG(chip
, CLK_DIV
, CLK_CHANGE
, CLK_CHANGE
);
809 RTS51X_WRITE_REG(chip
, SD_VP_CTL
, 0x1F, sample_point
);
810 RTS51X_WRITE_REG(chip
, SD_VPCLK0_CTL
, PHASE_NOT_RESET
, 0);
811 RTS51X_WRITE_REG(chip
, SD_VPCLK0_CTL
, PHASE_NOT_RESET
,
813 RTS51X_WRITE_REG(chip
, CLK_DIV
, CLK_CHANGE
, 0);
815 #ifdef CONFIG_RTS5139_DEBUG
816 RTS51X_READ_REG(chip
, SD_VP_CTL
, &val
);
817 RTS51X_DEBUGP("SD_VP_CTL: 0x%x\n", val
);
818 RTS51X_READ_REG(chip
, SD_DCMPS_CTL
, &val
);
819 RTS51X_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val
);
822 RTS51X_WRITE_REG(chip
, CLK_DIV
, CLK_CHANGE
, CLK_CHANGE
);
824 RTS51X_WRITE_REG(chip
, SD_VP_CTL
, 0xFF,
825 PHASE_NOT_RESET
| sample_point
);
828 rts51x_init_cmd(chip
);
829 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_DCMPS_CTL
, DCMPS_CHANGE
,
831 rts51x_add_cmd(chip
, CHECK_REG_CMD
, SD_DCMPS_CTL
,
832 DCMPS_CHANGE_DONE
, DCMPS_CHANGE_DONE
);
833 retval
= rts51x_send_cmd(chip
, MODE_CR
, 100);
834 if (retval
!= STATUS_SUCCESS
)
835 TRACE_GOTO(chip
, Fail
);
837 retval
= rts51x_get_rsp(chip
, 1, 500);
838 if (retval
!= STATUS_SUCCESS
)
839 TRACE_GOTO(chip
, Fail
);
841 val
= chip
->rsp_buf
[0];
842 if (val
& DCMPS_ERROR
)
843 TRACE_GOTO(chip
, Fail
);
844 if ((val
& DCMPS_CURRENT_PHASE
) != sample_point
)
845 TRACE_GOTO(chip
, Fail
);
846 RTS51X_WRITE_REG(chip
, SD_DCMPS_CTL
, DCMPS_CHANGE
, 0);
847 RTS51X_WRITE_REG(chip
, CLK_DIV
, CLK_CHANGE
, 0);
851 RTS51X_WRITE_REG(chip
, SD_CFG1
, SD_ASYNC_FIFO_RST
, 0);
853 return STATUS_SUCCESS
;
856 #ifdef CONFIG_RTS5139_DEBUG
857 rts51x_ep0_read_register(chip
, SD_VP_CTL
, &val
);
858 RTS51X_DEBUGP("SD_VP_CTL: 0x%x\n", val
);
859 rts51x_ep0_read_register(chip
, SD_DCMPS_CTL
, &val
);
860 RTS51X_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val
);
863 RTS51X_WRITE_REG(chip
, SD_DCMPS_CTL
, DCMPS_CHANGE
, 0);
864 RTS51X_WRITE_REG(chip
, SD_VP_CTL
, PHASE_CHANGE
, 0);
870 static int sd_check_spec(struct rts51x_chip
*chip
, u8 bus_width
)
872 struct sd_info
*sd_card
= &(chip
->sd_card
);
877 sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
,
879 if (retval
!= STATUS_SUCCESS
)
880 TRACE_RET(chip
, STATUS_FAIL
);
882 cmd
[0] = 0x40 | SEND_SCR
;
889 sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
, 5, 8, 1, bus_width
, buf
,
891 if (retval
!= STATUS_SUCCESS
) {
892 rts51x_clear_sd_error(chip
);
893 TRACE_RET(chip
, retval
);
896 memcpy(sd_card
->raw_scr
, buf
, 8);
898 if ((buf
[0] & 0x0F) == 0)
899 TRACE_RET(chip
, STATUS_FAIL
);
901 return STATUS_SUCCESS
;
904 static int sd_query_switch_result(struct rts51x_chip
*chip
, u8 func_group
,
905 u8 func_to_switch
, u8
*buf
, int buf_len
)
907 u8 support_mask
= 0, query_switch
= 0, switch_busy
= 0;
908 int support_offset
= 0, query_switch_offset
= 0, check_busy_offset
= 0;
910 if (func_group
== SD_FUNC_GROUP_1
) {
911 support_offset
= FUNCTION_GROUP1_SUPPORT_OFFSET
;
912 query_switch_offset
= FUNCTION_GROUP1_QUERY_SWITCH_OFFSET
;
913 check_busy_offset
= FUNCTION_GROUP1_CHECK_BUSY_OFFSET
;
915 switch (func_to_switch
) {
917 support_mask
= HS_SUPPORT_MASK
;
918 query_switch
= HS_QUERY_SWITCH_OK
;
919 switch_busy
= HS_SWITCH_BUSY
;
923 support_mask
= SDR50_SUPPORT_MASK
;
924 query_switch
= SDR50_QUERY_SWITCH_OK
;
925 switch_busy
= SDR50_SWITCH_BUSY
;
929 support_mask
= SDR104_SUPPORT_MASK
;
930 query_switch
= SDR104_QUERY_SWITCH_OK
;
931 switch_busy
= SDR104_SWITCH_BUSY
;
935 support_mask
= DDR50_SUPPORT_MASK
;
936 query_switch
= DDR50_QUERY_SWITCH_OK
;
937 switch_busy
= DDR50_SWITCH_BUSY
;
941 TRACE_RET(chip
, STATUS_FAIL
);
943 } else if (func_group
== SD_FUNC_GROUP_3
) {
944 support_offset
= FUNCTION_GROUP3_SUPPORT_OFFSET
;
945 query_switch_offset
= FUNCTION_GROUP3_QUERY_SWITCH_OFFSET
;
946 check_busy_offset
= FUNCTION_GROUP3_CHECK_BUSY_OFFSET
;
948 switch (func_to_switch
) {
950 support_mask
= DRIVING_TYPE_A_MASK
;
951 query_switch
= TYPE_A_QUERY_SWITCH_OK
;
952 switch_busy
= TYPE_A_SWITCH_BUSY
;
956 support_mask
= DRIVING_TYPE_C_MASK
;
957 query_switch
= TYPE_C_QUERY_SWITCH_OK
;
958 switch_busy
= TYPE_C_SWITCH_BUSY
;
962 support_mask
= DRIVING_TYPE_D_MASK
;
963 query_switch
= TYPE_D_QUERY_SWITCH_OK
;
964 switch_busy
= TYPE_D_SWITCH_BUSY
;
968 TRACE_RET(chip
, STATUS_FAIL
);
970 } else if (func_group
== SD_FUNC_GROUP_4
) {
971 support_offset
= FUNCTION_GROUP4_SUPPORT_OFFSET
;
972 query_switch_offset
= FUNCTION_GROUP4_QUERY_SWITCH_OFFSET
;
973 check_busy_offset
= FUNCTION_GROUP4_CHECK_BUSY_OFFSET
;
975 switch (func_to_switch
) {
976 case CURRENT_LIMIT_400
:
977 support_mask
= CURRENT_LIMIT_400_MASK
;
978 query_switch
= CURRENT_LIMIT_400_QUERY_SWITCH_OK
;
979 switch_busy
= CURRENT_LIMIT_400_SWITCH_BUSY
;
982 case CURRENT_LIMIT_600
:
983 support_mask
= CURRENT_LIMIT_600_MASK
;
984 query_switch
= CURRENT_LIMIT_600_QUERY_SWITCH_OK
;
985 switch_busy
= CURRENT_LIMIT_600_SWITCH_BUSY
;
988 case CURRENT_LIMIT_800
:
989 support_mask
= CURRENT_LIMIT_800_MASK
;
990 query_switch
= CURRENT_LIMIT_800_QUERY_SWITCH_OK
;
991 switch_busy
= CURRENT_LIMIT_800_SWITCH_BUSY
;
995 TRACE_RET(chip
, STATUS_FAIL
);
998 TRACE_RET(chip
, STATUS_FAIL
);
1001 if (func_group
== SD_FUNC_GROUP_4
)
1002 buf
[query_switch_offset
] =
1003 (buf
[query_switch_offset
] & 0xf0) >> 4;
1004 if (!(buf
[support_offset
] & support_mask
) ||
1005 ((buf
[query_switch_offset
] & 0x0F) != query_switch
))
1006 TRACE_RET(chip
, STATUS_FAIL
);
1008 if ((buf
[DATA_STRUCTURE_VER_OFFSET
] == 0x01) &&
1009 ((buf
[check_busy_offset
] & switch_busy
) == switch_busy
))
1010 TRACE_RET(chip
, STATUS_FAIL
);
1012 return STATUS_SUCCESS
;
1015 static int sd_check_switch_mode(struct rts51x_chip
*chip
, u8 mode
,
1016 u8 func_group
, u8 func_to_switch
, u8 bus_width
)
1018 struct sd_info
*sd_card
= &(chip
->sd_card
);
1022 RTS51X_DEBUGP("sd_check_switch_mode (mode = %d, func_group = %d,"
1023 "func_to_switch = %d)\n", mode
, func_group
, func_to_switch
);
1025 cmd
[0] = 0x40 | SWITCH
;
1028 if (func_group
== SD_FUNC_GROUP_1
) {
1031 cmd
[4] = 0xF0 + func_to_switch
;
1032 } else if (func_group
== SD_FUNC_GROUP_3
) {
1034 cmd
[3] = 0xF0 + func_to_switch
;
1036 } else if (func_group
== SD_FUNC_GROUP_4
) {
1038 cmd
[3] = 0x0F + (func_to_switch
<< 4);
1041 cmd
[1] = SD_CHECK_MODE
;
1048 sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
, 5, 64, 1, bus_width
, buf
,
1050 if (retval
!= STATUS_SUCCESS
) {
1051 rts51x_clear_sd_error(chip
);
1052 TRACE_RET(chip
, retval
);
1055 if (func_group
== NO_ARGUMENT
) {
1056 sd_card
->func_group1_mask
= buf
[0x0D];
1057 sd_card
->func_group2_mask
= buf
[0x0B];
1058 sd_card
->func_group3_mask
= buf
[0x09];
1059 sd_card
->func_group4_mask
= buf
[0x07];
1061 RTS51X_DEBUGP("func_group1_mask = 0x%02x\n", buf
[0x0D]);
1062 RTS51X_DEBUGP("func_group2_mask = 0x%02x\n", buf
[0x0B]);
1063 RTS51X_DEBUGP("func_group3_mask = 0x%02x\n", buf
[0x09]);
1064 RTS51X_DEBUGP("func_group4_mask = 0x%02x\n", buf
[0x07]);
1066 if ((buf
[0] == 0) && (buf
[1] == 0))
1067 TRACE_RET(chip
, STATUS_FAIL
);
1069 sd_query_switch_result(chip
, func_group
, func_to_switch
,
1071 if (retval
!= STATUS_SUCCESS
)
1072 TRACE_RET(chip
, retval
);
1075 return STATUS_SUCCESS
;
1078 static int sd_check_switch(struct rts51x_chip
*chip
,
1079 u8 func_group
, u8 func_to_switch
, u8 bus_width
)
1083 int switch_good
= 0;
1085 for (i
= 0; i
< 3; i
++) {
1086 if (monitor_card_cd(chip
, SD_CARD
) == CD_NOT_EXIST
) {
1087 sd_set_reset_fail(chip
, SD_RESET_FAIL
);
1088 TRACE_RET(chip
, STATUS_FAIL
);
1091 retval
= sd_check_switch_mode(chip
, SD_CHECK_MODE
, func_group
,
1092 func_to_switch
, bus_width
);
1093 if (retval
== STATUS_SUCCESS
) {
1096 retval
= sd_check_switch_mode(chip
, SD_SWITCH_MODE
,
1097 func_group
, func_to_switch
, bus_width
);
1098 if (retval
== STATUS_SUCCESS
) {
1103 RTS51X_READ_REG(chip
, SD_STAT1
, &stat
);
1105 if (stat
& SD_CRC16_ERR
) {
1106 RTS51X_DEBUGP("SD CRC16 error when switching"
1108 TRACE_RET(chip
, STATUS_FAIL
);
1116 TRACE_RET(chip
, STATUS_FAIL
);
1118 return STATUS_SUCCESS
;
1121 static int sd_switch_function(struct rts51x_chip
*chip
, u8 bus_width
)
1123 struct sd_info
*sd_card
= &(chip
->sd_card
);
1126 u8 func_to_switch
= 0;
1128 /* Get supported functions */
1129 retval
= sd_check_switch_mode(chip
, SD_CHECK_MODE
,
1130 NO_ARGUMENT
, NO_ARGUMENT
, bus_width
);
1131 if (retval
!= STATUS_SUCCESS
)
1132 TRACE_RET(chip
, retval
);
1134 sd_card
->func_group1_mask
&= ~(sd_card
->sd_switch_fail
);
1136 for (i
= 0; i
< 4; i
++) {
1137 switch ((u8
) (chip
->option
.sd_speed_prior
>> (i
* 8))) {
1139 if ((sd_card
->func_group1_mask
& DDR50_SUPPORT_MASK
)
1140 && (CHECK_UHS50(chip
)))
1141 func_to_switch
= DDR50_SUPPORT
;
1145 if ((sd_card
->func_group1_mask
& SDR50_SUPPORT_MASK
)
1146 && (CHECK_UHS50(chip
)))
1147 func_to_switch
= SDR50_SUPPORT
;
1151 if (sd_card
->func_group1_mask
& HS_SUPPORT_MASK
)
1152 func_to_switch
= HS_SUPPORT
;
1162 RTS51X_DEBUGP("SD_FUNC_GROUP_1: func_to_switch = 0x%02x",
1165 if (func_to_switch
) {
1167 sd_check_switch(chip
, SD_FUNC_GROUP_1
, func_to_switch
,
1169 if (retval
!= STATUS_SUCCESS
) {
1170 if (func_to_switch
== SDR104_SUPPORT
)
1171 sd_card
->sd_switch_fail
= SDR104_SUPPORT_MASK
;
1172 else if (func_to_switch
== DDR50_SUPPORT
)
1173 sd_card
->sd_switch_fail
= DDR50_SUPPORT_MASK
;
1174 else if (func_to_switch
== SDR50_SUPPORT
)
1175 sd_card
->sd_switch_fail
= SDR50_SUPPORT_MASK
;
1176 else if (func_to_switch
== HS_SUPPORT
)
1177 sd_card
->sd_switch_fail
= HS_SUPPORT_MASK
;
1179 TRACE_RET(chip
, retval
);
1182 if (func_to_switch
== SDR104_SUPPORT
)
1183 SET_SD_SDR104(sd_card
);
1184 else if (func_to_switch
== DDR50_SUPPORT
)
1185 SET_SD_DDR50(sd_card
);
1186 else if (func_to_switch
== SDR50_SUPPORT
)
1187 SET_SD_SDR50(sd_card
);
1192 if (CHK_SD_DDR50(sd_card
))
1193 RTS51X_WRITE_REG(chip
, SD_CFG1
, 0x0C, SD_DDR_MODE
);
1196 if (sd_card
->func_group4_mask
& CURRENT_LIMIT_400_MASK
)
1197 func_to_switch
= CURRENT_LIMIT_400
;
1199 if (func_to_switch
) {
1200 RTS51X_DEBUGP("Try to switch current_limit_400\n");
1202 sd_check_switch(chip
, SD_FUNC_GROUP_4
, func_to_switch
,
1204 RTS51X_DEBUGP("Switch current_limit_400 status: (%d)\n",
1208 return STATUS_SUCCESS
;
1211 static int sd_wait_data_idle(struct rts51x_chip
*chip
)
1213 int retval
= STATUS_TIMEDOUT
;
1217 for (i
= 0; i
< 100; i
++) {
1218 retval
= rts51x_ep0_read_register(chip
, SD_DATA_STATE
, &val
);
1219 if (retval
!= STATUS_SUCCESS
)
1220 TRACE_RET(chip
, STATUS_FAIL
);
1221 if (val
& SD_DATA_IDLE
) {
1222 retval
= STATUS_SUCCESS
;
1227 RTS51X_DEBUGP("SD_DATA_STATE: 0x%02x\n", val
);
1232 static int sd_sdr_tuning_rx_cmd(struct rts51x_chip
*chip
, u8 sample_point
)
1237 retval
= sd_change_phase(chip
, sample_point
, TUNE_RX
);
1238 if (retval
!= STATUS_SUCCESS
)
1239 TRACE_RET(chip
, retval
);
1241 cmd
[0] = 0x40 | SEND_TUNING_PATTERN
;
1247 retval
= sd_read_data(chip
, SD_TM_AUTO_TUNING
,
1248 cmd
, 5, 0x40, 1, SD_BUS_WIDTH_4
, NULL
, 0, 100);
1249 if (retval
!= STATUS_SUCCESS
) {
1250 /* Wait till SD DATA IDLE */
1251 (void)sd_wait_data_idle(chip
);
1253 rts51x_clear_sd_error(chip
);
1254 TRACE_RET(chip
, STATUS_FAIL
);
1257 return STATUS_SUCCESS
;
1260 static int sd_ddr_tuning_rx_cmd(struct rts51x_chip
*chip
, u8 sample_point
)
1262 struct sd_info
*sd_card
= &(chip
->sd_card
);
1266 retval
= sd_change_phase(chip
, sample_point
, TUNE_RX
);
1267 if (retval
!= STATUS_SUCCESS
)
1268 TRACE_RET(chip
, retval
);
1270 RTS51X_DEBUGP("sd ddr tuning rx\n");
1273 sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
,
1275 if (retval
!= STATUS_SUCCESS
)
1276 TRACE_RET(chip
, retval
);
1278 cmd
[0] = 0x40 | SD_STATUS
;
1284 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
,
1285 cmd
, 5, 64, 1, SD_BUS_WIDTH_4
, NULL
, 0, 100);
1286 if (retval
!= STATUS_SUCCESS
) {
1287 /* Wait till SD DATA IDLE */
1288 (void)sd_wait_data_idle(chip
);
1290 rts51x_clear_sd_error(chip
);
1291 TRACE_RET(chip
, STATUS_FAIL
);
1294 return STATUS_SUCCESS
;
1297 static int mmc_ddr_tunning_rx_cmd(struct rts51x_chip
*chip
, u8 sample_point
)
1299 struct sd_info
*sd_card
= &(chip
->sd_card
);
1301 u8 cmd
[5], bus_width
;
1303 if (CHK_MMC_8BIT(sd_card
))
1304 bus_width
= SD_BUS_WIDTH_8
;
1305 else if (CHK_MMC_4BIT(sd_card
))
1306 bus_width
= SD_BUS_WIDTH_4
;
1308 bus_width
= SD_BUS_WIDTH_1
;
1310 retval
= sd_change_phase(chip
, sample_point
, TUNE_RX
);
1311 if (retval
!= STATUS_SUCCESS
)
1312 TRACE_RET(chip
, retval
);
1314 RTS51X_DEBUGP("mmc ddr tuning rx\n");
1316 cmd
[0] = 0x40 | SEND_EXT_CSD
;
1322 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
,
1323 cmd
, 5, 0x200, 1, bus_width
, NULL
, 0, 100);
1324 if (retval
!= STATUS_SUCCESS
) {
1325 /* Wait till SD DATA IDLE */
1326 (void)sd_wait_data_idle(chip
);
1328 rts51x_clear_sd_error(chip
);
1329 TRACE_RET(chip
, STATUS_FAIL
);
1332 return STATUS_SUCCESS
;
1335 static int sd_sdr_tuning_tx_cmd(struct rts51x_chip
*chip
, u8 sample_point
)
1337 struct sd_info
*sd_card
= &(chip
->sd_card
);
1340 retval
= sd_change_phase(chip
, sample_point
, TUNE_TX
);
1341 if (retval
!= STATUS_SUCCESS
)
1342 TRACE_RET(chip
, retval
);
1344 RTS51X_WRITE_REG(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
,
1345 SD_RSP_80CLK_TIMEOUT_EN
);
1347 retval
= sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
1348 SD_RSP_TYPE_R1
, NULL
, 0);
1349 if (retval
!= STATUS_SUCCESS
) {
1350 if (sd_check_err_code(chip
, SD_RSP_TIMEOUT
)) {
1351 /* Tunning TX fail */
1352 rts51x_ep0_write_register(chip
, SD_CFG3
,
1353 SD_RSP_80CLK_TIMEOUT_EN
, 0);
1354 TRACE_RET(chip
, STATUS_FAIL
);
1358 RTS51X_WRITE_REG(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
, 0);
1360 return STATUS_SUCCESS
;
1363 static int sd_ddr_tuning_tx_cmd(struct rts51x_chip
*chip
, u8 sample_point
)
1365 struct sd_info
*sd_card
= &(chip
->sd_card
);
1367 u8 cmd
[5], bus_width
;
1369 retval
= sd_change_phase(chip
, sample_point
, TUNE_TX
);
1370 if (retval
!= STATUS_SUCCESS
)
1371 TRACE_RET(chip
, retval
);
1373 if (CHK_SD(sd_card
)) {
1374 bus_width
= SD_BUS_WIDTH_4
;
1376 if (CHK_MMC_8BIT(sd_card
))
1377 bus_width
= SD_BUS_WIDTH_8
;
1378 else if (CHK_MMC_4BIT(sd_card
))
1379 bus_width
= SD_BUS_WIDTH_4
;
1381 bus_width
= SD_BUS_WIDTH_1
;
1383 retval
= sd_wait_currentstate_dataready(chip
, 0x08, 1, 20);
1384 if (retval
!= STATUS_SUCCESS
)
1385 TRACE_RET(chip
, STATUS_FAIL
);
1387 RTS51X_WRITE_REG(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
,
1388 SD_RSP_80CLK_TIMEOUT_EN
);
1390 cmd
[0] = 0x40 | PROGRAM_CSD
;
1396 retval
= sd_write_data(chip
, SD_TM_AUTO_WRITE_2
,
1397 cmd
, 5, 16, 1, bus_width
, sd_card
->raw_csd
, 16, 100);
1398 if (retval
!= STATUS_SUCCESS
) {
1399 rts51x_clear_sd_error(chip
);
1400 /* Tunning TX fail */
1401 rts51x_ep0_write_register(chip
, SD_CFG3
,
1402 SD_RSP_80CLK_TIMEOUT_EN
, 0);
1403 TRACE_RET(chip
, STATUS_FAIL
);
1406 RTS51X_WRITE_REG(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
, 0);
1408 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
,
1411 return STATUS_SUCCESS
;
1414 static u8
sd_search_final_phase(struct rts51x_chip
*chip
, u32 phase_map
,
1417 struct sd_info
*sd_card
= &(chip
->sd_card
);
1418 struct timing_phase_path path
[MAX_PHASE
+ 1];
1419 int i
, j
, cont_path_cnt
;
1420 int new_block
, max_len
;
1421 u8 final_phase
= 0xFF;
1424 if (phase_map
== 0xffff) {
1425 if (CHK_SD_DDR50(sd_card
)) {
1426 if (tune_dir
== TUNE_TX
)
1427 final_phase
= chip
->option
.ddr50_tx_phase
;
1429 final_phase
= chip
->option
.ddr50_rx_phase
;
1430 RTS51X_DEBUGP("DDR50 tuning dir:%d all pass,"
1431 "so select default phase:0x%x.\n",
1432 tune_dir
, final_phase
);
1434 if (tune_dir
== TUNE_TX
)
1435 final_phase
= chip
->option
.sdr50_tx_phase
;
1437 final_phase
= chip
->option
.sdr50_rx_phase
;
1438 RTS51X_DEBUGP("SDR50 tuning dir:%d all pass,"
1439 "so select default phase:0x%x.\n",
1440 tune_dir
, final_phase
);
1448 for (i
= 0; i
< MAX_PHASE
+ 1; i
++) {
1449 if (phase_map
& (1 << i
)) {
1452 j
= cont_path_cnt
++;
1460 if (cont_path_cnt
) {
1461 int idx
= cont_path_cnt
- 1;
1463 path
[idx
].end
- path
[idx
].start
+ 1;
1465 path
[idx
].start
+ path
[idx
].len
/ 2;
1470 if (cont_path_cnt
== 0) {
1471 RTS51X_DEBUGP("No continuous phase path\n");
1474 int idx
= cont_path_cnt
- 1;
1475 path
[idx
].len
= path
[idx
].end
- path
[idx
].start
+ 1;
1476 path
[idx
].mid
= path
[idx
].start
+ path
[idx
].len
/ 2;
1479 if ((path
[0].start
== 0) &&
1480 (path
[cont_path_cnt
- 1].end
== MAX_PHASE
)) {
1481 path
[0].start
= path
[cont_path_cnt
- 1].start
- MAX_PHASE
- 1;
1482 path
[0].len
+= path
[cont_path_cnt
- 1].len
;
1483 path
[0].mid
= path
[0].start
+ path
[0].len
/ 2;
1484 if (path
[0].mid
< 0)
1485 path
[0].mid
+= MAX_PHASE
+ 1;
1491 for (i
= 0; i
< cont_path_cnt
; i
++) {
1492 if (path
[i
].len
> max_len
) {
1493 max_len
= path
[i
].len
;
1494 final_phase
= (u8
) path
[i
].mid
;
1498 RTS51X_DEBUGP("path[%d].start = %d\n", i
, path
[i
].start
);
1499 RTS51X_DEBUGP("path[%d].end = %d\n", i
, path
[i
].end
);
1500 RTS51X_DEBUGP("path[%d].len = %d\n", i
, path
[i
].len
);
1501 RTS51X_DEBUGP("path[%d].mid = %d\n", i
, path
[i
].mid
);
1502 RTS51X_DEBUGP("\n");
1505 if ((tune_dir
== TUNE_TX
) && (CHK_SD_SDR50(sd_card
))
1506 && chip
->option
.sdr50_phase_sel
) {
1508 int temp_mid
= (max_len
- 6) / 2;
1509 int temp_final_phase
=
1510 path
[final_path_idx
].end
- (max_len
-
1513 if (temp_final_phase
< 0)
1514 final_phase
= temp_final_phase
+ MAX_PHASE
+ 1;
1516 final_phase
= (u8
) temp_final_phase
;
1521 RTS51X_DEBUGP("Final chosen phase: %d\n", final_phase
);
1525 static int sd_tuning_rx(struct rts51x_chip
*chip
)
1527 struct sd_info
*sd_card
= &(chip
->sd_card
);
1530 u32 raw_phase_map
[3], phase_map
;
1532 int (*tuning_cmd
)(struct rts51x_chip
*chip
, u8 sample_point
);
1534 if (CHK_SD(sd_card
)) {
1535 if (CHK_SD_DDR50(sd_card
))
1536 tuning_cmd
= sd_ddr_tuning_rx_cmd
;
1538 tuning_cmd
= sd_sdr_tuning_rx_cmd
;
1540 if (CHK_MMC_DDR52(sd_card
))
1541 tuning_cmd
= mmc_ddr_tunning_rx_cmd
;
1543 TRACE_RET(chip
, STATUS_FAIL
);
1546 for (i
= 0; i
< 3; i
++) {
1547 raw_phase_map
[i
] = 0;
1548 for (j
= MAX_PHASE
; j
>= 0; j
--) {
1549 if (monitor_card_cd(chip
, SD_CARD
) == CD_NOT_EXIST
) {
1550 sd_set_reset_fail(chip
, SD_RESET_FAIL
);
1551 TRACE_RET(chip
, STATUS_FAIL
);
1554 retval
= tuning_cmd(chip
, (u8
) j
);
1555 if (retval
== STATUS_SUCCESS
)
1556 raw_phase_map
[i
] |= 1 << j
;
1558 RTS51X_DEBUGP("Tuning phase %d fail\n", j
);
1562 phase_map
= raw_phase_map
[0] & raw_phase_map
[1] & raw_phase_map
[2];
1563 for (i
= 0; i
< 3; i
++)
1564 RTS51X_DEBUGP("RX raw_phase_map[%d] = 0x%04x\n", i
,
1566 RTS51X_DEBUGP("RX phase_map = 0x%04x\n", phase_map
);
1568 final_phase
= sd_search_final_phase(chip
, phase_map
, TUNE_RX
);
1569 if (final_phase
== 0xFF)
1570 TRACE_RET(chip
, STATUS_FAIL
);
1572 retval
= tuning_cmd(chip
, final_phase
);
1573 if (retval
!= STATUS_SUCCESS
)
1574 TRACE_RET(chip
, retval
);
1576 return STATUS_SUCCESS
;
1579 static int sd_ddr_pre_tuning_tx(struct rts51x_chip
*chip
)
1581 struct sd_info
*sd_card
= &(chip
->sd_card
);
1584 u8 pre_tune_tx_phase
;
1585 u32 pre_tune_phase_map
;
1587 RTS51X_WRITE_REG(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
,
1588 SD_RSP_80CLK_TIMEOUT_EN
);
1590 pre_tune_tx_phase
= 0xFF;
1591 pre_tune_phase_map
= 0x0000;
1592 for (i
= 0; i
< MAX_PHASE
+ 1; i
++) {
1593 if (monitor_card_cd(chip
, SD_CARD
) == CD_NOT_EXIST
) {
1594 sd_set_reset_fail(chip
, SD_RESET_FAIL
);
1595 TRACE_RET(chip
, STATUS_FAIL
);
1598 retval
= sd_change_phase(chip
, (u8
) i
, TUNE_TX
);
1599 if (retval
!= STATUS_SUCCESS
)
1600 TRACE_RET(chip
, retval
);
1603 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
1604 SD_RSP_TYPE_R1
, NULL
, 0);
1605 if ((retval
== STATUS_SUCCESS
)
1606 || !sd_check_err_code(chip
, SD_RSP_TIMEOUT
))
1607 pre_tune_phase_map
|= (u32
) 1 << i
;
1610 RTS51X_WRITE_REG(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
, 0);
1613 sd_search_final_phase(chip
, pre_tune_phase_map
, TUNE_TX
);
1614 if (pre_tune_tx_phase
== 0xFF)
1615 TRACE_RET(chip
, STATUS_FAIL
);
1617 sd_change_phase(chip
, pre_tune_tx_phase
, TUNE_TX
);
1618 RTS51X_DEBUGP("DDR TX pre tune phase: %d\n", (int)pre_tune_tx_phase
);
1620 return STATUS_SUCCESS
;
1623 static int sd_tuning_tx(struct rts51x_chip
*chip
)
1625 struct sd_info
*sd_card
= &(chip
->sd_card
);
1628 u32 raw_phase_map
[3], phase_map
;
1630 int (*tuning_cmd
)(struct rts51x_chip
*chip
, u8 sample_point
);
1632 if (CHK_SD(sd_card
)) {
1633 if (CHK_SD_DDR50(sd_card
))
1634 tuning_cmd
= sd_ddr_tuning_tx_cmd
;
1636 tuning_cmd
= sd_sdr_tuning_tx_cmd
;
1638 if (CHK_MMC_DDR52(sd_card
))
1639 tuning_cmd
= sd_ddr_tuning_tx_cmd
;
1641 TRACE_RET(chip
, STATUS_FAIL
);
1644 for (i
= 0; i
< 3; i
++) {
1645 raw_phase_map
[i
] = 0;
1646 for (j
= MAX_PHASE
; j
>= 0; j
--) {
1647 if (monitor_card_cd(chip
, SD_CARD
) == CD_NOT_EXIST
) {
1648 sd_set_reset_fail(chip
, SD_RESET_FAIL
);
1649 TRACE_RET(chip
, STATUS_FAIL
);
1652 retval
= tuning_cmd(chip
, (u8
) j
);
1653 if (retval
== STATUS_SUCCESS
)
1654 raw_phase_map
[i
] |= 1 << j
;
1656 RTS51X_DEBUGP("Tuning phase %d fail\n", j
);
1660 phase_map
= raw_phase_map
[0] & raw_phase_map
[1] & raw_phase_map
[2];
1661 for (i
= 0; i
< 3; i
++)
1662 RTS51X_DEBUGP("TX raw_phase_map[%d] = 0x%04x\n", i
,
1664 RTS51X_DEBUGP("TX phase_map = 0x%04x\n", phase_map
);
1666 final_phase
= sd_search_final_phase(chip
, phase_map
, TUNE_TX
);
1667 if (final_phase
== 0xFF)
1668 TRACE_RET(chip
, STATUS_FAIL
);
1670 retval
= tuning_cmd(chip
, final_phase
);
1671 if (retval
!= STATUS_SUCCESS
)
1672 TRACE_RET(chip
, retval
);
1674 return STATUS_SUCCESS
;
1677 static int sd_sdr_tuning(struct rts51x_chip
*chip
)
1681 retval
= sd_tuning_tx(chip
);
1682 if (retval
!= STATUS_SUCCESS
)
1683 TRACE_RET(chip
, retval
);
1685 retval
= sd_tuning_rx(chip
);
1686 if (retval
!= STATUS_SUCCESS
)
1687 TRACE_RET(chip
, retval
);
1689 return STATUS_SUCCESS
;
1692 static int sd_ddr_tuning(struct rts51x_chip
*chip
)
1696 if (!(chip
->option
.sd_ctl
& SD_DDR_TX_PHASE_SET_BY_USER
)) {
1697 retval
= sd_ddr_pre_tuning_tx(chip
);
1698 if (retval
!= STATUS_SUCCESS
)
1699 TRACE_RET(chip
, retval
);
1702 sd_change_phase(chip
, (u8
) chip
->option
.sd_ddr_tx_phase
,
1704 if (retval
!= STATUS_SUCCESS
)
1705 TRACE_RET(chip
, retval
);
1708 retval
= sd_tuning_rx(chip
);
1709 if (retval
!= STATUS_SUCCESS
)
1710 TRACE_RET(chip
, retval
);
1712 if (!(chip
->option
.sd_ctl
& SD_DDR_TX_PHASE_SET_BY_USER
)) {
1713 retval
= sd_tuning_tx(chip
);
1714 if (retval
!= STATUS_SUCCESS
)
1715 TRACE_RET(chip
, retval
);
1718 return STATUS_SUCCESS
;
1721 static int mmc_ddr_tuning(struct rts51x_chip
*chip
)
1725 if (!(chip
->option
.sd_ctl
& MMC_DDR_TX_PHASE_SET_BY_USER
)) {
1726 retval
= sd_ddr_pre_tuning_tx(chip
);
1727 if (retval
!= STATUS_SUCCESS
)
1728 TRACE_RET(chip
, retval
);
1731 sd_change_phase(chip
, (u8
) chip
->option
.mmc_ddr_tx_phase
,
1733 if (retval
!= STATUS_SUCCESS
)
1734 TRACE_RET(chip
, retval
);
1737 retval
= sd_tuning_rx(chip
);
1738 if (retval
!= STATUS_SUCCESS
)
1739 TRACE_RET(chip
, retval
);
1741 if (!(chip
->option
.sd_ctl
& MMC_DDR_TX_PHASE_SET_BY_USER
)) {
1742 retval
= sd_tuning_tx(chip
);
1743 if (retval
!= STATUS_SUCCESS
)
1744 TRACE_RET(chip
, retval
);
1747 return STATUS_SUCCESS
;
1750 int rts51x_sd_switch_clock(struct rts51x_chip
*chip
)
1752 struct sd_info
*sd_card
= &(chip
->sd_card
);
1756 retval
= rts51x_select_card(chip
, SD_CARD
);
1757 if (retval
!= STATUS_SUCCESS
)
1758 TRACE_RET(chip
, retval
);
1760 if (CHK_SD30_SPEED(sd_card
) || CHK_MMC_DDR52(sd_card
)) {
1761 if (sd_card
->sd_clock
!= chip
->cur_clk
)
1765 retval
= switch_clock(chip
, sd_card
->sd_clock
);
1766 if (retval
!= STATUS_SUCCESS
)
1767 TRACE_RET(chip
, retval
);
1770 if (CHK_SD(sd_card
)) {
1771 if (CHK_SD_DDR50(sd_card
))
1772 retval
= sd_ddr_tuning(chip
);
1774 retval
= sd_sdr_tuning(chip
);
1776 if (CHK_MMC_DDR52(sd_card
))
1777 retval
= mmc_ddr_tuning(chip
);
1780 if (retval
!= STATUS_SUCCESS
)
1781 TRACE_RET(chip
, retval
);
1784 return STATUS_SUCCESS
;
1787 static int sd_prepare_reset(struct rts51x_chip
*chip
)
1789 struct sd_info
*sd_card
= &(chip
->sd_card
);
1792 if (chip
->asic_code
)
1793 sd_card
->sd_clock
= 29;
1795 sd_card
->sd_clock
= CLK_30
;
1798 retval
= sd_set_init_para(chip
);
1799 if (retval
!= STATUS_SUCCESS
)
1800 TRACE_RET(chip
, retval
);
1802 rts51x_init_cmd(chip
);
1804 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG1
, 0xFF,
1805 SD_CLK_DIVIDE_128
| SD_20_MODE
| SD_BUS_WIDTH_1
);
1806 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_SAMPLE_POINT_CTL
, 0xFF,
1808 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_PUSH_POINT_CTL
, 0xFF, 0);
1810 retval
= rts51x_send_cmd(chip
, MODE_C
, 100);
1811 if (retval
!= STATUS_SUCCESS
)
1812 TRACE_RET(chip
, retval
);
1814 retval
= rts51x_select_card(chip
, SD_CARD
);
1815 if (retval
!= STATUS_SUCCESS
)
1816 TRACE_RET(chip
, retval
);
1818 return STATUS_SUCCESS
;
1821 static void sd_pull_ctl_disable(struct rts51x_chip
*chip
)
1823 if (CHECK_PKG(chip
, LQFP48
)) {
1824 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL1
, 0xFF, 0x55);
1825 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL2
, 0xFF, 0x55);
1826 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL3
, 0xFF, 0x95);
1827 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL4
, 0xFF, 0x55);
1828 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL5
, 0xFF, 0x55);
1829 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL6
, 0xFF, 0xA5);
1831 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL1
, 0xFF, 0x65);
1832 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL2
, 0xFF, 0x55);
1833 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL3
, 0xFF, 0x95);
1834 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL4
, 0xFF, 0x55);
1835 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL5
, 0xFF, 0x56);
1836 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL6
, 0xFF, 0x59);
1840 static void sd_pull_ctl_enable(struct rts51x_chip
*chip
)
1842 if (CHECK_PKG(chip
, LQFP48
)) {
1843 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL1
, 0xFF, 0xAA);
1844 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL2
, 0xFF, 0xAA);
1845 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL3
, 0xFF, 0xA9);
1846 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL4
, 0xFF, 0x55);
1847 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL5
, 0xFF, 0x55);
1848 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL6
, 0xFF, 0xA5);
1850 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL1
, 0xFF, 0xA5);
1851 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL2
, 0xFF, 0x9A);
1852 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL3
, 0xFF, 0xA5);
1853 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL4
, 0xFF, 0x9A);
1854 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL5
, 0xFF, 0x65);
1855 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL6
, 0xFF, 0x5A);
1859 static int sd_init_power(struct rts51x_chip
*chip
)
1863 rts51x_init_cmd(chip
);
1865 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PWR_CTL
, LDO3318_PWR_MASK
,
1867 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_PAD_CTL
, SD_IO_USING_1V8
,
1869 if (chip
->asic_code
)
1870 rts51x_add_cmd(chip
, WRITE_REG_CMD
, LDO_POWER_CFG
,
1871 TUNE_SD18_MASK
, TUNE_SD18_3V3
);
1872 if (chip
->asic_code
)
1873 sd_pull_ctl_disable(chip
);
1875 rts51x_add_cmd(chip
, WRITE_REG_CMD
, FPGA_PULL_CTL
,
1876 FPGA_SD_PULL_CTL_BIT
| 0x20,
1877 FPGA_SD_PULL_CTL_BIT
);
1878 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_OE
, SD_OUTPUT_EN
, 0);
1879 if (!chip
->option
.FT2_fast_mode
)
1880 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PWR_CTL
, POWER_MASK
,
1883 retval
= rts51x_send_cmd(chip
, MODE_C
, 100);
1884 if (retval
!= STATUS_SUCCESS
)
1885 TRACE_RET(chip
, retval
);
1886 if (!chip
->option
.FT2_fast_mode
) {
1887 #ifdef SD_XD_IO_FOLLOW_PWR
1888 if (CHECK_PKG(chip
, LQFP48
)
1889 || chip
->option
.rts5129_D3318_off_enable
)
1890 rts51x_write_register(chip
, CARD_PWR_CTL
,
1895 #ifdef SD_XD_IO_FOLLOW_PWR
1896 if (CHECK_PKG(chip
, LQFP48
)
1897 || chip
->option
.rts5129_D3318_off_enable
) {
1898 rts51x_init_cmd(chip
);
1899 if (chip
->asic_code
)
1900 sd_pull_ctl_enable(chip
);
1902 rts51x_add_cmd(chip
, WRITE_REG_CMD
,
1904 FPGA_SD_PULL_CTL_BIT
| 0x20, 0);
1905 retval
= rts51x_send_cmd(chip
, MODE_C
, 100);
1906 if (retval
!= STATUS_SUCCESS
)
1907 TRACE_RET(chip
, retval
);
1909 if (chip
->asic_code
)
1910 rts51x_write_register(chip
, CARD_PULL_CTL6
,
1916 retval
= rts51x_card_power_on(chip
, SD_CARD
);
1917 if (retval
!= STATUS_SUCCESS
)
1918 TRACE_RET(chip
, retval
);
1923 rts51x_get_card_status(chip
, &(chip
->card_status
));
1924 chip
->ocp_stat
= (chip
->card_status
>> 4) & 0x03;
1926 if (chip
->ocp_stat
& (MS_OCP_NOW
| MS_OCP_EVER
)) {
1927 RTS51X_DEBUGP("Over current, OCPSTAT is 0x%x\n",
1929 TRACE_RET(chip
, STATUS_FAIL
);
1934 rts51x_init_cmd(chip
);
1935 if (chip
->asic_code
) {
1936 sd_pull_ctl_enable(chip
);
1938 rts51x_add_cmd(chip
, WRITE_REG_CMD
, FPGA_PULL_CTL
,
1939 FPGA_SD_PULL_CTL_BIT
| 0x20, 0);
1941 retval
= rts51x_send_cmd(chip
, MODE_C
, 100);
1942 if (retval
!= STATUS_SUCCESS
)
1943 TRACE_RET(chip
, retval
);
1944 #ifdef SD_XD_IO_FOLLOW_PWR
1945 rts51x_write_register(chip
, CARD_INT_PEND
, XD_INT
| MS_INT
| SD_INT
,
1946 XD_INT
| MS_INT
| SD_INT
);
1949 RTS51X_WRITE_REG(chip
, CARD_OE
, SD_OUTPUT_EN
, SD_OUTPUT_EN
);
1951 return STATUS_SUCCESS
;
1954 static int sd_dummy_clock(struct rts51x_chip
*chip
)
1956 RTS51X_WRITE_REG(chip
, SD_BUS_STAT
, SD_CLK_TOGGLE_EN
, SD_CLK_TOGGLE_EN
);
1958 RTS51X_WRITE_REG(chip
, SD_BUS_STAT
, SD_CLK_TOGGLE_EN
, 0x00);
1960 return STATUS_SUCCESS
;
1963 int reset_sd(struct rts51x_chip
*chip
)
1965 struct sd_info
*sd_card
= &(chip
->sd_card
);
1966 int retval
, i
= 0, j
= 0, k
= 0, hi_cap_flow
= 0;
1967 int sd_dont_switch
= 0;
1968 int support_1v8
= 0;
1970 u8 switch_bus_width
;
1976 CLR_RETRY_SD20_MODE(sd_card
);
1984 retval
= sd_prepare_reset(chip
);
1985 if (retval
!= STATUS_SUCCESS
)
1986 TRACE_RET(chip
, retval
);
1988 sd_dummy_clock(chip
);
1990 /* Start Initialization Process of SD Card */
1993 sd_send_cmd_get_rsp(chip
, GO_IDLE_STATE
, 0, SD_RSP_TYPE_R0
, NULL
,
1995 if (retval
!= STATUS_SUCCESS
)
1996 TRACE_RET(chip
, retval
);
2001 sd_send_cmd_get_rsp(chip
, SEND_IF_COND
, 0x000001AA, SD_RSP_TYPE_R7
,
2003 if (retval
== STATUS_SUCCESS
) {
2004 if ((rsp
[4] == 0xAA) && ((rsp
[3] & 0x0f) == 0x01)) {
2006 if (CHK_RETRY_SD20_MODE(sd_card
)) {
2009 SUPPORT_HIGH_AND_EXTENDED_CAPACITY
;
2013 SUPPORT_HIGH_AND_EXTENDED_CAPACITY
|
2014 SUPPORT_MAX_POWER_PERMANCE
| SUPPORT_1V8
;
2020 voltage
= SUPPORT_VOLTAGE
;
2023 sd_send_cmd_get_rsp(chip
, GO_IDLE_STATE
, 0, SD_RSP_TYPE_R0
,
2025 if (retval
!= STATUS_SUCCESS
)
2026 TRACE_RET(chip
, retval
);
2034 rts51x_read_register(chip
, CARD_INT_PEND
, &temp
);
2035 RTS51X_DEBUGP("CARD_INT_PEND:%x\n", temp
);
2036 if (temp
& SD_INT
) {
2037 chip
->reset_need_retry
= 1;
2038 rts51x_write_register(chip
, CARD_INT_PEND
,
2039 XD_INT
| SD_INT
| MS_INT
,
2040 XD_INT
| SD_INT
| MS_INT
);
2041 sd_set_reset_fail(chip
, SD_RESET_FAIL
);
2042 TRACE_RET(chip
, STATUS_FAIL
);
2048 sd_send_cmd_get_rsp(chip
, APP_CMD
, 0, SD_RSP_TYPE_R1
, NULL
,
2050 if (retval
!= STATUS_SUCCESS
) {
2051 if (monitor_card_cd(chip
, SD_CARD
) == CD_NOT_EXIST
) {
2052 sd_set_reset_fail(chip
, SD_RESET_FAIL
);
2053 TRACE_RET(chip
, STATUS_FAIL
);
2057 if (chip
->option
.speed_mmc
) {
2061 TRACE_RET(chip
, STATUS_FAIL
);
2066 TRACE_RET(chip
, STATUS_FAIL
);
2071 sd_send_cmd_get_rsp(chip
, SD_APP_OP_COND
, voltage
,
2072 SD_RSP_TYPE_R3
, rsp
, 5);
2073 if (retval
!= STATUS_SUCCESS
) {
2078 TRACE_RET(chip
, STATUS_FAIL
);
2083 } while (!(rsp
[1] & 0x80) && (i
< 255)); /* Not complete power on */
2087 TRACE_RET(chip
, STATUS_FAIL
);
2092 SET_SD_HCXC(sd_card
);
2094 CLR_SD_HCXC(sd_card
);
2095 if (!CHK_RETRY_SD20_MODE(sd_card
)) {
2096 if ((CHK_SD_HCXC(sd_card
)) && (CHECK_UHS50(chip
))) {
2097 support_1v8
= (rsp
[1] & 0x01) ? 1 : 0;
2098 RTS51X_DEBUGP("support_1v8 = %d\n",
2103 CLR_SD_HCXC(sd_card
);
2107 /* CMD11: Switch Voltage */
2108 if (support_1v8
&& CHECK_UHS50(chip
)
2109 && !(((u8
) chip
->option
.sd_speed_prior
& SDR104_SUPPORT
) ==
2111 retval
= sd_voltage_switch(chip
);
2112 if (retval
!= STATUS_SUCCESS
) {
2113 SET_RETRY_SD20_MODE(sd_card
);
2114 sd_init_power(chip
);
2115 RTS51X_DEBUGP("1.8v switch fail\n");
2122 sd_send_cmd_get_rsp(chip
, ALL_SEND_CID
, 0, SD_RSP_TYPE_R2
, NULL
, 0);
2123 if (retval
!= STATUS_SUCCESS
)
2124 TRACE_RET(chip
, retval
);
2128 sd_send_cmd_get_rsp(chip
, SEND_RELATIVE_ADDR
, 0, SD_RSP_TYPE_R6
,
2130 if (retval
!= STATUS_SUCCESS
)
2131 TRACE_RET(chip
, retval
);
2133 sd_card
->sd_addr
= (u32
) rsp
[1] << 24;
2134 sd_card
->sd_addr
+= (u32
) rsp
[2] << 16;
2136 /* Get CSD register for Calculating Timing,Capacity,
2137 * Check CSD to determine as if this is the SD ROM card */
2138 retval
= sd_check_csd(chip
, 1);
2139 if (retval
!= STATUS_SUCCESS
)
2140 TRACE_RET(chip
, retval
);
2141 /* Select SD card */
2142 retval
= rts51x_sd_select_card(chip
, 1);
2143 if (retval
!= STATUS_SUCCESS
)
2144 TRACE_RET(chip
, retval
);
2148 sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
,
2150 if (retval
!= STATUS_SUCCESS
)
2151 TRACE_RET(chip
, retval
);
2154 sd_send_cmd_get_rsp(chip
, SET_CLR_CARD_DETECT
, 0, SD_RSP_TYPE_R1
,
2156 if (retval
!= STATUS_SUCCESS
)
2157 TRACE_RET(chip
, retval
);
2162 sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
,
2163 SD_RSP_TYPE_R1
, NULL
, 0);
2164 if (retval
!= STATUS_SUCCESS
)
2165 TRACE_RET(chip
, retval
);
2166 /* Enable 4 bit data bus */
2168 sd_send_cmd_get_rsp(chip
, SET_BUS_WIDTH
, 2, SD_RSP_TYPE_R1
,
2170 if (retval
!= STATUS_SUCCESS
)
2171 TRACE_RET(chip
, retval
);
2172 switch_bus_width
= SD_BUS_WIDTH_4
;
2174 switch_bus_width
= SD_BUS_WIDTH_1
;
2177 /* Set block length 512 bytes for all block commands */
2178 retval
= sd_send_cmd_get_rsp(chip
, SET_BLOCKLEN
,
2179 0x200, SD_RSP_TYPE_R1
, NULL
, 0);
2180 if (retval
!= STATUS_SUCCESS
)
2181 TRACE_RET(chip
, retval
);
2183 RTS51X_WRITE_REG(chip
, SD_CFG1
, SD_CLK_DIVIDE_MASK
, SD_CLK_DIVIDE_0
);
2185 if (!(sd_card
->raw_csd
[4] & 0x40)) {
2187 RTS51X_DEBUGP("Not support class ten\n");
2190 if (!sd_dont_switch
) {
2191 /* Check the card whether flow SD1.1 spec or higher */
2192 retval
= sd_check_spec(chip
, switch_bus_width
);
2193 if (retval
== STATUS_SUCCESS
) {
2194 retval
= sd_switch_function(chip
, switch_bus_width
);
2195 if (retval
!= STATUS_SUCCESS
) {
2196 if ((sd_card
->sd_switch_fail
==
2197 SDR104_SUPPORT_MASK
)
2198 || (sd_card
->sd_switch_fail
==
2200 || (sd_card
->sd_switch_fail
==
2201 SDR50_SUPPORT_MASK
)) {
2202 sd_init_power(chip
);
2203 SET_RETRY_SD20_MODE(sd_card
);
2204 } else if (sd_card
->sd_switch_fail
==
2212 SET_RETRY_SD20_MODE(sd_card
);
2213 sd_init_power(chip
);
2224 sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
,
2225 SD_RSP_TYPE_R1
, NULL
, 0);
2226 if (retval
!= STATUS_SUCCESS
)
2227 TRACE_RET(chip
, retval
);
2228 /* Enable 4 bit data bus */
2230 sd_send_cmd_get_rsp(chip
, SET_BUS_WIDTH
, 2, SD_RSP_TYPE_R1
,
2232 if (retval
!= STATUS_SUCCESS
)
2233 TRACE_RET(chip
, retval
);
2236 if (CHK_SD30_SPEED(sd_card
)) {
2237 rts51x_write_register(chip
, SD30_DRIVE_SEL
, SD30_DRIVE_MASK
,
2240 retval
= sd_set_init_para(chip
);
2241 if (retval
!= STATUS_SUCCESS
)
2242 TRACE_RET(chip
, retval
);
2244 if (CHK_SD_DDR50(sd_card
))
2245 retval
= sd_ddr_tuning(chip
);
2247 retval
= sd_sdr_tuning(chip
);
2249 if (retval
!= STATUS_SUCCESS
) {
2250 SET_RETRY_SD20_MODE(sd_card
);
2251 RTS51X_DEBUGP("tuning phase fail,goto SD20 mode\n");
2252 sd_init_power(chip
);
2253 CLR_SD30_SPEED(sd_card
);
2256 if (STATUS_SUCCESS
==
2257 sd_wait_currentstate_dataready(chip
, 0x08, 1, 20)) {
2258 cmd
[0] = 0x40 | READ_SINGLE_BLOCK
;
2264 sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
, 5, 512,
2265 1, SD_BUS_WIDTH_4
, NULL
, 0, 600);
2266 if (retval
!= STATUS_SUCCESS
) {
2267 SET_RETRY_SD20_MODE(sd_card
);
2268 RTS51X_DEBUGP("read lba0 fail,"
2269 "goto SD20 mode\n");
2270 sd_init_power(chip
);
2271 CLR_SD30_SPEED(sd_card
);
2276 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
,
2279 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
,
2280 SD_RSP_TYPE_R1
, NULL
, 0);
2281 if (retval
== STATUS_SUCCESS
) {
2283 cmd
[0] = 0x40 | SEND_STATUS
;
2289 sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
, 5, 64, 1,
2290 SD_BUS_WIDTH_4
, buf
, 64, 600);
2291 if (ret
== STATUS_SUCCESS
) {
2292 sd_card_type
= ((u16
) buf
[2] << 8) | (u16
) buf
[3];
2293 RTS51X_DEBUGP("sd_card_type:0x%4x\n", sd_card_type
);
2294 if ((sd_card_type
== 0x0001)
2295 || (sd_card_type
== 0x0002))
2296 chip
->card_wp
|= SD_CARD
;
2298 rts51x_clear_sd_error(chip
);
2299 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
2300 SD_RSP_TYPE_R1
, NULL
, 0);
2303 rts51x_clear_sd_error(chip
);
2304 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
2305 SD_RSP_TYPE_R1
, NULL
, 0);
2308 /* Check SD Machanical Write-Protect Switch */
2309 retval
= rts51x_get_card_status(chip
, &(chip
->card_status
));
2310 if (retval
!= STATUS_SUCCESS
)
2311 TRACE_RET(chip
, retval
);
2312 if (chip
->card_status
& SD_WP
)
2313 chip
->card_wp
|= SD_CARD
;
2315 chip
->card_bus_width
[chip
->card2lun
[SD_CARD
]] = 4;
2317 return STATUS_SUCCESS
;
2320 static int mmc_test_switch_bus(struct rts51x_chip
*chip
, u8 width
)
2322 struct sd_info
*sd_card
= &(chip
->sd_card
);
2324 u8 buf
[8] = { 0 }, bus_width
;
2329 sd_send_cmd_get_rsp(chip
, BUSTEST_W
, 0, SD_RSP_TYPE_R1
, NULL
, 0);
2330 if (retval
!= STATUS_SUCCESS
)
2331 TRACE_RET(chip
, retval
);
2333 if (width
== MMC_8BIT_BUS
) {
2338 bus_width
= SD_BUS_WIDTH_8
;
2343 bus_width
= SD_BUS_WIDTH_4
;
2346 retval
= sd_write_data(chip
, SD_TM_AUTO_WRITE_3
,
2347 NULL
, 0, byte_cnt
, 1, bus_width
, buf
, len
, 100);
2348 if (retval
!= STATUS_SUCCESS
) {
2349 u8 val1
= 0, val2
= 0;
2350 rts51x_ep0_read_register(chip
, SD_STAT1
, &val1
);
2351 rts51x_ep0_read_register(chip
, SD_STAT2
, &val2
);
2352 rts51x_clear_sd_error(chip
);
2353 if ((val1
& 0xE0) || val2
)
2354 TRACE_RET(chip
, STATUS_FAIL
);
2356 RTS51X_DEBUGP("SD/MMC CMD %d\n", BUSTEST_R
);
2358 rts51x_init_cmd(chip
);
2361 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD0
, 0xFF, 0x40 | BUSTEST_R
);
2363 if (width
== MMC_8BIT_BUS
)
2364 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BYTE_CNT_L
, 0xFF, 0x08);
2366 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BYTE_CNT_L
, 0xFF, 0x04);
2368 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BLOCK_CNT_L
, 0xFF, 1);
2369 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BLOCK_CNT_H
, 0xFF, 0);
2371 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG2
, 0xFF,
2372 SD_CALCULATE_CRC7
| SD_NO_CHECK_CRC16
|
2373 SD_NO_WAIT_BUSY_END
| SD_CHECK_CRC7
| SD_RSP_LEN_6
);
2374 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01,
2376 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_TRANSFER
, 0xFF,
2377 SD_TM_NORMAL_READ
| SD_TRANSFER_START
);
2378 rts51x_add_cmd(chip
, CHECK_REG_CMD
, SD_TRANSFER
, SD_TRANSFER_END
,
2381 rts51x_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
, 0, 0);
2382 if (width
== MMC_8BIT_BUS
) {
2384 rts51x_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 1, 0, 0);
2389 retval
= rts51x_send_cmd(chip
, MODE_CR
, 100);
2390 if (retval
!= STATUS_SUCCESS
)
2391 TRACE_RET(chip
, retval
);
2393 retval
= rts51x_get_rsp(chip
, len
, 100);
2394 if (CHECK_SD_TRANS_FAIL(chip
, retval
)) {
2395 rts51x_clear_sd_error(chip
);
2396 TRACE_RET(chip
, STATUS_FAIL
);
2399 rts51x_read_rsp_buf(chip
, 1, buf
, 2);
2401 if (width
== MMC_8BIT_BUS
) {
2402 RTS51X_DEBUGP("BUSTEST_R [8bits]: 0x%02x 0x%02x\n",
2404 if ((buf
[0] == 0xAA) && (buf
[1] == 0x55)) {
2408 if (CHK_MMC_DDR52(sd_card
))
2412 /* Switch MMC to 8-bit mode */
2414 sd_send_cmd_get_rsp(chip
, SWITCH
, arg
,
2415 SD_RSP_TYPE_R1b
, rsp
, 5);
2416 if ((retval
== STATUS_SUCCESS
)
2417 && !(rsp
[4] & MMC_SWITCH_ERR
))
2418 return STATUS_SUCCESS
;
2421 RTS51X_DEBUGP("BUSTEST_R [4bits]: 0x%02x\n", buf
[0]);
2422 if (buf
[0] == 0xA5) {
2426 if (CHK_MMC_DDR52(sd_card
))
2430 /* Switch MMC to 4-bit mode */
2432 sd_send_cmd_get_rsp(chip
, SWITCH
, arg
,
2433 SD_RSP_TYPE_R1b
, rsp
, 5);
2434 if ((retval
== STATUS_SUCCESS
)
2435 && !(rsp
[4] & MMC_SWITCH_ERR
))
2436 return STATUS_SUCCESS
;
2440 TRACE_RET(chip
, STATUS_FAIL
);
2443 static int mmc_switch_timing_bus(struct rts51x_chip
*chip
)
2445 struct sd_info
*sd_card
= &(chip
->sd_card
);
2447 u8 card_type
, card_type_mask
= 0;
2450 CLR_MMC_HS(sd_card
);
2452 RTS51X_DEBUGP("SD/MMC CMD %d\n", SEND_EXT_CSD
);
2454 rts51x_init_cmd(chip
);
2456 /* SEND_EXT_CSD command */
2457 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD0
, 0xFF,
2458 0x40 | SEND_EXT_CSD
);
2459 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD1
, 0xFF, 0);
2460 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD2
, 0xFF, 0);
2461 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD3
, 0xFF, 0);
2462 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD4
, 0xFF, 0);
2464 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BYTE_CNT_L
, 0xFF, 0);
2465 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BYTE_CNT_H
, 0xFF, 2);
2466 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BLOCK_CNT_L
, 0xFF, 1);
2467 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BLOCK_CNT_H
, 0xFF, 0);
2469 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG2
, 0xFF,
2470 SD_CALCULATE_CRC7
| SD_CHECK_CRC16
| SD_NO_WAIT_BUSY_END
2471 | SD_CHECK_CRC7
| SD_RSP_LEN_6
);
2472 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01,
2474 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_TRANSFER
, 0xFF,
2475 SD_TM_NORMAL_READ
| SD_TRANSFER_START
);
2476 rts51x_add_cmd(chip
, CHECK_REG_CMD
, SD_TRANSFER
, SD_TRANSFER_END
,
2479 rts51x_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 196, 0xFF, 0);
2480 rts51x_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 212, 0xFF, 0);
2481 rts51x_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 213, 0xFF, 0);
2482 rts51x_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 214, 0xFF, 0);
2483 rts51x_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 215, 0xFF, 0);
2485 retval
= rts51x_send_cmd(chip
, MODE_CR
, 100);
2486 if (retval
!= STATUS_SUCCESS
)
2487 TRACE_RET(chip
, retval
);
2489 retval
= rts51x_get_rsp(chip
, 6, 1000);
2491 if (CHECK_SD_TRANS_FAIL(chip
, retval
)) {
2492 if (retval
== STATUS_TIMEDOUT
) {
2493 rts51x_clear_sd_error(chip
);
2494 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
2495 SD_RSP_TYPE_R1
, NULL
, 0);
2497 TRACE_RET(chip
, STATUS_FAIL
);
2500 rts51x_read_rsp_buf(chip
, 0, buf
, 6);
2502 if (buf
[0] & SD_TRANSFER_ERR
) {
2503 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
2504 SD_RSP_TYPE_R1
, NULL
, 0);
2505 TRACE_RET(chip
, STATUS_FAIL
);
2507 if (CHK_MMC_SECTOR_MODE(sd_card
))
2509 ((u32
) buf
[5] << 24) | ((u32
) buf
[4] << 16) |
2510 ((u32
) buf
[3] << 8) | ((u32
) buf
[2]);
2511 if (CHECK_UHS50(chip
))
2512 card_type_mask
= 0x07;
2514 card_type_mask
= 0x03;
2516 card_type
= buf
[1] & card_type_mask
;
2518 /* CARD TYPE FIELD = DDR52MHz, 52MHz or 26MHz */
2521 if (card_type
& 0x04)
2522 SET_MMC_DDR52(sd_card
);
2523 else if (card_type
& 0x02)
2524 SET_MMC_52M(sd_card
);
2526 SET_MMC_26M(sd_card
);
2529 sd_send_cmd_get_rsp(chip
, SWITCH
, 0x03B90100,
2530 SD_RSP_TYPE_R1b
, rsp
, 5);
2531 if ((retval
!= STATUS_SUCCESS
) || (rsp
[4] & MMC_SWITCH_ERR
))
2532 CLR_MMC_HS(sd_card
);
2534 sd_choose_proper_clock(chip
);
2535 retval
= switch_clock(chip
, sd_card
->sd_clock
);
2536 if (retval
!= STATUS_SUCCESS
)
2537 TRACE_RET(chip
, retval
);
2539 /* Test Bus Procedure */
2540 if (mmc_test_switch_bus(chip
, MMC_8BIT_BUS
) == STATUS_SUCCESS
) {
2541 SET_MMC_8BIT(sd_card
);
2542 chip
->card_bus_width
[chip
->card2lun
[SD_CARD
]] = 8;
2543 } else if (mmc_test_switch_bus(chip
, MMC_4BIT_BUS
) == STATUS_SUCCESS
) {
2544 SET_MMC_4BIT(sd_card
);
2545 chip
->card_bus_width
[chip
->card2lun
[SD_CARD
]] = 4;
2547 CLR_MMC_8BIT(sd_card
);
2548 CLR_MMC_4BIT(sd_card
);
2551 return STATUS_SUCCESS
;
2554 static int reset_mmc(struct rts51x_chip
*chip
)
2556 struct sd_info
*sd_card
= &(chip
->sd_card
);
2557 int retval
, i
= 0, j
= 0, k
= 0;
2560 u8 change_to_ddr52
= 1;
2565 retval
= sd_prepare_reset(chip
);
2566 if (retval
!= STATUS_SUCCESS
)
2567 TRACE_RET(chip
, retval
);
2573 sd_send_cmd_get_rsp(chip
, GO_IDLE_STATE
, 0, SD_RSP_TYPE_R0
, NULL
,
2575 if (retval
!= STATUS_SUCCESS
)
2576 TRACE_RET(chip
, retval
);
2581 rts51x_read_register(chip
, CARD_INT_PEND
, &temp
);
2582 if (temp
& SD_INT
) {
2583 chip
->reset_need_retry
= 1;
2584 rts51x_write_register(chip
, CARD_INT_PEND
,
2585 XD_INT
| SD_INT
| MS_INT
,
2586 XD_INT
| SD_INT
| MS_INT
);
2587 sd_set_reset_fail(chip
, MMC_RESET_FAIL
);
2588 TRACE_RET(chip
, STATUS_FAIL
);
2593 retval
= sd_send_cmd_get_rsp(chip
, SEND_OP_COND
,
2594 (SUPPORT_VOLTAGE
| 0x40000000),
2595 SD_RSP_TYPE_R3
, rsp
, 5);
2596 if (retval
!= STATUS_SUCCESS
) {
2597 if (monitor_card_cd(chip
, SD_CARD
) == CD_NOT_EXIST
) {
2598 sd_set_reset_fail(chip
, MMC_RESET_FAIL
);
2599 TRACE_RET(chip
, STATUS_FAIL
);
2602 if (sd_check_err_code(chip
, SD_BUSY
)
2603 || sd_check_err_code(chip
, SD_TO_ERR
)) {
2606 sd_clr_err_code(chip
);
2609 TRACE_RET(chip
, STATUS_FAIL
);
2614 sd_clr_err_code(chip
);
2617 TRACE_RET(chip
, STATUS_FAIL
);
2624 } while (!(rsp
[1] & 0x80) && (i
< 100)); /* Not complete power on */
2628 TRACE_RET(chip
, STATUS_FAIL
);
2631 if ((rsp
[1] & 0x60) == 0x40)
2632 SET_MMC_SECTOR_MODE(sd_card
);
2634 CLR_MMC_SECTOR_MODE(sd_card
);
2638 sd_send_cmd_get_rsp(chip
, ALL_SEND_CID
, 0, SD_RSP_TYPE_R2
, NULL
, 0);
2639 if (retval
!= STATUS_SUCCESS
)
2640 TRACE_RET(chip
, retval
);
2643 sd_card
->sd_addr
= 0x00100000;
2645 sd_send_cmd_get_rsp(chip
, SET_RELATIVE_ADDR
, sd_card
->sd_addr
,
2646 SD_RSP_TYPE_R6
, rsp
, 5);
2647 if (retval
!= STATUS_SUCCESS
)
2648 TRACE_RET(chip
, retval
);
2650 /* Get CSD register for Calculating Timing,Capacity
2651 * Check CSD to determine as if this is the SD ROM card */
2652 retval
= sd_check_csd(chip
, 1);
2653 if (retval
!= STATUS_SUCCESS
)
2654 TRACE_RET(chip
, retval
);
2655 /* Get MMC Spec_Ver in the CSD register */
2656 spec_ver
= (sd_card
->raw_csd
[0] & 0x3C) >> 2;
2658 /* Select MMC card */
2659 retval
= rts51x_sd_select_card(chip
, 1);
2660 if (retval
!= STATUS_SUCCESS
)
2661 TRACE_RET(chip
, retval
);
2663 /* Set block length 512 bytes for all block commands */
2665 sd_send_cmd_get_rsp(chip
, SET_BLOCKLEN
, 0x200, SD_RSP_TYPE_R1
, NULL
,
2667 if (retval
!= STATUS_SUCCESS
)
2668 TRACE_RET(chip
, retval
);
2670 RTS51X_WRITE_REG(chip
, SD_CFG1
, SD_CLK_DIVIDE_MASK
, SD_CLK_DIVIDE_0
);
2672 if (chip
->ic_version
< 2)
2673 rts51x_write_register(chip
, SD30_DRIVE_SEL
, SD30_DRIVE_MASK
,
2675 rts51x_write_register(chip
, CARD_DRIVE_SEL
, SD20_DRIVE_MASK
, DRIVE_8mA
);
2677 chip
->card_bus_width
[chip
->card2lun
[SD_CARD
]] = 1;
2678 if (spec_ver
== 4) {
2680 (void)mmc_switch_timing_bus(chip
);
2683 if (CHK_MMC_SECTOR_MODE(sd_card
) && (sd_card
->capacity
== 0))
2684 TRACE_RET(chip
, STATUS_FAIL
);
2686 if (CHK_MMC_DDR52(sd_card
) && change_to_ddr52
) {
2687 /* Card is extracted while identifying */
2688 if (monitor_card_cd(chip
, SD_CARD
) == CD_NOT_EXIST
)
2689 TRACE_RET(chip
, STATUS_FAIL
);
2691 retval
= sd_set_init_para(chip
);
2692 if (retval
!= STATUS_SUCCESS
) {
2693 CLR_MMC_DDR52(sd_card
);
2694 sd_init_power(chip
);
2695 change_to_ddr52
= 0;
2699 retval
= mmc_ddr_tuning(chip
);
2700 if (retval
!= STATUS_SUCCESS
) {
2701 CLR_MMC_DDR52(sd_card
);
2702 sd_init_power(chip
);
2703 change_to_ddr52
= 0;
2707 if (STATUS_SUCCESS
==
2708 sd_wait_currentstate_dataready(chip
, 0x08, 1, 20)) {
2709 cmd
[0] = 0x40 | READ_SINGLE_BLOCK
;
2714 if (CHK_MMC_8BIT(sd_card
)) {
2716 sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
,
2717 5, 512, 1, SD_BUS_WIDTH_8
,
2719 } else if (CHK_MMC_4BIT(sd_card
)) {
2721 sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
,
2722 5, 512, 1, SD_BUS_WIDTH_4
,
2726 sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
,
2727 5, 512, 1, SD_BUS_WIDTH_1
,
2731 if (retval
!= STATUS_SUCCESS
) {
2732 CLR_MMC_DDR52(sd_card
);
2733 change_to_ddr52
= 0;
2734 RTS51X_DEBUGP("read lba0 fail,"
2735 "goto SD20 mode\n");
2736 sd_init_power(chip
);
2742 retval
= rts51x_get_card_status(chip
, &(chip
->card_status
));
2743 if (retval
!= STATUS_SUCCESS
)
2744 TRACE_RET(chip
, retval
);
2745 if (chip
->card_status
& SD_WP
)
2746 chip
->card_wp
|= SD_CARD
;
2748 return STATUS_SUCCESS
;
2751 int rts51x_reset_sd_card(struct rts51x_chip
*chip
)
2753 struct sd_info
*sd_card
= &(chip
->sd_card
);
2757 memset(sd_card
, 0, sizeof(struct sd_info
));
2759 /* Init variables */
2760 sd_card
->sd_type
= 0;
2761 sd_card
->seq_mode
= 0;
2762 sd_card
->sd_data_buf_ready
= 0;
2763 sd_card
->capacity
= 0;
2764 sd_card
->sd_switch_fail
= 0;
2766 sd_clear_reset_fail(chip
);
2767 rts51x_enable_card_clock(chip
, SD_CARD
);
2769 sd_init_power(chip
);
2771 chip
->reset_need_retry
= 0;
2772 for (i
= 0; i
< 3; i
++) {
2773 if (!chip
->option
.reset_mmc_first
) { /* reset sd first */
2774 retval
= reset_sd(chip
);
2775 if (retval
!= STATUS_SUCCESS
) {
2776 /* Switch SD bus to 3V3 signal */
2777 RTS51X_WRITE_REG(chip
, SD_PAD_CTL
,
2778 SD_IO_USING_1V8
, 0);
2779 if (sd_check_reset_fail(chip
, SD_RESET_FAIL
))
2780 sd_clear_reset_fail(chip
);
2782 retval
= reset_mmc(chip
);
2784 } else { /* reset MMC first */
2785 retval
= reset_mmc(chip
);
2786 if (retval
!= STATUS_SUCCESS
) {
2787 if (sd_check_reset_fail(chip
, MMC_RESET_FAIL
)) {
2788 sd_clear_reset_fail(chip
);
2790 retval
= reset_sd(chip
);
2791 if (retval
!= STATUS_SUCCESS
) {
2794 RTS51X_WRITE_REG(chip
,
2796 SD_IO_USING_1V8
, 0);
2802 if ((retval
== STATUS_SUCCESS
) || (!chip
->reset_need_retry
)) {
2803 /* if reset success or don't need retry,then break */
2806 if (monitor_card_cd(chip
, SD_CARD
) == CD_NOT_EXIST
) {
2807 /* card is extracted */
2810 RTS51X_DEBUGP("retry reset sd card,%d\n", i
);
2811 chip
->reset_need_retry
= 0;
2814 sd_clear_reset_fail(chip
);
2815 chip
->reset_need_retry
= 0;
2817 if (retval
== STATUS_SUCCESS
) {
2818 rts51x_init_cmd(chip
);
2819 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG1
, SD_CLK_DIVIDE_MASK
,
2821 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BYTE_CNT_L
, 0xFF, 0);
2822 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BYTE_CNT_H
, 0xFF, 2);
2823 retval
= rts51x_send_cmd(chip
, MODE_C
, 100);
2824 if (retval
!= STATUS_SUCCESS
)
2825 TRACE_RET(chip
, retval
);
2827 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = sd_card
->capacity
= 0;
2828 if (chip
->option
.reset_or_rw_fail_set_pad_drive
) {
2829 rts51x_write_register(chip
, CARD_DRIVE_SEL
,
2830 SD20_DRIVE_MASK
, DRIVE_8mA
);
2832 TRACE_RET(chip
, STATUS_FAIL
);
2835 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = sd_card
->capacity
;
2837 if (chip
->option
.sd_send_status_en
) {
2838 sd_card
->sd_send_status_en
= 1;
2840 if (sd_card
->capacity
> 0x20000) { /* 64MB */
2841 sd_card
->sd_send_status_en
= 0;
2843 sd_card
->sd_send_status_en
= 1;
2846 RTS51X_DEBUGP("sd_card->sd_send_status = %d\n",
2847 sd_card
->sd_send_status_en
);
2849 retval
= sd_set_init_para(chip
);
2850 if (retval
!= STATUS_SUCCESS
)
2851 TRACE_RET(chip
, retval
);
2853 RTS51X_DEBUGP("sd_card->sd_type = 0x%x\n", sd_card
->sd_type
);
2855 return STATUS_SUCCESS
;
2858 #define WAIT_DATA_READY_RTY_CNT 255
2860 static int wait_data_buf_ready(struct rts51x_chip
*chip
)
2862 struct sd_info
*sd_card
= &(chip
->sd_card
);
2865 for (i
= 0; i
< WAIT_DATA_READY_RTY_CNT
; i
++) {
2866 if (monitor_card_cd(chip
, SD_CARD
) == CD_NOT_EXIST
)
2867 TRACE_RET(chip
, STATUS_FAIL
);
2869 sd_card
->sd_data_buf_ready
= 0;
2871 retval
= sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
2872 sd_card
->sd_addr
, SD_RSP_TYPE_R1
,
2874 if (retval
!= STATUS_SUCCESS
)
2875 TRACE_RET(chip
, retval
);
2877 if (sd_card
->sd_data_buf_ready
)
2878 return sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
2880 SD_RSP_TYPE_R1
, NULL
, 0);
2883 sd_set_err_code(chip
, SD_TO_ERR
);
2885 TRACE_RET(chip
, STATUS_FAIL
);
2888 static void sd_stop_seq_mode(struct rts51x_chip
*chip
)
2890 struct sd_info
*sd_card
= &(chip
->sd_card
);
2893 if (sd_card
->seq_mode
) {
2894 retval
= rts51x_sd_switch_clock(chip
);
2895 if (retval
!= STATUS_SUCCESS
)
2898 retval
= sd_send_cmd_get_rsp(chip
, STOP_TRANSMISSION
, 0,
2899 SD_RSP_TYPE_R1b
, NULL
, 0);
2900 if (retval
!= STATUS_SUCCESS
)
2901 sd_set_err_code(chip
, SD_STS_ERR
);
2902 sd_card
->seq_mode
= 0;
2904 rts51x_ep0_write_register(chip
, MC_FIFO_CTL
, FIFO_FLUSH
,
2909 static inline int sd_auto_tune_clock(struct rts51x_chip
*chip
)
2911 struct sd_info
*sd_card
= &(chip
->sd_card
);
2914 if (chip
->asic_code
) {
2915 if (sd_card
->sd_clock
> 30)
2916 sd_card
->sd_clock
-= 20;
2918 if (sd_card
->sd_clock
== CLK_100
)
2919 sd_card
->sd_clock
= CLK_80
;
2920 else if (sd_card
->sd_clock
== CLK_80
)
2921 sd_card
->sd_clock
= CLK_60
;
2922 else if (sd_card
->sd_clock
== CLK_60
)
2923 sd_card
->sd_clock
= CLK_50
;
2926 retval
= rts51x_sd_switch_clock(chip
);
2927 if (retval
!= STATUS_SUCCESS
)
2928 TRACE_RET(chip
, retval
);
2930 return STATUS_SUCCESS
;
2933 int rts51x_sd_rw(struct scsi_cmnd
*srb
, struct rts51x_chip
*chip
, u32 start_sector
,
2936 struct sd_info
*sd_card
= &(chip
->sd_card
);
2943 sd_card
->counter
= 0;
2945 if (!CHK_SD_HCXC(sd_card
) && !CHK_MMC_SECTOR_MODE(sd_card
))
2946 data_addr
= start_sector
<< 9;
2948 data_addr
= start_sector
;
2950 RTS51X_DEBUGP("rts51x_sd_rw, data_addr = 0x%x\n", data_addr
);
2952 sd_clr_err_code(chip
);
2954 retval
= rts51x_sd_switch_clock(chip
);
2955 if (retval
!= STATUS_SUCCESS
)
2956 TRACE_RET(chip
, retval
);
2958 if (sd_card
->seq_mode
&& ((sd_card
->pre_dir
!= srb
->sc_data_direction
)
2960 ((sd_card
->pre_sec_addr
+
2961 sd_card
->pre_sec_cnt
) != start_sector
))) {
2962 if ((sd_card
->pre_dir
== DMA_FROM_DEVICE
)
2963 && !CHK_SD30_SPEED(sd_card
)
2964 && !CHK_SD_HS(sd_card
)
2965 && !CHK_MMC_HS(sd_card
)
2966 && sd_card
->sd_send_status_en
) {
2967 sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
2968 sd_card
->sd_addr
, SD_RSP_TYPE_R1
,
2973 sd_send_cmd_get_rsp(chip
, STOP_TRANSMISSION
, 0,
2974 SD_RSP_TYPE_R1b
, NULL
, 0);
2975 if (retval
!= STATUS_SUCCESS
) {
2976 sd_set_err_code(chip
, SD_STS_ERR
);
2977 TRACE_RET(chip
, sd_parse_err_code(chip
));
2980 sd_card
->seq_mode
= 0;
2982 RTS51X_WRITE_REG(chip
, MC_FIFO_CTL
, FIFO_FLUSH
, FIFO_FLUSH
);
2984 if (!CHK_SD30_SPEED(sd_card
)
2985 && !CHK_SD_HS(sd_card
)
2986 && !CHK_MMC_HS(sd_card
)
2987 && sd_card
->sd_send_status_en
) {
2988 /* random rw, so pre_sec_cnt < 0x80 */
2989 sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
2990 sd_card
->sd_addr
, SD_RSP_TYPE_R1
,
2995 rts51x_init_cmd(chip
);
2997 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BYTE_CNT_L
, 0xFF, 0x00);
2998 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BYTE_CNT_H
, 0xFF, 0x02);
2999 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BLOCK_CNT_L
, 0xFF,
3001 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_BLOCK_CNT_H
, 0xFF,
3002 (u8
) (sector_cnt
>> 8));
3004 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01,
3007 if (CHK_MMC_8BIT(sd_card
))
3008 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG1
, 0x03,
3010 else if (CHK_MMC_4BIT(sd_card
) || CHK_SD(sd_card
))
3011 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG1
, 0x03,
3014 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG1
, 0x03,
3017 if (sd_card
->seq_mode
) {
3018 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG2
, 0xFF,
3019 SD_NO_CALCULATE_CRC7
| SD_CHECK_CRC16
|
3020 SD_NO_WAIT_BUSY_END
| SD_NO_CHECK_CRC7
|
3023 rts51x_trans_dma_enable(srb
->sc_data_direction
, chip
, sector_cnt
* 512,
3026 if (srb
->sc_data_direction
== DMA_FROM_DEVICE
) {
3028 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_TRANSFER
, 0xFF,
3029 SD_TM_AUTO_READ_3
| SD_TRANSFER_START
);
3032 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_TRANSFER
, 0xFF,
3033 SD_TM_AUTO_WRITE_3
| SD_TRANSFER_START
);
3036 rts51x_add_cmd(chip
, CHECK_REG_CMD
, SD_TRANSFER
,
3037 SD_TRANSFER_END
, SD_TRANSFER_END
);
3039 retval
= rts51x_send_cmd(chip
, flag
, 100);
3040 if (retval
!= STATUS_SUCCESS
)
3041 TRACE_RET(chip
, retval
);
3043 if (srb
->sc_data_direction
== DMA_FROM_DEVICE
) {
3044 RTS51X_DEBUGP("SD/MMC CMD %d\n", READ_MULTIPLE_BLOCK
);
3045 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD0
, 0xFF,
3046 0x40 | READ_MULTIPLE_BLOCK
);
3047 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD1
, 0xFF,
3048 (u8
) (data_addr
>> 24));
3049 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD2
, 0xFF,
3050 (u8
) (data_addr
>> 16));
3051 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD3
, 0xFF,
3052 (u8
) (data_addr
>> 8));
3053 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CMD4
, 0xFF,
3056 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG2
, 0xFF,
3057 SD_CALCULATE_CRC7
| SD_CHECK_CRC16
|
3058 SD_NO_WAIT_BUSY_END
| SD_CHECK_CRC7
|
3061 rts51x_trans_dma_enable(srb
->sc_data_direction
, chip
,
3062 sector_cnt
* 512, DMA_512
);
3064 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_TRANSFER
, 0xFF,
3065 SD_TM_AUTO_READ_2
| SD_TRANSFER_START
);
3066 rts51x_add_cmd(chip
, CHECK_REG_CMD
, SD_TRANSFER
,
3067 SD_TRANSFER_END
, SD_TRANSFER_END
);
3069 retval
= rts51x_send_cmd(chip
, MODE_CDIR
, 100);
3070 if (retval
!= STATUS_SUCCESS
)
3071 TRACE_RET(chip
, retval
);
3073 retval
= rts51x_send_cmd(chip
, MODE_C
, 50);
3074 if (retval
!= STATUS_SUCCESS
) {
3075 rts51x_clear_sd_error(chip
);
3077 sd_set_err_code(chip
, SD_TO_ERR
);
3078 TRACE_RET(chip
, sd_parse_err_code(chip
));
3081 retval
= wait_data_buf_ready(chip
);
3082 if (retval
!= STATUS_SUCCESS
) {
3083 sd_set_err_code(chip
, SD_TO_ERR
);
3084 TRACE_RET(chip
, sd_parse_err_code(chip
));
3087 retval
= sd_send_cmd_get_rsp(chip
, WRITE_MULTIPLE_BLOCK
,
3088 data_addr
, SD_RSP_TYPE_R1
,
3090 if (retval
!= STATUS_SUCCESS
) {
3091 sd_set_err_code(chip
, SD_CRC_ERR
);
3092 TRACE_RET(chip
, sd_parse_err_code(chip
));
3095 rts51x_init_cmd(chip
);
3097 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_CFG2
, 0xFF,
3098 SD_NO_CALCULATE_CRC7
| SD_CHECK_CRC16
|
3099 SD_NO_WAIT_BUSY_END
| SD_NO_CHECK_CRC7
|
3102 rts51x_trans_dma_enable(srb
->sc_data_direction
, chip
,
3103 sector_cnt
* 512, DMA_512
);
3105 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD_TRANSFER
, 0xFF,
3106 SD_TM_AUTO_WRITE_3
| SD_TRANSFER_START
);
3107 rts51x_add_cmd(chip
, CHECK_REG_CMD
, SD_TRANSFER
,
3108 SD_TRANSFER_END
, SD_TRANSFER_END
);
3110 retval
= rts51x_send_cmd(chip
, MODE_CDOR
, 100);
3111 if (retval
!= STATUS_SUCCESS
)
3112 TRACE_RET(chip
, retval
);
3115 sd_card
->seq_mode
= 1;
3118 if (srb
->sc_data_direction
== DMA_FROM_DEVICE
) {
3119 pipe
= RCV_BULK_PIPE(chip
);
3120 stageflag
= STAGE_DI
;
3122 pipe
= SND_BULK_PIPE(chip
);
3123 stageflag
= STAGE_DO
;
3127 rts51x_transfer_data_rcc(chip
, pipe
, scsi_sglist(srb
),
3128 scsi_bufflen(srb
), scsi_sg_count(srb
),
3129 NULL
, 10000, stageflag
);
3130 if (retval
!= STATUS_SUCCESS
) {
3134 sd_print_debug_reg(chip
);
3136 rts51x_ep0_read_register(chip
, SD_STAT1
, &stat
);
3137 RTS51X_DEBUGP("SD_STAT1: 0x%x\n", stat
);
3139 rts51x_clear_sd_error(chip
);
3142 sd_send_cmd_get_rsp(chip
, STOP_TRANSMISSION
, 0,
3143 SD_RSP_TYPE_R1b
, NULL
, 0);
3144 if (retval
!= STATUS_SUCCESS
) {
3145 sd_set_err_code(chip
, SD_STS_ERR
);
3146 TRACE_RET(chip
, retval
);
3149 if (stat
& (SD_CRC7_ERR
| SD_CRC16_ERR
| SD_CRC_WRITE_ERR
)) {
3150 RTS51X_DEBUGP("SD CRC error, tune clock!\n");
3151 sd_auto_tune_clock(chip
);
3154 sd_card
->seq_mode
= 0;
3156 TRACE_RET(chip
, err
);
3158 retval
= rts51x_get_rsp(chip
, 1, 2000);
3159 if (CHECK_SD_TRANS_FAIL(chip
, retval
)) {
3160 rts51x_clear_sd_error(chip
);
3161 TRACE_RET(chip
, STATUS_FAIL
);
3164 sd_card
->pre_sec_addr
= start_sector
;
3165 sd_card
->pre_sec_cnt
= sector_cnt
;
3166 sd_card
->pre_dir
= srb
->sc_data_direction
;
3168 return STATUS_SUCCESS
;
3171 void rts51x_sd_cleanup_work(struct rts51x_chip
*chip
)
3173 struct sd_info
*sd_card
= &(chip
->sd_card
);
3175 if (sd_card
->seq_mode
) {
3176 RTS51X_DEBUGP("SD: stop transmission\n");
3177 sd_stop_seq_mode(chip
);
3178 sd_card
->counter
= 0;
3182 static inline void sd_fill_power_off_card3v3(struct rts51x_chip
*chip
)
3184 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_CLK_EN
, SD_CLK_EN
, 0);
3186 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_OE
, SD_OUTPUT_EN
, 0);
3187 if (!chip
->option
.FT2_fast_mode
) {
3188 #ifdef SD_XD_IO_FOLLOW_PWR
3189 if (CHECK_PKG(chip
, LQFP48
)
3190 || chip
->option
.rts5129_D3318_off_enable
)
3191 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PWR_CTL
,
3192 POWER_MASK
| LDO_OFF
,
3193 POWER_OFF
| LDO_OFF
);
3195 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PWR_CTL
,
3196 POWER_MASK
, POWER_OFF
);
3198 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PWR_CTL
, POWER_MASK
,
3204 static int sd_power_off_card3v3(struct rts51x_chip
*chip
)
3208 rts51x_init_cmd(chip
);
3210 sd_fill_power_off_card3v3(chip
);
3212 retval
= rts51x_send_cmd(chip
, MODE_C
, 100);
3213 if (retval
!= STATUS_SUCCESS
)
3214 TRACE_RET(chip
, retval
);
3215 #ifdef SD_XD_IO_FOLLOW_PWR
3216 if (!chip
->option
.FT2_fast_mode
)
3217 wait_timeout(chip
->option
.D3318_off_delay
);
3220 return STATUS_SUCCESS
;
3223 int rts51x_release_sd_card(struct rts51x_chip
*chip
)
3225 struct sd_info
*sd_card
= &(chip
->sd_card
);
3228 RTS51X_DEBUGP("rts51x_release_sd_card\n");
3230 chip
->card_ready
&= ~SD_CARD
;
3231 chip
->card_fail
&= ~SD_CARD
;
3232 chip
->card_wp
&= ~SD_CARD
;
3234 memset(sd_card
->raw_csd
, 0, 16);
3235 memset(sd_card
->raw_scr
, 0, 8);
3237 rts51x_write_register(chip
, SFSM_ED
, HW_CMD_STOP
, HW_CMD_STOP
);
3238 rts51x_write_register(chip
, SD_PAD_CTL
, SD_IO_USING_1V8
, 0);
3239 if (CHECK_PKG(chip
, LQFP48
) || chip
->option
.rts5129_D3318_off_enable
)
3240 sd_power_off_card3v3(chip
);
3242 rts51x_init_cmd(chip
);
3243 if (!(CHECK_PKG(chip
, LQFP48
) || chip
->option
.rts5129_D3318_off_enable
))
3244 sd_fill_power_off_card3v3(chip
);
3246 if (chip
->asic_code
)
3247 sd_pull_ctl_disable(chip
);
3249 rts51x_add_cmd(chip
, WRITE_REG_CMD
, FPGA_PULL_CTL
,
3250 FPGA_SD_PULL_CTL_BIT
| 0x20,
3251 FPGA_SD_PULL_CTL_BIT
);
3253 /* Switch LDO3318 to 3.3V */
3254 rts51x_add_cmd(chip
, WRITE_REG_CMD
, LDO_POWER_CFG
, TUNE_SD18_MASK
,
3257 if (CHK_MMC_DDR52(sd_card
) && CHK_MMC_8BIT(sd_card
))
3258 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_DMA1_CTL
,
3259 EXTEND_DMA1_ASYNC_SIGNAL
,
3260 EXTEND_DMA1_ASYNC_SIGNAL
);
3261 if (CHK_SD30_SPEED(sd_card
) || CHK_MMC(sd_card
))
3262 rts51x_add_cmd(chip
, WRITE_REG_CMD
, SD30_DRIVE_SEL
,
3263 SD30_DRIVE_MASK
, chip
->option
.sd30_pad_drive
);
3264 /* Suspend LDO3318 */
3265 rts51x_add_cmd(chip
, WRITE_REG_CMD
, CARD_PWR_CTL
, LDO3318_PWR_MASK
,
3268 retval
= rts51x_send_cmd(chip
, MODE_C
, 100);
3269 if (retval
!= STATUS_SUCCESS
)
3270 TRACE_RET(chip
, retval
);
3273 return STATUS_SUCCESS
;