1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
30 #define SD_MAX_RETRY_COUNT 3
32 static u16 REG_SD_CFG1
;
33 static u16 REG_SD_CFG2
;
34 static u16 REG_SD_CFG3
;
35 static u16 REG_SD_STAT1
;
36 static u16 REG_SD_STAT2
;
37 static u16 REG_SD_BUS_STAT
;
38 static u16 REG_SD_PAD_CTL
;
39 static u16 REG_SD_SAMPLE_POINT_CTL
;
40 static u16 REG_SD_PUSH_POINT_CTL
;
41 static u16 REG_SD_CMD0
;
42 static u16 REG_SD_CMD1
;
43 static u16 REG_SD_CMD2
;
44 static u16 REG_SD_CMD3
;
45 static u16 REG_SD_CMD4
;
46 static u16 REG_SD_CMD5
;
47 static u16 REG_SD_BYTE_CNT_L
;
48 static u16 REG_SD_BYTE_CNT_H
;
49 static u16 REG_SD_BLOCK_CNT_L
;
50 static u16 REG_SD_BLOCK_CNT_H
;
51 static u16 REG_SD_TRANSFER
;
52 static u16 REG_SD_VPCLK0_CTL
;
53 static u16 REG_SD_VPCLK1_CTL
;
54 static u16 REG_SD_DCMPS0_CTL
;
55 static u16 REG_SD_DCMPS1_CTL
;
57 static inline void sd_set_err_code(struct rtsx_chip
*chip
, u8 err_code
)
59 struct sd_info
*sd_card
= &(chip
->sd_card
);
61 sd_card
->err_code
|= err_code
;
64 static inline void sd_clr_err_code(struct rtsx_chip
*chip
)
66 struct sd_info
*sd_card
= &(chip
->sd_card
);
68 sd_card
->err_code
= 0;
71 static inline int sd_check_err_code(struct rtsx_chip
*chip
, u8 err_code
)
73 struct sd_info
*sd_card
= &(chip
->sd_card
);
75 return sd_card
->err_code
& err_code
;
78 static void sd_init_reg_addr(struct rtsx_chip
*chip
)
83 REG_SD_STAT1
= 0xFD30;
87 REG_SD_SAMPLE_POINT_CTL
= 0;
88 REG_SD_PUSH_POINT_CTL
= 0;
95 REG_SD_BYTE_CNT_L
= 0xFD39;
96 REG_SD_BYTE_CNT_H
= 0xFD3A;
97 REG_SD_BLOCK_CNT_L
= 0xFD3B;
98 REG_SD_BLOCK_CNT_H
= 0xFD3C;
99 REG_SD_TRANSFER
= 0xFD32;
100 REG_SD_VPCLK0_CTL
= 0;
101 REG_SD_VPCLK1_CTL
= 0;
102 REG_SD_DCMPS0_CTL
= 0;
103 REG_SD_DCMPS1_CTL
= 0;
106 static int sd_check_data0_status(struct rtsx_chip
*chip
)
111 retval
= rtsx_read_register(chip
, REG_SD_STAT1
, &stat
);
117 if (!(stat
& SD_DAT0_STATUS
)) {
118 sd_set_err_code(chip
, SD_BUSY
);
123 return STATUS_SUCCESS
;
126 static int sd_send_cmd_get_rsp(struct rtsx_chip
*chip
, u8 cmd_idx
,
127 u32 arg
, u8 rsp_type
, u8
*rsp
, int rsp_len
)
129 struct sd_info
*sd_card
= &(chip
->sd_card
);
137 sd_clr_err_code(chip
);
139 dev_dbg(rtsx_dev(chip
), "SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx
, arg
);
141 if (rsp_type
== SD_RSP_TYPE_R1b
)
148 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD0
, 0xFF, 0x40 | cmd_idx
);
149 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD1
, 0xFF, (u8
)(arg
>> 24));
150 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD2
, 0xFF, (u8
)(arg
>> 16));
151 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD3
, 0xFF, (u8
)(arg
>> 8));
152 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD4
, 0xFF, (u8
)arg
);
154 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF, rsp_type
);
155 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
,
156 0x01, PINGPONG_BUFFER
);
157 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
,
158 0xFF, SD_TM_CMD_RSP
| SD_TRANSFER_START
);
159 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
,
160 SD_TRANSFER_END
| SD_STAT_IDLE
, SD_TRANSFER_END
| SD_STAT_IDLE
);
162 if (rsp_type
== SD_RSP_TYPE_R2
) {
163 for (reg_addr
= PPBUF_BASE2
; reg_addr
< PPBUF_BASE2
+ 16;
165 rtsx_add_cmd(chip
, READ_REG_CMD
, reg_addr
, 0, 0);
168 } else if (rsp_type
!= SD_RSP_TYPE_R0
) {
169 for (reg_addr
= REG_SD_CMD0
; reg_addr
<= REG_SD_CMD4
;
171 rtsx_add_cmd(chip
, READ_REG_CMD
, reg_addr
, 0, 0);
176 rtsx_add_cmd(chip
, READ_REG_CMD
, REG_SD_STAT1
, 0, 0);
178 retval
= rtsx_send_cmd(chip
, SD_CARD
, timeout
);
182 rtsx_read_register(chip
, REG_SD_STAT1
, &val
);
183 dev_dbg(rtsx_dev(chip
), "SD_STAT1: 0x%x\n", val
);
185 rtsx_read_register(chip
, REG_SD_CFG3
, &val
);
186 dev_dbg(rtsx_dev(chip
), "SD_CFG3: 0x%x\n", val
);
188 if (retval
== -ETIMEDOUT
) {
189 if (rsp_type
& SD_WAIT_BUSY_END
) {
190 retval
= sd_check_data0_status(chip
);
191 if (retval
!= STATUS_SUCCESS
) {
192 rtsx_clear_sd_error(chip
);
197 sd_set_err_code(chip
, SD_TO_ERR
);
199 retval
= STATUS_TIMEDOUT
;
201 retval
= STATUS_FAIL
;
203 rtsx_clear_sd_error(chip
);
209 if (rsp_type
== SD_RSP_TYPE_R0
)
210 return STATUS_SUCCESS
;
212 ptr
= rtsx_get_cmd_data(chip
) + 1;
214 if ((ptr
[0] & 0xC0) != 0) {
215 sd_set_err_code(chip
, SD_STS_ERR
);
220 if (!(rsp_type
& SD_NO_CHECK_CRC7
)) {
221 if (ptr
[stat_idx
] & SD_CRC7_ERR
) {
222 if (cmd_idx
== WRITE_MULTIPLE_BLOCK
) {
223 sd_set_err_code(chip
, SD_CRC_ERR
);
227 if (rty_cnt
< SD_MAX_RETRY_COUNT
) {
232 sd_set_err_code(chip
, SD_CRC_ERR
);
239 if ((rsp_type
== SD_RSP_TYPE_R1
) || (rsp_type
== SD_RSP_TYPE_R1b
)) {
240 if ((cmd_idx
!= SEND_RELATIVE_ADDR
) &&
241 (cmd_idx
!= SEND_IF_COND
)) {
242 if (cmd_idx
!= STOP_TRANSMISSION
) {
248 #ifdef SUPPORT_SD_LOCK
253 dev_dbg(rtsx_dev(chip
), "ptr[1]: 0x%02x\n",
259 dev_dbg(rtsx_dev(chip
), "ptr[2]: 0x%02x\n",
265 dev_dbg(rtsx_dev(chip
), "ptr[3]: 0x%02x\n",
271 sd_card
->sd_data_buf_ready
= 1;
273 sd_card
->sd_data_buf_ready
= 0;
278 memcpy(rsp
, ptr
, rsp_len
);
280 return STATUS_SUCCESS
;
283 static int sd_read_data(struct rtsx_chip
*chip
,
284 u8 trans_mode
, u8
*cmd
, int cmd_len
, u16 byte_cnt
,
285 u16 blk_cnt
, u8 bus_width
, u8
*buf
, int buf_len
,
288 struct sd_info
*sd_card
= &(chip
->sd_card
);
292 sd_clr_err_code(chip
);
305 dev_dbg(rtsx_dev(chip
), "SD/MMC CMD %d\n", cmd
[0] - 0x40);
306 for (i
= 0; i
< (min(cmd_len
, 6)); i
++)
307 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD0
+ i
,
310 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF,
312 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_H
, 0xFF,
313 (u8
)(byte_cnt
>> 8));
314 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
, 0xFF,
316 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
, 0xFF,
319 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG1
, 0x03, bus_width
);
321 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF,
322 SD_CALCULATE_CRC7
| SD_CHECK_CRC16
| SD_NO_WAIT_BUSY_END
|
323 SD_CHECK_CRC7
| SD_RSP_LEN_6
);
324 if (trans_mode
!= SD_TM_AUTO_TUNING
)
325 rtsx_add_cmd(chip
, WRITE_REG_CMD
,
326 CARD_DATA_SOURCE
, 0x01, PINGPONG_BUFFER
);
328 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
329 trans_mode
| SD_TRANSFER_START
);
330 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
, SD_TRANSFER_END
,
333 retval
= rtsx_send_cmd(chip
, SD_CARD
, timeout
);
335 if (retval
== -ETIMEDOUT
) {
336 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
337 SD_RSP_TYPE_R1
, NULL
, 0);
344 if (buf
&& buf_len
) {
345 retval
= rtsx_read_ppbuf(chip
, buf
, buf_len
);
346 if (retval
!= STATUS_SUCCESS
) {
352 return STATUS_SUCCESS
;
355 static int sd_write_data(struct rtsx_chip
*chip
, u8 trans_mode
,
356 u8
*cmd
, int cmd_len
, u16 byte_cnt
, u16 blk_cnt
, u8 bus_width
,
357 u8
*buf
, int buf_len
, int timeout
)
359 struct sd_info
*sd_card
= &(chip
->sd_card
);
363 sd_clr_err_code(chip
);
369 /* This function can't write data more than one page */
374 if (buf
&& buf_len
) {
375 retval
= rtsx_write_ppbuf(chip
, buf
, buf_len
);
376 if (retval
!= STATUS_SUCCESS
) {
385 dev_dbg(rtsx_dev(chip
), "SD/MMC CMD %d\n", cmd
[0] - 0x40);
386 for (i
= 0; i
< (min(cmd_len
, 6)); i
++) {
387 rtsx_add_cmd(chip
, WRITE_REG_CMD
,
388 REG_SD_CMD0
+ i
, 0xFF, cmd
[i
]);
391 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF,
393 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_H
, 0xFF,
394 (u8
)(byte_cnt
>> 8));
395 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
, 0xFF,
397 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
, 0xFF,
400 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG1
, 0x03, bus_width
);
402 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF,
403 SD_CALCULATE_CRC7
| SD_CHECK_CRC16
| SD_NO_WAIT_BUSY_END
|
404 SD_CHECK_CRC7
| SD_RSP_LEN_6
);
406 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
407 trans_mode
| SD_TRANSFER_START
);
408 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
, SD_TRANSFER_END
,
411 retval
= rtsx_send_cmd(chip
, SD_CARD
, timeout
);
413 if (retval
== -ETIMEDOUT
) {
414 sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
415 sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
422 return STATUS_SUCCESS
;
425 static int sd_check_csd(struct rtsx_chip
*chip
, char check_wp
)
427 struct sd_info
*sd_card
= &(chip
->sd_card
);
430 u8 csd_ver
, trans_speed
;
433 for (i
= 0; i
< 6; i
++) {
434 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
435 sd_set_err_code(chip
, SD_NO_CARD
);
440 retval
= sd_send_cmd_get_rsp(chip
, SEND_CSD
, sd_card
->sd_addr
,
441 SD_RSP_TYPE_R2
, rsp
, 16);
442 if (retval
== STATUS_SUCCESS
)
451 memcpy(sd_card
->raw_csd
, rsp
+ 1, 15);
453 dev_dbg(rtsx_dev(chip
), "CSD Response:\n");
454 dev_dbg(rtsx_dev(chip
), "%*ph\n", 16, sd_card
->raw_csd
);
456 csd_ver
= (rsp
[1] & 0xc0) >> 6;
457 dev_dbg(rtsx_dev(chip
), "csd_ver = %d\n", csd_ver
);
459 trans_speed
= rsp
[4];
460 if ((trans_speed
& 0x07) == 0x02) {
461 if ((trans_speed
& 0xf8) >= 0x30) {
463 sd_card
->sd_clock
= 47;
465 sd_card
->sd_clock
= CLK_50
;
467 } else if ((trans_speed
& 0xf8) == 0x28) {
469 sd_card
->sd_clock
= 39;
471 sd_card
->sd_clock
= CLK_40
;
473 } else if ((trans_speed
& 0xf8) == 0x20) {
475 sd_card
->sd_clock
= 29;
477 sd_card
->sd_clock
= CLK_30
;
479 } else if ((trans_speed
& 0xf8) >= 0x10) {
481 sd_card
->sd_clock
= 23;
483 sd_card
->sd_clock
= CLK_20
;
485 } else if ((trans_speed
& 0x08) >= 0x08) {
487 sd_card
->sd_clock
= 19;
489 sd_card
->sd_clock
= CLK_20
;
499 if (CHK_MMC_SECTOR_MODE(sd_card
)) {
500 sd_card
->capacity
= 0;
502 if ((!CHK_SD_HCXC(sd_card
)) || (csd_ver
== 0)) {
503 u8 blk_size
, c_size_mult
;
506 blk_size
= rsp
[6] & 0x0F;
507 c_size
= ((u16
)(rsp
[7] & 0x03) << 10)
509 + ((u16
)(rsp
[9] & 0xC0) >> 6);
510 c_size_mult
= (u8
)((rsp
[10] & 0x03) << 1);
511 c_size_mult
+= (rsp
[11] & 0x80) >> 7;
512 sd_card
->capacity
= (((u32
)(c_size
+ 1)) *
513 (1 << (c_size_mult
+ 2)))
516 u32 total_sector
= 0;
518 total_sector
= (((u32
)rsp
[8] & 0x3f) << 16) |
519 ((u32
)rsp
[9] << 8) | (u32
)rsp
[10];
520 sd_card
->capacity
= (total_sector
+ 1) << 10;
526 chip
->card_wp
|= SD_CARD
;
528 dev_dbg(rtsx_dev(chip
), "CSD WP Status: 0x%x\n", rsp
[15]);
531 return STATUS_SUCCESS
;
534 static int sd_set_sample_push_timing(struct rtsx_chip
*chip
)
537 struct sd_info
*sd_card
= &(chip
->sd_card
);
540 if ((chip
->sd_ctl
& SD_PUSH_POINT_CTL_MASK
) == SD_PUSH_POINT_DELAY
)
543 if ((chip
->sd_ctl
& SD_SAMPLE_POINT_CTL_MASK
) == SD_SAMPLE_POINT_AUTO
) {
544 if (chip
->asic_code
) {
545 if (CHK_SD_HS(sd_card
) || CHK_MMC_52M(sd_card
)) {
557 } else if ((chip
->sd_ctl
& SD_SAMPLE_POINT_CTL_MASK
) ==
558 SD_SAMPLE_POINT_DELAY
) {
565 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, 0x1C, val
);
571 return STATUS_SUCCESS
;
574 static void sd_choose_proper_clock(struct rtsx_chip
*chip
)
576 struct sd_info
*sd_card
= &(chip
->sd_card
);
578 if (CHK_SD_SDR104(sd_card
)) {
580 sd_card
->sd_clock
= chip
->asic_sd_sdr104_clk
;
582 sd_card
->sd_clock
= chip
->fpga_sd_sdr104_clk
;
584 } else if (CHK_SD_DDR50(sd_card
)) {
586 sd_card
->sd_clock
= chip
->asic_sd_ddr50_clk
;
588 sd_card
->sd_clock
= chip
->fpga_sd_ddr50_clk
;
590 } else if (CHK_SD_SDR50(sd_card
)) {
592 sd_card
->sd_clock
= chip
->asic_sd_sdr50_clk
;
594 sd_card
->sd_clock
= chip
->fpga_sd_sdr50_clk
;
596 } else if (CHK_SD_HS(sd_card
)) {
598 sd_card
->sd_clock
= chip
->asic_sd_hs_clk
;
600 sd_card
->sd_clock
= chip
->fpga_sd_hs_clk
;
602 } else if (CHK_MMC_52M(sd_card
) || CHK_MMC_DDR52(sd_card
)) {
604 sd_card
->sd_clock
= chip
->asic_mmc_52m_clk
;
606 sd_card
->sd_clock
= chip
->fpga_mmc_52m_clk
;
608 } else if (CHK_MMC_26M(sd_card
)) {
610 sd_card
->sd_clock
= 48;
612 sd_card
->sd_clock
= CLK_50
;
616 static int sd_set_clock_divider(struct rtsx_chip
*chip
, u8 clk_div
)
619 u8 mask
= 0, val
= 0;
622 if (clk_div
== SD_CLK_DIVIDE_0
)
624 else if (clk_div
== SD_CLK_DIVIDE_128
)
626 else if (clk_div
== SD_CLK_DIVIDE_256
)
629 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, mask
, val
);
635 return STATUS_SUCCESS
;
638 static int sd_set_init_para(struct rtsx_chip
*chip
)
640 struct sd_info
*sd_card
= &(chip
->sd_card
);
643 retval
= sd_set_sample_push_timing(chip
);
644 if (retval
!= STATUS_SUCCESS
) {
649 sd_choose_proper_clock(chip
);
651 retval
= switch_clock(chip
, sd_card
->sd_clock
);
652 if (retval
!= STATUS_SUCCESS
) {
657 return STATUS_SUCCESS
;
660 int sd_select_card(struct rtsx_chip
*chip
, int select
)
662 struct sd_info
*sd_card
= &(chip
->sd_card
);
664 u8 cmd_idx
, cmd_type
;
668 cmd_idx
= SELECT_CARD
;
669 cmd_type
= SD_RSP_TYPE_R1
;
670 addr
= sd_card
->sd_addr
;
672 cmd_idx
= DESELECT_CARD
;
673 cmd_type
= SD_RSP_TYPE_R0
;
677 retval
= sd_send_cmd_get_rsp(chip
, cmd_idx
, addr
, cmd_type
, NULL
, 0);
678 if (retval
!= STATUS_SUCCESS
) {
683 return STATUS_SUCCESS
;
686 #ifdef SUPPORT_SD_LOCK
687 static int sd_update_lock_status(struct rtsx_chip
*chip
)
689 struct sd_info
*sd_card
= &(chip
->sd_card
);
693 retval
= sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
694 SD_RSP_TYPE_R1
, rsp
, 5);
695 if (retval
!= STATUS_SUCCESS
) {
701 sd_card
->sd_lock_status
|= SD_LOCKED
;
703 sd_card
->sd_lock_status
&= ~SD_LOCKED
;
705 dev_dbg(rtsx_dev(chip
), "sd_card->sd_lock_status = 0x%x\n",
706 sd_card
->sd_lock_status
);
713 return STATUS_SUCCESS
;
717 static int sd_wait_state_data_ready(struct rtsx_chip
*chip
, u8 state
,
718 u8 data_ready
, int polling_cnt
)
720 struct sd_info
*sd_card
= &(chip
->sd_card
);
724 for (i
= 0; i
< polling_cnt
; i
++) {
725 retval
= sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
726 sd_card
->sd_addr
, SD_RSP_TYPE_R1
, rsp
,
728 if (retval
!= STATUS_SUCCESS
) {
733 if (((rsp
[3] & 0x1E) == state
) &&
734 ((rsp
[3] & 0x01) == data_ready
))
735 return STATUS_SUCCESS
;
742 static int sd_change_bank_voltage(struct rtsx_chip
*chip
, u8 voltage
)
746 if (voltage
== SD_IO_3V3
) {
747 if (chip
->asic_code
) {
748 retval
= rtsx_write_phy_register(chip
, 0x08,
751 if (retval
!= STATUS_SUCCESS
) {
756 retval
= rtsx_write_register(chip
, SD_PAD_CTL
,
763 } else if (voltage
== SD_IO_1V8
) {
764 if (chip
->asic_code
) {
765 retval
= rtsx_write_phy_register(chip
, 0x08,
768 if (retval
!= STATUS_SUCCESS
) {
773 retval
= rtsx_write_register(chip
, SD_PAD_CTL
,
786 return STATUS_SUCCESS
;
789 static int sd_voltage_switch(struct rtsx_chip
*chip
)
794 retval
= rtsx_write_register(chip
, SD_BUS_STAT
,
795 SD_CLK_TOGGLE_EN
| SD_CLK_FORCE_STOP
,
802 retval
= sd_send_cmd_get_rsp(chip
, VOLTAGE_SWITCH
, 0, SD_RSP_TYPE_R1
,
804 if (retval
!= STATUS_SUCCESS
) {
809 udelay(chip
->sd_voltage_switch_delay
);
811 retval
= rtsx_read_register(chip
, SD_BUS_STAT
, &stat
);
816 if (stat
& (SD_CMD_STATUS
| SD_DAT3_STATUS
| SD_DAT2_STATUS
|
817 SD_DAT1_STATUS
| SD_DAT0_STATUS
)) {
822 retval
= rtsx_write_register(chip
, SD_BUS_STAT
, 0xFF,
828 retval
= sd_change_bank_voltage(chip
, SD_IO_1V8
);
829 if (retval
!= STATUS_SUCCESS
) {
836 retval
= rtsx_write_register(chip
, SD_BUS_STAT
, 0xFF,
844 retval
= rtsx_read_register(chip
, SD_BUS_STAT
, &stat
);
849 if ((stat
& (SD_CMD_STATUS
| SD_DAT3_STATUS
| SD_DAT2_STATUS
|
850 SD_DAT1_STATUS
| SD_DAT0_STATUS
)) !=
851 (SD_CMD_STATUS
| SD_DAT3_STATUS
| SD_DAT2_STATUS
|
852 SD_DAT1_STATUS
| SD_DAT0_STATUS
)) {
853 dev_dbg(rtsx_dev(chip
), "SD_BUS_STAT: 0x%x\n", stat
);
854 rtsx_write_register(chip
, SD_BUS_STAT
,
855 SD_CLK_TOGGLE_EN
| SD_CLK_FORCE_STOP
, 0);
856 rtsx_write_register(chip
, CARD_CLK_EN
, 0xFF, 0);
861 retval
= rtsx_write_register(chip
, SD_BUS_STAT
,
862 SD_CLK_TOGGLE_EN
| SD_CLK_FORCE_STOP
, 0);
868 return STATUS_SUCCESS
;
871 static int sd_reset_dcm(struct rtsx_chip
*chip
, u8 tune_dir
)
875 if (tune_dir
== TUNE_RX
) {
876 retval
= rtsx_write_register(chip
, DCM_DRP_CTL
, 0xFF,
882 retval
= rtsx_write_register(chip
, DCM_DRP_CTL
, 0xFF, DCM_RX
);
888 retval
= rtsx_write_register(chip
, DCM_DRP_CTL
, 0xFF,
894 retval
= rtsx_write_register(chip
, DCM_DRP_CTL
, 0xFF, DCM_TX
);
901 return STATUS_SUCCESS
;
904 static int sd_change_phase(struct rtsx_chip
*chip
, u8 sample_point
, u8 tune_dir
)
906 struct sd_info
*sd_card
= &(chip
->sd_card
);
907 u16 SD_VP_CTL
, SD_DCMPS_CTL
;
912 dev_dbg(rtsx_dev(chip
), "sd_change_phase (sample_point = %d, tune_dir = %d)\n",
913 sample_point
, tune_dir
);
915 if (tune_dir
== TUNE_RX
) {
916 SD_VP_CTL
= SD_VPRX_CTL
;
917 SD_DCMPS_CTL
= SD_DCMPS_RX_CTL
;
918 if (CHK_SD_DDR50(sd_card
))
921 SD_VP_CTL
= SD_VPTX_CTL
;
922 SD_DCMPS_CTL
= SD_DCMPS_TX_CTL
;
925 if (chip
->asic_code
) {
926 retval
= rtsx_write_register(chip
, CLK_CTL
, CHANGE_CLK
,
932 retval
= rtsx_write_register(chip
, SD_VP_CTL
, 0x1F,
938 retval
= rtsx_write_register(chip
, SD_VPCLK0_CTL
,
944 retval
= rtsx_write_register(chip
, SD_VPCLK0_CTL
,
945 PHASE_NOT_RESET
, PHASE_NOT_RESET
);
950 retval
= rtsx_write_register(chip
, CLK_CTL
, CHANGE_CLK
, 0);
956 rtsx_read_register(chip
, SD_VP_CTL
, &val
);
957 dev_dbg(rtsx_dev(chip
), "SD_VP_CTL: 0x%x\n", val
);
958 rtsx_read_register(chip
, SD_DCMPS_CTL
, &val
);
959 dev_dbg(rtsx_dev(chip
), "SD_DCMPS_CTL: 0x%x\n", val
);
962 retval
= rtsx_write_register(chip
, SD_VP_CTL
,
970 retval
= rtsx_write_register(chip
, SD_VP_CTL
, 0xFF,
971 PHASE_CHANGE
| PHASE_NOT_RESET
| sample_point
);
977 retval
= rtsx_write_register(chip
, CLK_CTL
,
978 CHANGE_CLK
, CHANGE_CLK
);
984 retval
= rtsx_write_register(chip
, SD_VP_CTL
, 0xFF,
985 PHASE_NOT_RESET
| sample_point
);
994 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SD_DCMPS_CTL
, DCMPS_CHANGE
,
996 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SD_DCMPS_CTL
,
997 DCMPS_CHANGE_DONE
, DCMPS_CHANGE_DONE
);
998 retval
= rtsx_send_cmd(chip
, SD_CARD
, 100);
999 if (retval
!= STATUS_SUCCESS
) {
1004 val
= *rtsx_get_cmd_data(chip
);
1005 if (val
& DCMPS_ERROR
) {
1010 if ((val
& DCMPS_CURRENT_PHASE
) != sample_point
) {
1015 retval
= rtsx_write_register(chip
, SD_DCMPS_CTL
,
1022 retval
= rtsx_write_register(chip
, SD_VP_CTL
,
1029 retval
= rtsx_write_register(chip
, CLK_CTL
,
1040 retval
= rtsx_write_register(chip
, SD_CFG1
, SD_ASYNC_FIFO_NOT_RST
, 0);
1046 return STATUS_SUCCESS
;
1049 rtsx_read_register(chip
, SD_VP_CTL
, &val
);
1050 dev_dbg(rtsx_dev(chip
), "SD_VP_CTL: 0x%x\n", val
);
1051 rtsx_read_register(chip
, SD_DCMPS_CTL
, &val
);
1052 dev_dbg(rtsx_dev(chip
), "SD_DCMPS_CTL: 0x%x\n", val
);
1054 rtsx_write_register(chip
, SD_DCMPS_CTL
, DCMPS_CHANGE
, 0);
1055 rtsx_write_register(chip
, SD_VP_CTL
, PHASE_CHANGE
, 0);
1057 sd_reset_dcm(chip
, tune_dir
);
1061 static int sd_check_spec(struct rtsx_chip
*chip
, u8 bus_width
)
1063 struct sd_info
*sd_card
= &(chip
->sd_card
);
1067 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
,
1068 SD_RSP_TYPE_R1
, NULL
, 0);
1069 if (retval
!= STATUS_SUCCESS
) {
1074 cmd
[0] = 0x40 | SEND_SCR
;
1080 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
, 5, 8, 1, bus_width
,
1082 if (retval
!= STATUS_SUCCESS
) {
1083 rtsx_clear_sd_error(chip
);
1088 memcpy(sd_card
->raw_scr
, buf
, 8);
1090 if ((buf
[0] & 0x0F) == 0) {
1095 return STATUS_SUCCESS
;
1098 static int sd_query_switch_result(struct rtsx_chip
*chip
, u8 func_group
,
1099 u8 func_to_switch
, u8
*buf
, int buf_len
)
1101 u8 support_mask
= 0, query_switch
= 0, switch_busy
= 0;
1102 int support_offset
= 0, query_switch_offset
= 0, check_busy_offset
= 0;
1104 if (func_group
== SD_FUNC_GROUP_1
) {
1105 support_offset
= FUNCTION_GROUP1_SUPPORT_OFFSET
;
1106 query_switch_offset
= FUNCTION_GROUP1_QUERY_SWITCH_OFFSET
;
1107 check_busy_offset
= FUNCTION_GROUP1_CHECK_BUSY_OFFSET
;
1109 switch (func_to_switch
) {
1111 support_mask
= HS_SUPPORT_MASK
;
1112 query_switch
= HS_QUERY_SWITCH_OK
;
1113 switch_busy
= HS_SWITCH_BUSY
;
1117 support_mask
= SDR50_SUPPORT_MASK
;
1118 query_switch
= SDR50_QUERY_SWITCH_OK
;
1119 switch_busy
= SDR50_SWITCH_BUSY
;
1122 case SDR104_SUPPORT
:
1123 support_mask
= SDR104_SUPPORT_MASK
;
1124 query_switch
= SDR104_QUERY_SWITCH_OK
;
1125 switch_busy
= SDR104_SWITCH_BUSY
;
1129 support_mask
= DDR50_SUPPORT_MASK
;
1130 query_switch
= DDR50_QUERY_SWITCH_OK
;
1131 switch_busy
= DDR50_SWITCH_BUSY
;
1138 } else if (func_group
== SD_FUNC_GROUP_3
) {
1139 support_offset
= FUNCTION_GROUP3_SUPPORT_OFFSET
;
1140 query_switch_offset
= FUNCTION_GROUP3_QUERY_SWITCH_OFFSET
;
1141 check_busy_offset
= FUNCTION_GROUP3_CHECK_BUSY_OFFSET
;
1143 switch (func_to_switch
) {
1144 case DRIVING_TYPE_A
:
1145 support_mask
= DRIVING_TYPE_A_MASK
;
1146 query_switch
= TYPE_A_QUERY_SWITCH_OK
;
1147 switch_busy
= TYPE_A_SWITCH_BUSY
;
1150 case DRIVING_TYPE_C
:
1151 support_mask
= DRIVING_TYPE_C_MASK
;
1152 query_switch
= TYPE_C_QUERY_SWITCH_OK
;
1153 switch_busy
= TYPE_C_SWITCH_BUSY
;
1156 case DRIVING_TYPE_D
:
1157 support_mask
= DRIVING_TYPE_D_MASK
;
1158 query_switch
= TYPE_D_QUERY_SWITCH_OK
;
1159 switch_busy
= TYPE_D_SWITCH_BUSY
;
1166 } else if (func_group
== SD_FUNC_GROUP_4
) {
1167 support_offset
= FUNCTION_GROUP4_SUPPORT_OFFSET
;
1168 query_switch_offset
= FUNCTION_GROUP4_QUERY_SWITCH_OFFSET
;
1169 check_busy_offset
= FUNCTION_GROUP4_CHECK_BUSY_OFFSET
;
1171 switch (func_to_switch
) {
1172 case CURRENT_LIMIT_400
:
1173 support_mask
= CURRENT_LIMIT_400_MASK
;
1174 query_switch
= CURRENT_LIMIT_400_QUERY_SWITCH_OK
;
1175 switch_busy
= CURRENT_LIMIT_400_SWITCH_BUSY
;
1178 case CURRENT_LIMIT_600
:
1179 support_mask
= CURRENT_LIMIT_600_MASK
;
1180 query_switch
= CURRENT_LIMIT_600_QUERY_SWITCH_OK
;
1181 switch_busy
= CURRENT_LIMIT_600_SWITCH_BUSY
;
1184 case CURRENT_LIMIT_800
:
1185 support_mask
= CURRENT_LIMIT_800_MASK
;
1186 query_switch
= CURRENT_LIMIT_800_QUERY_SWITCH_OK
;
1187 switch_busy
= CURRENT_LIMIT_800_SWITCH_BUSY
;
1199 if (func_group
== SD_FUNC_GROUP_1
) {
1200 if (!(buf
[support_offset
] & support_mask
) ||
1201 ((buf
[query_switch_offset
] & 0x0F) != query_switch
)) {
1207 /* Check 'Busy Status' */
1208 if ((buf
[DATA_STRUCTURE_VER_OFFSET
] == 0x01) &&
1209 ((buf
[check_busy_offset
] & switch_busy
) == switch_busy
)) {
1214 return STATUS_SUCCESS
;
1217 static int sd_check_switch_mode(struct rtsx_chip
*chip
, u8 mode
,
1218 u8 func_group
, u8 func_to_switch
, u8 bus_width
)
1220 struct sd_info
*sd_card
= &(chip
->sd_card
);
1224 dev_dbg(rtsx_dev(chip
), "sd_check_switch_mode (mode = %d, func_group = %d, func_to_switch = %d)\n",
1225 mode
, func_group
, func_to_switch
);
1227 cmd
[0] = 0x40 | SWITCH
;
1230 if (func_group
== SD_FUNC_GROUP_1
) {
1233 cmd
[4] = 0xF0 + func_to_switch
;
1234 } else if (func_group
== SD_FUNC_GROUP_3
) {
1236 cmd
[3] = 0xF0 + func_to_switch
;
1238 } else if (func_group
== SD_FUNC_GROUP_4
) {
1240 cmd
[3] = 0x0F + (func_to_switch
<< 4);
1243 cmd
[1] = SD_CHECK_MODE
;
1249 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
, 5, 64, 1, bus_width
,
1251 if (retval
!= STATUS_SUCCESS
) {
1252 rtsx_clear_sd_error(chip
);
1257 dev_dbg(rtsx_dev(chip
), "%*ph\n", 64, buf
);
1259 if (func_group
== NO_ARGUMENT
) {
1260 sd_card
->func_group1_mask
= buf
[0x0D];
1261 sd_card
->func_group2_mask
= buf
[0x0B];
1262 sd_card
->func_group3_mask
= buf
[0x09];
1263 sd_card
->func_group4_mask
= buf
[0x07];
1265 dev_dbg(rtsx_dev(chip
), "func_group1_mask = 0x%02x\n",
1267 dev_dbg(rtsx_dev(chip
), "func_group2_mask = 0x%02x\n",
1269 dev_dbg(rtsx_dev(chip
), "func_group3_mask = 0x%02x\n",
1271 dev_dbg(rtsx_dev(chip
), "func_group4_mask = 0x%02x\n",
1274 /* Maximum current consumption, check whether current is
1275 * acceptable; bit[511:496] = 0x0000 means some error happened.
1277 u16 cc
= ((u16
)buf
[0] << 8) | buf
[1];
1279 dev_dbg(rtsx_dev(chip
), "Maximum current consumption: %dmA\n",
1281 if ((cc
== 0) || (cc
> 800)) {
1286 retval
= sd_query_switch_result(chip
, func_group
,
1287 func_to_switch
, buf
, 64);
1288 if (retval
!= STATUS_SUCCESS
) {
1293 if ((cc
> 400) || (func_to_switch
> CURRENT_LIMIT_400
)) {
1294 retval
= rtsx_write_register(chip
, OCPPARA2
,
1296 chip
->sd_800mA_ocp_thd
);
1301 retval
= rtsx_write_register(chip
, CARD_PWR_CTL
,
1311 return STATUS_SUCCESS
;
1314 static u8
downgrade_switch_mode(u8 func_group
, u8 func_to_switch
)
1316 if (func_group
== SD_FUNC_GROUP_1
) {
1317 if (func_to_switch
> HS_SUPPORT
)
1320 } else if (func_group
== SD_FUNC_GROUP_4
) {
1321 if (func_to_switch
> CURRENT_LIMIT_200
)
1325 return func_to_switch
;
1328 static int sd_check_switch(struct rtsx_chip
*chip
,
1329 u8 func_group
, u8 func_to_switch
, u8 bus_width
)
1333 bool switch_good
= false;
1335 for (i
= 0; i
< 3; i
++) {
1336 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
1337 sd_set_err_code(chip
, SD_NO_CARD
);
1342 retval
= sd_check_switch_mode(chip
, SD_CHECK_MODE
, func_group
,
1343 func_to_switch
, bus_width
);
1344 if (retval
== STATUS_SUCCESS
) {
1347 retval
= sd_check_switch_mode(chip
, SD_SWITCH_MODE
,
1348 func_group
, func_to_switch
, bus_width
);
1349 if (retval
== STATUS_SUCCESS
) {
1354 retval
= rtsx_read_register(chip
, SD_STAT1
, &stat
);
1359 if (stat
& SD_CRC16_ERR
) {
1360 dev_dbg(rtsx_dev(chip
), "SD CRC16 error when switching mode\n");
1366 func_to_switch
= downgrade_switch_mode(func_group
,
1377 return STATUS_SUCCESS
;
1380 static int sd_switch_function(struct rtsx_chip
*chip
, u8 bus_width
)
1382 struct sd_info
*sd_card
= &(chip
->sd_card
);
1385 u8 func_to_switch
= 0;
1387 /* Get supported functions */
1388 retval
= sd_check_switch_mode(chip
, SD_CHECK_MODE
,
1389 NO_ARGUMENT
, NO_ARGUMENT
, bus_width
);
1390 if (retval
!= STATUS_SUCCESS
) {
1395 sd_card
->func_group1_mask
&= ~(sd_card
->sd_switch_fail
);
1397 /* Function Group 1: Access Mode */
1398 for (i
= 0; i
< 4; i
++) {
1399 switch ((u8
)(chip
->sd_speed_prior
>> (i
*8))) {
1400 case SDR104_SUPPORT
:
1401 if ((sd_card
->func_group1_mask
& SDR104_SUPPORT_MASK
)
1402 && chip
->sdr104_en
) {
1403 func_to_switch
= SDR104_SUPPORT
;
1408 if ((sd_card
->func_group1_mask
& DDR50_SUPPORT_MASK
)
1409 && chip
->ddr50_en
) {
1410 func_to_switch
= DDR50_SUPPORT
;
1415 if ((sd_card
->func_group1_mask
& SDR50_SUPPORT_MASK
)
1416 && chip
->sdr50_en
) {
1417 func_to_switch
= SDR50_SUPPORT
;
1422 if (sd_card
->func_group1_mask
& HS_SUPPORT_MASK
)
1423 func_to_switch
= HS_SUPPORT
;
1435 dev_dbg(rtsx_dev(chip
), "SD_FUNC_GROUP_1: func_to_switch = 0x%02x",
1438 #ifdef SUPPORT_SD_LOCK
1439 if ((sd_card
->sd_lock_status
& SD_SDR_RST
) &&
1440 (func_to_switch
== DDR50_SUPPORT
) &&
1441 (sd_card
->func_group1_mask
& SDR50_SUPPORT_MASK
)) {
1442 func_to_switch
= SDR50_SUPPORT
;
1443 dev_dbg(rtsx_dev(chip
), "Using SDR50 instead of DDR50 for SD Lock\n");
1447 if (func_to_switch
) {
1448 retval
= sd_check_switch(chip
, SD_FUNC_GROUP_1
, func_to_switch
,
1450 if (retval
!= STATUS_SUCCESS
) {
1451 if (func_to_switch
== SDR104_SUPPORT
) {
1452 sd_card
->sd_switch_fail
= SDR104_SUPPORT_MASK
;
1453 } else if (func_to_switch
== DDR50_SUPPORT
) {
1454 sd_card
->sd_switch_fail
= SDR104_SUPPORT_MASK
|
1456 } else if (func_to_switch
== SDR50_SUPPORT
) {
1457 sd_card
->sd_switch_fail
= SDR104_SUPPORT_MASK
|
1458 DDR50_SUPPORT_MASK
| SDR50_SUPPORT_MASK
;
1464 if (func_to_switch
== SDR104_SUPPORT
)
1465 SET_SD_SDR104(sd_card
);
1466 else if (func_to_switch
== DDR50_SUPPORT
)
1467 SET_SD_DDR50(sd_card
);
1468 else if (func_to_switch
== SDR50_SUPPORT
)
1469 SET_SD_SDR50(sd_card
);
1474 if (CHK_SD_DDR50(sd_card
)) {
1475 retval
= rtsx_write_register(chip
, SD_PUSH_POINT_CTL
, 0x06,
1481 retval
= sd_set_sample_push_timing(chip
);
1482 if (retval
!= STATUS_SUCCESS
) {
1488 if (!func_to_switch
|| (func_to_switch
== HS_SUPPORT
)) {
1489 /* Do not try to switch current limit if the card doesn't
1490 * support UHS mode or we don't want it to support UHS mode
1492 return STATUS_SUCCESS
;
1495 /* Function Group 4: Current Limit */
1496 func_to_switch
= 0xFF;
1498 for (i
= 0; i
< 4; i
++) {
1499 switch ((u8
)(chip
->sd_current_prior
>> (i
*8))) {
1500 case CURRENT_LIMIT_800
:
1501 if (sd_card
->func_group4_mask
& CURRENT_LIMIT_800_MASK
)
1502 func_to_switch
= CURRENT_LIMIT_800
;
1506 case CURRENT_LIMIT_600
:
1507 if (sd_card
->func_group4_mask
& CURRENT_LIMIT_600_MASK
)
1508 func_to_switch
= CURRENT_LIMIT_600
;
1512 case CURRENT_LIMIT_400
:
1513 if (sd_card
->func_group4_mask
& CURRENT_LIMIT_400_MASK
)
1514 func_to_switch
= CURRENT_LIMIT_400
;
1518 case CURRENT_LIMIT_200
:
1519 if (sd_card
->func_group4_mask
& CURRENT_LIMIT_200_MASK
)
1520 func_to_switch
= CURRENT_LIMIT_200
;
1528 if (func_to_switch
!= 0xFF)
1532 dev_dbg(rtsx_dev(chip
), "SD_FUNC_GROUP_4: func_to_switch = 0x%02x",
1535 if (func_to_switch
<= CURRENT_LIMIT_800
) {
1536 retval
= sd_check_switch(chip
, SD_FUNC_GROUP_4
, func_to_switch
,
1538 if (retval
!= STATUS_SUCCESS
) {
1539 if (sd_check_err_code(chip
, SD_NO_CARD
)) {
1544 dev_dbg(rtsx_dev(chip
), "Switch current limit finished! (%d)\n",
1548 if (CHK_SD_DDR50(sd_card
)) {
1549 retval
= rtsx_write_register(chip
, SD_PUSH_POINT_CTL
, 0x06, 0);
1556 return STATUS_SUCCESS
;
1559 static int sd_wait_data_idle(struct rtsx_chip
*chip
)
1561 int retval
= STATUS_TIMEDOUT
;
1565 for (i
= 0; i
< 100; i
++) {
1566 retval
= rtsx_read_register(chip
, SD_DATA_STATE
, &val
);
1571 if (val
& SD_DATA_IDLE
) {
1572 retval
= STATUS_SUCCESS
;
1577 dev_dbg(rtsx_dev(chip
), "SD_DATA_STATE: 0x%02x\n", val
);
1582 static int sd_sdr_tuning_rx_cmd(struct rtsx_chip
*chip
, u8 sample_point
)
1587 retval
= sd_change_phase(chip
, sample_point
, TUNE_RX
);
1588 if (retval
!= STATUS_SUCCESS
) {
1593 cmd
[0] = 0x40 | SEND_TUNING_PATTERN
;
1599 retval
= sd_read_data(chip
, SD_TM_AUTO_TUNING
,
1600 cmd
, 5, 0x40, 1, SD_BUS_WIDTH_4
, NULL
, 0, 100);
1601 if (retval
!= STATUS_SUCCESS
) {
1602 (void)sd_wait_data_idle(chip
);
1604 rtsx_clear_sd_error(chip
);
1609 return STATUS_SUCCESS
;
1612 static int sd_ddr_tuning_rx_cmd(struct rtsx_chip
*chip
, u8 sample_point
)
1614 struct sd_info
*sd_card
= &(chip
->sd_card
);
1618 retval
= sd_change_phase(chip
, sample_point
, TUNE_RX
);
1619 if (retval
!= STATUS_SUCCESS
) {
1624 dev_dbg(rtsx_dev(chip
), "sd ddr tuning rx\n");
1626 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
,
1627 SD_RSP_TYPE_R1
, NULL
, 0);
1628 if (retval
!= STATUS_SUCCESS
) {
1633 cmd
[0] = 0x40 | SD_STATUS
;
1639 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
,
1640 cmd
, 5, 64, 1, SD_BUS_WIDTH_4
, NULL
, 0, 100);
1641 if (retval
!= STATUS_SUCCESS
) {
1642 (void)sd_wait_data_idle(chip
);
1644 rtsx_clear_sd_error(chip
);
1649 return STATUS_SUCCESS
;
1652 static int mmc_ddr_tunning_rx_cmd(struct rtsx_chip
*chip
, u8 sample_point
)
1654 struct sd_info
*sd_card
= &(chip
->sd_card
);
1656 u8 cmd
[5], bus_width
;
1658 if (CHK_MMC_8BIT(sd_card
))
1659 bus_width
= SD_BUS_WIDTH_8
;
1660 else if (CHK_MMC_4BIT(sd_card
))
1661 bus_width
= SD_BUS_WIDTH_4
;
1663 bus_width
= SD_BUS_WIDTH_1
;
1665 retval
= sd_change_phase(chip
, sample_point
, TUNE_RX
);
1666 if (retval
!= STATUS_SUCCESS
) {
1671 dev_dbg(rtsx_dev(chip
), "mmc ddr tuning rx\n");
1673 cmd
[0] = 0x40 | SEND_EXT_CSD
;
1679 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
,
1680 cmd
, 5, 0x200, 1, bus_width
, NULL
, 0, 100);
1681 if (retval
!= STATUS_SUCCESS
) {
1682 (void)sd_wait_data_idle(chip
);
1684 rtsx_clear_sd_error(chip
);
1689 return STATUS_SUCCESS
;
1692 static int sd_sdr_tuning_tx_cmd(struct rtsx_chip
*chip
, u8 sample_point
)
1694 struct sd_info
*sd_card
= &(chip
->sd_card
);
1697 retval
= sd_change_phase(chip
, sample_point
, TUNE_TX
);
1698 if (retval
!= STATUS_SUCCESS
) {
1703 retval
= rtsx_write_register(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
,
1704 SD_RSP_80CLK_TIMEOUT_EN
);
1710 retval
= sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
1711 SD_RSP_TYPE_R1
, NULL
, 0);
1712 if (retval
!= STATUS_SUCCESS
) {
1713 if (sd_check_err_code(chip
, SD_RSP_TIMEOUT
)) {
1714 rtsx_write_register(chip
, SD_CFG3
,
1715 SD_RSP_80CLK_TIMEOUT_EN
, 0);
1721 retval
= rtsx_write_register(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
,
1728 return STATUS_SUCCESS
;
1731 static int sd_ddr_tuning_tx_cmd(struct rtsx_chip
*chip
, u8 sample_point
)
1733 struct sd_info
*sd_card
= &(chip
->sd_card
);
1735 u8 cmd
[5], bus_width
;
1737 retval
= sd_change_phase(chip
, sample_point
, TUNE_TX
);
1738 if (retval
!= STATUS_SUCCESS
) {
1743 if (CHK_SD(sd_card
)) {
1744 bus_width
= SD_BUS_WIDTH_4
;
1746 if (CHK_MMC_8BIT(sd_card
))
1747 bus_width
= SD_BUS_WIDTH_8
;
1748 else if (CHK_MMC_4BIT(sd_card
))
1749 bus_width
= SD_BUS_WIDTH_4
;
1751 bus_width
= SD_BUS_WIDTH_1
;
1754 retval
= sd_wait_state_data_ready(chip
, 0x08, 1, 1000);
1755 if (retval
!= STATUS_SUCCESS
) {
1760 retval
= rtsx_write_register(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
,
1761 SD_RSP_80CLK_TIMEOUT_EN
);
1767 cmd
[0] = 0x40 | PROGRAM_CSD
;
1773 retval
= sd_write_data(chip
, SD_TM_AUTO_WRITE_2
,
1774 cmd
, 5, 16, 1, bus_width
, sd_card
->raw_csd
, 16, 100);
1775 if (retval
!= STATUS_SUCCESS
) {
1776 rtsx_clear_sd_error(chip
);
1777 rtsx_write_register(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
, 0);
1782 retval
= rtsx_write_register(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
,
1789 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
, SD_RSP_TYPE_R1
,
1792 return STATUS_SUCCESS
;
1795 static u8
sd_search_final_phase(struct rtsx_chip
*chip
, u32 phase_map
,
1798 struct sd_info
*sd_card
= &(chip
->sd_card
);
1799 struct timing_phase_path path
[MAX_PHASE
+ 1];
1800 int i
, j
, cont_path_cnt
;
1802 int max_len
, final_path_idx
;
1803 u8 final_phase
= 0xFF;
1805 if (phase_map
== 0xFFFFFFFF) {
1806 if (tune_dir
== TUNE_RX
)
1807 final_phase
= (u8
)chip
->sd_default_rx_phase
;
1809 final_phase
= (u8
)chip
->sd_default_tx_phase
;
1817 for (i
= 0; i
< MAX_PHASE
+ 1; i
++) {
1818 if (phase_map
& (1 << i
)) {
1821 j
= cont_path_cnt
++;
1829 if (cont_path_cnt
) {
1830 int idx
= cont_path_cnt
- 1;
1832 path
[idx
].len
= path
[idx
].end
-
1833 path
[idx
].start
+ 1;
1834 path
[idx
].mid
= path
[idx
].start
+
1840 if (cont_path_cnt
== 0) {
1841 dev_dbg(rtsx_dev(chip
), "No continuous phase path\n");
1844 int idx
= cont_path_cnt
- 1;
1846 path
[idx
].len
= path
[idx
].end
- path
[idx
].start
+ 1;
1847 path
[idx
].mid
= path
[idx
].start
+ path
[idx
].len
/ 2;
1850 if ((path
[0].start
== 0) &&
1851 (path
[cont_path_cnt
- 1].end
== MAX_PHASE
)) {
1852 path
[0].start
= path
[cont_path_cnt
- 1].start
- MAX_PHASE
- 1;
1853 path
[0].len
+= path
[cont_path_cnt
- 1].len
;
1854 path
[0].mid
= path
[0].start
+ path
[0].len
/ 2;
1855 if (path
[0].mid
< 0)
1856 path
[0].mid
+= MAX_PHASE
+ 1;
1864 for (i
= 0; i
< cont_path_cnt
; i
++) {
1865 if (path
[i
].len
> max_len
) {
1866 max_len
= path
[i
].len
;
1867 final_phase
= (u8
)path
[i
].mid
;
1871 dev_dbg(rtsx_dev(chip
), "path[%d].start = %d\n",
1873 dev_dbg(rtsx_dev(chip
), "path[%d].end = %d\n", i
, path
[i
].end
);
1874 dev_dbg(rtsx_dev(chip
), "path[%d].len = %d\n", i
, path
[i
].len
);
1875 dev_dbg(rtsx_dev(chip
), "path[%d].mid = %d\n", i
, path
[i
].mid
);
1876 dev_dbg(rtsx_dev(chip
), "\n");
1879 if (tune_dir
== TUNE_TX
) {
1880 if (CHK_SD_SDR104(sd_card
)) {
1882 int temp_mid
= (max_len
- 16) / 2;
1883 int temp_final_phase
=
1884 path
[final_path_idx
].end
-
1885 (max_len
- (6 + temp_mid
));
1887 if (temp_final_phase
< 0)
1888 final_phase
= (u8
)(temp_final_phase
+
1891 final_phase
= (u8
)temp_final_phase
;
1893 } else if (CHK_SD_SDR50(sd_card
)) {
1895 int temp_mid
= (max_len
- 13) / 2;
1896 int temp_final_phase
=
1897 path
[final_path_idx
].end
-
1898 (max_len
- (3 + temp_mid
));
1900 if (temp_final_phase
< 0)
1901 final_phase
= (u8
)(temp_final_phase
+
1904 final_phase
= (u8
)temp_final_phase
;
1910 dev_dbg(rtsx_dev(chip
), "Final chosen phase: %d\n", final_phase
);
1914 static int sd_tuning_rx(struct rtsx_chip
*chip
)
1916 struct sd_info
*sd_card
= &(chip
->sd_card
);
1919 u32 raw_phase_map
[3], phase_map
;
1921 int (*tuning_cmd
)(struct rtsx_chip
*chip
, u8 sample_point
);
1923 if (CHK_SD(sd_card
)) {
1924 if (CHK_SD_DDR50(sd_card
))
1925 tuning_cmd
= sd_ddr_tuning_rx_cmd
;
1927 tuning_cmd
= sd_sdr_tuning_rx_cmd
;
1930 if (CHK_MMC_DDR52(sd_card
)) {
1931 tuning_cmd
= mmc_ddr_tunning_rx_cmd
;
1938 for (i
= 0; i
< 3; i
++) {
1939 raw_phase_map
[i
] = 0;
1940 for (j
= MAX_PHASE
; j
>= 0; j
--) {
1941 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
1942 sd_set_err_code(chip
, SD_NO_CARD
);
1947 retval
= tuning_cmd(chip
, (u8
)j
);
1948 if (retval
== STATUS_SUCCESS
)
1949 raw_phase_map
[i
] |= 1 << j
;
1953 phase_map
= raw_phase_map
[0] & raw_phase_map
[1] & raw_phase_map
[2];
1954 for (i
= 0; i
< 3; i
++)
1955 dev_dbg(rtsx_dev(chip
), "RX raw_phase_map[%d] = 0x%08x\n",
1956 i
, raw_phase_map
[i
]);
1958 dev_dbg(rtsx_dev(chip
), "RX phase_map = 0x%08x\n", phase_map
);
1960 final_phase
= sd_search_final_phase(chip
, phase_map
, TUNE_RX
);
1961 if (final_phase
== 0xFF) {
1966 retval
= sd_change_phase(chip
, final_phase
, TUNE_RX
);
1967 if (retval
!= STATUS_SUCCESS
) {
1972 return STATUS_SUCCESS
;
1975 static int sd_ddr_pre_tuning_tx(struct rtsx_chip
*chip
)
1977 struct sd_info
*sd_card
= &(chip
->sd_card
);
1983 retval
= rtsx_write_register(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
,
1984 SD_RSP_80CLK_TIMEOUT_EN
);
1991 for (i
= MAX_PHASE
; i
>= 0; i
--) {
1992 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
1993 sd_set_err_code(chip
, SD_NO_CARD
);
1994 rtsx_write_register(chip
, SD_CFG3
,
1995 SD_RSP_80CLK_TIMEOUT_EN
, 0);
2000 retval
= sd_change_phase(chip
, (u8
)i
, TUNE_TX
);
2001 if (retval
!= STATUS_SUCCESS
)
2004 retval
= sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
2005 sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
,
2007 if ((retval
== STATUS_SUCCESS
) ||
2008 !sd_check_err_code(chip
, SD_RSP_TIMEOUT
))
2009 phase_map
|= 1 << i
;
2012 retval
= rtsx_write_register(chip
, SD_CFG3
, SD_RSP_80CLK_TIMEOUT_EN
,
2019 dev_dbg(rtsx_dev(chip
), "DDR TX pre tune phase_map = 0x%08x\n",
2022 final_phase
= sd_search_final_phase(chip
, phase_map
, TUNE_TX
);
2023 if (final_phase
== 0xFF) {
2028 retval
= sd_change_phase(chip
, final_phase
, TUNE_TX
);
2029 if (retval
!= STATUS_SUCCESS
) {
2034 dev_dbg(rtsx_dev(chip
), "DDR TX pre tune phase: %d\n",
2037 return STATUS_SUCCESS
;
2040 static int sd_tuning_tx(struct rtsx_chip
*chip
)
2042 struct sd_info
*sd_card
= &(chip
->sd_card
);
2045 u32 raw_phase_map
[3], phase_map
;
2047 int (*tuning_cmd
)(struct rtsx_chip
*chip
, u8 sample_point
);
2049 if (CHK_SD(sd_card
)) {
2050 if (CHK_SD_DDR50(sd_card
))
2051 tuning_cmd
= sd_ddr_tuning_tx_cmd
;
2053 tuning_cmd
= sd_sdr_tuning_tx_cmd
;
2056 if (CHK_MMC_DDR52(sd_card
)) {
2057 tuning_cmd
= sd_ddr_tuning_tx_cmd
;
2064 for (i
= 0; i
< 3; i
++) {
2065 raw_phase_map
[i
] = 0;
2066 for (j
= MAX_PHASE
; j
>= 0; j
--) {
2067 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
2068 sd_set_err_code(chip
, SD_NO_CARD
);
2069 rtsx_write_register(chip
, SD_CFG3
,
2070 SD_RSP_80CLK_TIMEOUT_EN
, 0);
2075 retval
= tuning_cmd(chip
, (u8
)j
);
2076 if (retval
== STATUS_SUCCESS
)
2077 raw_phase_map
[i
] |= 1 << j
;
2081 phase_map
= raw_phase_map
[0] & raw_phase_map
[1] & raw_phase_map
[2];
2082 for (i
= 0; i
< 3; i
++)
2083 dev_dbg(rtsx_dev(chip
), "TX raw_phase_map[%d] = 0x%08x\n",
2084 i
, raw_phase_map
[i
]);
2086 dev_dbg(rtsx_dev(chip
), "TX phase_map = 0x%08x\n", phase_map
);
2088 final_phase
= sd_search_final_phase(chip
, phase_map
, TUNE_TX
);
2089 if (final_phase
== 0xFF) {
2094 retval
= sd_change_phase(chip
, final_phase
, TUNE_TX
);
2095 if (retval
!= STATUS_SUCCESS
) {
2100 return STATUS_SUCCESS
;
2103 static int sd_sdr_tuning(struct rtsx_chip
*chip
)
2107 retval
= sd_tuning_tx(chip
);
2108 if (retval
!= STATUS_SUCCESS
) {
2113 retval
= sd_tuning_rx(chip
);
2114 if (retval
!= STATUS_SUCCESS
) {
2119 return STATUS_SUCCESS
;
2122 static int sd_ddr_tuning(struct rtsx_chip
*chip
)
2126 if (!(chip
->sd_ctl
& SD_DDR_TX_PHASE_SET_BY_USER
)) {
2127 retval
= sd_ddr_pre_tuning_tx(chip
);
2128 if (retval
!= STATUS_SUCCESS
) {
2133 retval
= sd_change_phase(chip
, (u8
)chip
->sd_ddr_tx_phase
,
2135 if (retval
!= STATUS_SUCCESS
) {
2141 retval
= sd_tuning_rx(chip
);
2142 if (retval
!= STATUS_SUCCESS
) {
2147 if (!(chip
->sd_ctl
& SD_DDR_TX_PHASE_SET_BY_USER
)) {
2148 retval
= sd_tuning_tx(chip
);
2149 if (retval
!= STATUS_SUCCESS
) {
2155 return STATUS_SUCCESS
;
2158 static int mmc_ddr_tuning(struct rtsx_chip
*chip
)
2162 if (!(chip
->sd_ctl
& MMC_DDR_TX_PHASE_SET_BY_USER
)) {
2163 retval
= sd_ddr_pre_tuning_tx(chip
);
2164 if (retval
!= STATUS_SUCCESS
) {
2169 retval
= sd_change_phase(chip
, (u8
)chip
->mmc_ddr_tx_phase
,
2171 if (retval
!= STATUS_SUCCESS
) {
2177 retval
= sd_tuning_rx(chip
);
2178 if (retval
!= STATUS_SUCCESS
) {
2183 if (!(chip
->sd_ctl
& MMC_DDR_TX_PHASE_SET_BY_USER
)) {
2184 retval
= sd_tuning_tx(chip
);
2185 if (retval
!= STATUS_SUCCESS
) {
2191 return STATUS_SUCCESS
;
2194 int sd_switch_clock(struct rtsx_chip
*chip
)
2196 struct sd_info
*sd_card
= &(chip
->sd_card
);
2200 retval
= select_card(chip
, SD_CARD
);
2201 if (retval
!= STATUS_SUCCESS
) {
2206 retval
= switch_clock(chip
, sd_card
->sd_clock
);
2207 if (retval
!= STATUS_SUCCESS
) {
2213 if (CHK_SD(sd_card
)) {
2214 if (CHK_SD_DDR50(sd_card
))
2215 retval
= sd_ddr_tuning(chip
);
2217 retval
= sd_sdr_tuning(chip
);
2219 if (CHK_MMC_DDR52(sd_card
))
2220 retval
= mmc_ddr_tuning(chip
);
2223 if (retval
!= STATUS_SUCCESS
) {
2229 return STATUS_SUCCESS
;
2232 static int sd_prepare_reset(struct rtsx_chip
*chip
)
2234 struct sd_info
*sd_card
= &(chip
->sd_card
);
2237 if (chip
->asic_code
)
2238 sd_card
->sd_clock
= 29;
2240 sd_card
->sd_clock
= CLK_30
;
2242 sd_card
->sd_type
= 0;
2243 sd_card
->seq_mode
= 0;
2244 sd_card
->sd_data_buf_ready
= 0;
2245 sd_card
->capacity
= 0;
2247 #ifdef SUPPORT_SD_LOCK
2248 sd_card
->sd_lock_status
= 0;
2249 sd_card
->sd_erase_status
= 0;
2252 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = 0;
2255 retval
= sd_set_init_para(chip
);
2256 if (retval
!= STATUS_SUCCESS
) {
2261 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, 0xFF, 0x40);
2267 retval
= rtsx_write_register(chip
, CARD_STOP
, SD_STOP
| SD_CLR_ERR
,
2268 SD_STOP
| SD_CLR_ERR
);
2274 retval
= select_card(chip
, SD_CARD
);
2275 if (retval
!= STATUS_SUCCESS
) {
2280 return STATUS_SUCCESS
;
2283 static int sd_pull_ctl_disable(struct rtsx_chip
*chip
)
2287 if (CHECK_PID(chip
, 0x5208)) {
2288 retval
= rtsx_write_register(chip
, CARD_PULL_CTL1
, 0xFF,
2289 XD_D3_PD
| SD_D7_PD
| SD_CLK_PD
| SD_D5_PD
);
2294 retval
= rtsx_write_register(chip
, CARD_PULL_CTL2
, 0xFF,
2295 SD_D6_PD
| SD_D0_PD
| SD_D1_PD
| XD_D5_PD
);
2300 retval
= rtsx_write_register(chip
, CARD_PULL_CTL3
, 0xFF,
2301 SD_D4_PD
| XD_CE_PD
| XD_CLE_PD
| XD_CD_PU
);
2306 retval
= rtsx_write_register(chip
, CARD_PULL_CTL4
, 0xFF,
2307 XD_RDY_PD
| SD_D3_PD
| SD_D2_PD
| XD_ALE_PD
);
2312 retval
= rtsx_write_register(chip
, CARD_PULL_CTL5
, 0xFF,
2313 MS_INS_PU
| SD_WP_PD
| SD_CD_PU
| SD_CMD_PD
);
2318 retval
= rtsx_write_register(chip
, CARD_PULL_CTL6
, 0xFF,
2319 MS_D5_PD
| MS_D4_PD
);
2324 } else if (CHECK_PID(chip
, 0x5288)) {
2325 if (CHECK_BARO_PKG(chip
, QFN
)) {
2326 retval
= rtsx_write_register(chip
, CARD_PULL_CTL1
,
2332 retval
= rtsx_write_register(chip
, CARD_PULL_CTL2
,
2338 retval
= rtsx_write_register(chip
, CARD_PULL_CTL3
,
2344 retval
= rtsx_write_register(chip
, CARD_PULL_CTL4
,
2353 return STATUS_SUCCESS
;
2356 int sd_pull_ctl_enable(struct rtsx_chip
*chip
)
2360 rtsx_init_cmd(chip
);
2362 if (CHECK_PID(chip
, 0x5208)) {
2363 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL1
, 0xFF,
2364 XD_D3_PD
| SD_DAT7_PU
| SD_CLK_NP
| SD_D5_PU
);
2365 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL2
, 0xFF,
2366 SD_D6_PU
| SD_D0_PU
| SD_D1_PU
| XD_D5_PD
);
2367 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL3
, 0xFF,
2368 SD_D4_PU
| XD_CE_PD
| XD_CLE_PD
| XD_CD_PU
);
2369 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL4
, 0xFF,
2370 XD_RDY_PD
| SD_D3_PU
| SD_D2_PU
| XD_ALE_PD
);
2371 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL5
, 0xFF,
2372 MS_INS_PU
| SD_WP_PU
| SD_CD_PU
| SD_CMD_PU
);
2373 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL6
, 0xFF,
2374 MS_D5_PD
| MS_D4_PD
);
2375 } else if (CHECK_PID(chip
, 0x5288)) {
2376 if (CHECK_BARO_PKG(chip
, QFN
)) {
2377 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL1
, 0xFF,
2379 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL2
, 0xFF,
2381 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL3
, 0xFF,
2383 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_PULL_CTL4
, 0xFF,
2388 retval
= rtsx_send_cmd(chip
, SD_CARD
, 100);
2394 return STATUS_SUCCESS
;
2397 static int sd_init_power(struct rtsx_chip
*chip
)
2401 retval
= sd_power_off_card3v3(chip
);
2402 if (retval
!= STATUS_SUCCESS
) {
2407 if (!chip
->ft2_fast_mode
)
2410 retval
= enable_card_clock(chip
, SD_CARD
);
2411 if (retval
!= STATUS_SUCCESS
) {
2416 if (chip
->asic_code
) {
2417 retval
= sd_pull_ctl_enable(chip
);
2418 if (retval
!= STATUS_SUCCESS
) {
2423 retval
= rtsx_write_register(chip
, FPGA_PULL_CTL
,
2424 FPGA_SD_PULL_CTL_BIT
| 0x20, 0);
2431 if (!chip
->ft2_fast_mode
) {
2432 retval
= card_power_on(chip
, SD_CARD
);
2433 if (retval
!= STATUS_SUCCESS
) {
2441 if (chip
->ocp_stat
& (SD_OC_NOW
| SD_OC_EVER
)) {
2442 dev_dbg(rtsx_dev(chip
), "Over current, OCPSTAT is 0x%x\n",
2450 retval
= rtsx_write_register(chip
, CARD_OE
, SD_OUTPUT_EN
,
2457 return STATUS_SUCCESS
;
2460 static int sd_dummy_clock(struct rtsx_chip
*chip
)
2464 retval
= rtsx_write_register(chip
, REG_SD_CFG3
, 0x01, 0x01);
2470 retval
= rtsx_write_register(chip
, REG_SD_CFG3
, 0x01, 0);
2476 return STATUS_SUCCESS
;
2479 static int sd_read_lba0(struct rtsx_chip
*chip
)
2481 struct sd_info
*sd_card
= &(chip
->sd_card
);
2483 u8 cmd
[5], bus_width
;
2485 cmd
[0] = 0x40 | READ_SINGLE_BLOCK
;
2491 if (CHK_SD(sd_card
)) {
2492 bus_width
= SD_BUS_WIDTH_4
;
2494 if (CHK_MMC_8BIT(sd_card
))
2495 bus_width
= SD_BUS_WIDTH_8
;
2496 else if (CHK_MMC_4BIT(sd_card
))
2497 bus_width
= SD_BUS_WIDTH_4
;
2499 bus_width
= SD_BUS_WIDTH_1
;
2502 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
,
2503 5, 512, 1, bus_width
, NULL
, 0, 100);
2504 if (retval
!= STATUS_SUCCESS
) {
2505 rtsx_clear_sd_error(chip
);
2510 return STATUS_SUCCESS
;
2513 static int sd_check_wp_state(struct rtsx_chip
*chip
)
2515 struct sd_info
*sd_card
= &(chip
->sd_card
);
2521 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
,
2522 sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
2523 if (retval
!= STATUS_SUCCESS
) {
2528 cmd
[0] = 0x40 | SD_STATUS
;
2534 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
, 5, 64, 1,
2535 SD_BUS_WIDTH_4
, buf
, 64, 250);
2536 if (retval
!= STATUS_SUCCESS
) {
2537 rtsx_clear_sd_error(chip
);
2539 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
2540 SD_RSP_TYPE_R1
, NULL
, 0);
2545 dev_dbg(rtsx_dev(chip
), "ACMD13:\n");
2546 dev_dbg(rtsx_dev(chip
), "%*ph\n", 64, buf
);
2548 sd_card_type
= ((u16
)buf
[2] << 8) | buf
[3];
2549 dev_dbg(rtsx_dev(chip
), "sd_card_type = 0x%04x\n", sd_card_type
);
2550 if ((sd_card_type
== 0x0001) || (sd_card_type
== 0x0002)) {
2551 /* ROM card or OTP */
2552 chip
->card_wp
|= SD_CARD
;
2555 /* Check SD Machanical Write-Protect Switch */
2556 val
= rtsx_readl(chip
, RTSX_BIPR
);
2557 if (val
& SD_WRITE_PROTECT
)
2558 chip
->card_wp
|= SD_CARD
;
2560 return STATUS_SUCCESS
;
2563 static int reset_sd(struct rtsx_chip
*chip
)
2565 struct sd_info
*sd_card
= &(chip
->sd_card
);
2566 bool hi_cap_flow
= false;
2567 int retval
, i
= 0, j
= 0, k
= 0;
2568 bool sd_dont_switch
= false;
2569 bool support_1v8
= false;
2570 bool try_sdio
= true;
2572 u8 switch_bus_width
;
2574 bool sd20_mode
= false;
2583 hi_cap_flow
= false;
2585 #ifdef SUPPORT_SD_LOCK
2586 if (sd_card
->sd_lock_status
& SD_UNLOCK_POW_ON
)
2587 goto SD_UNLOCK_ENTRY
;
2590 retval
= sd_prepare_reset(chip
);
2591 if (retval
!= STATUS_SUCCESS
)
2594 retval
= sd_dummy_clock(chip
);
2595 if (retval
!= STATUS_SUCCESS
)
2598 if (CHK_SDIO_EXIST(chip
) && !CHK_SDIO_IGNORED(chip
) && try_sdio
) {
2601 for (; rty_cnt
< chip
->sdio_retry_cnt
; rty_cnt
++) {
2602 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
2603 sd_set_err_code(chip
, SD_NO_CARD
);
2607 retval
= sd_send_cmd_get_rsp(chip
, IO_SEND_OP_COND
, 0,
2608 SD_RSP_TYPE_R4
, rsp
, 5);
2609 if (retval
== STATUS_SUCCESS
) {
2610 int func_num
= (rsp
[1] >> 4) & 0x07;
2613 dev_dbg(rtsx_dev(chip
), "SD_IO card (Function number: %d)!\n",
2622 sd_init_power(chip
);
2624 sd_dummy_clock(chip
);
2627 dev_dbg(rtsx_dev(chip
), "Normal card!\n");
2630 /* Start Initialization Process of SD Card */
2632 retval
= sd_send_cmd_get_rsp(chip
, GO_IDLE_STATE
, 0, SD_RSP_TYPE_R0
,
2634 if (retval
!= STATUS_SUCCESS
)
2639 retval
= sd_send_cmd_get_rsp(chip
, SEND_IF_COND
, 0x000001AA,
2640 SD_RSP_TYPE_R7
, rsp
, 5);
2641 if (retval
== STATUS_SUCCESS
) {
2642 if ((rsp
[4] == 0xAA) && ((rsp
[3] & 0x0f) == 0x01)) {
2644 voltage
= SUPPORT_VOLTAGE
| 0x40000000;
2649 voltage
= SUPPORT_VOLTAGE
;
2651 retval
= sd_send_cmd_get_rsp(chip
, GO_IDLE_STATE
, 0,
2652 SD_RSP_TYPE_R0
, NULL
, 0);
2653 if (retval
!= STATUS_SUCCESS
)
2660 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
, 0, SD_RSP_TYPE_R1
,
2662 if (retval
!= STATUS_SUCCESS
) {
2663 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
2664 sd_set_err_code(chip
, SD_NO_CARD
);
2675 retval
= sd_send_cmd_get_rsp(chip
, SD_APP_OP_COND
, voltage
,
2676 SD_RSP_TYPE_R3
, rsp
, 5);
2677 if (retval
!= STATUS_SUCCESS
) {
2687 } while (!(rsp
[1] & 0x80) && (i
< 255));
2694 SET_SD_HCXC(sd_card
);
2696 CLR_SD_HCXC(sd_card
);
2698 support_1v8
= false;
2700 CLR_SD_HCXC(sd_card
);
2701 support_1v8
= false;
2703 dev_dbg(rtsx_dev(chip
), "support_1v8 = %d\n", support_1v8
);
2706 retval
= sd_voltage_switch(chip
);
2707 if (retval
!= STATUS_SUCCESS
)
2711 retval
= sd_send_cmd_get_rsp(chip
, ALL_SEND_CID
, 0, SD_RSP_TYPE_R2
,
2713 if (retval
!= STATUS_SUCCESS
)
2716 for (i
= 0; i
< 3; i
++) {
2717 retval
= sd_send_cmd_get_rsp(chip
, SEND_RELATIVE_ADDR
, 0,
2718 SD_RSP_TYPE_R6
, rsp
, 5);
2719 if (retval
!= STATUS_SUCCESS
)
2722 sd_card
->sd_addr
= (u32
)rsp
[1] << 24;
2723 sd_card
->sd_addr
+= (u32
)rsp
[2] << 16;
2725 if (sd_card
->sd_addr
)
2729 retval
= sd_check_csd(chip
, 1);
2730 if (retval
!= STATUS_SUCCESS
)
2733 retval
= sd_select_card(chip
, 1);
2734 if (retval
!= STATUS_SUCCESS
)
2737 #ifdef SUPPORT_SD_LOCK
2739 retval
= sd_update_lock_status(chip
);
2740 if (retval
!= STATUS_SUCCESS
)
2743 if (sd_card
->sd_lock_status
& SD_LOCKED
) {
2744 sd_card
->sd_lock_status
|= (SD_LOCK_1BIT_MODE
| SD_PWD_EXIST
);
2745 return STATUS_SUCCESS
;
2746 } else if (!(sd_card
->sd_lock_status
& SD_UNLOCK_POW_ON
)) {
2747 sd_card
->sd_lock_status
&= ~SD_PWD_EXIST
;
2751 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
,
2752 SD_RSP_TYPE_R1
, NULL
, 0);
2753 if (retval
!= STATUS_SUCCESS
)
2756 retval
= sd_send_cmd_get_rsp(chip
, SET_CLR_CARD_DETECT
, 0,
2757 SD_RSP_TYPE_R1
, NULL
, 0);
2758 if (retval
!= STATUS_SUCCESS
)
2762 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
,
2763 SD_RSP_TYPE_R1
, NULL
, 0);
2764 if (retval
!= STATUS_SUCCESS
)
2767 retval
= sd_send_cmd_get_rsp(chip
, SET_BUS_WIDTH
, 2,
2768 SD_RSP_TYPE_R1
, NULL
, 0);
2769 if (retval
!= STATUS_SUCCESS
)
2772 switch_bus_width
= SD_BUS_WIDTH_4
;
2774 switch_bus_width
= SD_BUS_WIDTH_1
;
2777 retval
= sd_send_cmd_get_rsp(chip
, SET_BLOCKLEN
, 0x200, SD_RSP_TYPE_R1
,
2779 if (retval
!= STATUS_SUCCESS
)
2782 retval
= sd_set_clock_divider(chip
, SD_CLK_DIVIDE_0
);
2783 if (retval
!= STATUS_SUCCESS
)
2786 if (!(sd_card
->raw_csd
[4] & 0x40))
2787 sd_dont_switch
= true;
2789 if (!sd_dont_switch
) {
2791 /* Set sd_switch_fail here, because we needn't
2792 * switch to UHS mode
2794 sd_card
->sd_switch_fail
= SDR104_SUPPORT_MASK
|
2795 DDR50_SUPPORT_MASK
| SDR50_SUPPORT_MASK
;
2798 /* Check the card whether follow SD1.1 spec or higher */
2799 retval
= sd_check_spec(chip
, switch_bus_width
);
2800 if (retval
== STATUS_SUCCESS
) {
2801 retval
= sd_switch_function(chip
, switch_bus_width
);
2802 if (retval
!= STATUS_SUCCESS
) {
2803 sd_init_power(chip
);
2804 sd_dont_switch
= true;
2811 sd_init_power(chip
);
2812 sd_dont_switch
= true;
2821 retval
= sd_send_cmd_get_rsp(chip
, APP_CMD
, sd_card
->sd_addr
,
2822 SD_RSP_TYPE_R1
, NULL
, 0);
2823 if (retval
!= STATUS_SUCCESS
)
2826 retval
= sd_send_cmd_get_rsp(chip
, SET_BUS_WIDTH
, 2,
2827 SD_RSP_TYPE_R1
, NULL
, 0);
2828 if (retval
!= STATUS_SUCCESS
)
2832 #ifdef SUPPORT_SD_LOCK
2833 sd_card
->sd_lock_status
&= ~SD_LOCK_1BIT_MODE
;
2836 if (!sd20_mode
&& CHK_SD30_SPEED(sd_card
)) {
2839 retval
= rtsx_write_register(chip
, SD30_DRIVE_SEL
, 0x07,
2840 chip
->sd30_drive_sel_1v8
);
2846 retval
= sd_set_init_para(chip
);
2847 if (retval
!= STATUS_SUCCESS
)
2850 if (CHK_SD_DDR50(sd_card
))
2851 retval
= sd_ddr_tuning(chip
);
2853 retval
= sd_sdr_tuning(chip
);
2855 if (retval
!= STATUS_SUCCESS
) {
2859 retval
= sd_init_power(chip
);
2860 if (retval
!= STATUS_SUCCESS
)
2869 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
2870 SD_RSP_TYPE_R1
, NULL
, 0);
2872 if (CHK_SD_DDR50(sd_card
)) {
2873 retval
= sd_wait_state_data_ready(chip
, 0x08, 1, 1000);
2874 if (retval
!= STATUS_SUCCESS
)
2879 retval
= sd_read_lba0(chip
);
2880 if (retval
!= STATUS_SUCCESS
) {
2884 retval
= sd_init_power(chip
);
2885 if (retval
!= STATUS_SUCCESS
)
2896 retval
= sd_check_wp_state(chip
);
2897 if (retval
!= STATUS_SUCCESS
)
2900 chip
->card_bus_width
[chip
->card2lun
[SD_CARD
]] = 4;
2902 #ifdef SUPPORT_SD_LOCK
2903 if (sd_card
->sd_lock_status
& SD_UNLOCK_POW_ON
) {
2904 retval
= rtsx_write_register(chip
, REG_SD_BLOCK_CNT_H
, 0xFF,
2910 retval
= rtsx_write_register(chip
, REG_SD_BLOCK_CNT_L
, 0xFF,
2919 return STATUS_SUCCESS
;
2926 static int mmc_test_switch_bus(struct rtsx_chip
*chip
, u8 width
)
2928 struct sd_info
*sd_card
= &(chip
->sd_card
);
2930 u8 buf
[8] = {0}, bus_width
, *ptr
;
2934 retval
= sd_send_cmd_get_rsp(chip
, BUSTEST_W
, 0, SD_RSP_TYPE_R1
, NULL
,
2936 if (retval
!= STATUS_SUCCESS
) {
2941 if (width
== MMC_8BIT_BUS
) {
2946 bus_width
= SD_BUS_WIDTH_8
;
2951 bus_width
= SD_BUS_WIDTH_4
;
2954 retval
= rtsx_write_register(chip
, REG_SD_CFG3
, 0x02, 0x02);
2955 if (retval
!= STATUS_SUCCESS
) {
2960 retval
= sd_write_data(chip
, SD_TM_AUTO_WRITE_3
,
2961 NULL
, 0, byte_cnt
, 1, bus_width
, buf
, len
, 100);
2962 if (retval
!= STATUS_SUCCESS
) {
2963 rtsx_clear_sd_error(chip
);
2964 rtsx_write_register(chip
, REG_SD_CFG3
, 0x02, 0);
2969 retval
= rtsx_write_register(chip
, REG_SD_CFG3
, 0x02, 0);
2970 if (retval
!= STATUS_SUCCESS
) {
2975 dev_dbg(rtsx_dev(chip
), "SD/MMC CMD %d\n", BUSTEST_R
);
2977 rtsx_init_cmd(chip
);
2979 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD0
, 0xFF, 0x40 | BUSTEST_R
);
2981 if (width
== MMC_8BIT_BUS
)
2982 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
,
2985 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
,
2988 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
, 0xFF, 1);
2989 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
, 0xFF, 0);
2991 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF,
2992 SD_CALCULATE_CRC7
| SD_NO_CHECK_CRC16
| SD_NO_WAIT_BUSY_END
|
2993 SD_CHECK_CRC7
| SD_RSP_LEN_6
);
2994 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01,
2996 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
2997 SD_TM_NORMAL_READ
| SD_TRANSFER_START
);
2998 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
, SD_TRANSFER_END
,
3001 rtsx_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
, 0, 0);
3002 if (width
== MMC_8BIT_BUS
)
3003 rtsx_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 1, 0, 0);
3005 retval
= rtsx_send_cmd(chip
, SD_CARD
, 100);
3007 rtsx_clear_sd_error(chip
);
3012 ptr
= rtsx_get_cmd_data(chip
) + 1;
3014 if (width
== MMC_8BIT_BUS
) {
3015 dev_dbg(rtsx_dev(chip
), "BUSTEST_R [8bits]: 0x%02x 0x%02x\n",
3017 if ((ptr
[0] == 0xAA) && (ptr
[1] == 0x55)) {
3021 if (CHK_MMC_DDR52(sd_card
))
3026 retval
= sd_send_cmd_get_rsp(chip
, SWITCH
, arg
,
3027 SD_RSP_TYPE_R1b
, rsp
, 5);
3028 if ((retval
== STATUS_SUCCESS
) &&
3029 !(rsp
[4] & MMC_SWITCH_ERR
))
3030 return SWITCH_SUCCESS
;
3033 dev_dbg(rtsx_dev(chip
), "BUSTEST_R [4bits]: 0x%02x\n", ptr
[0]);
3034 if (ptr
[0] == 0xA5) {
3038 if (CHK_MMC_DDR52(sd_card
))
3043 retval
= sd_send_cmd_get_rsp(chip
, SWITCH
, arg
,
3044 SD_RSP_TYPE_R1b
, rsp
, 5);
3045 if ((retval
== STATUS_SUCCESS
) &&
3046 !(rsp
[4] & MMC_SWITCH_ERR
))
3047 return SWITCH_SUCCESS
;
3055 static int mmc_switch_timing_bus(struct rtsx_chip
*chip
, bool switch_ddr
)
3057 struct sd_info
*sd_card
= &(chip
->sd_card
);
3059 u8
*ptr
, card_type
, card_type_mask
= 0;
3061 CLR_MMC_HS(sd_card
);
3063 dev_dbg(rtsx_dev(chip
), "SD/MMC CMD %d\n", SEND_EXT_CSD
);
3065 rtsx_init_cmd(chip
);
3067 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD0
, 0xFF,
3068 0x40 | SEND_EXT_CSD
);
3069 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD1
, 0xFF, 0);
3070 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD2
, 0xFF, 0);
3071 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD3
, 0xFF, 0);
3072 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD4
, 0xFF, 0);
3074 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF, 0);
3075 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_H
, 0xFF, 2);
3076 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
, 0xFF, 1);
3077 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
, 0xFF, 0);
3079 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF,
3080 SD_CALCULATE_CRC7
| SD_CHECK_CRC16
| SD_NO_WAIT_BUSY_END
|
3081 SD_CHECK_CRC7
| SD_RSP_LEN_6
);
3082 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01,
3084 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
3085 SD_TM_NORMAL_READ
| SD_TRANSFER_START
);
3086 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
, SD_TRANSFER_END
,
3089 rtsx_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 196, 0xFF, 0);
3090 rtsx_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 212, 0xFF, 0);
3091 rtsx_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 213, 0xFF, 0);
3092 rtsx_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 214, 0xFF, 0);
3093 rtsx_add_cmd(chip
, READ_REG_CMD
, PPBUF_BASE2
+ 215, 0xFF, 0);
3095 retval
= rtsx_send_cmd(chip
, SD_CARD
, 1000);
3097 if (retval
== -ETIMEDOUT
) {
3098 rtsx_clear_sd_error(chip
);
3099 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
3100 SD_RSP_TYPE_R1
, NULL
, 0);
3106 ptr
= rtsx_get_cmd_data(chip
);
3107 if (ptr
[0] & SD_TRANSFER_ERR
) {
3108 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
3109 SD_RSP_TYPE_R1
, NULL
, 0);
3114 if (CHK_MMC_SECTOR_MODE(sd_card
)) {
3115 sd_card
->capacity
= ((u32
)ptr
[5] << 24) | ((u32
)ptr
[4] << 16) |
3116 ((u32
)ptr
[3] << 8) | ((u32
)ptr
[2]);
3119 card_type_mask
= 0x03;
3120 card_type
= ptr
[1] & card_type_mask
;
3124 if (card_type
& 0x04) {
3126 SET_MMC_DDR52(sd_card
);
3128 SET_MMC_52M(sd_card
);
3129 } else if (card_type
& 0x02) {
3130 SET_MMC_52M(sd_card
);
3132 SET_MMC_26M(sd_card
);
3135 retval
= sd_send_cmd_get_rsp(chip
, SWITCH
,
3136 0x03B90100, SD_RSP_TYPE_R1b
, rsp
, 5);
3137 if ((retval
!= STATUS_SUCCESS
) || (rsp
[4] & MMC_SWITCH_ERR
))
3138 CLR_MMC_HS(sd_card
);
3141 sd_choose_proper_clock(chip
);
3142 retval
= switch_clock(chip
, sd_card
->sd_clock
);
3143 if (retval
!= STATUS_SUCCESS
) {
3148 /* Test Bus Procedure */
3149 retval
= mmc_test_switch_bus(chip
, MMC_8BIT_BUS
);
3150 if (retval
== SWITCH_SUCCESS
) {
3151 SET_MMC_8BIT(sd_card
);
3152 chip
->card_bus_width
[chip
->card2lun
[SD_CARD
]] = 8;
3153 #ifdef SUPPORT_SD_LOCK
3154 sd_card
->sd_lock_status
&= ~SD_LOCK_1BIT_MODE
;
3156 } else if (retval
== SWITCH_FAIL
) {
3157 retval
= mmc_test_switch_bus(chip
, MMC_4BIT_BUS
);
3158 if (retval
== SWITCH_SUCCESS
) {
3159 SET_MMC_4BIT(sd_card
);
3160 chip
->card_bus_width
[chip
->card2lun
[SD_CARD
]] = 4;
3161 #ifdef SUPPORT_SD_LOCK
3162 sd_card
->sd_lock_status
&= ~SD_LOCK_1BIT_MODE
;
3164 } else if (retval
== SWITCH_FAIL
) {
3165 CLR_MMC_8BIT(sd_card
);
3166 CLR_MMC_4BIT(sd_card
);
3176 return STATUS_SUCCESS
;
3179 static int reset_mmc(struct rtsx_chip
*chip
)
3181 struct sd_info
*sd_card
= &(chip
->sd_card
);
3182 int retval
, i
= 0, j
= 0, k
= 0;
3183 bool switch_ddr
= true;
3188 #ifdef SUPPORT_SD_LOCK
3189 if (sd_card
->sd_lock_status
& SD_UNLOCK_POW_ON
)
3190 goto MMC_UNLOCK_ENTRY
;
3194 retval
= sd_prepare_reset(chip
);
3195 if (retval
!= STATUS_SUCCESS
) {
3203 retval
= sd_send_cmd_get_rsp(chip
, GO_IDLE_STATE
, 0, SD_RSP_TYPE_R0
,
3205 if (retval
!= STATUS_SUCCESS
) {
3211 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
3212 sd_set_err_code(chip
, SD_NO_CARD
);
3217 retval
= sd_send_cmd_get_rsp(chip
, SEND_OP_COND
,
3218 (SUPPORT_VOLTAGE
| 0x40000000),
3219 SD_RSP_TYPE_R3
, rsp
, 5);
3220 if (retval
!= STATUS_SUCCESS
) {
3221 if (sd_check_err_code(chip
, SD_BUSY
) ||
3222 sd_check_err_code(chip
, SD_TO_ERR
)) {
3225 sd_clr_err_code(chip
);
3234 sd_clr_err_code(chip
);
3245 } while (!(rsp
[1] & 0x80) && (i
< 255));
3252 if ((rsp
[1] & 0x60) == 0x40)
3253 SET_MMC_SECTOR_MODE(sd_card
);
3255 CLR_MMC_SECTOR_MODE(sd_card
);
3257 retval
= sd_send_cmd_get_rsp(chip
, ALL_SEND_CID
, 0, SD_RSP_TYPE_R2
,
3259 if (retval
!= STATUS_SUCCESS
) {
3264 sd_card
->sd_addr
= 0x00100000;
3265 retval
= sd_send_cmd_get_rsp(chip
, SET_RELATIVE_ADDR
, sd_card
->sd_addr
,
3266 SD_RSP_TYPE_R6
, rsp
, 5);
3267 if (retval
!= STATUS_SUCCESS
) {
3272 retval
= sd_check_csd(chip
, 1);
3273 if (retval
!= STATUS_SUCCESS
) {
3278 spec_ver
= (sd_card
->raw_csd
[0] & 0x3C) >> 2;
3280 retval
= sd_select_card(chip
, 1);
3281 if (retval
!= STATUS_SUCCESS
) {
3286 retval
= sd_send_cmd_get_rsp(chip
, SET_BLOCKLEN
, 0x200, SD_RSP_TYPE_R1
,
3288 if (retval
!= STATUS_SUCCESS
) {
3293 #ifdef SUPPORT_SD_LOCK
3295 retval
= sd_update_lock_status(chip
);
3296 if (retval
!= STATUS_SUCCESS
) {
3302 retval
= sd_set_clock_divider(chip
, SD_CLK_DIVIDE_0
);
3303 if (retval
!= STATUS_SUCCESS
) {
3308 chip
->card_bus_width
[chip
->card2lun
[SD_CARD
]] = 1;
3310 if (!sd_card
->mmc_dont_switch_bus
) {
3311 if (spec_ver
== 4) {
3313 retval
= mmc_switch_timing_bus(chip
, switch_ddr
);
3314 if (retval
!= STATUS_SUCCESS
) {
3315 retval
= sd_init_power(chip
);
3316 if (retval
!= STATUS_SUCCESS
) {
3320 sd_card
->mmc_dont_switch_bus
= 1;
3326 if (CHK_MMC_SECTOR_MODE(sd_card
) && (sd_card
->capacity
== 0)) {
3331 if (switch_ddr
&& CHK_MMC_DDR52(sd_card
)) {
3332 retval
= sd_set_init_para(chip
);
3333 if (retval
!= STATUS_SUCCESS
) {
3338 retval
= mmc_ddr_tuning(chip
);
3339 if (retval
!= STATUS_SUCCESS
) {
3340 retval
= sd_init_power(chip
);
3341 if (retval
!= STATUS_SUCCESS
) {
3351 retval
= sd_wait_state_data_ready(chip
, 0x08, 1, 1000);
3352 if (retval
== STATUS_SUCCESS
) {
3353 retval
= sd_read_lba0(chip
);
3354 if (retval
!= STATUS_SUCCESS
) {
3355 retval
= sd_init_power(chip
);
3356 if (retval
!= STATUS_SUCCESS
) {
3369 #ifdef SUPPORT_SD_LOCK
3370 if (sd_card
->sd_lock_status
& SD_UNLOCK_POW_ON
) {
3371 retval
= rtsx_write_register(chip
, REG_SD_BLOCK_CNT_H
, 0xFF,
3377 retval
= rtsx_write_register(chip
, REG_SD_BLOCK_CNT_L
, 0xFF,
3386 temp
= rtsx_readl(chip
, RTSX_BIPR
);
3387 if (temp
& SD_WRITE_PROTECT
)
3388 chip
->card_wp
|= SD_CARD
;
3390 return STATUS_SUCCESS
;
3393 int reset_sd_card(struct rtsx_chip
*chip
)
3395 struct sd_info
*sd_card
= &(chip
->sd_card
);
3398 sd_init_reg_addr(chip
);
3400 memset(sd_card
, 0, sizeof(struct sd_info
));
3401 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = 0;
3403 retval
= enable_card_clock(chip
, SD_CARD
);
3404 if (retval
!= STATUS_SUCCESS
) {
3409 if (chip
->ignore_sd
&& CHK_SDIO_EXIST(chip
) &&
3410 !CHK_SDIO_IGNORED(chip
)) {
3411 if (chip
->asic_code
) {
3412 retval
= sd_pull_ctl_enable(chip
);
3413 if (retval
!= STATUS_SUCCESS
) {
3418 retval
= rtsx_write_register(chip
, FPGA_PULL_CTL
,
3419 FPGA_SD_PULL_CTL_BIT
| 0x20, 0);
3420 if (retval
!= STATUS_SUCCESS
) {
3425 retval
= card_share_mode(chip
, SD_CARD
);
3426 if (retval
!= STATUS_SUCCESS
) {
3436 retval
= sd_init_power(chip
);
3437 if (retval
!= STATUS_SUCCESS
) {
3442 if (chip
->sd_ctl
& RESET_MMC_FIRST
) {
3443 retval
= reset_mmc(chip
);
3444 if (retval
!= STATUS_SUCCESS
) {
3445 if (sd_check_err_code(chip
, SD_NO_CARD
)) {
3450 retval
= reset_sd(chip
);
3451 if (retval
!= STATUS_SUCCESS
) {
3457 retval
= reset_sd(chip
);
3458 if (retval
!= STATUS_SUCCESS
) {
3459 if (sd_check_err_code(chip
, SD_NO_CARD
)) {
3468 retval
= reset_mmc(chip
);
3469 if (retval
!= STATUS_SUCCESS
) {
3476 retval
= sd_set_clock_divider(chip
, SD_CLK_DIVIDE_0
);
3477 if (retval
!= STATUS_SUCCESS
) {
3482 retval
= rtsx_write_register(chip
, REG_SD_BYTE_CNT_L
, 0xFF, 0);
3487 retval
= rtsx_write_register(chip
, REG_SD_BYTE_CNT_H
, 0xFF, 2);
3493 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = sd_card
->capacity
;
3495 retval
= sd_set_init_para(chip
);
3496 if (retval
!= STATUS_SUCCESS
) {
3501 dev_dbg(rtsx_dev(chip
), "sd_card->sd_type = 0x%x\n", sd_card
->sd_type
);
3503 return STATUS_SUCCESS
;
3506 static int reset_mmc_only(struct rtsx_chip
*chip
)
3508 struct sd_info
*sd_card
= &(chip
->sd_card
);
3511 sd_card
->sd_type
= 0;
3512 sd_card
->seq_mode
= 0;
3513 sd_card
->sd_data_buf_ready
= 0;
3514 sd_card
->capacity
= 0;
3515 sd_card
->sd_switch_fail
= 0;
3517 #ifdef SUPPORT_SD_LOCK
3518 sd_card
->sd_lock_status
= 0;
3519 sd_card
->sd_erase_status
= 0;
3522 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = sd_card
->capacity
= 0;
3524 retval
= enable_card_clock(chip
, SD_CARD
);
3525 if (retval
!= STATUS_SUCCESS
) {
3530 retval
= sd_init_power(chip
);
3531 if (retval
!= STATUS_SUCCESS
) {
3536 retval
= reset_mmc(chip
);
3537 if (retval
!= STATUS_SUCCESS
) {
3542 retval
= sd_set_clock_divider(chip
, SD_CLK_DIVIDE_0
);
3543 if (retval
!= STATUS_SUCCESS
) {
3548 retval
= rtsx_write_register(chip
, REG_SD_BYTE_CNT_L
, 0xFF, 0);
3553 retval
= rtsx_write_register(chip
, REG_SD_BYTE_CNT_H
, 0xFF, 2);
3559 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = sd_card
->capacity
;
3561 retval
= sd_set_init_para(chip
);
3562 if (retval
!= STATUS_SUCCESS
) {
3567 dev_dbg(rtsx_dev(chip
), "In reset_mmc_only, sd_card->sd_type = 0x%x\n",
3570 return STATUS_SUCCESS
;
3573 #define WAIT_DATA_READY_RTY_CNT 255
3575 static int wait_data_buf_ready(struct rtsx_chip
*chip
)
3577 struct sd_info
*sd_card
= &(chip
->sd_card
);
3580 for (i
= 0; i
< WAIT_DATA_READY_RTY_CNT
; i
++) {
3581 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
3582 sd_set_err_code(chip
, SD_NO_CARD
);
3587 sd_card
->sd_data_buf_ready
= 0;
3589 retval
= sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
3590 sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
3591 if (retval
!= STATUS_SUCCESS
) {
3596 if (sd_card
->sd_data_buf_ready
) {
3597 return sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
3598 sd_card
->sd_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
3602 sd_set_err_code(chip
, SD_TO_ERR
);
3608 void sd_stop_seq_mode(struct rtsx_chip
*chip
)
3610 struct sd_info
*sd_card
= &(chip
->sd_card
);
3613 if (sd_card
->seq_mode
) {
3614 retval
= sd_switch_clock(chip
);
3615 if (retval
!= STATUS_SUCCESS
)
3618 retval
= sd_send_cmd_get_rsp(chip
, STOP_TRANSMISSION
, 0,
3619 SD_RSP_TYPE_R1b
, NULL
, 0);
3620 if (retval
!= STATUS_SUCCESS
)
3621 sd_set_err_code(chip
, SD_STS_ERR
);
3623 retval
= sd_wait_state_data_ready(chip
, 0x08, 1, 1000);
3624 if (retval
!= STATUS_SUCCESS
)
3625 sd_set_err_code(chip
, SD_STS_ERR
);
3627 sd_card
->seq_mode
= 0;
3629 rtsx_write_register(chip
, RBCTL
, RB_FLUSH
, RB_FLUSH
);
3633 static inline int sd_auto_tune_clock(struct rtsx_chip
*chip
)
3635 struct sd_info
*sd_card
= &(chip
->sd_card
);
3638 if (chip
->asic_code
) {
3639 if (sd_card
->sd_clock
> 30)
3640 sd_card
->sd_clock
-= 20;
3642 switch (sd_card
->sd_clock
) {
3644 sd_card
->sd_clock
= CLK_150
;
3648 sd_card
->sd_clock
= CLK_120
;
3652 sd_card
->sd_clock
= CLK_100
;
3656 sd_card
->sd_clock
= CLK_80
;
3660 sd_card
->sd_clock
= CLK_60
;
3664 sd_card
->sd_clock
= CLK_50
;
3672 retval
= sd_switch_clock(chip
);
3673 if (retval
!= STATUS_SUCCESS
) {
3678 return STATUS_SUCCESS
;
3681 int sd_rw(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
, u32 start_sector
,
3684 struct sd_info
*sd_card
= &(chip
->sd_card
);
3689 if (srb
->sc_data_direction
== DMA_FROM_DEVICE
) {
3690 dev_dbg(rtsx_dev(chip
), "sd_rw: Read %d %s from 0x%x\n",
3691 sector_cnt
, (sector_cnt
> 1) ? "sectors" : "sector",
3694 dev_dbg(rtsx_dev(chip
), "sd_rw: Write %d %s to 0x%x\n",
3695 sector_cnt
, (sector_cnt
> 1) ? "sectors" : "sector",
3699 sd_card
->cleanup_counter
= 0;
3701 if (!(chip
->card_ready
& SD_CARD
)) {
3702 sd_card
->seq_mode
= 0;
3704 retval
= reset_sd_card(chip
);
3705 if (retval
== STATUS_SUCCESS
) {
3706 chip
->card_ready
|= SD_CARD
;
3707 chip
->card_fail
&= ~SD_CARD
;
3709 chip
->card_ready
&= ~SD_CARD
;
3710 chip
->card_fail
|= SD_CARD
;
3711 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = 0;
3712 chip
->rw_need_retry
= 1;
3718 if (!CHK_SD_HCXC(sd_card
) && !CHK_MMC_SECTOR_MODE(sd_card
))
3719 data_addr
= start_sector
<< 9;
3721 data_addr
= start_sector
;
3723 sd_clr_err_code(chip
);
3725 retval
= sd_switch_clock(chip
);
3726 if (retval
!= STATUS_SUCCESS
) {
3727 sd_set_err_code(chip
, SD_IO_ERR
);
3732 if (sd_card
->seq_mode
&&
3733 ((sd_card
->pre_dir
!= srb
->sc_data_direction
) ||
3734 ((sd_card
->pre_sec_addr
+ sd_card
->pre_sec_cnt
) !=
3736 if ((sd_card
->pre_sec_cnt
< 0x80)
3737 && (sd_card
->pre_dir
== DMA_FROM_DEVICE
)
3738 && !CHK_SD30_SPEED(sd_card
)
3739 && !CHK_SD_HS(sd_card
)
3740 && !CHK_MMC_HS(sd_card
)) {
3741 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
3742 SD_RSP_TYPE_R1
, NULL
, 0);
3745 retval
= sd_send_cmd_get_rsp(chip
, STOP_TRANSMISSION
,
3746 0, SD_RSP_TYPE_R1b
, NULL
, 0);
3747 if (retval
!= STATUS_SUCCESS
) {
3748 chip
->rw_need_retry
= 1;
3749 sd_set_err_code(chip
, SD_STS_ERR
);
3754 sd_card
->seq_mode
= 0;
3756 retval
= rtsx_write_register(chip
, RBCTL
, RB_FLUSH
, RB_FLUSH
);
3757 if (retval
!= STATUS_SUCCESS
) {
3758 sd_set_err_code(chip
, SD_IO_ERR
);
3763 if ((sd_card
->pre_sec_cnt
< 0x80)
3764 && !CHK_SD30_SPEED(sd_card
)
3765 && !CHK_SD_HS(sd_card
)
3766 && !CHK_MMC_HS(sd_card
)) {
3767 sd_send_cmd_get_rsp(chip
, SEND_STATUS
, sd_card
->sd_addr
,
3768 SD_RSP_TYPE_R1
, NULL
, 0);
3772 rtsx_init_cmd(chip
);
3774 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF, 0x00);
3775 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_H
, 0xFF, 0x02);
3776 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
, 0xFF,
3778 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
, 0xFF,
3779 (u8
)(sector_cnt
>> 8));
3781 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, RING_BUFFER
);
3783 if (CHK_MMC_8BIT(sd_card
))
3784 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG1
,
3785 0x03, SD_BUS_WIDTH_8
);
3786 else if (CHK_MMC_4BIT(sd_card
) || CHK_SD(sd_card
))
3787 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG1
,
3788 0x03, SD_BUS_WIDTH_4
);
3790 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG1
,
3791 0x03, SD_BUS_WIDTH_1
);
3793 if (sd_card
->seq_mode
) {
3794 cfg2
= SD_NO_CALCULATE_CRC7
| SD_CHECK_CRC16
|
3795 SD_NO_WAIT_BUSY_END
| SD_NO_CHECK_CRC7
|
3797 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF, cfg2
);
3799 trans_dma_enable(srb
->sc_data_direction
, chip
, sector_cnt
* 512,
3802 if (srb
->sc_data_direction
== DMA_FROM_DEVICE
) {
3803 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
3804 SD_TM_AUTO_READ_3
| SD_TRANSFER_START
);
3806 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
3807 SD_TM_AUTO_WRITE_3
| SD_TRANSFER_START
);
3810 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
,
3811 SD_TRANSFER_END
, SD_TRANSFER_END
);
3813 rtsx_send_cmd_no_wait(chip
);
3815 if (srb
->sc_data_direction
== DMA_FROM_DEVICE
) {
3816 dev_dbg(rtsx_dev(chip
), "SD/MMC CMD %d\n",
3817 READ_MULTIPLE_BLOCK
);
3818 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD0
, 0xFF,
3819 0x40 | READ_MULTIPLE_BLOCK
);
3820 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD1
, 0xFF,
3821 (u8
)(data_addr
>> 24));
3822 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD2
, 0xFF,
3823 (u8
)(data_addr
>> 16));
3824 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD3
, 0xFF,
3825 (u8
)(data_addr
>> 8));
3826 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD4
, 0xFF,
3829 cfg2
= SD_CALCULATE_CRC7
| SD_CHECK_CRC16
|
3830 SD_NO_WAIT_BUSY_END
| SD_CHECK_CRC7
|
3832 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF,
3835 trans_dma_enable(srb
->sc_data_direction
, chip
,
3836 sector_cnt
* 512, DMA_512
);
3838 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
3839 SD_TM_AUTO_READ_2
| SD_TRANSFER_START
);
3840 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
,
3841 SD_TRANSFER_END
, SD_TRANSFER_END
);
3843 rtsx_send_cmd_no_wait(chip
);
3845 retval
= rtsx_send_cmd(chip
, SD_CARD
, 50);
3847 rtsx_clear_sd_error(chip
);
3849 chip
->rw_need_retry
= 1;
3850 sd_set_err_code(chip
, SD_TO_ERR
);
3855 retval
= wait_data_buf_ready(chip
);
3856 if (retval
!= STATUS_SUCCESS
) {
3857 chip
->rw_need_retry
= 1;
3858 sd_set_err_code(chip
, SD_TO_ERR
);
3863 retval
= sd_send_cmd_get_rsp(chip
, WRITE_MULTIPLE_BLOCK
,
3864 data_addr
, SD_RSP_TYPE_R1
, NULL
, 0);
3865 if (retval
!= STATUS_SUCCESS
) {
3866 chip
->rw_need_retry
= 1;
3871 rtsx_init_cmd(chip
);
3873 cfg2
= SD_NO_CALCULATE_CRC7
| SD_CHECK_CRC16
|
3874 SD_NO_WAIT_BUSY_END
|
3875 SD_NO_CHECK_CRC7
| SD_RSP_LEN_0
;
3876 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF,
3879 trans_dma_enable(srb
->sc_data_direction
, chip
,
3880 sector_cnt
* 512, DMA_512
);
3882 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
3883 SD_TM_AUTO_WRITE_3
| SD_TRANSFER_START
);
3884 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
,
3885 SD_TRANSFER_END
, SD_TRANSFER_END
);
3887 rtsx_send_cmd_no_wait(chip
);
3890 sd_card
->seq_mode
= 1;
3893 retval
= rtsx_transfer_data(chip
, SD_CARD
, scsi_sglist(srb
),
3894 scsi_bufflen(srb
), scsi_sg_count(srb
),
3895 srb
->sc_data_direction
, chip
->sd_timeout
);
3900 sd_card
->seq_mode
= 0;
3902 if (retval
== -ETIMEDOUT
)
3903 err
= STATUS_TIMEDOUT
;
3907 rtsx_read_register(chip
, REG_SD_STAT1
, &stat
);
3908 rtsx_clear_sd_error(chip
);
3909 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
3910 chip
->rw_need_retry
= 0;
3911 dev_dbg(rtsx_dev(chip
), "No card exist, exit sd_rw\n");
3916 chip
->rw_need_retry
= 1;
3918 retval
= sd_send_cmd_get_rsp(chip
, STOP_TRANSMISSION
, 0,
3919 SD_RSP_TYPE_R1b
, NULL
, 0);
3920 if (retval
!= STATUS_SUCCESS
) {
3921 sd_set_err_code(chip
, SD_STS_ERR
);
3926 if (stat
& (SD_CRC7_ERR
| SD_CRC16_ERR
| SD_CRC_WRITE_ERR
)) {
3927 dev_dbg(rtsx_dev(chip
), "SD CRC error, tune clock!\n");
3928 sd_set_err_code(chip
, SD_CRC_ERR
);
3933 if (err
== STATUS_TIMEDOUT
) {
3934 sd_set_err_code(chip
, SD_TO_ERR
);
3943 sd_card
->pre_sec_addr
= start_sector
;
3944 sd_card
->pre_sec_cnt
= sector_cnt
;
3945 sd_card
->pre_dir
= srb
->sc_data_direction
;
3947 return STATUS_SUCCESS
;
3950 sd_card
->seq_mode
= 0;
3952 if (detect_card_cd(chip
, SD_CARD
) != STATUS_SUCCESS
) {
3953 chip
->rw_need_retry
= 0;
3954 dev_dbg(rtsx_dev(chip
), "No card exist, exit sd_rw\n");
3959 if (sd_check_err_code(chip
, SD_CRC_ERR
)) {
3960 if (CHK_MMC_4BIT(sd_card
) || CHK_MMC_8BIT(sd_card
)) {
3961 sd_card
->mmc_dont_switch_bus
= 1;
3962 reset_mmc_only(chip
);
3963 sd_card
->mmc_dont_switch_bus
= 0;
3965 sd_card
->need_retune
= 1;
3966 sd_auto_tune_clock(chip
);
3968 } else if (sd_check_err_code(chip
, SD_TO_ERR
| SD_STS_ERR
)) {
3969 retval
= reset_sd_card(chip
);
3970 if (retval
!= STATUS_SUCCESS
) {
3971 chip
->card_ready
&= ~SD_CARD
;
3972 chip
->card_fail
|= SD_CARD
;
3973 chip
->capacity
[chip
->card2lun
[SD_CARD
]] = 0;
3982 int soft_reset_sd_card(struct rtsx_chip
*chip
)
3984 return reset_sd(chip
);
3987 int ext_sd_send_cmd_get_rsp(struct rtsx_chip
*chip
, u8 cmd_idx
,
3988 u32 arg
, u8 rsp_type
, u8
*rsp
, int rsp_len
, bool special_check
)
3997 dev_dbg(rtsx_dev(chip
), "EXT SD/MMC CMD %d\n", cmd_idx
);
3999 if (rsp_type
== SD_RSP_TYPE_R1b
)
4004 rtsx_init_cmd(chip
);
4006 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD0
, 0xFF, 0x40 | cmd_idx
);
4007 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD1
, 0xFF, (u8
)(arg
>> 24));
4008 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD2
, 0xFF, (u8
)(arg
>> 16));
4009 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD3
, 0xFF, (u8
)(arg
>> 8));
4010 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD4
, 0xFF, (u8
)arg
);
4012 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF, rsp_type
);
4013 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
,
4014 0x01, PINGPONG_BUFFER
);
4015 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
,
4016 0xFF, SD_TM_CMD_RSP
| SD_TRANSFER_START
);
4017 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
, SD_TRANSFER_END
,
4020 if (rsp_type
== SD_RSP_TYPE_R2
) {
4021 for (reg_addr
= PPBUF_BASE2
; reg_addr
< PPBUF_BASE2
+ 16;
4023 rtsx_add_cmd(chip
, READ_REG_CMD
, reg_addr
, 0, 0);
4026 } else if (rsp_type
!= SD_RSP_TYPE_R0
) {
4027 for (reg_addr
= REG_SD_CMD0
; reg_addr
<= REG_SD_CMD4
;
4029 rtsx_add_cmd(chip
, READ_REG_CMD
, reg_addr
, 0, 0);
4033 rtsx_add_cmd(chip
, READ_REG_CMD
, REG_SD_CMD5
, 0, 0);
4035 rtsx_add_cmd(chip
, READ_REG_CMD
, REG_SD_STAT1
, 0, 0);
4037 retval
= rtsx_send_cmd(chip
, SD_CARD
, timeout
);
4039 if (retval
== -ETIMEDOUT
) {
4040 rtsx_clear_sd_error(chip
);
4042 if (rsp_type
& SD_WAIT_BUSY_END
) {
4043 retval
= sd_check_data0_status(chip
);
4044 if (retval
!= STATUS_SUCCESS
) {
4049 sd_set_err_code(chip
, SD_TO_ERR
);
4056 if (rsp_type
== SD_RSP_TYPE_R0
)
4057 return STATUS_SUCCESS
;
4059 ptr
= rtsx_get_cmd_data(chip
) + 1;
4061 if ((ptr
[0] & 0xC0) != 0) {
4062 sd_set_err_code(chip
, SD_STS_ERR
);
4067 if (!(rsp_type
& SD_NO_CHECK_CRC7
)) {
4068 if (ptr
[stat_idx
] & SD_CRC7_ERR
) {
4069 if (cmd_idx
== WRITE_MULTIPLE_BLOCK
) {
4070 sd_set_err_code(chip
, SD_CRC_ERR
);
4074 if (rty_cnt
< SD_MAX_RETRY_COUNT
) {
4079 sd_set_err_code(chip
, SD_CRC_ERR
);
4086 if ((cmd_idx
== SELECT_CARD
) || (cmd_idx
== APP_CMD
) ||
4087 (cmd_idx
== SEND_STATUS
) || (cmd_idx
== STOP_TRANSMISSION
)) {
4088 if ((cmd_idx
!= STOP_TRANSMISSION
) && !special_check
) {
4089 if (ptr
[1] & 0x80) {
4094 #ifdef SUPPORT_SD_LOCK
4095 if (ptr
[1] & 0x7D) {
4097 if (ptr
[1] & 0x7F) {
4102 if (ptr
[2] & 0xF8) {
4107 if (cmd_idx
== SELECT_CARD
) {
4108 if (rsp_type
== SD_RSP_TYPE_R2
) {
4109 if ((ptr
[3] & 0x1E) != 0x04) {
4114 } else if (rsp_type
== SD_RSP_TYPE_R0
) {
4115 if ((ptr
[3] & 0x1E) != 0x03) {
4124 memcpy(rsp
, ptr
, rsp_len
);
4126 return STATUS_SUCCESS
;
4129 int ext_sd_get_rsp(struct rtsx_chip
*chip
, int len
, u8
*rsp
, u8 rsp_type
)
4131 int retval
, rsp_len
;
4134 if (rsp_type
== SD_RSP_TYPE_R0
)
4135 return STATUS_SUCCESS
;
4137 rtsx_init_cmd(chip
);
4139 if (rsp_type
== SD_RSP_TYPE_R2
) {
4140 for (reg_addr
= PPBUF_BASE2
; reg_addr
< PPBUF_BASE2
+ 16;
4142 rtsx_add_cmd(chip
, READ_REG_CMD
, reg_addr
, 0xFF, 0);
4145 } else if (rsp_type
!= SD_RSP_TYPE_R0
) {
4146 for (reg_addr
= REG_SD_CMD0
; reg_addr
<= REG_SD_CMD4
;
4148 rtsx_add_cmd(chip
, READ_REG_CMD
, reg_addr
, 0xFF, 0);
4152 rtsx_add_cmd(chip
, READ_REG_CMD
, REG_SD_CMD5
, 0xFF, 0);
4154 retval
= rtsx_send_cmd(chip
, SD_CARD
, 100);
4155 if (retval
!= STATUS_SUCCESS
) {
4161 int min_len
= (rsp_len
< len
) ? rsp_len
: len
;
4163 memcpy(rsp
, rtsx_get_cmd_data(chip
), min_len
);
4165 dev_dbg(rtsx_dev(chip
), "min_len = %d\n", min_len
);
4166 dev_dbg(rtsx_dev(chip
), "Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n",
4167 rsp
[0], rsp
[1], rsp
[2], rsp
[3]);
4170 return STATUS_SUCCESS
;
4173 int sd_pass_thru_mode(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
4175 struct sd_info
*sd_card
= &(chip
->sd_card
);
4176 unsigned int lun
= SCSI_LUN(srb
);
4199 sd_card
->pre_cmd_err
= 0;
4201 if (!(CHK_BIT(chip
->lun_mc
, lun
))) {
4202 SET_BIT(chip
->lun_mc
, lun
);
4203 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_CHANGE
);
4205 return TRANSPORT_FAILED
;
4208 if ((srb
->cmnd
[2] != 0x53) || (srb
->cmnd
[3] != 0x44) ||
4209 (srb
->cmnd
[4] != 0x20) || (srb
->cmnd
[5] != 0x43) ||
4210 (srb
->cmnd
[6] != 0x61) || (srb
->cmnd
[7] != 0x72) ||
4211 (srb
->cmnd
[8] != 0x64)) {
4212 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4214 return TRANSPORT_FAILED
;
4217 switch (srb
->cmnd
[1] & 0x0F) {
4219 sd_card
->sd_pass_thru_en
= 0;
4223 sd_card
->sd_pass_thru_en
= 1;
4227 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4229 return TRANSPORT_FAILED
;
4232 buf
[5] = (CHK_SD(sd_card
) == 1) ? 0x01 : 0x02;
4233 if (chip
->card_wp
& SD_CARD
)
4236 buf
[6] = (u8
)(sd_card
->sd_addr
>> 16);
4237 buf
[7] = (u8
)(sd_card
->sd_addr
>> 24);
4239 buf
[15] = chip
->max_lun
;
4241 len
= min_t(int, 18, scsi_bufflen(srb
));
4242 rtsx_stor_set_xfer_buf(buf
, len
, srb
);
4244 return TRANSPORT_GOOD
;
4247 static inline int get_rsp_type(struct scsi_cmnd
*srb
, u8
*rsp_type
,
4250 if (!rsp_type
|| !rsp_len
)
4253 switch (srb
->cmnd
[10]) {
4255 *rsp_type
= SD_RSP_TYPE_R0
;
4260 *rsp_type
= SD_RSP_TYPE_R1
;
4265 *rsp_type
= SD_RSP_TYPE_R1b
;
4270 *rsp_type
= SD_RSP_TYPE_R2
;
4275 *rsp_type
= SD_RSP_TYPE_R3
;
4283 return STATUS_SUCCESS
;
4286 int sd_execute_no_data(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
4288 struct sd_info
*sd_card
= &(chip
->sd_card
);
4289 unsigned int lun
= SCSI_LUN(srb
);
4290 int retval
, rsp_len
;
4291 u8 cmd_idx
, rsp_type
;
4292 bool standby
= false, acmd
= false;
4295 if (!sd_card
->sd_pass_thru_en
) {
4296 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4298 return TRANSPORT_FAILED
;
4301 retval
= sd_switch_clock(chip
);
4302 if (retval
!= STATUS_SUCCESS
) {
4304 return TRANSPORT_FAILED
;
4307 if (sd_card
->pre_cmd_err
) {
4308 sd_card
->pre_cmd_err
= 0;
4309 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_CHANGE
);
4311 return TRANSPORT_FAILED
;
4314 cmd_idx
= srb
->cmnd
[2] & 0x3F;
4315 if (srb
->cmnd
[1] & 0x02)
4318 if (srb
->cmnd
[1] & 0x01)
4321 arg
= ((u32
)srb
->cmnd
[3] << 24) | ((u32
)srb
->cmnd
[4] << 16) |
4322 ((u32
)srb
->cmnd
[5] << 8) | srb
->cmnd
[6];
4324 retval
= get_rsp_type(srb
, &rsp_type
, &rsp_len
);
4325 if (retval
!= STATUS_SUCCESS
) {
4326 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4328 return TRANSPORT_FAILED
;
4330 sd_card
->last_rsp_type
= rsp_type
;
4332 retval
= sd_switch_clock(chip
);
4333 if (retval
!= STATUS_SUCCESS
) {
4335 return TRANSPORT_FAILED
;
4338 #ifdef SUPPORT_SD_LOCK
4339 if ((sd_card
->sd_lock_status
& SD_LOCK_1BIT_MODE
) == 0) {
4340 if (CHK_MMC_8BIT(sd_card
)) {
4341 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, 0x03,
4343 if (retval
!= STATUS_SUCCESS
) {
4345 return TRANSPORT_FAILED
;
4348 } else if (CHK_SD(sd_card
) || CHK_MMC_4BIT(sd_card
)) {
4349 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, 0x03,
4351 if (retval
!= STATUS_SUCCESS
) {
4353 return TRANSPORT_FAILED
;
4358 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, 0x03, SD_BUS_WIDTH_4
);
4359 if (retval
!= STATUS_SUCCESS
) {
4361 return TRANSPORT_FAILED
;
4366 retval
= sd_select_card(chip
, 0);
4367 if (retval
!= STATUS_SUCCESS
) {
4369 goto SD_Execute_Cmd_Failed
;
4374 retval
= ext_sd_send_cmd_get_rsp(chip
, APP_CMD
,
4376 SD_RSP_TYPE_R1
, NULL
, 0, false);
4377 if (retval
!= STATUS_SUCCESS
) {
4379 goto SD_Execute_Cmd_Failed
;
4383 retval
= ext_sd_send_cmd_get_rsp(chip
, cmd_idx
, arg
, rsp_type
,
4384 sd_card
->rsp
, rsp_len
, false);
4385 if (retval
!= STATUS_SUCCESS
) {
4387 goto SD_Execute_Cmd_Failed
;
4391 retval
= sd_select_card(chip
, 1);
4392 if (retval
!= STATUS_SUCCESS
) {
4394 goto SD_Execute_Cmd_Failed
;
4398 #ifdef SUPPORT_SD_LOCK
4399 retval
= sd_update_lock_status(chip
);
4400 if (retval
!= STATUS_SUCCESS
) {
4402 goto SD_Execute_Cmd_Failed
;
4406 scsi_set_resid(srb
, 0);
4407 return TRANSPORT_GOOD
;
4409 SD_Execute_Cmd_Failed
:
4410 sd_card
->pre_cmd_err
= 1;
4411 set_sense_type(chip
, lun
, SENSE_TYPE_NO_SENSE
);
4412 release_sd_card(chip
);
4413 do_reset_sd_card(chip
);
4414 if (!(chip
->card_ready
& SD_CARD
))
4415 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_NOT_PRESENT
);
4418 return TRANSPORT_FAILED
;
4421 int sd_execute_read_data(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
4423 struct sd_info
*sd_card
= &(chip
->sd_card
);
4424 unsigned int lun
= SCSI_LUN(srb
);
4425 int retval
, rsp_len
, i
;
4426 bool read_err
= false, cmd13_checkbit
= false;
4427 u8 cmd_idx
, rsp_type
, bus_width
;
4428 bool standby
= false, send_cmd12
= false, acmd
= false;
4431 if (!sd_card
->sd_pass_thru_en
) {
4432 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4434 return TRANSPORT_FAILED
;
4437 if (sd_card
->pre_cmd_err
) {
4438 sd_card
->pre_cmd_err
= 0;
4439 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_CHANGE
);
4441 return TRANSPORT_FAILED
;
4444 retval
= sd_switch_clock(chip
);
4445 if (retval
!= STATUS_SUCCESS
) {
4447 return TRANSPORT_FAILED
;
4450 cmd_idx
= srb
->cmnd
[2] & 0x3F;
4451 if (srb
->cmnd
[1] & 0x04)
4454 if (srb
->cmnd
[1] & 0x02)
4457 if (srb
->cmnd
[1] & 0x01)
4460 data_len
= ((u32
)srb
->cmnd
[7] << 16) | ((u32
)srb
->cmnd
[8]
4461 << 8) | srb
->cmnd
[9];
4463 retval
= get_rsp_type(srb
, &rsp_type
, &rsp_len
);
4464 if (retval
!= STATUS_SUCCESS
) {
4465 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4467 return TRANSPORT_FAILED
;
4469 sd_card
->last_rsp_type
= rsp_type
;
4471 retval
= sd_switch_clock(chip
);
4472 if (retval
!= STATUS_SUCCESS
) {
4474 return TRANSPORT_FAILED
;
4477 #ifdef SUPPORT_SD_LOCK
4478 if ((sd_card
->sd_lock_status
& SD_LOCK_1BIT_MODE
) == 0) {
4479 if (CHK_MMC_8BIT(sd_card
))
4480 bus_width
= SD_BUS_WIDTH_8
;
4481 else if (CHK_SD(sd_card
) || CHK_MMC_4BIT(sd_card
))
4482 bus_width
= SD_BUS_WIDTH_4
;
4484 bus_width
= SD_BUS_WIDTH_1
;
4486 bus_width
= SD_BUS_WIDTH_4
;
4488 dev_dbg(rtsx_dev(chip
), "bus_width = %d\n", bus_width
);
4490 bus_width
= SD_BUS_WIDTH_4
;
4493 if (data_len
< 512) {
4494 retval
= ext_sd_send_cmd_get_rsp(chip
, SET_BLOCKLEN
, data_len
,
4495 SD_RSP_TYPE_R1
, NULL
, 0, false);
4496 if (retval
!= STATUS_SUCCESS
) {
4498 goto SD_Execute_Read_Cmd_Failed
;
4503 retval
= sd_select_card(chip
, 0);
4504 if (retval
!= STATUS_SUCCESS
) {
4506 goto SD_Execute_Read_Cmd_Failed
;
4511 retval
= ext_sd_send_cmd_get_rsp(chip
, APP_CMD
,
4513 SD_RSP_TYPE_R1
, NULL
, 0, false);
4514 if (retval
!= STATUS_SUCCESS
) {
4516 goto SD_Execute_Read_Cmd_Failed
;
4520 if (data_len
<= 512) {
4523 u16 byte_cnt
, blk_cnt
;
4526 byte_cnt
= ((u16
)(srb
->cmnd
[8] & 0x03) << 8) | srb
->cmnd
[9];
4529 cmd
[0] = 0x40 | cmd_idx
;
4530 cmd
[1] = srb
->cmnd
[3];
4531 cmd
[2] = srb
->cmnd
[4];
4532 cmd
[3] = srb
->cmnd
[5];
4533 cmd
[4] = srb
->cmnd
[6];
4535 buf
= kmalloc(data_len
, GFP_KERNEL
);
4538 return TRANSPORT_ERROR
;
4541 retval
= sd_read_data(chip
, SD_TM_NORMAL_READ
, cmd
, 5, byte_cnt
,
4542 blk_cnt
, bus_width
, buf
, data_len
, 2000);
4543 if (retval
!= STATUS_SUCCESS
) {
4546 rtsx_clear_sd_error(chip
);
4548 goto SD_Execute_Read_Cmd_Failed
;
4551 min_len
= min(data_len
, scsi_bufflen(srb
));
4552 rtsx_stor_set_xfer_buf(buf
, min_len
, srb
);
4555 } else if (!(data_len
& 0x1FF)) {
4556 rtsx_init_cmd(chip
);
4558 trans_dma_enable(DMA_FROM_DEVICE
, chip
, data_len
, DMA_512
);
4560 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_H
, 0xFF,
4562 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF,
4564 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
,
4565 0xFF, (srb
->cmnd
[7] & 0xFE) >> 1);
4566 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
,
4567 0xFF, (u8
)((data_len
& 0x0001FE00) >> 9));
4569 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD0
, 0xFF,
4571 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD1
, 0xFF,
4573 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD2
, 0xFF,
4575 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD3
, 0xFF,
4577 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CMD4
, 0xFF,
4580 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG1
, 0x03, bus_width
);
4581 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_CFG2
, 0xFF, rsp_type
);
4583 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
,
4584 0xFF, SD_TM_AUTO_READ_2
| SD_TRANSFER_START
);
4585 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
,
4586 SD_TRANSFER_END
, SD_TRANSFER_END
);
4588 rtsx_send_cmd_no_wait(chip
);
4590 retval
= rtsx_transfer_data(chip
, SD_CARD
, scsi_sglist(srb
),
4591 scsi_bufflen(srb
), scsi_sg_count(srb
),
4592 DMA_FROM_DEVICE
, 10000);
4595 rtsx_clear_sd_error(chip
);
4597 goto SD_Execute_Read_Cmd_Failed
;
4602 goto SD_Execute_Read_Cmd_Failed
;
4605 retval
= ext_sd_get_rsp(chip
, rsp_len
, sd_card
->rsp
, rsp_type
);
4606 if (retval
!= STATUS_SUCCESS
) {
4608 goto SD_Execute_Read_Cmd_Failed
;
4612 retval
= sd_select_card(chip
, 1);
4613 if (retval
!= STATUS_SUCCESS
) {
4615 goto SD_Execute_Read_Cmd_Failed
;
4620 retval
= ext_sd_send_cmd_get_rsp(chip
, STOP_TRANSMISSION
,
4621 0, SD_RSP_TYPE_R1b
, NULL
, 0, false);
4622 if (retval
!= STATUS_SUCCESS
) {
4624 goto SD_Execute_Read_Cmd_Failed
;
4628 if (data_len
< 512) {
4629 retval
= ext_sd_send_cmd_get_rsp(chip
, SET_BLOCKLEN
, 0x200,
4630 SD_RSP_TYPE_R1
, NULL
, 0, false);
4631 if (retval
!= STATUS_SUCCESS
) {
4633 goto SD_Execute_Read_Cmd_Failed
;
4636 retval
= rtsx_write_register(chip
, SD_BYTE_CNT_H
, 0xFF, 0x02);
4637 if (retval
!= STATUS_SUCCESS
) {
4639 goto SD_Execute_Read_Cmd_Failed
;
4642 retval
= rtsx_write_register(chip
, SD_BYTE_CNT_L
, 0xFF, 0x00);
4643 if (retval
!= STATUS_SUCCESS
) {
4645 goto SD_Execute_Read_Cmd_Failed
;
4649 if ((srb
->cmnd
[1] & 0x02) || (srb
->cmnd
[1] & 0x04))
4650 cmd13_checkbit
= true;
4652 for (i
= 0; i
< 3; i
++) {
4653 retval
= ext_sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
4655 SD_RSP_TYPE_R1
, NULL
, 0,
4657 if (retval
== STATUS_SUCCESS
)
4660 if (retval
!= STATUS_SUCCESS
) {
4662 goto SD_Execute_Read_Cmd_Failed
;
4665 scsi_set_resid(srb
, 0);
4666 return TRANSPORT_GOOD
;
4668 SD_Execute_Read_Cmd_Failed
:
4669 sd_card
->pre_cmd_err
= 1;
4670 set_sense_type(chip
, lun
, SENSE_TYPE_NO_SENSE
);
4672 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR
);
4674 release_sd_card(chip
);
4675 do_reset_sd_card(chip
);
4676 if (!(chip
->card_ready
& SD_CARD
))
4677 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_NOT_PRESENT
);
4680 return TRANSPORT_FAILED
;
4683 int sd_execute_write_data(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
4685 struct sd_info
*sd_card
= &(chip
->sd_card
);
4686 unsigned int lun
= SCSI_LUN(srb
);
4687 int retval
, rsp_len
, i
;
4688 bool write_err
= false, cmd13_checkbit
= false;
4689 u8 cmd_idx
, rsp_type
;
4690 bool standby
= false, send_cmd12
= false, acmd
= false;
4692 #ifdef SUPPORT_SD_LOCK
4693 int lock_cmd_fail
= 0;
4694 u8 sd_lock_state
= 0;
4695 u8 lock_cmd_type
= 0;
4698 if (!sd_card
->sd_pass_thru_en
) {
4699 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4701 return TRANSPORT_FAILED
;
4704 if (sd_card
->pre_cmd_err
) {
4705 sd_card
->pre_cmd_err
= 0;
4706 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_CHANGE
);
4708 return TRANSPORT_FAILED
;
4711 retval
= sd_switch_clock(chip
);
4712 if (retval
!= STATUS_SUCCESS
) {
4714 return TRANSPORT_FAILED
;
4717 cmd_idx
= srb
->cmnd
[2] & 0x3F;
4718 if (srb
->cmnd
[1] & 0x04)
4721 if (srb
->cmnd
[1] & 0x02)
4724 if (srb
->cmnd
[1] & 0x01)
4727 data_len
= ((u32
)srb
->cmnd
[7] << 16) | ((u32
)srb
->cmnd
[8]
4728 << 8) | srb
->cmnd
[9];
4729 arg
= ((u32
)srb
->cmnd
[3] << 24) | ((u32
)srb
->cmnd
[4] << 16) |
4730 ((u32
)srb
->cmnd
[5] << 8) | srb
->cmnd
[6];
4732 #ifdef SUPPORT_SD_LOCK
4733 if (cmd_idx
== LOCK_UNLOCK
) {
4734 sd_lock_state
= sd_card
->sd_lock_status
;
4735 sd_lock_state
&= SD_LOCKED
;
4739 retval
= get_rsp_type(srb
, &rsp_type
, &rsp_len
);
4740 if (retval
!= STATUS_SUCCESS
) {
4741 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
4743 return TRANSPORT_FAILED
;
4745 sd_card
->last_rsp_type
= rsp_type
;
4747 retval
= sd_switch_clock(chip
);
4748 if (retval
!= STATUS_SUCCESS
) {
4750 return TRANSPORT_FAILED
;
4753 #ifdef SUPPORT_SD_LOCK
4754 if ((sd_card
->sd_lock_status
& SD_LOCK_1BIT_MODE
) == 0) {
4755 if (CHK_MMC_8BIT(sd_card
)) {
4756 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, 0x03,
4758 if (retval
!= STATUS_SUCCESS
) {
4760 return TRANSPORT_FAILED
;
4763 } else if (CHK_SD(sd_card
) || CHK_MMC_4BIT(sd_card
)) {
4764 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, 0x03,
4766 if (retval
!= STATUS_SUCCESS
) {
4768 return TRANSPORT_FAILED
;
4773 retval
= rtsx_write_register(chip
, REG_SD_CFG1
, 0x03, SD_BUS_WIDTH_4
);
4774 if (retval
!= STATUS_SUCCESS
) {
4776 return TRANSPORT_FAILED
;
4780 if (data_len
< 512) {
4781 retval
= ext_sd_send_cmd_get_rsp(chip
, SET_BLOCKLEN
, data_len
,
4782 SD_RSP_TYPE_R1
, NULL
, 0, false);
4783 if (retval
!= STATUS_SUCCESS
) {
4785 goto SD_Execute_Write_Cmd_Failed
;
4790 retval
= sd_select_card(chip
, 0);
4791 if (retval
!= STATUS_SUCCESS
) {
4793 goto SD_Execute_Write_Cmd_Failed
;
4798 retval
= ext_sd_send_cmd_get_rsp(chip
, APP_CMD
,
4800 SD_RSP_TYPE_R1
, NULL
, 0, false);
4801 if (retval
!= STATUS_SUCCESS
) {
4803 goto SD_Execute_Write_Cmd_Failed
;
4807 retval
= ext_sd_send_cmd_get_rsp(chip
, cmd_idx
, arg
, rsp_type
,
4808 sd_card
->rsp
, rsp_len
, false);
4809 if (retval
!= STATUS_SUCCESS
) {
4811 goto SD_Execute_Write_Cmd_Failed
;
4814 if (data_len
<= 512) {
4818 buf
= kmalloc(data_len
, GFP_KERNEL
);
4821 return TRANSPORT_ERROR
;
4824 rtsx_stor_get_xfer_buf(buf
, data_len
, srb
);
4826 #ifdef SUPPORT_SD_LOCK
4827 if (cmd_idx
== LOCK_UNLOCK
)
4828 lock_cmd_type
= buf
[0] & 0x0F;
4831 if (data_len
> 256) {
4832 rtsx_init_cmd(chip
);
4833 for (i
= 0; i
< 256; i
++) {
4834 rtsx_add_cmd(chip
, WRITE_REG_CMD
,
4835 PPBUF_BASE2
+ i
, 0xFF, buf
[i
]);
4837 retval
= rtsx_send_cmd(chip
, 0, 250);
4838 if (retval
!= STATUS_SUCCESS
) {
4841 goto SD_Execute_Write_Cmd_Failed
;
4844 rtsx_init_cmd(chip
);
4845 for (i
= 256; i
< data_len
; i
++) {
4846 rtsx_add_cmd(chip
, WRITE_REG_CMD
,
4847 PPBUF_BASE2
+ i
, 0xFF, buf
[i
]);
4849 retval
= rtsx_send_cmd(chip
, 0, 250);
4850 if (retval
!= STATUS_SUCCESS
) {
4853 goto SD_Execute_Write_Cmd_Failed
;
4856 rtsx_init_cmd(chip
);
4857 for (i
= 0; i
< data_len
; i
++) {
4858 rtsx_add_cmd(chip
, WRITE_REG_CMD
,
4859 PPBUF_BASE2
+ i
, 0xFF, buf
[i
]);
4861 retval
= rtsx_send_cmd(chip
, 0, 250);
4862 if (retval
!= STATUS_SUCCESS
) {
4865 goto SD_Execute_Write_Cmd_Failed
;
4871 rtsx_init_cmd(chip
);
4873 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_H
, 0xFF,
4874 srb
->cmnd
[8] & 0x03);
4875 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF,
4877 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
, 0xFF,
4879 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
, 0xFF,
4881 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01,
4884 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
4885 SD_TM_AUTO_WRITE_3
| SD_TRANSFER_START
);
4886 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
,
4887 SD_TRANSFER_END
, SD_TRANSFER_END
);
4889 retval
= rtsx_send_cmd(chip
, SD_CARD
, 250);
4890 } else if (!(data_len
& 0x1FF)) {
4891 rtsx_init_cmd(chip
);
4893 trans_dma_enable(DMA_TO_DEVICE
, chip
, data_len
, DMA_512
);
4895 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_H
, 0xFF,
4897 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BYTE_CNT_L
, 0xFF,
4899 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_H
,
4900 0xFF, (srb
->cmnd
[7] & 0xFE) >> 1);
4901 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_BLOCK_CNT_L
,
4902 0xFF, (u8
)((data_len
& 0x0001FE00) >> 9));
4904 rtsx_add_cmd(chip
, WRITE_REG_CMD
, REG_SD_TRANSFER
, 0xFF,
4905 SD_TM_AUTO_WRITE_3
| SD_TRANSFER_START
);
4906 rtsx_add_cmd(chip
, CHECK_REG_CMD
, REG_SD_TRANSFER
,
4907 SD_TRANSFER_END
, SD_TRANSFER_END
);
4909 rtsx_send_cmd_no_wait(chip
);
4911 retval
= rtsx_transfer_data(chip
, SD_CARD
, scsi_sglist(srb
),
4912 scsi_bufflen(srb
), scsi_sg_count(srb
),
4913 DMA_TO_DEVICE
, 10000);
4917 goto SD_Execute_Write_Cmd_Failed
;
4922 rtsx_clear_sd_error(chip
);
4924 goto SD_Execute_Write_Cmd_Failed
;
4927 #ifdef SUPPORT_SD_LOCK
4928 if (cmd_idx
== LOCK_UNLOCK
) {
4929 if (lock_cmd_type
== SD_ERASE
) {
4930 sd_card
->sd_erase_status
= SD_UNDER_ERASING
;
4931 scsi_set_resid(srb
, 0);
4932 return TRANSPORT_GOOD
;
4935 rtsx_init_cmd(chip
);
4936 rtsx_add_cmd(chip
, CHECK_REG_CMD
, 0xFD30, 0x02, 0x02);
4938 rtsx_send_cmd(chip
, SD_CARD
, 250);
4940 retval
= sd_update_lock_status(chip
);
4941 if (retval
!= STATUS_SUCCESS
) {
4942 dev_dbg(rtsx_dev(chip
), "Lock command fail!\n");
4946 #endif /* SUPPORT_SD_LOCK */
4949 retval
= sd_select_card(chip
, 1);
4950 if (retval
!= STATUS_SUCCESS
) {
4952 goto SD_Execute_Write_Cmd_Failed
;
4957 retval
= ext_sd_send_cmd_get_rsp(chip
, STOP_TRANSMISSION
,
4958 0, SD_RSP_TYPE_R1b
, NULL
, 0, false);
4959 if (retval
!= STATUS_SUCCESS
) {
4961 goto SD_Execute_Write_Cmd_Failed
;
4965 if (data_len
< 512) {
4966 retval
= ext_sd_send_cmd_get_rsp(chip
, SET_BLOCKLEN
, 0x200,
4967 SD_RSP_TYPE_R1
, NULL
, 0, false);
4968 if (retval
!= STATUS_SUCCESS
) {
4970 goto SD_Execute_Write_Cmd_Failed
;
4973 retval
= rtsx_write_register(chip
, SD_BYTE_CNT_H
, 0xFF, 0x02);
4974 if (retval
!= STATUS_SUCCESS
) {
4976 goto SD_Execute_Write_Cmd_Failed
;
4979 rtsx_write_register(chip
, SD_BYTE_CNT_L
, 0xFF, 0x00);
4980 if (retval
!= STATUS_SUCCESS
) {
4982 goto SD_Execute_Write_Cmd_Failed
;
4986 if ((srb
->cmnd
[1] & 0x02) || (srb
->cmnd
[1] & 0x04))
4987 cmd13_checkbit
= true;
4989 for (i
= 0; i
< 3; i
++) {
4990 retval
= ext_sd_send_cmd_get_rsp(chip
, SEND_STATUS
,
4992 SD_RSP_TYPE_R1
, NULL
, 0,
4994 if (retval
== STATUS_SUCCESS
)
4997 if (retval
!= STATUS_SUCCESS
) {
4999 goto SD_Execute_Write_Cmd_Failed
;
5002 #ifdef SUPPORT_SD_LOCK
5003 if (cmd_idx
== LOCK_UNLOCK
) {
5004 if (!lock_cmd_fail
) {
5005 dev_dbg(rtsx_dev(chip
), "lock_cmd_type = 0x%x\n",
5007 if (lock_cmd_type
& SD_CLR_PWD
)
5008 sd_card
->sd_lock_status
&= ~SD_PWD_EXIST
;
5010 if (lock_cmd_type
& SD_SET_PWD
)
5011 sd_card
->sd_lock_status
|= SD_PWD_EXIST
;
5014 dev_dbg(rtsx_dev(chip
), "sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n",
5015 sd_lock_state
, sd_card
->sd_lock_status
);
5016 if (sd_lock_state
^ (sd_card
->sd_lock_status
& SD_LOCKED
)) {
5017 sd_card
->sd_lock_notify
= 1;
5018 if (sd_lock_state
) {
5019 if (sd_card
->sd_lock_status
& SD_LOCK_1BIT_MODE
) {
5020 sd_card
->sd_lock_status
|= (
5021 SD_UNLOCK_POW_ON
| SD_SDR_RST
);
5022 if (CHK_SD(sd_card
)) {
5023 retval
= reset_sd(chip
);
5024 if (retval
!= STATUS_SUCCESS
) {
5025 sd_card
->sd_lock_status
&= ~(SD_UNLOCK_POW_ON
| SD_SDR_RST
);
5027 goto SD_Execute_Write_Cmd_Failed
;
5031 sd_card
->sd_lock_status
&= ~(SD_UNLOCK_POW_ON
| SD_SDR_RST
);
5037 if (lock_cmd_fail
) {
5038 scsi_set_resid(srb
, 0);
5039 set_sense_type(chip
, lun
, SENSE_TYPE_NO_SENSE
);
5041 return TRANSPORT_FAILED
;
5043 #endif /* SUPPORT_SD_LOCK */
5045 scsi_set_resid(srb
, 0);
5046 return TRANSPORT_GOOD
;
5048 SD_Execute_Write_Cmd_Failed
:
5049 sd_card
->pre_cmd_err
= 1;
5050 set_sense_type(chip
, lun
, SENSE_TYPE_NO_SENSE
);
5052 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_WRITE_ERR
);
5054 release_sd_card(chip
);
5055 do_reset_sd_card(chip
);
5056 if (!(chip
->card_ready
& SD_CARD
))
5057 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_NOT_PRESENT
);
5060 return TRANSPORT_FAILED
;
5063 int sd_get_cmd_rsp(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
5065 struct sd_info
*sd_card
= &(chip
->sd_card
);
5066 unsigned int lun
= SCSI_LUN(srb
);
5070 if (!sd_card
->sd_pass_thru_en
) {
5071 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
5073 return TRANSPORT_FAILED
;
5076 if (sd_card
->pre_cmd_err
) {
5077 sd_card
->pre_cmd_err
= 0;
5078 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_CHANGE
);
5080 return TRANSPORT_FAILED
;
5083 data_len
= ((u16
)srb
->cmnd
[7] << 8) | srb
->cmnd
[8];
5085 if (sd_card
->last_rsp_type
== SD_RSP_TYPE_R0
) {
5086 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
5088 return TRANSPORT_FAILED
;
5089 } else if (sd_card
->last_rsp_type
== SD_RSP_TYPE_R2
) {
5090 count
= (data_len
< 17) ? data_len
: 17;
5092 count
= (data_len
< 6) ? data_len
: 6;
5094 rtsx_stor_set_xfer_buf(sd_card
->rsp
, count
, srb
);
5096 dev_dbg(rtsx_dev(chip
), "Response length: %d\n", data_len
);
5097 dev_dbg(rtsx_dev(chip
), "Response: 0x%x 0x%x 0x%x 0x%x\n",
5098 sd_card
->rsp
[0], sd_card
->rsp
[1],
5099 sd_card
->rsp
[2], sd_card
->rsp
[3]);
5101 scsi_set_resid(srb
, 0);
5102 return TRANSPORT_GOOD
;
5105 int sd_hw_rst(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
5107 struct sd_info
*sd_card
= &(chip
->sd_card
);
5108 unsigned int lun
= SCSI_LUN(srb
);
5111 if (!sd_card
->sd_pass_thru_en
) {
5112 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
5114 return TRANSPORT_FAILED
;
5117 if (sd_card
->pre_cmd_err
) {
5118 sd_card
->pre_cmd_err
= 0;
5119 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_CHANGE
);
5121 return TRANSPORT_FAILED
;
5124 if ((srb
->cmnd
[2] != 0x53) || (srb
->cmnd
[3] != 0x44) ||
5125 (srb
->cmnd
[4] != 0x20) || (srb
->cmnd
[5] != 0x43) ||
5126 (srb
->cmnd
[6] != 0x61) || (srb
->cmnd
[7] != 0x72) ||
5127 (srb
->cmnd
[8] != 0x64)) {
5128 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
5130 return TRANSPORT_FAILED
;
5133 switch (srb
->cmnd
[1] & 0x0F) {
5135 #ifdef SUPPORT_SD_LOCK
5136 if (srb
->cmnd
[9] == 0x64)
5137 sd_card
->sd_lock_status
|= SD_SDR_RST
;
5139 retval
= reset_sd_card(chip
);
5140 if (retval
!= STATUS_SUCCESS
) {
5141 #ifdef SUPPORT_SD_LOCK
5142 sd_card
->sd_lock_status
&= ~SD_SDR_RST
;
5144 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_NOT_PRESENT
);
5145 sd_card
->pre_cmd_err
= 1;
5147 return TRANSPORT_FAILED
;
5149 #ifdef SUPPORT_SD_LOCK
5150 sd_card
->sd_lock_status
&= ~SD_SDR_RST
;
5155 retval
= soft_reset_sd_card(chip
);
5156 if (retval
!= STATUS_SUCCESS
) {
5157 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_NOT_PRESENT
);
5158 sd_card
->pre_cmd_err
= 1;
5160 return TRANSPORT_FAILED
;
5165 set_sense_type(chip
, lun
, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD
);
5167 return TRANSPORT_FAILED
;
5170 scsi_set_resid(srb
, 0);
5171 return TRANSPORT_GOOD
;
5175 void sd_cleanup_work(struct rtsx_chip
*chip
)
5177 struct sd_info
*sd_card
= &(chip
->sd_card
);
5179 if (sd_card
->seq_mode
) {
5180 dev_dbg(rtsx_dev(chip
), "SD: stop transmission\n");
5181 sd_stop_seq_mode(chip
);
5182 sd_card
->cleanup_counter
= 0;
5186 int sd_power_off_card3v3(struct rtsx_chip
*chip
)
5190 retval
= disable_card_clock(chip
, SD_CARD
);
5191 if (retval
!= STATUS_SUCCESS
) {
5196 retval
= rtsx_write_register(chip
, CARD_OE
, SD_OUTPUT_EN
, 0);
5202 if (!chip
->ft2_fast_mode
) {
5203 retval
= card_power_off(chip
, SD_CARD
);
5204 if (retval
!= STATUS_SUCCESS
) {
5212 if (chip
->asic_code
) {
5213 retval
= sd_pull_ctl_disable(chip
);
5214 if (retval
!= STATUS_SUCCESS
) {
5219 retval
= rtsx_write_register(chip
, FPGA_PULL_CTL
,
5220 FPGA_SD_PULL_CTL_BIT
| 0x20,
5221 FPGA_SD_PULL_CTL_BIT
);
5228 return STATUS_SUCCESS
;
5231 int release_sd_card(struct rtsx_chip
*chip
)
5233 struct sd_info
*sd_card
= &(chip
->sd_card
);
5236 chip
->card_ready
&= ~SD_CARD
;
5237 chip
->card_fail
&= ~SD_CARD
;
5238 chip
->card_wp
&= ~SD_CARD
;
5243 #ifdef SUPPORT_SD_LOCK
5244 sd_card
->sd_lock_status
= 0;
5245 sd_card
->sd_erase_status
= 0;
5248 memset(sd_card
->raw_csd
, 0, 16);
5249 memset(sd_card
->raw_scr
, 0, 8);
5251 retval
= sd_power_off_card3v3(chip
);
5252 if (retval
!= STATUS_SUCCESS
) {
5257 return STATUS_SUCCESS
;