]>
git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/staging/rts5208/spi.c
1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
30 static inline void spi_set_err_code(struct rtsx_chip
*chip
, u8 err_code
)
32 struct spi_info
*spi
= &(chip
->spi
);
34 spi
->err_code
= err_code
;
37 static int spi_init(struct rtsx_chip
*chip
)
41 retval
= rtsx_write_register(chip
, SPI_CONTROL
, 0xFF,
42 CS_POLARITY_LOW
| DTO_MSB_FIRST
43 | SPI_MASTER
| SPI_MODE0
| SPI_AUTO
);
48 retval
= rtsx_write_register(chip
, SPI_TCTL
, EDO_TIMING_MASK
,
55 return STATUS_SUCCESS
;
58 static int spi_set_init_para(struct rtsx_chip
*chip
)
60 struct spi_info
*spi
= &(chip
->spi
);
63 retval
= rtsx_write_register(chip
, SPI_CLK_DIVIDER1
, 0xFF,
64 (u8
)(spi
->clk_div
>> 8));
69 retval
= rtsx_write_register(chip
, SPI_CLK_DIVIDER0
, 0xFF,
76 retval
= switch_clock(chip
, spi
->spi_clock
);
77 if (retval
!= STATUS_SUCCESS
) {
82 retval
= select_card(chip
, SPI_CARD
);
83 if (retval
!= STATUS_SUCCESS
) {
88 retval
= rtsx_write_register(chip
, CARD_CLK_EN
, SPI_CLK_EN
,
94 retval
= rtsx_write_register(chip
, CARD_OE
, SPI_OUTPUT_EN
,
103 retval
= spi_init(chip
);
104 if (retval
!= STATUS_SUCCESS
) {
109 return STATUS_SUCCESS
;
112 static int sf_polling_status(struct rtsx_chip
*chip
, int msec
)
118 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, SPI_RDSR
);
119 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
120 SPI_TRANSFER0_START
| SPI_POLLING_MODE0
);
121 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
,
124 retval
= rtsx_send_cmd(chip
, 0, msec
);
126 rtsx_clear_spi_error(chip
);
127 spi_set_err_code(chip
, SPI_BUSY_ERR
);
132 return STATUS_SUCCESS
;
135 static int sf_enable_write(struct rtsx_chip
*chip
, u8 ins
)
137 struct spi_info
*spi
= &(chip
->spi
);
141 return STATUS_SUCCESS
;
145 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, ins
);
146 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF,
147 SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_24
);
148 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
149 SPI_TRANSFER0_START
| SPI_C_MODE0
);
150 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
,
153 retval
= rtsx_send_cmd(chip
, 0, 100);
155 rtsx_clear_spi_error(chip
);
156 spi_set_err_code(chip
, SPI_HW_ERR
);
161 return STATUS_SUCCESS
;
164 static int sf_disable_write(struct rtsx_chip
*chip
, u8 ins
)
166 struct spi_info
*spi
= &(chip
->spi
);
170 return STATUS_SUCCESS
;
174 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, ins
);
175 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF,
176 SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_24
);
177 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
178 SPI_TRANSFER0_START
| SPI_C_MODE0
);
179 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
,
182 retval
= rtsx_send_cmd(chip
, 0, 100);
184 rtsx_clear_spi_error(chip
);
185 spi_set_err_code(chip
, SPI_HW_ERR
);
190 return STATUS_SUCCESS
;
193 static void sf_program(struct rtsx_chip
*chip
, u8 ins
, u8 addr_mode
, u32 addr
,
196 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, ins
);
197 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF,
198 SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_24
);
199 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH0
, 0xFF, (u8
)len
);
200 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH1
, 0xFF, (u8
)(len
>> 8));
202 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR0
, 0xFF, (u8
)addr
);
203 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF,
205 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR2
, 0xFF,
207 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
208 SPI_TRANSFER0_START
| SPI_CADO_MODE0
);
210 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
211 SPI_TRANSFER0_START
| SPI_CDO_MODE0
);
213 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
,
217 static int sf_erase(struct rtsx_chip
*chip
, u8 ins
, u8 addr_mode
, u32 addr
)
223 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, ins
);
224 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF,
225 SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_24
);
227 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR0
, 0xFF, (u8
)addr
);
228 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF,
230 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR2
, 0xFF,
232 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
233 SPI_TRANSFER0_START
| SPI_CA_MODE0
);
235 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
236 SPI_TRANSFER0_START
| SPI_C_MODE0
);
238 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
,
241 retval
= rtsx_send_cmd(chip
, 0, 100);
243 rtsx_clear_spi_error(chip
);
244 spi_set_err_code(chip
, SPI_HW_ERR
);
249 return STATUS_SUCCESS
;
252 static int spi_init_eeprom(struct rtsx_chip
*chip
)
262 retval
= rtsx_write_register(chip
, SPI_CLK_DIVIDER1
, 0xFF, 0x00);
267 retval
= rtsx_write_register(chip
, SPI_CLK_DIVIDER0
, 0xFF, 0x27);
273 retval
= switch_clock(chip
, clk
);
274 if (retval
!= STATUS_SUCCESS
) {
279 retval
= select_card(chip
, SPI_CARD
);
280 if (retval
!= STATUS_SUCCESS
) {
285 retval
= rtsx_write_register(chip
, CARD_CLK_EN
, SPI_CLK_EN
,
291 retval
= rtsx_write_register(chip
, CARD_OE
, SPI_OUTPUT_EN
,
300 retval
= rtsx_write_register(chip
, SPI_CONTROL
, 0xFF,
301 CS_POLARITY_HIGH
| SPI_EEPROM_AUTO
);
306 retval
= rtsx_write_register(chip
, SPI_TCTL
, EDO_TIMING_MASK
,
313 return STATUS_SUCCESS
;
316 static int spi_eeprom_program_enable(struct rtsx_chip
*chip
)
322 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, 0x86);
323 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, 0x13);
324 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
325 SPI_TRANSFER0_START
| SPI_CA_MODE0
);
326 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
,
329 retval
= rtsx_send_cmd(chip
, 0, 100);
335 return STATUS_SUCCESS
;
338 int spi_erase_eeprom_chip(struct rtsx_chip
*chip
)
342 retval
= spi_init_eeprom(chip
);
343 if (retval
!= STATUS_SUCCESS
) {
348 retval
= spi_eeprom_program_enable(chip
);
349 if (retval
!= STATUS_SUCCESS
) {
356 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_GPIO_DIR
, 0x01, 0);
357 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, RING_BUFFER
);
358 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, 0x12);
359 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, 0x84);
360 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
361 SPI_TRANSFER0_START
| SPI_CA_MODE0
);
362 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
,
365 retval
= rtsx_send_cmd(chip
, 0, 100);
371 retval
= rtsx_write_register(chip
, CARD_GPIO_DIR
, 0x01, 0x01);
377 return STATUS_SUCCESS
;
380 int spi_erase_eeprom_byte(struct rtsx_chip
*chip
, u16 addr
)
384 retval
= spi_init_eeprom(chip
);
385 if (retval
!= STATUS_SUCCESS
) {
390 retval
= spi_eeprom_program_enable(chip
);
391 if (retval
!= STATUS_SUCCESS
) {
398 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_GPIO_DIR
, 0x01, 0);
399 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, RING_BUFFER
);
400 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, 0x07);
401 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR0
, 0xFF, (u8
)addr
);
402 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF, (u8
)(addr
>> 8));
403 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, 0x46);
404 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
405 SPI_TRANSFER0_START
| SPI_CA_MODE0
);
406 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
,
409 retval
= rtsx_send_cmd(chip
, 0, 100);
415 retval
= rtsx_write_register(chip
, CARD_GPIO_DIR
, 0x01, 0x01);
421 return STATUS_SUCCESS
;
424 int spi_read_eeprom(struct rtsx_chip
*chip
, u16 addr
, u8
*val
)
429 retval
= spi_init_eeprom(chip
);
430 if (retval
!= STATUS_SUCCESS
) {
437 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_GPIO_DIR
, 0x01, 0);
438 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, RING_BUFFER
);
439 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, 0x06);
440 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR0
, 0xFF, (u8
)addr
);
441 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF, (u8
)(addr
>> 8));
442 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, 0x46);
443 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH0
, 0xFF, 1);
444 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
445 SPI_TRANSFER0_START
| SPI_CADI_MODE0
);
446 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
,
449 retval
= rtsx_send_cmd(chip
, 0, 100);
456 retval
= rtsx_read_register(chip
, SPI_DATA
, &data
);
465 retval
= rtsx_write_register(chip
, CARD_GPIO_DIR
, 0x01, 0x01);
471 return STATUS_SUCCESS
;
474 int spi_write_eeprom(struct rtsx_chip
*chip
, u16 addr
, u8 val
)
478 retval
= spi_init_eeprom(chip
);
479 if (retval
!= STATUS_SUCCESS
) {
484 retval
= spi_eeprom_program_enable(chip
);
485 if (retval
!= STATUS_SUCCESS
) {
492 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_GPIO_DIR
, 0x01, 0);
493 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01, RING_BUFFER
);
494 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, 0x05);
495 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR0
, 0xFF, val
);
496 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF, (u8
)addr
);
497 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR2
, 0xFF, (u8
)(addr
>> 8));
498 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF, 0x4E);
499 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
500 SPI_TRANSFER0_START
| SPI_CA_MODE0
);
501 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
,
504 retval
= rtsx_send_cmd(chip
, 0, 100);
510 retval
= rtsx_write_register(chip
, CARD_GPIO_DIR
, 0x01, 0x01);
516 return STATUS_SUCCESS
;
519 int spi_get_status(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
521 struct spi_info
*spi
= &(chip
->spi
);
523 dev_dbg(rtsx_dev(chip
), "spi_get_status: err_code = 0x%x\n",
525 rtsx_stor_set_xfer_buf(&(spi
->err_code
),
526 min_t(int, scsi_bufflen(srb
), 1), srb
);
527 scsi_set_resid(srb
, scsi_bufflen(srb
) - 1);
529 return STATUS_SUCCESS
;
532 int spi_set_parameter(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
534 struct spi_info
*spi
= &(chip
->spi
);
536 spi_set_err_code(chip
, SPI_NO_ERR
);
539 spi
->spi_clock
= ((u16
)(srb
->cmnd
[8]) << 8) | srb
->cmnd
[9];
541 spi
->spi_clock
= srb
->cmnd
[3];
543 spi
->clk_div
= ((u16
)(srb
->cmnd
[4]) << 8) | srb
->cmnd
[5];
544 spi
->write_en
= srb
->cmnd
[6];
546 dev_dbg(rtsx_dev(chip
), "spi_set_parameter: spi_clock = %d, clk_div = %d, write_en = %d\n",
547 spi
->spi_clock
, spi
->clk_div
, spi
->write_en
);
549 return STATUS_SUCCESS
;
552 int spi_read_flash_id(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
558 spi_set_err_code(chip
, SPI_NO_ERR
);
560 len
= ((u16
)(srb
->cmnd
[7]) << 8) | srb
->cmnd
[8];
562 spi_set_err_code(chip
, SPI_INVALID_COMMAND
);
567 retval
= spi_set_init_para(chip
);
568 if (retval
!= STATUS_SUCCESS
) {
569 spi_set_err_code(chip
, SPI_HW_ERR
);
576 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01,
579 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, srb
->cmnd
[3]);
580 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR2
, 0xFF, srb
->cmnd
[4]);
581 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF, srb
->cmnd
[5]);
582 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR0
, 0xFF, srb
->cmnd
[6]);
583 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF,
584 SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_24
);
585 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH1
, 0xFF, srb
->cmnd
[7]);
586 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH0
, 0xFF, srb
->cmnd
[8]);
590 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
,
591 0xFF, SPI_TRANSFER0_START
| SPI_CA_MODE0
);
593 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
,
594 0xFF, SPI_TRANSFER0_START
| SPI_C_MODE0
);
598 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
599 SPI_TRANSFER0_START
| SPI_CADI_MODE0
);
601 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
602 SPI_TRANSFER0_START
| SPI_CDI_MODE0
);
606 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
,
609 retval
= rtsx_send_cmd(chip
, 0, 100);
611 rtsx_clear_spi_error(chip
);
612 spi_set_err_code(chip
, SPI_HW_ERR
);
618 buf
= kmalloc(len
, GFP_KERNEL
);
624 retval
= rtsx_read_ppbuf(chip
, buf
, len
);
625 if (retval
!= STATUS_SUCCESS
) {
626 spi_set_err_code(chip
, SPI_READ_ERR
);
632 rtsx_stor_set_xfer_buf(buf
, scsi_bufflen(srb
), srb
);
633 scsi_set_resid(srb
, 0);
638 return STATUS_SUCCESS
;
641 int spi_read_flash(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
644 unsigned int index
= 0, offset
= 0;
650 spi_set_err_code(chip
, SPI_NO_ERR
);
653 addr
= ((u32
)(srb
->cmnd
[4]) << 16) | ((u32
)(srb
->cmnd
[5])
654 << 8) | srb
->cmnd
[6];
655 len
= ((u16
)(srb
->cmnd
[7]) << 8) | srb
->cmnd
[8];
656 slow_read
= srb
->cmnd
[9];
658 retval
= spi_set_init_para(chip
);
659 if (retval
!= STATUS_SUCCESS
) {
660 spi_set_err_code(chip
, SPI_HW_ERR
);
665 buf
= kmalloc(SF_PAGE_LEN
, GFP_KERNEL
);
672 u16 pagelen
= SF_PAGE_LEN
- (u8
)addr
;
679 trans_dma_enable(DMA_FROM_DEVICE
, chip
, 256, DMA_256
);
681 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, ins
);
684 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR0
, 0xFF,
686 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF,
688 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR2
, 0xFF,
690 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF,
691 SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_24
);
693 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR1
, 0xFF,
695 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR2
, 0xFF,
697 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_ADDR3
, 0xFF,
699 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF,
700 SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_32
);
703 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH1
, 0xFF,
705 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH0
, 0xFF,
708 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
709 SPI_TRANSFER0_START
| SPI_CADI_MODE0
);
710 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
,
711 SPI_TRANSFER0_END
, SPI_TRANSFER0_END
);
713 rtsx_send_cmd_no_wait(chip
);
715 retval
= rtsx_transfer_data(chip
, 0, buf
, pagelen
, 0,
716 DMA_FROM_DEVICE
, 10000);
719 rtsx_clear_spi_error(chip
);
720 spi_set_err_code(chip
, SPI_HW_ERR
);
725 rtsx_stor_access_xfer_buf(buf
, pagelen
, srb
, &index
, &offset
,
732 scsi_set_resid(srb
, 0);
735 return STATUS_SUCCESS
;
738 int spi_write_flash(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
741 u8 ins
, program_mode
;
745 unsigned int index
= 0, offset
= 0;
747 spi_set_err_code(chip
, SPI_NO_ERR
);
750 addr
= ((u32
)(srb
->cmnd
[4]) << 16) | ((u32
)(srb
->cmnd
[5])
751 << 8) | srb
->cmnd
[6];
752 len
= ((u16
)(srb
->cmnd
[7]) << 8) | srb
->cmnd
[8];
753 program_mode
= srb
->cmnd
[9];
755 retval
= spi_set_init_para(chip
);
756 if (retval
!= STATUS_SUCCESS
) {
757 spi_set_err_code(chip
, SPI_HW_ERR
);
762 if (program_mode
== BYTE_PROGRAM
) {
763 buf
= kmalloc(4, GFP_KERNEL
);
770 retval
= sf_enable_write(chip
, SPI_WREN
);
771 if (retval
!= STATUS_SUCCESS
) {
777 rtsx_stor_access_xfer_buf(buf
, 1, srb
, &index
, &offset
,
782 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
,
783 0x01, PINGPONG_BUFFER
);
784 rtsx_add_cmd(chip
, WRITE_REG_CMD
, PPBUF_BASE2
, 0xFF,
786 sf_program(chip
, ins
, 1, addr
, 1);
788 retval
= rtsx_send_cmd(chip
, 0, 100);
791 rtsx_clear_spi_error(chip
);
792 spi_set_err_code(chip
, SPI_HW_ERR
);
797 retval
= sf_polling_status(chip
, 100);
798 if (retval
!= STATUS_SUCCESS
) {
810 } else if (program_mode
== AAI_PROGRAM
) {
813 retval
= sf_enable_write(chip
, SPI_WREN
);
814 if (retval
!= STATUS_SUCCESS
) {
819 buf
= kmalloc(4, GFP_KERNEL
);
826 rtsx_stor_access_xfer_buf(buf
, 1, srb
, &index
, &offset
,
831 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
,
832 0x01, PINGPONG_BUFFER
);
833 rtsx_add_cmd(chip
, WRITE_REG_CMD
, PPBUF_BASE2
, 0xFF,
836 sf_program(chip
, ins
, 1, addr
, 1);
839 sf_program(chip
, ins
, 0, 0, 1);
842 retval
= rtsx_send_cmd(chip
, 0, 100);
845 rtsx_clear_spi_error(chip
);
846 spi_set_err_code(chip
, SPI_HW_ERR
);
851 retval
= sf_polling_status(chip
, 100);
852 if (retval
!= STATUS_SUCCESS
) {
863 retval
= sf_disable_write(chip
, SPI_WRDI
);
864 if (retval
!= STATUS_SUCCESS
) {
869 retval
= sf_polling_status(chip
, 100);
870 if (retval
!= STATUS_SUCCESS
) {
874 } else if (program_mode
== PAGE_PROGRAM
) {
875 buf
= kmalloc(SF_PAGE_LEN
, GFP_KERNEL
);
882 u16 pagelen
= SF_PAGE_LEN
- (u8
)addr
;
887 retval
= sf_enable_write(chip
, SPI_WREN
);
888 if (retval
!= STATUS_SUCCESS
) {
896 trans_dma_enable(DMA_TO_DEVICE
, chip
, 256, DMA_256
);
897 sf_program(chip
, ins
, 1, addr
, pagelen
);
899 rtsx_send_cmd_no_wait(chip
);
901 rtsx_stor_access_xfer_buf(buf
, pagelen
, srb
, &index
,
902 &offset
, FROM_XFER_BUF
);
904 retval
= rtsx_transfer_data(chip
, 0, buf
, pagelen
, 0,
908 rtsx_clear_spi_error(chip
);
909 spi_set_err_code(chip
, SPI_HW_ERR
);
914 retval
= sf_polling_status(chip
, 100);
915 if (retval
!= STATUS_SUCCESS
) {
927 spi_set_err_code(chip
, SPI_INVALID_COMMAND
);
932 return STATUS_SUCCESS
;
935 int spi_erase_flash(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
941 spi_set_err_code(chip
, SPI_NO_ERR
);
944 addr
= ((u32
)(srb
->cmnd
[4]) << 16) | ((u32
)(srb
->cmnd
[5])
945 << 8) | srb
->cmnd
[6];
946 erase_mode
= srb
->cmnd
[9];
948 retval
= spi_set_init_para(chip
);
949 if (retval
!= STATUS_SUCCESS
) {
950 spi_set_err_code(chip
, SPI_HW_ERR
);
955 if (erase_mode
== PAGE_ERASE
) {
956 retval
= sf_enable_write(chip
, SPI_WREN
);
957 if (retval
!= STATUS_SUCCESS
) {
962 retval
= sf_erase(chip
, ins
, 1, addr
);
963 if (retval
!= STATUS_SUCCESS
) {
967 } else if (erase_mode
== CHIP_ERASE
) {
968 retval
= sf_enable_write(chip
, SPI_WREN
);
969 if (retval
!= STATUS_SUCCESS
) {
974 retval
= sf_erase(chip
, ins
, 0, 0);
975 if (retval
!= STATUS_SUCCESS
) {
980 spi_set_err_code(chip
, SPI_INVALID_COMMAND
);
985 return STATUS_SUCCESS
;
988 int spi_write_flash_status(struct scsi_cmnd
*srb
, struct rtsx_chip
*chip
)
991 u8 ins
, status
, ewsr
;
994 status
= srb
->cmnd
[4];
997 retval
= spi_set_init_para(chip
);
998 if (retval
!= STATUS_SUCCESS
) {
999 spi_set_err_code(chip
, SPI_HW_ERR
);
1004 retval
= sf_enable_write(chip
, ewsr
);
1005 if (retval
!= STATUS_SUCCESS
) {
1010 rtsx_init_cmd(chip
);
1012 rtsx_add_cmd(chip
, WRITE_REG_CMD
, CARD_DATA_SOURCE
, 0x01,
1015 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_COMMAND
, 0xFF, ins
);
1016 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_CA_NUMBER
, 0xFF,
1017 SPI_COMMAND_BIT_8
| SPI_ADDRESS_BIT_24
);
1018 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH1
, 0xFF, 0);
1019 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_LENGTH0
, 0xFF, 1);
1020 rtsx_add_cmd(chip
, WRITE_REG_CMD
, PPBUF_BASE2
, 0xFF, status
);
1021 rtsx_add_cmd(chip
, WRITE_REG_CMD
, SPI_TRANSFER0
, 0xFF,
1022 SPI_TRANSFER0_START
| SPI_CDO_MODE0
);
1023 rtsx_add_cmd(chip
, CHECK_REG_CMD
, SPI_TRANSFER0
, SPI_TRANSFER0_END
,
1026 retval
= rtsx_send_cmd(chip
, 0, 100);
1027 if (retval
!= STATUS_SUCCESS
) {
1028 rtsx_clear_spi_error(chip
);
1029 spi_set_err_code(chip
, SPI_HW_ERR
);
1034 return STATUS_SUCCESS
;