1 /******************************************************************************/
3 /* Bypass Control utility, Copyright (c) 2005-2011 Silicom */
5 /* This program is free software; you can redistribute it and/or modify */
6 /* it under the terms of the GNU General Public License as published by */
7 /* the Free Software Foundation, located in the file LICENSE. */
8 /* Copyright(c) 2007 - 2009, 2013 Intel Corporation. All rights reserved. */
11 /******************************************************************************/
13 #include <linux/kernel.h> /* We're doing kernel work */
14 #include <linux/module.h> /* Specifically, a module */
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/netdevice.h>
19 #include <linux/rtnetlink.h>
20 #include <linux/rcupdate.h>
21 #include <linux/etherdevice.h>
23 #include <linux/uaccess.h> /* for get_user and put_user */
24 #include <linux/sched.h>
25 #include <linux/ethtool.h>
26 #include <linux/proc_fs.h>
34 #define BP_MOD_VER "9.0.4"
35 #define BP_MOD_DESCR "Silicom Bypass-SD Control driver"
36 #define BP_SYNC_FLAG 1
40 MODULE_AUTHOR("Anna Lukin, annal@silicom.co.il");
41 MODULE_LICENSE("GPL");
42 MODULE_DESCRIPTION(BP_MOD_DESCR
);
43 MODULE_VERSION(BP_MOD_VER
);
46 #define unlock_bpctl() \
57 struct bypass_pfs_sd
{
59 struct proc_dir_entry
*bypass_entry
;
65 struct pci_dev
*pdev
; /* PCI device */
66 struct net_device
*ndev
; /* net device */
67 unsigned long mem_map
;
81 unsigned long bypass_wdt_on_time
;
82 uint32_t bypass_timer_interval
;
83 struct timer_list bp_timer
;
87 enum bp_media_type media_type
;
89 struct timer_list bp_tpl_timer
;
90 spinlock_t bypass_wr_lock
;
97 int (*hard_start_xmit_save
) (struct sk_buff
*skb
,
98 struct net_device
*dev
);
99 const struct net_device_ops
*old_ops
;
100 struct net_device_ops new_ops
;
101 int bp_self_test_flag
;
103 struct bypass_pfs_sd bypass_pfs_set
;
107 static struct bpctl_dev
*bpctl_dev_arr
;
109 static struct semaphore bpctl_sema
;
110 static int device_num
;
112 static int get_dev_idx(int ifindex
);
113 static struct bpctl_dev
*get_master_port_fn(struct bpctl_dev
*pbpctl_dev
);
114 static int disc_status(struct bpctl_dev
*pbpctl_dev
);
115 static int bypass_status(struct bpctl_dev
*pbpctl_dev
);
116 static int wdt_timer(struct bpctl_dev
*pbpctl_dev
, int *time_left
);
117 static struct bpctl_dev
*get_status_port_fn(struct bpctl_dev
*pbpctl_dev
);
118 static void if_scan_init(void);
120 int bypass_proc_create_dev_sd(struct bpctl_dev
*pbp_device_block
);
121 int bypass_proc_remove_dev_sd(struct bpctl_dev
*pbp_device_block
);
122 int bp_proc_create(void);
124 int is_bypass_fn(struct bpctl_dev
*pbpctl_dev
);
125 int get_dev_idx_bsf(int bus
, int slot
, int func
);
127 static int bp_get_dev_idx_bsf(struct net_device
*dev
, int *index
)
129 struct ethtool_drvinfo drvinfo
= {0};
133 if (dev
->ethtool_ops
&& dev
->ethtool_ops
->get_drvinfo
)
134 dev
->ethtool_ops
->get_drvinfo(dev
, &drvinfo
);
138 if (!strcmp(drvinfo
.bus_info
, "N/A"))
141 buf
= strchr(drvinfo
.bus_info
, ':');
145 if (sscanf(buf
, "%x:%x.%x", &bus
, &slot
, &func
) != 3)
148 *index
= get_dev_idx_bsf(bus
, slot
, func
);
152 static int bp_device_event(struct notifier_block
*unused
,
153 unsigned long event
, void *ptr
)
155 struct net_device
*dev
= netdev_notifier_info_to_dev(ptr
);
156 static struct bpctl_dev
*pbpctl_dev
, *pbpctl_dev_m
;
157 int dev_num
= 0, ret
= 0, ret_d
= 0, time_left
= 0;
159 /* printk("BP_PROC_SUPPORT event =%d %s %d\n", event,dev->name, dev->ifindex ); */
160 /* return NOTIFY_DONE; */
164 if (event
== NETDEV_REGISTER
) {
167 if (bp_get_dev_idx_bsf(dev
, &idx_dev
))
173 bpctl_dev_arr
[idx_dev
].ifindex
= dev
->ifindex
;
174 bpctl_dev_arr
[idx_dev
].ndev
= dev
;
176 bypass_proc_remove_dev_sd(&bpctl_dev_arr
[idx_dev
]);
177 bypass_proc_create_dev_sd(&bpctl_dev_arr
[idx_dev
]);
180 if (event
== NETDEV_UNREGISTER
) {
183 ((bpctl_dev_arr
[idx_dev
].pdev
!= NULL
)
184 && (idx_dev
< device_num
)); idx_dev
++) {
185 if (bpctl_dev_arr
[idx_dev
].ndev
== dev
) {
186 bypass_proc_remove_dev_sd(&bpctl_dev_arr
188 bpctl_dev_arr
[idx_dev
].ndev
= NULL
;
197 if (event
== NETDEV_CHANGENAME
) {
200 ((bpctl_dev_arr
[idx_dev
].pdev
!= NULL
)
201 && (idx_dev
< device_num
)); idx_dev
++) {
202 if (bpctl_dev_arr
[idx_dev
].ndev
== dev
) {
203 bypass_proc_remove_dev_sd(&bpctl_dev_arr
205 bypass_proc_create_dev_sd(&bpctl_dev_arr
220 if (netif_carrier_ok(dev
))
223 if (((dev_num
= get_dev_idx(dev
->ifindex
)) == -1) ||
224 (!(pbpctl_dev
= &bpctl_dev_arr
[dev_num
])))
227 if ((is_bypass_fn(pbpctl_dev
)) == 1)
228 pbpctl_dev_m
= pbpctl_dev
;
230 pbpctl_dev_m
= get_master_port_fn(pbpctl_dev
);
233 ret
= bypass_status(pbpctl_dev_m
);
235 printk("bpmod: %s is in the Bypass mode now",
237 ret_d
= disc_status(pbpctl_dev_m
);
240 ("bpmod: %s is in the Disconnect mode now",
243 wdt_timer(pbpctl_dev_m
, &time_left
);
245 printk("; WDT has expired");
261 static struct notifier_block bp_notifier_block
= {
262 .notifier_call
= bp_device_event
,
265 int is_bypass_fn(struct bpctl_dev
*pbpctl_dev
);
266 int wdt_time_left(struct bpctl_dev
*pbpctl_dev
);
268 static void write_pulse(struct bpctl_dev
*pbpctl_dev
,
269 unsigned int ctrl_ext
,
270 unsigned char value
, unsigned char len
)
272 unsigned char ctrl_val
= 0;
273 unsigned int i
= len
;
274 unsigned int ctrl
= 0;
275 struct bpctl_dev
*pbpctl_dev_c
= NULL
;
277 if (pbpctl_dev
->bp_i80
)
278 ctrl
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
279 if (pbpctl_dev
->bp_540
)
280 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
282 if (pbpctl_dev
->bp_10g9
) {
283 pbpctl_dev_c
= get_status_port_fn(pbpctl_dev
);
286 ctrl
= BP10G_READ_REG(pbpctl_dev_c
, ESDP
);
290 ctrl_val
= (value
>> i
) & 0x1;
292 if (pbpctl_dev
->bp_10g9
) {
294 /* To start management : MCLK 1, MDIO 1, output */
296 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
297 BP10G_WRITE_REG(pbpctl_dev
, I2CCTL
,
299 BP10G_MDIO_DATA_OUT9
);
300 BP10G_WRITE_REG(pbpctl_dev_c
, ESDP
,
301 (ctrl
| BP10G_MCLK_DATA_OUT9
|
302 BP10G_MCLK_DIR_OUT9
));
304 } else if (pbpctl_dev
->bp_fiber5
) {
305 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, (ctrl_ext
|
306 BPCTLI_CTRL_EXT_MCLK_DIR5
308 BPCTLI_CTRL_EXT_MDIO_DIR5
310 BPCTLI_CTRL_EXT_MDIO_DATA5
312 BPCTLI_CTRL_EXT_MCLK_DATA5
));
314 } else if (pbpctl_dev
->bp_i80
) {
315 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, (ctrl_ext
|
316 BPCTLI_CTRL_EXT_MDIO_DIR80
318 BPCTLI_CTRL_EXT_MDIO_DATA80
));
320 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, (ctrl
|
321 BPCTLI_CTRL_EXT_MCLK_DIR80
323 BPCTLI_CTRL_EXT_MCLK_DATA80
));
325 } else if (pbpctl_dev
->bp_540
) {
326 BP10G_WRITE_REG(pbpctl_dev
, ESDP
, (ctrl
|
335 } else if (pbpctl_dev
->bp_10gb
) {
336 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
,
337 (ctrl_ext
| BP10GB_MDIO_SET
|
344 } else if (!pbpctl_dev
->bp_10g
)
345 /* To start management : MCLK 1, MDIO 1, output */
346 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
348 BPCTLI_CTRL_EXT_MCLK_DIR
|
349 BPCTLI_CTRL_EXT_MDIO_DIR
|
350 BPCTLI_CTRL_EXT_MDIO_DATA
|
351 BPCTLI_CTRL_EXT_MCLK_DATA
));
354 /* To start management : MCLK 1, MDIO 1, output*/
355 BP10G_WRITE_REG(pbpctl_dev
, EODSDP
,
356 (ctrl_ext
| BP10G_MCLK_DATA_OUT
357 | BP10G_MDIO_DATA_OUT
));
361 usec_delay(PULSE_TIME
);
362 if (pbpctl_dev
->bp_10g9
) {
364 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~(BP10G_MCLK_DATA_OUT9))); */
366 BP10G_WRITE_REG(pbpctl_dev
, I2CCTL
,
368 BP10G_MDIO_DATA_OUT9
);
369 BP10G_WRITE_REG(pbpctl_dev_c
, ESDP
,
370 (ctrl
| BP10G_MCLK_DIR_OUT9
) &
371 ~BP10G_MCLK_DATA_OUT9
);
373 } else if (pbpctl_dev
->bp_fiber5
) {
374 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
376 BPCTLI_CTRL_EXT_MCLK_DIR5
|
377 BPCTLI_CTRL_EXT_MDIO_DIR5
|
378 BPCTLI_CTRL_EXT_MDIO_DATA5
)
381 (BPCTLI_CTRL_EXT_MCLK_DATA5
)));
383 } else if (pbpctl_dev
->bp_i80
) {
384 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, (ctrl_ext
|
385 BPCTLI_CTRL_EXT_MDIO_DIR80
387 BPCTLI_CTRL_EXT_MDIO_DATA80
));
388 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
390 BPCTLI_CTRL_EXT_MCLK_DIR80
)
393 (BPCTLI_CTRL_EXT_MCLK_DATA80
)));
395 } else if (pbpctl_dev
->bp_540
) {
396 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
397 (ctrl
| BP540_MDIO_DIR
|
402 } else if (pbpctl_dev
->bp_10gb
) {
404 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
,
405 (ctrl_ext
| BP10GB_MDIO_SET
|
412 } else if (!pbpctl_dev
->bp_10g
)
414 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
416 BPCTLI_CTRL_EXT_MCLK_DIR
|
417 BPCTLI_CTRL_EXT_MDIO_DIR
|
418 BPCTLI_CTRL_EXT_MDIO_DATA
)
421 (BPCTLI_CTRL_EXT_MCLK_DATA
)));
424 BP10G_WRITE_REG(pbpctl_dev
, EODSDP
,
426 BP10G_MDIO_DATA_OUT
) &
427 ~(BP10G_MCLK_DATA_OUT
)));
430 usec_delay(PULSE_TIME
);
433 if (pbpctl_dev
->bp_10g9
) {
435 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
436 BP10G_WRITE_REG(pbpctl_dev
, I2CCTL
,
438 ~BP10G_MDIO_DATA_OUT9
));
439 BP10G_WRITE_REG(pbpctl_dev_c
, ESDP
,
440 (ctrl
| BP10G_MCLK_DATA_OUT9
|
441 BP10G_MCLK_DIR_OUT9
));
443 } else if (pbpctl_dev
->bp_fiber5
) {
444 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
446 BPCTLI_CTRL_EXT_MCLK_DIR5
|
447 BPCTLI_CTRL_EXT_MDIO_DIR5
|
448 BPCTLI_CTRL_EXT_MCLK_DATA5
)
451 (BPCTLI_CTRL_EXT_MDIO_DATA5
)));
453 } else if (pbpctl_dev
->bp_i80
) {
454 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
456 BPCTLI_CTRL_EXT_MDIO_DIR80
)
459 (BPCTLI_CTRL_EXT_MDIO_DATA80
)));
460 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
462 BPCTLI_CTRL_EXT_MCLK_DIR80
|
463 BPCTLI_CTRL_EXT_MCLK_DATA80
));
465 } else if (pbpctl_dev
->bp_540
) {
466 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
467 ((ctrl
| BP540_MCLK_DIR
|
470 ~(BP540_MDIO_DATA
)));
472 } else if (pbpctl_dev
->bp_10gb
) {
473 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
,
474 (ctrl_ext
| BP10GB_MDIO_CLR
|
481 } else if (!pbpctl_dev
->bp_10g
)
483 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
485 BPCTLI_CTRL_EXT_MCLK_DIR
|
486 BPCTLI_CTRL_EXT_MDIO_DIR
|
487 BPCTLI_CTRL_EXT_MCLK_DATA
)
490 (BPCTLI_CTRL_EXT_MDIO_DATA
)));
493 BP10G_WRITE_REG(pbpctl_dev
, EODSDP
,
495 BP10G_MCLK_DATA_OUT
) &
496 ~BP10G_MDIO_DATA_OUT
));
499 usec_delay(PULSE_TIME
);
500 if (pbpctl_dev
->bp_10g9
) {
502 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
503 BP10G_WRITE_REG(pbpctl_dev
, I2CCTL
,
505 ~BP10G_MDIO_DATA_OUT9
));
506 BP10G_WRITE_REG(pbpctl_dev_c
, ESDP
,
507 ((ctrl
| BP10G_MCLK_DIR_OUT9
) &
508 ~(BP10G_MCLK_DATA_OUT9
)));
510 } else if (pbpctl_dev
->bp_fiber5
) {
511 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
513 BPCTLI_CTRL_EXT_MCLK_DIR5
|
514 BPCTLI_CTRL_EXT_MDIO_DIR5
)
516 ~(BPCTLI_CTRL_EXT_MCLK_DATA5
518 BPCTLI_CTRL_EXT_MDIO_DATA5
)));
520 } else if (pbpctl_dev
->bp_i80
) {
521 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
523 BPCTLI_CTRL_EXT_MDIO_DIR80
)
525 ~BPCTLI_CTRL_EXT_MDIO_DATA80
));
526 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
528 BPCTLI_CTRL_EXT_MCLK_DIR80
)
531 (BPCTLI_CTRL_EXT_MCLK_DATA80
)));
533 } else if (pbpctl_dev
->bp_540
) {
534 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
535 ((ctrl
| BP540_MCLK_DIR
|
539 } else if (pbpctl_dev
->bp_10gb
) {
541 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
,
542 (ctrl_ext
| BP10GB_MDIO_CLR
|
549 } else if (!pbpctl_dev
->bp_10g
)
550 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
552 BPCTLI_CTRL_EXT_MCLK_DIR
|
553 BPCTLI_CTRL_EXT_MDIO_DIR
) &
554 ~(BPCTLI_CTRL_EXT_MCLK_DATA
556 BPCTLI_CTRL_EXT_MDIO_DATA
)));
559 BP10G_WRITE_REG(pbpctl_dev
, EODSDP
,
561 ~(BP10G_MCLK_DATA_OUT
|
562 BP10G_MDIO_DATA_OUT
)));
565 usec_delay(PULSE_TIME
);
571 static int read_pulse(struct bpctl_dev
*pbpctl_dev
, unsigned int ctrl_ext
,
574 unsigned char ctrl_val
= 0;
575 unsigned int i
= len
;
576 unsigned int ctrl
= 0;
577 struct bpctl_dev
*pbpctl_dev_c
= NULL
;
579 if (pbpctl_dev
->bp_i80
)
580 ctrl
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
581 if (pbpctl_dev
->bp_540
)
582 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
583 if (pbpctl_dev
->bp_10g9
) {
584 pbpctl_dev_c
= get_status_port_fn(pbpctl_dev
);
587 ctrl
= BP10G_READ_REG(pbpctl_dev_c
, ESDP
);
592 if (pbpctl_dev
->bp_10g9
) {
593 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~BP10G_MCLK_DATA_OUT9)); */
595 BP10G_WRITE_REG(pbpctl_dev_c
, ESDP
,
596 ((ctrl
| BP10G_MCLK_DIR_OUT9
) &
597 ~(BP10G_MCLK_DATA_OUT9
)));
599 } else if (pbpctl_dev
->bp_fiber5
) {
600 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
601 BPCTLI_CTRL_EXT_MCLK_DIR5
)
604 (BPCTLI_CTRL_EXT_MDIO_DIR5
606 BPCTLI_CTRL_EXT_MCLK_DATA5
)));
608 } else if (pbpctl_dev
->bp_i80
) {
609 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
611 ~BPCTLI_CTRL_EXT_MDIO_DIR80
));
612 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
613 ((ctrl
| BPCTLI_CTRL_EXT_MCLK_DIR80
)
614 & ~(BPCTLI_CTRL_EXT_MCLK_DATA80
)));
616 } else if (pbpctl_dev
->bp_540
) {
617 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
618 ((ctrl
| BP540_MCLK_DIR
) &
619 ~(BP540_MDIO_DIR
| BP540_MCLK_DATA
)));
621 } else if (pbpctl_dev
->bp_10gb
) {
623 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
,
624 (ctrl_ext
| BP10GB_MDIO_DIR
|
625 BP10GB_MCLK_CLR
) & ~(BP10GB_MCLK_DIR
|
630 } else if (!pbpctl_dev
->bp_10g
)
631 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
632 BPCTLI_CTRL_EXT_MCLK_DIR
)
635 (BPCTLI_CTRL_EXT_MDIO_DIR
637 BPCTLI_CTRL_EXT_MCLK_DATA
)));
640 BP10G_WRITE_REG(pbpctl_dev
, EODSDP
, ((ctrl_ext
| BP10G_MDIO_DATA_OUT
) & ~BP10G_MCLK_DATA_OUT
)); /* ? */
641 /* printk("0x28=0x%x\n",BP10G_READ_REG(pbpctl_dev,EODSDP);); */
645 usec_delay(PULSE_TIME
);
646 if (pbpctl_dev
->bp_10g9
) {
647 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
649 BP10G_WRITE_REG(pbpctl_dev_c
, ESDP
,
650 (ctrl
| BP10G_MCLK_DATA_OUT9
|
651 BP10G_MCLK_DIR_OUT9
));
653 } else if (pbpctl_dev
->bp_fiber5
) {
654 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
655 BPCTLI_CTRL_EXT_MCLK_DIR5
657 BPCTLI_CTRL_EXT_MCLK_DATA5
)
660 (BPCTLI_CTRL_EXT_MDIO_DIR5
)));
662 } else if (pbpctl_dev
->bp_i80
) {
663 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
665 ~(BPCTLI_CTRL_EXT_MDIO_DIR80
)));
666 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
667 (ctrl
| BPCTLI_CTRL_EXT_MCLK_DIR80
|
668 BPCTLI_CTRL_EXT_MCLK_DATA80
));
670 } else if (pbpctl_dev
->bp_540
) {
671 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
672 ((ctrl
| BP540_MCLK_DIR
|
676 } else if (pbpctl_dev
->bp_10gb
) {
677 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
,
678 (ctrl_ext
| BP10GB_MDIO_DIR
|
679 BP10GB_MCLK_SET
) & ~(BP10GB_MCLK_DIR
|
684 } else if (!pbpctl_dev
->bp_10g
)
685 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
686 BPCTLI_CTRL_EXT_MCLK_DIR
688 BPCTLI_CTRL_EXT_MCLK_DATA
)
691 (BPCTLI_CTRL_EXT_MDIO_DIR
)));
694 BP10G_WRITE_REG(pbpctl_dev
, EODSDP
,
695 (ctrl_ext
| BP10G_MCLK_DATA_OUT
|
696 BP10G_MDIO_DATA_OUT
));
700 if (pbpctl_dev
->bp_10g9
)
701 ctrl_ext
= BP10G_READ_REG(pbpctl_dev
, I2CCTL
);
702 else if ((pbpctl_dev
->bp_fiber5
) || (pbpctl_dev
->bp_i80
))
703 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL
);
704 else if (pbpctl_dev
->bp_540
)
705 ctrl_ext
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
706 else if (pbpctl_dev
->bp_10gb
)
707 ctrl_ext
= BP10GB_READ_REG(pbpctl_dev
, MISC_REG_SPIO
);
708 else if (!pbpctl_dev
->bp_10g
)
709 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
711 ctrl_ext
= BP10G_READ_REG(pbpctl_dev
, EODSDP
);
713 usec_delay(PULSE_TIME
);
714 if (pbpctl_dev
->bp_10g9
) {
715 if (ctrl_ext
& BP10G_MDIO_DATA_IN9
)
718 } else if (pbpctl_dev
->bp_fiber5
) {
719 if (ctrl_ext
& BPCTLI_CTRL_EXT_MDIO_DATA5
)
721 } else if (pbpctl_dev
->bp_i80
) {
722 if (ctrl_ext
& BPCTLI_CTRL_EXT_MDIO_DATA80
)
724 } else if (pbpctl_dev
->bp_540
) {
725 if (ctrl_ext
& BP540_MDIO_DATA
)
727 } else if (pbpctl_dev
->bp_10gb
) {
728 if (ctrl_ext
& BP10GB_MDIO_DATA
)
731 } else if (!pbpctl_dev
->bp_10g
) {
733 if (ctrl_ext
& BPCTLI_CTRL_EXT_MDIO_DATA
)
737 if (ctrl_ext
& BP10G_MDIO_DATA_IN
)
746 static void write_reg(struct bpctl_dev
*pbpctl_dev
, unsigned char value
,
749 uint32_t ctrl_ext
= 0, ctrl
= 0;
750 struct bpctl_dev
*pbpctl_dev_c
= NULL
;
752 if (pbpctl_dev
->bp_10g9
) {
753 pbpctl_dev_c
= get_status_port_fn(pbpctl_dev
);
757 if ((pbpctl_dev
->wdt_status
== WDT_STATUS_EN
) &&
758 (pbpctl_dev
->bp_ext_ver
< PXG4BPFI_VER
))
759 wdt_time_left(pbpctl_dev
);
762 spin_lock_irqsave(&pbpctl_dev
->bypass_wr_lock
, flags
);
764 atomic_set(&pbpctl_dev
->wdt_busy
, 1);
766 if (pbpctl_dev
->bp_10g9
) {
768 ctrl_ext
= BP10G_READ_REG(pbpctl_dev
, I2CCTL
);
769 ctrl
= BP10G_READ_REG(pbpctl_dev_c
, ESDP
);
771 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
772 BP10G_WRITE_REG(pbpctl_dev
, I2CCTL
,
773 (ctrl_ext
& ~BP10G_MDIO_DATA_OUT9
));
774 BP10G_WRITE_REG(pbpctl_dev_c
, ESDP
,
775 ((ctrl
| BP10G_MCLK_DIR_OUT9
) &
776 ~(BP10G_MCLK_DATA_OUT9
)));
778 } else if (pbpctl_dev
->bp_fiber5
) {
779 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL
);
780 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
781 BPCTLI_CTRL_EXT_MCLK_DIR5
783 BPCTLI_CTRL_EXT_MDIO_DIR5
)
786 (BPCTLI_CTRL_EXT_MDIO_DATA5
788 BPCTLI_CTRL_EXT_MCLK_DATA5
)));
789 } else if (pbpctl_dev
->bp_i80
) {
790 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL
);
791 ctrl
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
792 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
793 BPCTLI_CTRL_EXT_MDIO_DIR80
)
795 ~BPCTLI_CTRL_EXT_MDIO_DATA80
));
796 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
797 ((ctrl
| BPCTLI_CTRL_EXT_MCLK_DIR80
) &
798 ~BPCTLI_CTRL_EXT_MCLK_DATA80
));
800 } else if (pbpctl_dev
->bp_540
) {
801 ctrl
= ctrl_ext
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
802 BP10G_WRITE_REG(pbpctl_dev
, ESDP
, ((ctrl
|
808 } else if (pbpctl_dev
->bp_10gb
) {
809 ctrl_ext
= BP10GB_READ_REG(pbpctl_dev
, MISC_REG_SPIO
);
811 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
,
812 (ctrl_ext
| BP10GB_MDIO_CLR
| BP10GB_MCLK_CLR
)
813 & ~(BP10GB_MCLK_DIR
| BP10GB_MDIO_DIR
|
814 BP10GB_MDIO_SET
| BP10GB_MCLK_SET
));
816 } else if (!pbpctl_dev
->bp_10g
) {
818 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
819 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
820 BPCTLI_CTRL_EXT_MCLK_DIR
822 BPCTLI_CTRL_EXT_MDIO_DIR
)
825 (BPCTLI_CTRL_EXT_MDIO_DATA
827 BPCTLI_CTRL_EXT_MCLK_DATA
)));
829 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
830 ctrl_ext
= BP10G_READ_REG(pbpctl_dev
, EODSDP
);
831 BP10G_WRITE_REG(pbpctl_dev
, EODSDP
,
833 ~(BP10G_MCLK_DATA_OUT
| BP10G_MDIO_DATA_OUT
)));
835 usec_delay(CMND_INTERVAL
);
838 write_pulse(pbpctl_dev
, ctrl_ext
, SYNC_CMD_VAL
, SYNC_CMD_LEN
);
840 write_pulse(pbpctl_dev
, ctrl_ext
, WR_CMD_VAL
, WR_CMD_LEN
);
841 write_pulse(pbpctl_dev
, ctrl_ext
, addr
, ADDR_CMD_LEN
);
844 write_pulse(pbpctl_dev
, ctrl_ext
, value
, WR_DATA_LEN
);
845 if (pbpctl_dev
->bp_10g9
) {
846 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
848 BP10G_WRITE_REG(pbpctl_dev
, I2CCTL
,
849 (ctrl_ext
& ~BP10G_MDIO_DATA_OUT9
));
850 BP10G_WRITE_REG(pbpctl_dev_c
, ESDP
,
851 ((ctrl
| BP10G_MCLK_DIR_OUT9
) &
852 ~(BP10G_MCLK_DATA_OUT9
)));
854 } else if (pbpctl_dev
->bp_fiber5
) {
855 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
856 BPCTLI_CTRL_EXT_MCLK_DIR5
858 BPCTLI_CTRL_EXT_MDIO_DIR5
)
861 (BPCTLI_CTRL_EXT_MDIO_DATA5
863 BPCTLI_CTRL_EXT_MCLK_DATA5
)));
864 } else if (pbpctl_dev
->bp_i80
) {
865 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
866 BPCTLI_CTRL_EXT_MDIO_DIR80
)
868 ~BPCTLI_CTRL_EXT_MDIO_DATA80
));
869 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
870 ((ctrl
| BPCTLI_CTRL_EXT_MCLK_DIR80
) &
871 ~BPCTLI_CTRL_EXT_MCLK_DATA80
));
872 } else if (pbpctl_dev
->bp_540
) {
873 BP10G_WRITE_REG(pbpctl_dev
, ESDP
, ((ctrl
|
878 } else if (pbpctl_dev
->bp_10gb
) {
879 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
,
880 (ctrl_ext
| BP10GB_MDIO_CLR
| BP10GB_MCLK_CLR
)
881 & ~(BP10GB_MCLK_DIR
| BP10GB_MDIO_DIR
|
882 BP10GB_MDIO_SET
| BP10GB_MCLK_SET
));
884 } else if (!pbpctl_dev
->bp_10g
)
886 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
887 BPCTLI_CTRL_EXT_MCLK_DIR
889 BPCTLI_CTRL_EXT_MDIO_DIR
)
892 (BPCTLI_CTRL_EXT_MDIO_DATA
894 BPCTLI_CTRL_EXT_MCLK_DATA
)));
896 BP10G_WRITE_REG(pbpctl_dev
, EODSDP
,
898 ~(BP10G_MCLK_DATA_OUT
| BP10G_MDIO_DATA_OUT
)));
902 usec_delay(CMND_INTERVAL
* 4);
904 if ((pbpctl_dev
->wdt_status
== WDT_STATUS_EN
) &&
905 (pbpctl_dev
->bp_ext_ver
< PXG4BPFI_VER
) && (addr
== CMND_REG_ADDR
))
906 pbpctl_dev
->bypass_wdt_on_time
= jiffies
;
908 spin_unlock_irqrestore(&pbpctl_dev
->bypass_wr_lock
, flags
);
910 atomic_set(&pbpctl_dev
->wdt_busy
, 0);
915 static void write_data(struct bpctl_dev
*pbpctl_dev
, unsigned char value
)
917 write_reg(pbpctl_dev
, value
, CMND_REG_ADDR
);
920 static int read_reg(struct bpctl_dev
*pbpctl_dev
, unsigned char addr
)
922 uint32_t ctrl_ext
= 0, ctrl
= 0, ctrl_value
= 0;
923 struct bpctl_dev
*pbpctl_dev_c
= NULL
;
927 spin_lock_irqsave(&pbpctl_dev
->bypass_wr_lock
, flags
);
929 atomic_set(&pbpctl_dev
->wdt_busy
, 1);
931 if (pbpctl_dev
->bp_10g9
) {
932 pbpctl_dev_c
= get_status_port_fn(pbpctl_dev
);
937 if (pbpctl_dev
->bp_10g9
) {
938 ctrl_ext
= BP10G_READ_REG(pbpctl_dev
, I2CCTL
);
939 ctrl
= BP10G_READ_REG(pbpctl_dev_c
, ESDP
);
941 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
943 BP10G_WRITE_REG(pbpctl_dev
, I2CCTL
,
944 (ctrl_ext
& ~BP10G_MDIO_DATA_OUT9
));
945 BP10G_WRITE_REG(pbpctl_dev_c
, ESDP
,
946 ((ctrl
| BP10G_MCLK_DIR_OUT9
) &
947 ~(BP10G_MCLK_DATA_OUT9
)));
949 } else if (pbpctl_dev
->bp_fiber5
) {
950 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL
);
952 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
953 BPCTLI_CTRL_EXT_MCLK_DIR5
955 BPCTLI_CTRL_EXT_MDIO_DIR5
)
958 (BPCTLI_CTRL_EXT_MDIO_DATA5
960 BPCTLI_CTRL_EXT_MCLK_DATA5
)));
961 } else if (pbpctl_dev
->bp_i80
) {
962 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL
);
963 ctrl
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
965 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
966 BPCTLI_CTRL_EXT_MDIO_DIR80
)
968 ~BPCTLI_CTRL_EXT_MDIO_DATA80
));
969 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
970 ((ctrl
| BPCTLI_CTRL_EXT_MCLK_DIR80
) &
971 ~BPCTLI_CTRL_EXT_MCLK_DATA80
));
972 } else if (pbpctl_dev
->bp_540
) {
973 ctrl_ext
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
974 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
976 BP10G_WRITE_REG(pbpctl_dev
, ESDP
, ((ctrl
| BP540_MCLK_DIR
|
980 } else if (pbpctl_dev
->bp_10gb
) {
981 ctrl_ext
= BP10GB_READ_REG(pbpctl_dev
, MISC_REG_SPIO
);
983 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
,
984 (ctrl_ext
| BP10GB_MDIO_CLR
| BP10GB_MCLK_CLR
)
985 & ~(BP10GB_MCLK_DIR
| BP10GB_MDIO_DIR
|
986 BP10GB_MDIO_SET
| BP10GB_MCLK_SET
));
989 /*BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, (ctrl_ext | BP10GB_MCLK_DIR | BP10GB_MDIO_DIR|
990 BP10GB_MCLK_CLR|BP10GB_MDIO_CLR));
991 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
992 printk("1reg=%x\n", ctrl_ext); */
994 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
, ((ctrl_ext
|
997 & ~(BP10GB_MCLK_CLR
| BP10GB_MDIO_SET
|
998 BP10GB_MCLK_DIR
| BP10GB_MDIO_DIR
));
1000 /* bnx2x_set_spio(pbpctl_dev, 5, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1001 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1002 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_INPUT_HI_Z); */
1004 ctrl_ext
= BP10GB_READ_REG(pbpctl_dev
, MISC_REG_SPIO
);
1006 printk("2reg=%x\n", ctrl_ext
);
1009 spin_unlock_irqrestore(&pbpctl_dev
->bypass_wr_lock
, flags
);
1011 atomic_set(&pbpctl_dev
->wdt_busy
, 0);
1018 } else if (!pbpctl_dev
->bp_10g
) {
1020 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
1022 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
1023 BPCTLI_CTRL_EXT_MCLK_DIR
1025 BPCTLI_CTRL_EXT_MDIO_DIR
)
1028 (BPCTLI_CTRL_EXT_MDIO_DATA
1030 BPCTLI_CTRL_EXT_MCLK_DATA
)));
1033 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
1034 ctrl_ext
= BP10G_READ_REG(pbpctl_dev
, EODSDP
);
1035 BP10G_WRITE_REG(pbpctl_dev
, EODSDP
,
1037 ~(BP10G_MCLK_DATA_OUT
| BP10G_MDIO_DATA_OUT
)));
1041 usec_delay(CMND_INTERVAL
);
1044 write_pulse(pbpctl_dev
, ctrl_ext
, SYNC_CMD_VAL
, SYNC_CMD_LEN
);
1046 write_pulse(pbpctl_dev
, ctrl_ext
, RD_CMD_VAL
, RD_CMD_LEN
);
1048 write_pulse(pbpctl_dev
, ctrl_ext
, addr
, ADDR_CMD_LEN
);
1051 if (pbpctl_dev
->bp_10g9
) {
1053 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
1054 BP10G_WRITE_REG(pbpctl_dev
, I2CCTL
,
1055 (ctrl_ext
| BP10G_MDIO_DATA_OUT9
));
1056 BP10G_WRITE_REG(pbpctl_dev_c
, ESDP
,
1057 (ctrl
| BP10G_MCLK_DATA_OUT9
|
1058 BP10G_MCLK_DIR_OUT9
));
1060 } else if (pbpctl_dev
->bp_fiber5
) {
1061 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
1062 BPCTLI_CTRL_EXT_MCLK_DIR5
1064 BPCTLI_CTRL_EXT_MCLK_DATA5
)
1067 (BPCTLI_CTRL_EXT_MDIO_DIR5
1069 BPCTLI_CTRL_EXT_MDIO_DATA5
)));
1071 } else if (pbpctl_dev
->bp_i80
) {
1072 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
1074 ~(BPCTLI_CTRL_EXT_MDIO_DATA80
|
1075 BPCTLI_CTRL_EXT_MDIO_DIR80
)));
1076 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
1077 (ctrl
| BPCTLI_CTRL_EXT_MCLK_DIR80
|
1078 BPCTLI_CTRL_EXT_MCLK_DATA80
));
1080 } else if (pbpctl_dev
->bp_540
) {
1081 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
1082 (((ctrl
| BP540_MDIO_DIR
| BP540_MCLK_DIR
|
1083 BP540_MCLK_DATA
) & ~BP540_MDIO_DATA
)));
1085 } else if (pbpctl_dev
->bp_10gb
) {
1087 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
,
1088 (ctrl_ext
| BP10GB_MDIO_DIR
| BP10GB_MCLK_SET
)
1089 & ~(BP10GB_MCLK_DIR
| BP10GB_MDIO_SET
|
1090 BP10GB_MDIO_CLR
| BP10GB_MCLK_CLR
));
1092 } else if (!pbpctl_dev
->bp_10g
)
1093 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
1094 BPCTLI_CTRL_EXT_MCLK_DIR
1096 BPCTLI_CTRL_EXT_MCLK_DATA
)
1099 (BPCTLI_CTRL_EXT_MDIO_DIR
1101 BPCTLI_CTRL_EXT_MDIO_DATA
)));
1104 BP10G_WRITE_REG(pbpctl_dev
, EODSDP
,
1105 (ctrl_ext
| BP10G_MCLK_DATA_OUT
|
1106 BP10G_MDIO_DATA_OUT
));
1110 usec_delay(PULSE_TIME
);
1112 ctrl_value
= read_pulse(pbpctl_dev
, ctrl_ext
, RD_DATA_LEN
);
1114 if (pbpctl_dev
->bp_10g9
) {
1115 ctrl_ext
= BP10G_READ_REG(pbpctl_dev
, I2CCTL
);
1116 ctrl
= BP10G_READ_REG(pbpctl_dev_c
, ESDP
);
1118 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1120 BP10G_WRITE_REG(pbpctl_dev
, I2CCTL
,
1121 (ctrl_ext
& ~BP10G_MDIO_DATA_OUT9
));
1122 BP10G_WRITE_REG(pbpctl_dev_c
, ESDP
,
1123 ((ctrl
| BP10G_MCLK_DIR_OUT9
) &
1124 ~(BP10G_MCLK_DATA_OUT9
)));
1126 } else if (pbpctl_dev
->bp_fiber5
) {
1127 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
1128 BPCTLI_CTRL_EXT_MCLK_DIR5
1130 BPCTLI_CTRL_EXT_MDIO_DIR5
)
1133 (BPCTLI_CTRL_EXT_MDIO_DATA5
1135 BPCTLI_CTRL_EXT_MCLK_DATA5
)));
1136 } else if (pbpctl_dev
->bp_i80
) {
1137 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
1138 BPCTLI_CTRL_EXT_MDIO_DIR80
)
1140 ~BPCTLI_CTRL_EXT_MDIO_DATA80
));
1141 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
1142 ((ctrl
| BPCTLI_CTRL_EXT_MCLK_DIR80
) &
1143 ~BPCTLI_CTRL_EXT_MCLK_DATA80
));
1145 } else if (pbpctl_dev
->bp_540
) {
1146 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
1147 BP10G_WRITE_REG(pbpctl_dev
, ESDP
, ((ctrl
| BP540_MCLK_DIR
|
1152 } else if (pbpctl_dev
->bp_10gb
) {
1153 ctrl_ext
= BP10GB_READ_REG(pbpctl_dev
, MISC_REG_SPIO
);
1154 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
,
1155 (ctrl_ext
| BP10GB_MDIO_CLR
| BP10GB_MCLK_CLR
)
1156 & ~(BP10GB_MCLK_DIR
| BP10GB_MDIO_DIR
|
1157 BP10GB_MDIO_SET
| BP10GB_MCLK_SET
));
1159 } else if (!pbpctl_dev
->bp_10g
) {
1160 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
1161 BPCTLI_CTRL_EXT_MCLK_DIR
1163 BPCTLI_CTRL_EXT_MDIO_DIR
)
1166 (BPCTLI_CTRL_EXT_MDIO_DATA
1168 BPCTLI_CTRL_EXT_MCLK_DATA
)));
1171 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
1172 ctrl_ext
= BP10G_READ_REG(pbpctl_dev
, EODSDP
);
1173 BP10G_WRITE_REG(pbpctl_dev
, EODSDP
,
1175 ~(BP10G_MCLK_DATA_OUT
| BP10G_MDIO_DATA_OUT
)));
1179 usec_delay(CMND_INTERVAL
* 4);
1181 spin_unlock_irqrestore(&pbpctl_dev
->bypass_wr_lock
, flags
);
1183 atomic_set(&pbpctl_dev
->wdt_busy
, 0);
1189 static int wdt_pulse(struct bpctl_dev
*pbpctl_dev
)
1191 uint32_t ctrl_ext
= 0, ctrl
= 0;
1192 struct bpctl_dev
*pbpctl_dev_c
= NULL
;
1195 unsigned long flags
;
1197 spin_lock_irqsave(&pbpctl_dev
->bypass_wr_lock
, flags
);
1200 if ((atomic_read(&pbpctl_dev
->wdt_busy
)) == 1)
1203 if (pbpctl_dev
->bp_10g9
) {
1204 pbpctl_dev_c
= get_status_port_fn(pbpctl_dev
);
1209 if (pbpctl_dev
->bp_10g9
) {
1210 ctrl_ext
= BP10G_READ_REG(pbpctl_dev
, I2CCTL
);
1211 ctrl
= BP10G_READ_REG(pbpctl_dev_c
, ESDP
);
1213 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1215 BP10G_WRITE_REG(pbpctl_dev
, I2CCTL
,
1216 (ctrl_ext
& ~BP10G_MDIO_DATA_OUT9
));
1217 BP10G_WRITE_REG(pbpctl_dev_c
, ESDP
,
1218 ((ctrl
| BP10G_MCLK_DIR_OUT9
) &
1219 ~(BP10G_MCLK_DATA_OUT9
)));
1221 } else if (pbpctl_dev
->bp_fiber5
) {
1222 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL
);
1223 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
1224 BPCTLI_CTRL_EXT_MCLK_DIR5
1226 BPCTLI_CTRL_EXT_MDIO_DIR5
)
1229 (BPCTLI_CTRL_EXT_MDIO_DATA5
1231 BPCTLI_CTRL_EXT_MCLK_DATA5
)));
1232 } else if (pbpctl_dev
->bp_i80
) {
1233 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL
);
1234 ctrl
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
1235 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
1236 BPCTLI_CTRL_EXT_MDIO_DIR80
)
1238 ~BPCTLI_CTRL_EXT_MDIO_DATA80
));
1239 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
1240 ((ctrl
| BPCTLI_CTRL_EXT_MCLK_DIR80
) &
1241 ~BPCTLI_CTRL_EXT_MCLK_DATA80
));
1242 } else if (pbpctl_dev
->bp_540
) {
1243 ctrl_ext
= ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
1244 BP10G_WRITE_REG(pbpctl_dev
, ESDP
, ((ctrl
| BP540_MCLK_DIR
|
1248 } else if (pbpctl_dev
->bp_10gb
) {
1249 ctrl_ext
= BP10GB_READ_REG(pbpctl_dev
, MISC_REG_SPIO
);
1250 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
,
1251 (ctrl_ext
| BP10GB_MDIO_CLR
| BP10GB_MCLK_CLR
)
1252 & ~(BP10GB_MCLK_DIR
| BP10GB_MDIO_DIR
|
1253 BP10GB_MDIO_SET
| BP10GB_MCLK_SET
));
1255 } else if (!pbpctl_dev
->bp_10g
) {
1257 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
1258 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
1259 BPCTLI_CTRL_EXT_MCLK_DIR
1261 BPCTLI_CTRL_EXT_MDIO_DIR
)
1264 (BPCTLI_CTRL_EXT_MDIO_DATA
1266 BPCTLI_CTRL_EXT_MCLK_DATA
)));
1269 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
1270 ctrl_ext
= BP10G_READ_REG(pbpctl_dev
, EODSDP
);
1271 BP10G_WRITE_REG(pbpctl_dev
, EODSDP
,
1273 ~(BP10G_MCLK_DATA_OUT
| BP10G_MDIO_DATA_OUT
)));
1276 if (pbpctl_dev
->bp_10g9
) {
1277 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
1279 BP10G_WRITE_REG(pbpctl_dev
, I2CCTL
,
1280 (ctrl_ext
& ~BP10G_MDIO_DATA_OUT9
));
1281 BP10G_WRITE_REG(pbpctl_dev_c
, ESDP
,
1282 (ctrl
| BP10G_MCLK_DATA_OUT9
|
1283 BP10G_MCLK_DIR_OUT9
));
1285 } else if (pbpctl_dev
->bp_fiber5
) {
1286 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
1287 BPCTLI_CTRL_EXT_MCLK_DIR5
1289 BPCTLI_CTRL_EXT_MDIO_DIR5
1291 BPCTLI_CTRL_EXT_MCLK_DATA5
)
1294 (BPCTLI_CTRL_EXT_MDIO_DATA5
)));
1295 } else if (pbpctl_dev
->bp_i80
) {
1296 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
1297 BPCTLI_CTRL_EXT_MDIO_DIR80
)
1299 ~BPCTLI_CTRL_EXT_MDIO_DATA80
));
1300 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
1301 (ctrl
| BPCTLI_CTRL_EXT_MCLK_DIR80
|
1302 BPCTLI_CTRL_EXT_MCLK_DATA80
));
1304 } else if (pbpctl_dev
->bp_540
) {
1305 BP10G_WRITE_REG(pbpctl_dev
, ESDP
, ((ctrl
|
1311 } else if (pbpctl_dev
->bp_10gb
) {
1312 ctrl_ext
= BP10GB_READ_REG(pbpctl_dev
, MISC_REG_SPIO
);
1314 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
,
1315 (ctrl_ext
| BP10GB_MDIO_CLR
| BP10GB_MCLK_SET
)
1316 & ~(BP10GB_MCLK_DIR
| BP10GB_MDIO_DIR
|
1317 BP10GB_MDIO_SET
| BP10GB_MCLK_CLR
));
1319 } else if (!pbpctl_dev
->bp_10g
)
1320 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
1321 BPCTLI_CTRL_EXT_MCLK_DIR
1323 BPCTLI_CTRL_EXT_MDIO_DIR
1325 BPCTLI_CTRL_EXT_MCLK_DATA
)
1328 (BPCTLI_CTRL_EXT_MDIO_DATA
)));
1331 BP10G_WRITE_REG(pbpctl_dev
, EODSDP
,
1332 ((ctrl_ext
| BP10G_MCLK_DATA_OUT
) &
1333 ~BP10G_MDIO_DATA_OUT
));
1337 usec_delay(WDT_INTERVAL
);
1338 if (pbpctl_dev
->bp_10g9
) {
1339 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1341 BP10G_WRITE_REG(pbpctl_dev
, I2CCTL
,
1342 (ctrl_ext
& ~BP10G_MDIO_DATA_OUT9
));
1343 BP10G_WRITE_REG(pbpctl_dev_c
, ESDP
,
1344 ((ctrl
| BP10G_MCLK_DIR_OUT9
) &
1345 ~(BP10G_MCLK_DATA_OUT9
)));
1347 } else if (pbpctl_dev
->bp_fiber5
) {
1348 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
1349 BPCTLI_CTRL_EXT_MCLK_DIR5
1351 BPCTLI_CTRL_EXT_MDIO_DIR5
)
1354 (BPCTLI_CTRL_EXT_MCLK_DATA5
1356 BPCTLI_CTRL_EXT_MDIO_DATA5
)));
1357 } else if (pbpctl_dev
->bp_i80
) {
1358 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, ((ctrl_ext
|
1359 BPCTLI_CTRL_EXT_MDIO_DIR80
)
1361 ~BPCTLI_CTRL_EXT_MDIO_DATA80
));
1362 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
1363 ((ctrl
| BPCTLI_CTRL_EXT_MCLK_DIR80
) &
1364 ~BPCTLI_CTRL_EXT_MCLK_DATA80
));
1366 } else if (pbpctl_dev
->bp_540
) {
1367 BP10G_WRITE_REG(pbpctl_dev
, ESDP
, ((ctrl
| BP540_MCLK_DIR
|
1372 } else if (pbpctl_dev
->bp_10gb
) {
1373 ctrl_ext
= BP10GB_READ_REG(pbpctl_dev
, MISC_REG_SPIO
);
1374 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_SPIO
,
1375 (ctrl_ext
| BP10GB_MDIO_CLR
| BP10GB_MCLK_CLR
)
1376 & ~(BP10GB_MCLK_DIR
| BP10GB_MDIO_DIR
|
1377 BP10GB_MDIO_SET
| BP10GB_MCLK_SET
));
1379 } else if (!pbpctl_dev
->bp_10g
)
1380 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
1381 BPCTLI_CTRL_EXT_MCLK_DIR
1383 BPCTLI_CTRL_EXT_MDIO_DIR
)
1386 (BPCTLI_CTRL_EXT_MCLK_DATA
1388 BPCTLI_CTRL_EXT_MDIO_DATA
)));
1391 BP10G_WRITE_REG(pbpctl_dev
, EODSDP
,
1393 ~(BP10G_MCLK_DATA_OUT
| BP10G_MDIO_DATA_OUT
)));
1395 if ((pbpctl_dev
->wdt_status
== WDT_STATUS_EN
))
1396 /*&& (pbpctl_dev->bp_ext_ver<PXG4BPFI_VER) */
1397 pbpctl_dev
->bypass_wdt_on_time
= jiffies
;
1399 spin_unlock_irqrestore(&pbpctl_dev
->bypass_wr_lock
, flags
);
1401 usec_delay(CMND_INTERVAL
* 4);
1405 static void data_pulse(struct bpctl_dev
*pbpctl_dev
, unsigned char value
)
1408 uint32_t ctrl_ext
= 0;
1410 unsigned long flags
;
1412 wdt_time_left(pbpctl_dev
);
1414 spin_lock_irqsave(&pbpctl_dev
->bypass_wr_lock
, flags
);
1416 atomic_set(&pbpctl_dev
->wdt_busy
, 1);
1419 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
1420 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
1421 BPCTLI_CTRL_EXT_SDP6_DIR
|
1422 BPCTLI_CTRL_EXT_SDP7_DIR
) &
1423 ~(BPCTLI_CTRL_EXT_SDP6_DATA
|
1424 BPCTLI_CTRL_EXT_SDP7_DATA
)));
1426 usec_delay(INIT_CMND_INTERVAL
);
1427 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
1428 BPCTLI_CTRL_EXT_SDP6_DIR
|
1429 BPCTLI_CTRL_EXT_SDP7_DIR
|
1430 BPCTLI_CTRL_EXT_SDP6_DATA
) &
1432 (BPCTLI_CTRL_EXT_SDP7_DATA
)));
1433 usec_delay(INIT_CMND_INTERVAL
);
1436 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ctrl_ext
|
1437 BPCTLI_CTRL_EXT_SDP6_DIR
|
1438 BPCTLI_CTRL_EXT_SDP7_DIR
|
1439 BPCTLI_CTRL_EXT_SDP6_DATA
|
1440 BPCTLI_CTRL_EXT_SDP7_DATA
);
1441 usec_delay(PULSE_INTERVAL
);
1442 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
1443 BPCTLI_CTRL_EXT_SDP6_DIR
1445 BPCTLI_CTRL_EXT_SDP7_DIR
1447 BPCTLI_CTRL_EXT_SDP6_DATA
)
1449 ~BPCTLI_CTRL_EXT_SDP7_DATA
));
1450 usec_delay(PULSE_INTERVAL
);
1454 usec_delay(INIT_CMND_INTERVAL
- PULSE_INTERVAL
);
1455 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
1456 BPCTLI_CTRL_EXT_SDP6_DIR
|
1457 BPCTLI_CTRL_EXT_SDP7_DIR
) &
1458 ~(BPCTLI_CTRL_EXT_SDP6_DATA
|
1459 BPCTLI_CTRL_EXT_SDP7_DATA
)));
1460 usec_delay(WDT_TIME_CNT
);
1461 if (pbpctl_dev
->wdt_status
== WDT_STATUS_EN
)
1462 pbpctl_dev
->bypass_wdt_on_time
= jiffies
;
1464 spin_unlock_irqrestore(&pbpctl_dev
->bypass_wr_lock
, flags
);
1466 atomic_set(&pbpctl_dev
->wdt_busy
, 0);
1471 static int send_wdt_pulse(struct bpctl_dev
*pbpctl_dev
)
1473 uint32_t ctrl_ext
= 0;
1476 unsigned long flags
;
1478 spin_lock_irqsave(&pbpctl_dev
->bypass_wr_lock
, flags
);
1481 if ((atomic_read(&pbpctl_dev
->wdt_busy
)) == 1)
1484 wdt_time_left(pbpctl_dev
);
1485 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
1487 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ctrl_ext
| /* 1 */
1488 BPCTLI_CTRL_EXT_SDP7_DIR
|
1489 BPCTLI_CTRL_EXT_SDP7_DATA
);
1490 usec_delay(PULSE_INTERVAL
);
1491 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
| /* 0 */
1492 BPCTLI_CTRL_EXT_SDP7_DIR
) &
1493 ~BPCTLI_CTRL_EXT_SDP7_DATA
));
1495 usec_delay(PULSE_INTERVAL
);
1496 if (pbpctl_dev
->wdt_status
== WDT_STATUS_EN
)
1497 pbpctl_dev
->bypass_wdt_on_time
= jiffies
;
1499 spin_unlock_irqrestore(&pbpctl_dev
->bypass_wr_lock
, flags
);
1505 void send_bypass_clear_pulse(struct bpctl_dev
*pbpctl_dev
, unsigned int value
)
1507 uint32_t ctrl_ext
= 0;
1509 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
1510 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
| /* 0 */
1511 BPCTLI_CTRL_EXT_SDP6_DIR
) &
1512 ~BPCTLI_CTRL_EXT_SDP6_DATA
));
1514 usec_delay(PULSE_INTERVAL
);
1516 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ctrl_ext
| /* 1 */
1517 BPCTLI_CTRL_EXT_SDP6_DIR
|
1518 BPCTLI_CTRL_EXT_SDP6_DATA
);
1519 usec_delay(PULSE_INTERVAL
);
1522 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
| /* 0 */
1523 BPCTLI_CTRL_EXT_SDP6_DIR
) &
1524 ~BPCTLI_CTRL_EXT_SDP6_DATA
));
1525 usec_delay(PULSE_INTERVAL
);
1531 int pulse_set_fn(struct bpctl_dev
*pbpctl_dev
, unsigned int counter
)
1533 uint32_t ctrl_ext
= 0;
1538 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
1539 write_pulse_1(pbpctl_dev
, ctrl_ext
, counter
, counter
);
1541 pbpctl_dev
->bypass_wdt_status
= 0;
1542 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
1543 write_pulse_1(pbpctl_dev
, ctrl_ext
, counter
, counter
);
1545 wdt_time_left(pbpctl_dev
);
1546 if (pbpctl_dev
->wdt_status
== WDT_STATUS_EN
) {
1547 pbpctl_dev
->wdt_status
= 0;
1548 data_pulse(pbpctl_dev
, counter
);
1549 pbpctl_dev
->wdt_status
= WDT_STATUS_EN
;
1550 pbpctl_dev
->bypass_wdt_on_time
= jiffies
;
1553 data_pulse(pbpctl_dev
, counter
);
1559 int zero_set_fn(struct bpctl_dev
*pbpctl_dev
)
1561 uint32_t ctrl_ext
= 0, ctrl_value
= 0;
1565 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
1568 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
1570 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
1571 BPCTLI_CTRL_EXT_MCLK_DIR
)
1574 (BPCTLI_CTRL_EXT_MCLK_DATA
1576 BPCTLI_CTRL_EXT_MDIO_DIR
1578 BPCTLI_CTRL_EXT_MDIO_DATA
)));
1584 int pulse_get2_fn(struct bpctl_dev
*pbpctl_dev
)
1586 uint32_t ctrl_ext
= 0, ctrl_value
= 0;
1590 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
1591 printk("pulse_get_fn\n");
1592 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
1593 ctrl_value
= read_pulse_2(pbpctl_dev
, ctrl_ext
);
1594 printk("read:%d\n", ctrl_value
);
1599 int pulse_get1_fn(struct bpctl_dev
*pbpctl_dev
)
1601 uint32_t ctrl_ext
= 0, ctrl_value
= 0;
1605 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
1607 printk("pulse_get_fn\n");
1609 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
1610 ctrl_value
= read_pulse_1(pbpctl_dev
, ctrl_ext
);
1611 printk("read:%d\n", ctrl_value
);
1616 int gpio6_set_fn(struct bpctl_dev
*pbpctl_dev
)
1618 uint32_t ctrl_ext
= 0;
1620 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
1621 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ctrl_ext
|
1622 BPCTLI_CTRL_EXT_SDP6_DIR
|
1623 BPCTLI_CTRL_EXT_SDP6_DATA
);
1627 int gpio7_set_fn(struct bpctl_dev
*pbpctl_dev
)
1629 uint32_t ctrl_ext
= 0;
1631 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
1632 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ctrl_ext
|
1633 BPCTLI_CTRL_EXT_SDP7_DIR
|
1634 BPCTLI_CTRL_EXT_SDP7_DATA
);
1638 int gpio7_clear_fn(struct bpctl_dev
*pbpctl_dev
)
1640 uint32_t ctrl_ext
= 0;
1642 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
1643 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
1644 BPCTLI_CTRL_EXT_SDP7_DIR
) &
1645 ~BPCTLI_CTRL_EXT_SDP7_DATA
));
1649 int gpio6_clear_fn(struct bpctl_dev
*pbpctl_dev
)
1651 uint32_t ctrl_ext
= 0;
1653 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
1654 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, ((ctrl_ext
|
1655 BPCTLI_CTRL_EXT_SDP6_DIR
) &
1656 ~BPCTLI_CTRL_EXT_SDP6_DATA
));
1659 #endif /*BYPASS_DEBUG */
1661 static struct bpctl_dev
*lookup_port(struct bpctl_dev
*dev
)
1663 struct bpctl_dev
*p
;
1665 for (n
= 0, p
= bpctl_dev_arr
; n
< device_num
&& p
->pdev
; n
++) {
1666 if (p
->bus
== dev
->bus
1667 && p
->slot
== dev
->slot
1668 && p
->func
== (dev
->func
^ 1))
1674 static struct bpctl_dev
*get_status_port_fn(struct bpctl_dev
*pbpctl_dev
)
1677 if (pbpctl_dev
->func
== 0 || pbpctl_dev
->func
== 2)
1678 return lookup_port(pbpctl_dev
);
1683 static struct bpctl_dev
*get_master_port_fn(struct bpctl_dev
*pbpctl_dev
)
1686 if (pbpctl_dev
->func
== 1 || pbpctl_dev
->func
== 3)
1687 return lookup_port(pbpctl_dev
);
1692 /**************************************/
1693 /**************INTEL API***************/
1694 /**************************************/
1696 static void write_data_port_int(struct bpctl_dev
*pbpctl_dev
,
1697 unsigned char ctrl_value
)
1701 value
= BPCTL_READ_REG(pbpctl_dev
, CTRL
);
1702 /* Make SDP0 Pin Directonality to Output */
1703 value
|= BPCTLI_CTRL_SDP0_DIR
;
1704 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, value
);
1706 value
&= ~BPCTLI_CTRL_SDP0_DATA
;
1707 value
|= ((ctrl_value
& 0x1) << BPCTLI_CTRL_SDP0_SHIFT
);
1708 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
, value
);
1710 value
= (BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
));
1711 /* Make SDP2 Pin Directonality to Output */
1712 value
|= BPCTLI_CTRL_EXT_SDP6_DIR
;
1713 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, value
);
1715 value
&= ~BPCTLI_CTRL_EXT_SDP6_DATA
;
1716 value
|= (((ctrl_value
& 0x2) >> 1) << BPCTLI_CTRL_EXT_SDP6_SHIFT
);
1717 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
, value
);
1721 static int write_data_int(struct bpctl_dev
*pbpctl_dev
, unsigned char value
)
1723 struct bpctl_dev
*pbpctl_dev_b
= NULL
;
1725 pbpctl_dev_b
= get_status_port_fn(pbpctl_dev
);
1728 atomic_set(&pbpctl_dev
->wdt_busy
, 1);
1729 write_data_port_int(pbpctl_dev
, value
& 0x3);
1730 write_data_port_int(pbpctl_dev_b
, ((value
& 0xc) >> 2));
1731 atomic_set(&pbpctl_dev
->wdt_busy
, 0);
1736 static int wdt_pulse_int(struct bpctl_dev
*pbpctl_dev
)
1739 if ((atomic_read(&pbpctl_dev
->wdt_busy
)) == 1)
1742 if ((write_data_int(pbpctl_dev
, RESET_WDT_INT
)) < 0)
1744 msec_delay_bp(CMND_INTERVAL_INT
);
1745 if ((write_data_int(pbpctl_dev
, CMND_OFF_INT
)) < 0)
1747 msec_delay_bp(CMND_INTERVAL_INT
);
1749 if (pbpctl_dev
->wdt_status
== WDT_STATUS_EN
)
1750 pbpctl_dev
->bypass_wdt_on_time
= jiffies
;
1755 /*************************************/
1756 /************* COMMANDS **************/
1757 /*************************************/
1759 /* CMND_ON 0x4 (100)*/
1760 int cmnd_on(struct bpctl_dev
*pbpctl_dev
)
1762 int ret
= BP_NOT_CAP
;
1764 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
1765 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
))
1767 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
)
1768 write_data(pbpctl_dev
, CMND_ON
);
1770 data_pulse(pbpctl_dev
, CMND_ON
);
1776 /* CMND_OFF 0x2 (10)*/
1777 int cmnd_off(struct bpctl_dev
*pbpctl_dev
)
1779 int ret
= BP_NOT_CAP
;
1781 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
1782 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
)) {
1783 write_data_int(pbpctl_dev
, CMND_OFF_INT
);
1784 msec_delay_bp(CMND_INTERVAL_INT
);
1785 } else if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
)
1786 write_data(pbpctl_dev
, CMND_OFF
);
1788 data_pulse(pbpctl_dev
, CMND_OFF
);
1794 /* BYPASS_ON (0xa)*/
1795 int bypass_on(struct bpctl_dev
*pbpctl_dev
)
1797 int ret
= BP_NOT_CAP
;
1799 if (pbpctl_dev
->bp_caps
& BP_CAP
) {
1800 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
)) {
1801 write_data_int(pbpctl_dev
, BYPASS_ON_INT
);
1802 msec_delay_bp(BYPASS_DELAY_INT
);
1803 pbpctl_dev
->bp_status_un
= 0;
1804 } else if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
1805 write_data(pbpctl_dev
, BYPASS_ON
);
1806 if (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
)
1807 msec_delay_bp(LATCH_DELAY
);
1809 data_pulse(pbpctl_dev
, BYPASS_ON
);
1815 /* BYPASS_OFF (0x8 111)*/
1816 int bypass_off(struct bpctl_dev
*pbpctl_dev
)
1818 int ret
= BP_NOT_CAP
;
1820 if (pbpctl_dev
->bp_caps
& BP_CAP
) {
1821 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
)) {
1822 write_data_int(pbpctl_dev
, DIS_BYPASS_CAP_INT
);
1823 msec_delay_bp(BYPASS_DELAY_INT
);
1824 write_data_int(pbpctl_dev
, PWROFF_BYPASS_ON_INT
);
1825 msec_delay_bp(BYPASS_DELAY_INT
);
1826 pbpctl_dev
->bp_status_un
= 0;
1827 } else if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
1828 write_data(pbpctl_dev
, BYPASS_OFF
);
1829 if (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
)
1830 msec_delay_bp(LATCH_DELAY
);
1832 data_pulse(pbpctl_dev
, BYPASS_OFF
);
1839 int tap_off(struct bpctl_dev
*pbpctl_dev
)
1841 int ret
= BP_NOT_CAP
;
1842 if ((pbpctl_dev
->bp_caps
& TAP_CAP
)
1843 && (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
)) {
1844 write_data(pbpctl_dev
, TAP_OFF
);
1845 msec_delay_bp(LATCH_DELAY
);
1852 int tap_on(struct bpctl_dev
*pbpctl_dev
)
1854 int ret
= BP_NOT_CAP
;
1855 if ((pbpctl_dev
->bp_caps
& TAP_CAP
)
1856 && (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
)) {
1857 write_data(pbpctl_dev
, TAP_ON
);
1858 msec_delay_bp(LATCH_DELAY
);
1865 int disc_off(struct bpctl_dev
*pbpctl_dev
)
1868 if ((pbpctl_dev
->bp_caps
& DISC_CAP
) && (pbpctl_dev
->bp_ext_ver
>= 0x8)) {
1869 write_data(pbpctl_dev
, DISC_OFF
);
1870 msec_delay_bp(LATCH_DELAY
);
1877 int disc_on(struct bpctl_dev
*pbpctl_dev
)
1880 if ((pbpctl_dev
->bp_caps
& DISC_CAP
) && (pbpctl_dev
->bp_ext_ver
>= 0x8)) {
1881 write_data(pbpctl_dev
, /*DISC_ON */ 0x85);
1882 msec_delay_bp(LATCH_DELAY
);
1889 int disc_port_on(struct bpctl_dev
*pbpctl_dev
)
1892 struct bpctl_dev
*pbpctl_dev_m
;
1894 if ((is_bypass_fn(pbpctl_dev
)) == 1)
1895 pbpctl_dev_m
= pbpctl_dev
;
1897 pbpctl_dev_m
= get_master_port_fn(pbpctl_dev
);
1898 if (pbpctl_dev_m
== NULL
)
1901 if (pbpctl_dev_m
->bp_caps_ex
& DISC_PORT_CAP_EX
) {
1902 if (is_bypass_fn(pbpctl_dev
) == 1)
1903 write_data(pbpctl_dev_m
, TX_DISA
);
1905 write_data(pbpctl_dev_m
, TX_DISB
);
1907 msec_delay_bp(LATCH_DELAY
);
1914 int disc_port_off(struct bpctl_dev
*pbpctl_dev
)
1917 struct bpctl_dev
*pbpctl_dev_m
;
1919 if ((is_bypass_fn(pbpctl_dev
)) == 1)
1920 pbpctl_dev_m
= pbpctl_dev
;
1922 pbpctl_dev_m
= get_master_port_fn(pbpctl_dev
);
1923 if (pbpctl_dev_m
== NULL
)
1926 if (pbpctl_dev_m
->bp_caps_ex
& DISC_PORT_CAP_EX
) {
1927 if (is_bypass_fn(pbpctl_dev
) == 1)
1928 write_data(pbpctl_dev_m
, TX_ENA
);
1930 write_data(pbpctl_dev_m
, TX_ENB
);
1932 msec_delay_bp(LATCH_DELAY
);
1938 /*TWO_PORT_LINK_HW_EN (0xe)*/
1939 int tpl_hw_on(struct bpctl_dev
*pbpctl_dev
)
1941 int ret
= 0, ctrl
= 0;
1942 struct bpctl_dev
*pbpctl_dev_b
= NULL
;
1944 pbpctl_dev_b
= get_status_port_fn(pbpctl_dev
);
1948 if (pbpctl_dev
->bp_caps_ex
& TPL2_CAP_EX
) {
1949 cmnd_on(pbpctl_dev
);
1950 write_data(pbpctl_dev
, TPL2_ON
);
1951 msec_delay_bp(LATCH_DELAY
+ EEPROM_WR_DELAY
);
1952 cmnd_off(pbpctl_dev
);
1956 if (TPL_IF_SERIES(pbpctl_dev
->subdevice
)) {
1957 ctrl
= BPCTL_READ_REG(pbpctl_dev_b
, CTRL
);
1958 BPCTL_BP_WRITE_REG(pbpctl_dev_b
, CTRL
,
1959 ((ctrl
| BPCTLI_CTRL_SWDPIO0
) &
1960 ~BPCTLI_CTRL_SWDPIN0
));
1966 /*TWO_PORT_LINK_HW_DIS (0xc)*/
1967 int tpl_hw_off(struct bpctl_dev
*pbpctl_dev
)
1969 int ret
= 0, ctrl
= 0;
1970 struct bpctl_dev
*pbpctl_dev_b
= NULL
;
1972 pbpctl_dev_b
= get_status_port_fn(pbpctl_dev
);
1975 if (pbpctl_dev
->bp_caps_ex
& TPL2_CAP_EX
) {
1976 cmnd_on(pbpctl_dev
);
1977 write_data(pbpctl_dev
, TPL2_OFF
);
1978 msec_delay_bp(LATCH_DELAY
+ EEPROM_WR_DELAY
);
1979 cmnd_off(pbpctl_dev
);
1982 if (TPL_IF_SERIES(pbpctl_dev
->subdevice
)) {
1983 ctrl
= BPCTL_READ_REG(pbpctl_dev_b
, CTRL
);
1984 BPCTL_BP_WRITE_REG(pbpctl_dev_b
, CTRL
,
1985 (ctrl
| BPCTLI_CTRL_SWDPIO0
|
1986 BPCTLI_CTRL_SWDPIN0
));
1992 /* WDT_OFF (0x6 110)*/
1993 int wdt_off(struct bpctl_dev
*pbpctl_dev
)
1995 int ret
= BP_NOT_CAP
;
1997 if (pbpctl_dev
->bp_caps
& WD_CTL_CAP
) {
1998 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
))
1999 bypass_off(pbpctl_dev
);
2000 else if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
)
2001 write_data(pbpctl_dev
, WDT_OFF
);
2003 data_pulse(pbpctl_dev
, WDT_OFF
);
2004 pbpctl_dev
->wdt_status
= WDT_STATUS_DIS
;
2014 wdt_val_array
[] = { 1000, 1500, 2000, 3000, 4000, 8000, 16000, 32000, 0 };
2016 int wdt_on(struct bpctl_dev
*pbpctl_dev
, unsigned int timeout
)
2019 if (pbpctl_dev
->bp_caps
& WD_CTL_CAP
) {
2020 unsigned int pulse
= 0, temp_value
= 0, temp_cnt
= 0;
2021 pbpctl_dev
->wdt_status
= 0;
2023 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
)) {
2024 for (; wdt_val_array
[temp_cnt
]; temp_cnt
++)
2025 if (timeout
<= wdt_val_array
[temp_cnt
])
2028 if (!wdt_val_array
[temp_cnt
])
2031 timeout
= wdt_val_array
[temp_cnt
];
2034 write_data_int(pbpctl_dev
, DIS_BYPASS_CAP_INT
);
2035 msec_delay_bp(BYPASS_DELAY_INT
);
2036 pbpctl_dev
->bp_status_un
= 0;
2037 write_data_int(pbpctl_dev
, temp_cnt
);
2038 pbpctl_dev
->bypass_wdt_on_time
= jiffies
;
2039 msec_delay_bp(CMND_INTERVAL_INT
);
2040 pbpctl_dev
->bypass_timer_interval
= timeout
;
2044 TIMEOUT_UNIT
? TIMEOUT_UNIT
: (timeout
>
2048 temp_value
= timeout
/ 100;
2049 while ((temp_value
>>= 1))
2051 if (timeout
> ((1 << temp_cnt
) * 100))
2053 pbpctl_dev
->bypass_wdt_on_time
= jiffies
;
2054 pulse
= (WDT_ON
| temp_cnt
);
2055 if (pbpctl_dev
->bp_ext_ver
== OLD_IF_VER
)
2056 data_pulse(pbpctl_dev
, pulse
);
2058 write_data(pbpctl_dev
, pulse
);
2059 pbpctl_dev
->bypass_timer_interval
=
2060 (1 << temp_cnt
) * 100;
2062 pbpctl_dev
->wdt_status
= WDT_STATUS_EN
;
2068 void bp75_put_hw_semaphore_generic(struct bpctl_dev
*pbpctl_dev
)
2072 swsm
= BPCTL_READ_REG(pbpctl_dev
, SWSM
);
2074 swsm
&= ~(BPCTLI_SWSM_SMBI
| BPCTLI_SWSM_SWESMBI
);
2076 BPCTL_WRITE_REG(pbpctl_dev
, SWSM
, swsm
);
2079 s32
bp75_get_hw_semaphore_generic(struct bpctl_dev
*pbpctl_dev
)
2083 s32 timeout
= 8192 + 1;
2086 /* Get the SW semaphore */
2087 while (i
< timeout
) {
2088 swsm
= BPCTL_READ_REG(pbpctl_dev
, SWSM
);
2089 if (!(swsm
& BPCTLI_SWSM_SMBI
))
2098 ("bpctl_mod: Driver can't access device - SMBI bit is set.\n");
2103 /* Get the FW semaphore. */
2104 for (i
= 0; i
< timeout
; i
++) {
2105 swsm
= BPCTL_READ_REG(pbpctl_dev
, SWSM
);
2106 BPCTL_WRITE_REG(pbpctl_dev
, SWSM
, swsm
| BPCTLI_SWSM_SWESMBI
);
2108 /* Semaphore acquired if bit latched */
2109 if (BPCTL_READ_REG(pbpctl_dev
, SWSM
) & BPCTLI_SWSM_SWESMBI
)
2116 /* Release semaphores */
2117 bp75_put_hw_semaphore_generic(pbpctl_dev
);
2118 printk("bpctl_mod: Driver can't access the NVM\n");
2127 static void bp75_release_phy(struct bpctl_dev
*pbpctl_dev
)
2129 u16 mask
= BPCTLI_SWFW_PHY0_SM
;
2133 if ((pbpctl_dev
->func
== 1) || (pbpctl_dev
->func
== 3))
2134 mask
= BPCTLI_SWFW_PHY1_SM
;
2137 ret_val
= bp75_get_hw_semaphore_generic(pbpctl_dev
);
2138 while (ret_val
!= 0);
2140 swfw_sync
= BPCTL_READ_REG(pbpctl_dev
, SW_FW_SYNC
);
2142 BPCTL_WRITE_REG(pbpctl_dev
, SW_FW_SYNC
, swfw_sync
);
2144 bp75_put_hw_semaphore_generic(pbpctl_dev
);
2147 static s32
bp75_acquire_phy(struct bpctl_dev
*pbpctl_dev
)
2149 u16 mask
= BPCTLI_SWFW_PHY0_SM
;
2154 s32 i
= 0, timeout
= 200;
2156 if ((pbpctl_dev
->func
== 1) || (pbpctl_dev
->func
== 3))
2157 mask
= BPCTLI_SWFW_PHY1_SM
;
2160 fwmask
= mask
<< 16;
2162 while (i
< timeout
) {
2163 if (bp75_get_hw_semaphore_generic(pbpctl_dev
)) {
2168 swfw_sync
= BPCTL_READ_REG(pbpctl_dev
, SW_FW_SYNC
);
2169 if (!(swfw_sync
& (fwmask
| swmask
)))
2172 bp75_put_hw_semaphore_generic(pbpctl_dev
);
2179 ("bpctl_mod: Driver can't access resource, SW_FW_SYNC timeout.\n");
2184 swfw_sync
|= swmask
;
2185 BPCTL_WRITE_REG(pbpctl_dev
, SW_FW_SYNC
, swfw_sync
);
2187 bp75_put_hw_semaphore_generic(pbpctl_dev
);
2193 s32
bp75_read_phy_reg_mdic(struct bpctl_dev
*pbpctl_dev
, u32 offset
, u16
*data
)
2199 mdic
= ((offset
<< BPCTLI_MDIC_REG_SHIFT
) |
2200 (phy_addr
<< BPCTLI_MDIC_PHY_SHIFT
) | (BPCTLI_MDIC_OP_READ
));
2202 BPCTL_WRITE_REG(pbpctl_dev
, MDIC
, mdic
);
2204 for (i
= 0; i
< (BPCTLI_GEN_POLL_TIMEOUT
* 3); i
++) {
2206 mdic
= BPCTL_READ_REG(pbpctl_dev
, MDIC
);
2207 if (mdic
& BPCTLI_MDIC_READY
)
2210 if (!(mdic
& BPCTLI_MDIC_READY
)) {
2211 printk("bpctl_mod: MDI Read did not complete\n");
2215 if (mdic
& BPCTLI_MDIC_ERROR
) {
2216 printk("bpctl_mod: MDI Error\n");
2226 s32
bp75_write_phy_reg_mdic(struct bpctl_dev
*pbpctl_dev
, u32 offset
, u16 data
)
2232 mdic
= (((u32
) data
) |
2233 (offset
<< BPCTLI_MDIC_REG_SHIFT
) |
2234 (phy_addr
<< BPCTLI_MDIC_PHY_SHIFT
) | (BPCTLI_MDIC_OP_WRITE
));
2236 BPCTL_WRITE_REG(pbpctl_dev
, MDIC
, mdic
);
2238 for (i
= 0; i
< (BPCTLI_GEN_POLL_TIMEOUT
* 3); i
++) {
2240 mdic
= BPCTL_READ_REG(pbpctl_dev
, MDIC
);
2241 if (mdic
& BPCTLI_MDIC_READY
)
2244 if (!(mdic
& BPCTLI_MDIC_READY
)) {
2245 printk("bpctl_mod: MDI Write did not complete\n");
2249 if (mdic
& BPCTLI_MDIC_ERROR
) {
2250 printk("bpctl_mod: MDI Error\n");
2259 static s32
bp75_read_phy_reg(struct bpctl_dev
*pbpctl_dev
, u32 offset
, u16
*data
)
2263 ret_val
= bp75_acquire_phy(pbpctl_dev
);
2267 if (offset
> BPCTLI_MAX_PHY_MULTI_PAGE_REG
) {
2268 ret_val
= bp75_write_phy_reg_mdic(pbpctl_dev
,
2269 BPCTLI_IGP01E1000_PHY_PAGE_SELECT
,
2276 bp75_read_phy_reg_mdic(pbpctl_dev
,
2277 BPCTLI_MAX_PHY_REG_ADDRESS
& offset
, data
);
2280 bp75_release_phy(pbpctl_dev
);
2285 static s32
bp75_write_phy_reg(struct bpctl_dev
*pbpctl_dev
, u32 offset
, u16 data
)
2289 ret_val
= bp75_acquire_phy(pbpctl_dev
);
2293 if (offset
> BPCTLI_MAX_PHY_MULTI_PAGE_REG
) {
2294 ret_val
= bp75_write_phy_reg_mdic(pbpctl_dev
,
2295 BPCTLI_IGP01E1000_PHY_PAGE_SELECT
,
2302 bp75_write_phy_reg_mdic(pbpctl_dev
,
2303 BPCTLI_MAX_PHY_REG_ADDRESS
& offset
, data
);
2306 bp75_release_phy(pbpctl_dev
);
2312 /* SET_TX (non-Bypass command :)) */
2313 static int set_tx(struct bpctl_dev
*pbpctl_dev
, int tx_state
)
2315 int ret
= 0, ctrl
= 0;
2316 struct bpctl_dev
*pbpctl_dev_m
;
2317 if ((is_bypass_fn(pbpctl_dev
)) == 1)
2318 pbpctl_dev_m
= pbpctl_dev
;
2320 pbpctl_dev_m
= get_master_port_fn(pbpctl_dev
);
2321 if (pbpctl_dev_m
== NULL
)
2323 if (pbpctl_dev_m
->bp_caps_ex
& DISC_PORT_CAP_EX
) {
2324 ctrl
= BPCTL_READ_REG(pbpctl_dev
, CTRL
);
2326 if (pbpctl_dev
->bp_540
) {
2327 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
2328 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
2329 (ctrl
| BP10G_SDP1_DIR
|
2333 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
2334 (ctrl
| BPCTLI_CTRL_SDP1_DIR
2335 | BPCTLI_CTRL_SWDPIN1
));
2338 if (pbpctl_dev
->bp_540
) {
2339 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
2340 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
2341 ((ctrl
| BP10G_SDP1_DIR
) &
2344 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
2346 BPCTLI_CTRL_SDP1_DIR
) &
2347 ~BPCTLI_CTRL_SWDPIN1
));
2352 } else if (pbpctl_dev
->bp_caps
& TX_CTL_CAP
) {
2353 if (PEG5_IF_SERIES(pbpctl_dev
->subdevice
)) {
2358 bp75_read_phy_reg(pbpctl_dev
,
2361 if (mii_reg
& BPCTLI_MII_CR_POWER_DOWN
) {
2367 ~BPCTLI_MII_CR_POWER_DOWN
);
2374 bp75_read_phy_reg(pbpctl_dev
,
2378 mii_reg
|= BPCTLI_MII_CR_POWER_DOWN
;
2380 bp75_write_phy_reg(pbpctl_dev
,
2387 if (pbpctl_dev
->bp_fiber5
)
2388 ctrl
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
2389 else if (pbpctl_dev
->bp_10gb
)
2390 ctrl
= BP10GB_READ_REG(pbpctl_dev
, MISC_REG_GPIO
);
2391 else if (!pbpctl_dev
->bp_10g
)
2392 ctrl
= BPCTL_READ_REG(pbpctl_dev
, CTRL
);
2394 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
2397 if (pbpctl_dev
->bp_10g9
) {
2398 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
2399 (ctrl
| BP10G_SDP3_DATA
|
2402 } else if (pbpctl_dev
->bp_fiber5
) {
2403 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
2405 BPCTLI_CTRL_EXT_SDP6_DIR
|
2406 BPCTLI_CTRL_EXT_SDP6_DATA
));
2408 } else if (pbpctl_dev
->bp_10gb
) {
2409 if ((pbpctl_dev
->func
== 1)
2410 || (pbpctl_dev
->func
== 3))
2411 BP10GB_WRITE_REG(pbpctl_dev
,
2414 BP10GB_GPIO0_SET_P1
) &
2415 ~(BP10GB_GPIO0_CLR_P1
|
2416 BP10GB_GPIO0_OE_P1
));
2418 BP10GB_WRITE_REG(pbpctl_dev
,
2421 BP10GB_GPIO0_OE_P0
|
2422 BP10GB_GPIO0_SET_P0
));
2424 } else if (pbpctl_dev
->bp_i80
) {
2425 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
2426 (ctrl
| BPCTLI_CTRL_SDP1_DIR
2427 | BPCTLI_CTRL_SWDPIN1
));
2429 } else if (pbpctl_dev
->bp_540
) {
2430 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
2431 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
2432 (ctrl
| BP10G_SDP1_DIR
|
2437 else if (!pbpctl_dev
->bp_10g
)
2438 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
2439 (ctrl
| BPCTLI_CTRL_SWDPIO0
|
2440 BPCTLI_CTRL_SWDPIN0
));
2443 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
2444 (ctrl
| BP10G_SDP0_DATA
|
2448 if (pbpctl_dev
->bp_10g9
) {
2449 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
2450 ((ctrl
| BP10G_SDP3_DIR
) &
2453 } else if (pbpctl_dev
->bp_fiber5
) {
2454 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL_EXT
,
2456 BPCTLI_CTRL_EXT_SDP6_DIR
) &
2457 ~BPCTLI_CTRL_EXT_SDP6_DATA
));
2459 } else if (pbpctl_dev
->bp_10gb
) {
2460 if ((bpctl_dev_arr
->func
== 1)
2461 || (bpctl_dev_arr
->func
== 3))
2462 BP10GB_WRITE_REG(pbpctl_dev
,
2465 BP10GB_GPIO0_CLR_P1
) &
2466 ~(BP10GB_GPIO0_SET_P1
|
2467 BP10GB_GPIO0_OE_P1
));
2469 BP10GB_WRITE_REG(pbpctl_dev
,
2472 BP10GB_GPIO0_OE_P0
|
2473 BP10GB_GPIO0_CLR_P0
));
2475 } else if (pbpctl_dev
->bp_i80
) {
2476 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
2478 BPCTLI_CTRL_SDP1_DIR
) &
2479 ~BPCTLI_CTRL_SWDPIN1
));
2480 } else if (pbpctl_dev
->bp_540
) {
2481 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
2482 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
2483 ((ctrl
| BP10G_SDP1_DIR
) &
2487 else if (!pbpctl_dev
->bp_10g
) {
2488 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
2489 ((ctrl
| BPCTLI_CTRL_SWDPIO0
)
2490 & ~BPCTLI_CTRL_SWDPIN0
));
2491 if (!PEGF_IF_SERIES(pbpctl_dev
->subdevice
)) {
2492 BPCTL_BP_WRITE_REG(pbpctl_dev
, CTRL
,
2495 (BPCTLI_CTRL_SDP0_DATA
2497 BPCTLI_CTRL_SDP0_DIR
)));
2500 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
2501 ((ctrl
| BP10G_SDP0_DIR
) &
2512 /* SET_FORCE_LINK (non-Bypass command :)) */
2513 static int set_bp_force_link(struct bpctl_dev
*pbpctl_dev
, int tx_state
)
2515 int ret
= 0, ctrl
= 0;
2517 if (DBI_IF_SERIES(pbpctl_dev
->subdevice
)) {
2519 if ((pbpctl_dev
->bp_10g
) || (pbpctl_dev
->bp_10g9
)) {
2521 ctrl
= BPCTL_READ_REG(pbpctl_dev
, CTRL
);
2523 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
2524 ctrl
& ~BP10G_SDP1_DIR
);
2526 BP10G_WRITE_REG(pbpctl_dev
, ESDP
,
2527 ((ctrl
| BP10G_SDP1_DIR
) &
2536 /*RESET_CONT 0x20 */
2537 int reset_cont(struct bpctl_dev
*pbpctl_dev
)
2539 int ret
= BP_NOT_CAP
;
2541 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
2542 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
))
2544 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
)
2545 write_data(pbpctl_dev
, RESET_CONT
);
2547 data_pulse(pbpctl_dev
, RESET_CONT
);
2553 /*DIS_BYPASS_CAP 0x22 */
2554 int dis_bypass_cap(struct bpctl_dev
*pbpctl_dev
)
2557 if (pbpctl_dev
->bp_caps
& BP_DIS_CAP
) {
2558 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
)) {
2559 write_data_int(pbpctl_dev
, DIS_BYPASS_CAP_INT
);
2560 msec_delay_bp(BYPASS_DELAY_INT
);
2562 write_data(pbpctl_dev
, BYPASS_OFF
);
2563 msec_delay_bp(LATCH_DELAY
);
2564 write_data(pbpctl_dev
, DIS_BYPASS_CAP
);
2565 msec_delay_bp(BYPASS_CAP_DELAY
);
2572 /*EN_BYPASS_CAP 0x24 */
2573 int en_bypass_cap(struct bpctl_dev
*pbpctl_dev
)
2575 if (pbpctl_dev
->bp_caps
& BP_DIS_CAP
) {
2576 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
)) {
2577 write_data_int(pbpctl_dev
, PWROFF_BYPASS_ON_INT
);
2578 msec_delay_bp(BYPASS_DELAY_INT
);
2580 write_data(pbpctl_dev
, EN_BYPASS_CAP
);
2581 msec_delay_bp(BYPASS_CAP_DELAY
);
2588 /* BYPASS_STATE_PWRON 0x26*/
2589 int bypass_state_pwron(struct bpctl_dev
*pbpctl_dev
)
2591 if (pbpctl_dev
->bp_caps
& BP_PWUP_CTL_CAP
) {
2592 write_data(pbpctl_dev
, BYPASS_STATE_PWRON
);
2593 if (pbpctl_dev
->bp_ext_ver
== PXG2BPI_VER
)
2594 msec_delay_bp(DFLT_PWRON_DELAY
);
2596 msec_delay_bp(LATCH_DELAY
+ EEPROM_WR_DELAY
);
2602 /* NORMAL_STATE_PWRON 0x28*/
2603 int normal_state_pwron(struct bpctl_dev
*pbpctl_dev
)
2605 if ((pbpctl_dev
->bp_caps
& BP_PWUP_CTL_CAP
)
2606 || (pbpctl_dev
->bp_caps
& TAP_PWUP_CTL_CAP
)) {
2607 write_data(pbpctl_dev
, NORMAL_STATE_PWRON
);
2608 if (pbpctl_dev
->bp_ext_ver
== PXG2BPI_VER
)
2609 msec_delay_bp(DFLT_PWRON_DELAY
);
2611 msec_delay_bp(LATCH_DELAY
+ EEPROM_WR_DELAY
);
2617 /* BYPASS_STATE_PWROFF 0x27*/
2618 int bypass_state_pwroff(struct bpctl_dev
*pbpctl_dev
)
2620 if (pbpctl_dev
->bp_caps
& BP_PWOFF_CTL_CAP
) {
2621 write_data(pbpctl_dev
, BYPASS_STATE_PWROFF
);
2622 msec_delay_bp(LATCH_DELAY
+ EEPROM_WR_DELAY
);
2628 /* NORMAL_STATE_PWROFF 0x29*/
2629 int normal_state_pwroff(struct bpctl_dev
*pbpctl_dev
)
2631 if ((pbpctl_dev
->bp_caps
& BP_PWOFF_CTL_CAP
)) {
2632 write_data(pbpctl_dev
, NORMAL_STATE_PWROFF
);
2633 msec_delay_bp(LATCH_DELAY
+ EEPROM_WR_DELAY
);
2639 /*TAP_STATE_PWRON 0x2a*/
2640 int tap_state_pwron(struct bpctl_dev
*pbpctl_dev
)
2642 if (pbpctl_dev
->bp_caps
& TAP_PWUP_CTL_CAP
) {
2643 write_data(pbpctl_dev
, TAP_STATE_PWRON
);
2644 msec_delay_bp(LATCH_DELAY
+ EEPROM_WR_DELAY
);
2650 /*DIS_TAP_CAP 0x2c*/
2651 int dis_tap_cap(struct bpctl_dev
*pbpctl_dev
)
2653 if (pbpctl_dev
->bp_caps
& TAP_DIS_CAP
) {
2654 write_data(pbpctl_dev
, DIS_TAP_CAP
);
2655 msec_delay_bp(BYPASS_CAP_DELAY
);
2662 int en_tap_cap(struct bpctl_dev
*pbpctl_dev
)
2664 if (pbpctl_dev
->bp_caps
& TAP_DIS_CAP
) {
2665 write_data(pbpctl_dev
, EN_TAP_CAP
);
2666 msec_delay_bp(BYPASS_CAP_DELAY
);
2672 /*DISC_STATE_PWRON 0x2a*/
2673 int disc_state_pwron(struct bpctl_dev
*pbpctl_dev
)
2675 if (pbpctl_dev
->bp_caps
& DISC_PWUP_CTL_CAP
) {
2676 if (pbpctl_dev
->bp_ext_ver
>= 0x8) {
2677 write_data(pbpctl_dev
, DISC_STATE_PWRON
);
2678 msec_delay_bp(LATCH_DELAY
+ EEPROM_WR_DELAY
);
2685 /*DIS_DISC_CAP 0x2c*/
2686 int dis_disc_cap(struct bpctl_dev
*pbpctl_dev
)
2688 if (pbpctl_dev
->bp_caps
& DISC_DIS_CAP
) {
2689 if (pbpctl_dev
->bp_ext_ver
>= 0x8) {
2690 write_data(pbpctl_dev
, DIS_DISC_CAP
);
2691 msec_delay_bp(BYPASS_CAP_DELAY
);
2698 /*DISC_STATE_PWRON 0x2a*/
2699 int disc_port_state_pwron(struct bpctl_dev
*pbpctl_dev
)
2702 struct bpctl_dev
*pbpctl_dev_m
;
2706 if ((is_bypass_fn(pbpctl_dev
)) == 1)
2707 pbpctl_dev_m
= pbpctl_dev
;
2709 pbpctl_dev_m
= get_master_port_fn(pbpctl_dev
);
2710 if (pbpctl_dev_m
== NULL
)
2713 if (pbpctl_dev_m
->bp_caps_ex
& DISC_PORT_CAP_EX
) {
2714 if (is_bypass_fn(pbpctl_dev
) == 1)
2715 write_data(pbpctl_dev_m
, TX_DISA_PWRUP
);
2717 write_data(pbpctl_dev_m
, TX_DISB_PWRUP
);
2719 msec_delay_bp(LATCH_DELAY
);
2725 int normal_port_state_pwron(struct bpctl_dev
*pbpctl_dev
)
2728 struct bpctl_dev
*pbpctl_dev_m
;
2731 if ((is_bypass_fn(pbpctl_dev
)) == 1)
2732 pbpctl_dev_m
= pbpctl_dev
;
2734 pbpctl_dev_m
= get_master_port_fn(pbpctl_dev
);
2735 if (pbpctl_dev_m
== NULL
)
2738 if (pbpctl_dev_m
->bp_caps_ex
& DISC_PORT_CAP_EX
) {
2739 if (is_bypass_fn(pbpctl_dev
) == 1)
2740 write_data(pbpctl_dev_m
, TX_ENA_PWRUP
);
2742 write_data(pbpctl_dev_m
, TX_ENB_PWRUP
);
2744 msec_delay_bp(LATCH_DELAY
);
2751 int en_disc_cap(struct bpctl_dev
*pbpctl_dev
)
2753 if (pbpctl_dev
->bp_caps
& DISC_DIS_CAP
) {
2754 if (pbpctl_dev
->bp_ext_ver
>= 0x8) {
2755 write_data(pbpctl_dev
, EN_DISC_CAP
);
2756 msec_delay_bp(BYPASS_CAP_DELAY
);
2763 int std_nic_on(struct bpctl_dev
*pbpctl_dev
)
2766 if (pbpctl_dev
->bp_caps
& STD_NIC_CAP
) {
2768 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
)) {
2769 write_data_int(pbpctl_dev
, DIS_BYPASS_CAP_INT
);
2770 msec_delay_bp(BYPASS_DELAY_INT
);
2771 pbpctl_dev
->bp_status_un
= 0;
2775 if (pbpctl_dev
->bp_ext_ver
>= 0x8) {
2776 write_data(pbpctl_dev
, STD_NIC_ON
);
2777 msec_delay_bp(BYPASS_CAP_DELAY
);
2782 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
2783 wdt_off(pbpctl_dev
);
2785 if (pbpctl_dev
->bp_caps
& BP_CAP
) {
2786 write_data(pbpctl_dev
, BYPASS_OFF
);
2787 msec_delay_bp(LATCH_DELAY
);
2790 if (pbpctl_dev
->bp_caps
& TAP_CAP
) {
2791 write_data(pbpctl_dev
, TAP_OFF
);
2792 msec_delay_bp(LATCH_DELAY
);
2795 write_data(pbpctl_dev
, NORMAL_STATE_PWRON
);
2796 if (pbpctl_dev
->bp_ext_ver
== PXG2BPI_VER
)
2797 msec_delay_bp(DFLT_PWRON_DELAY
);
2799 msec_delay_bp(LATCH_DELAY
+ EEPROM_WR_DELAY
);
2801 if (pbpctl_dev
->bp_caps
& BP_DIS_CAP
) {
2802 write_data(pbpctl_dev
, DIS_BYPASS_CAP
);
2803 msec_delay_bp(BYPASS_CAP_DELAY
);
2806 if (pbpctl_dev
->bp_caps
& TAP_DIS_CAP
) {
2807 write_data(pbpctl_dev
, DIS_TAP_CAP
);
2808 msec_delay_bp(BYPASS_CAP_DELAY
);
2817 int std_nic_off(struct bpctl_dev
*pbpctl_dev
)
2820 if (pbpctl_dev
->bp_caps
& STD_NIC_CAP
) {
2821 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
)) {
2822 write_data_int(pbpctl_dev
, PWROFF_BYPASS_ON_INT
);
2823 msec_delay_bp(BYPASS_DELAY_INT
);
2826 if (pbpctl_dev
->bp_ext_ver
>= 0x8) {
2827 write_data(pbpctl_dev
, STD_NIC_OFF
);
2828 msec_delay_bp(BYPASS_CAP_DELAY
);
2833 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
2835 if (pbpctl_dev
->bp_caps
& TAP_PWUP_CTL_CAP
) {
2836 write_data(pbpctl_dev
, TAP_STATE_PWRON
);
2837 msec_delay_bp(LATCH_DELAY
+ EEPROM_WR_DELAY
);
2840 if (pbpctl_dev
->bp_caps
& BP_PWUP_CTL_CAP
) {
2841 write_data(pbpctl_dev
, BYPASS_STATE_PWRON
);
2842 if (pbpctl_dev
->bp_ext_ver
> PXG2BPI_VER
)
2843 msec_delay_bp(LATCH_DELAY
+
2846 msec_delay_bp(DFLT_PWRON_DELAY
);
2849 if (pbpctl_dev
->bp_caps
& TAP_DIS_CAP
) {
2850 write_data(pbpctl_dev
, EN_TAP_CAP
);
2851 msec_delay_bp(BYPASS_CAP_DELAY
);
2853 if (pbpctl_dev
->bp_caps
& DISC_DIS_CAP
) {
2854 write_data(pbpctl_dev
, EN_DISC_CAP
);
2855 msec_delay_bp(BYPASS_CAP_DELAY
);
2858 if (pbpctl_dev
->bp_caps
& BP_DIS_CAP
) {
2859 write_data(pbpctl_dev
, EN_BYPASS_CAP
);
2860 msec_delay_bp(BYPASS_CAP_DELAY
);
2869 int wdt_time_left(struct bpctl_dev
*pbpctl_dev
)
2872 /* unsigned long curr_time=((long long)(jiffies*1000))/HZ, delta_time=0,wdt_on_time=((long long)(pbpctl_dev->bypass_wdt_on_time*1000))/HZ; */
2873 unsigned long curr_time
= jiffies
, delta_time
= 0, wdt_on_time
=
2874 pbpctl_dev
->bypass_wdt_on_time
, delta_time_msec
= 0;
2877 switch (pbpctl_dev
->wdt_status
) {
2878 case WDT_STATUS_DIS
:
2884 wdt_on_time
) ? (curr_time
- wdt_on_time
) : (~wdt_on_time
+
2886 delta_time_msec
= jiffies_to_msecs(delta_time
);
2887 time_left
= pbpctl_dev
->bypass_timer_interval
- delta_time_msec
;
2888 if (time_left
< 0) {
2890 pbpctl_dev
->wdt_status
= WDT_STATUS_EXP
;
2893 case WDT_STATUS_EXP
:
2901 static int wdt_timer(struct bpctl_dev
*pbpctl_dev
, int *time_left
)
2904 if (pbpctl_dev
->bp_caps
& WD_CTL_CAP
) {
2906 if (pbpctl_dev
->wdt_status
== WDT_STATUS_UNKNOWN
)
2909 *time_left
= wdt_time_left(pbpctl_dev
);
2917 static int wdt_timer_reload(struct bpctl_dev
*pbpctl_dev
)
2922 if ((pbpctl_dev
->bp_caps
& WD_CTL_CAP
) &&
2923 (pbpctl_dev
->wdt_status
!= WDT_STATUS_UNKNOWN
)) {
2924 if (pbpctl_dev
->wdt_status
== WDT_STATUS_DIS
)
2926 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
)
2927 ret
= wdt_pulse(pbpctl_dev
);
2928 else if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
))
2929 ret
= wdt_pulse_int(pbpctl_dev
);
2931 ret
= send_wdt_pulse(pbpctl_dev
);
2933 mod_timer(&pbpctl_dev->bp_timer, jiffies+1);*/
2939 static void wd_reset_timer(unsigned long param
)
2941 struct bpctl_dev
*pbpctl_dev
= (struct bpctl_dev
*) param
;
2943 struct sk_buff
*skb_tmp
;
2946 if ((pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) &&
2947 ((atomic_read(&pbpctl_dev
->wdt_busy
)) == 1)) {
2948 mod_timer(&pbpctl_dev
->bp_timer
, jiffies
+ 1);
2953 if (pbpctl_dev
->bp_self_test_flag
== 1) {
2954 skb_tmp
= dev_alloc_skb(BPTEST_DATA_LEN
+ 2);
2955 if ((skb_tmp
) && (pbpctl_dev
->ndev
) && (pbpctl_dev
->bp_tx_data
)) {
2956 memcpy(skb_put(skb_tmp
, BPTEST_DATA_LEN
),
2957 pbpctl_dev
->bp_tx_data
, BPTEST_DATA_LEN
);
2958 skb_tmp
->dev
= pbpctl_dev
->ndev
;
2960 eth_type_trans(skb_tmp
, pbpctl_dev
->ndev
);
2961 skb_tmp
->ip_summed
= CHECKSUM_UNNECESSARY
;
2962 netif_receive_skb(skb_tmp
);
2963 goto bp_timer_reload
;
2969 wdt_timer_reload(pbpctl_dev
);
2973 if (pbpctl_dev
->reset_time
) {
2974 mod_timer(&pbpctl_dev
->bp_timer
,
2975 jiffies
+ (HZ
* pbpctl_dev
->reset_time
) / 1000);
2979 /*WAIT_AT_PWRUP 0x80 */
2980 int bp_wait_at_pwup_en(struct bpctl_dev
*pbpctl_dev
)
2983 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
2984 if (pbpctl_dev
->bp_ext_ver
>= BP_FW_EXT_VER8
) {
2985 write_data(pbpctl_dev
, BP_WAIT_AT_PWUP_EN
);
2986 msec_delay_bp(LATCH_DELAY
+ EEPROM_WR_DELAY
);
2994 /*DIS_WAIT_AT_PWRUP 0x81 */
2995 int bp_wait_at_pwup_dis(struct bpctl_dev
*pbpctl_dev
)
2998 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
3000 if (pbpctl_dev
->bp_ext_ver
>= BP_FW_EXT_VER8
) {
3001 write_data(pbpctl_dev
, BP_WAIT_AT_PWUP_DIS
);
3002 msec_delay_bp(LATCH_DELAY
+ EEPROM_WR_DELAY
);
3010 /*EN_HW_RESET 0x82 */
3012 int bp_hw_reset_en(struct bpctl_dev
*pbpctl_dev
)
3015 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
3016 if (pbpctl_dev
->bp_ext_ver
>= BP_FW_EXT_VER8
) {
3017 write_data(pbpctl_dev
, BP_HW_RESET_EN
);
3018 msec_delay_bp(LATCH_DELAY
+ EEPROM_WR_DELAY
);
3026 /*DIS_HW_RESET 0x83 */
3028 int bp_hw_reset_dis(struct bpctl_dev
*pbpctl_dev
)
3031 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
3032 if (pbpctl_dev
->bp_ext_ver
>= BP_FW_EXT_VER8
) {
3033 write_data(pbpctl_dev
, BP_HW_RESET_DIS
);
3034 msec_delay_bp(LATCH_DELAY
+ EEPROM_WR_DELAY
);
3043 int wdt_exp_mode(struct bpctl_dev
*pbpctl_dev
, int mode
)
3045 uint32_t status_reg
= 0, status_reg1
= 0;
3047 if ((pbpctl_dev
->bp_caps
& (TAP_STATUS_CAP
| DISC_CAP
)) &&
3048 (pbpctl_dev
->bp_caps
& BP_CAP
)) {
3049 if (pbpctl_dev
->bp_ext_ver
>= PXE2TBPI_VER
) {
3051 if ((pbpctl_dev
->bp_ext_ver
>= 0x8) &&
3052 (mode
== 2) && (pbpctl_dev
->bp_caps
& DISC_CAP
)) {
3054 read_reg(pbpctl_dev
, STATUS_DISC_REG_ADDR
);
3055 if (!(status_reg1
& WDTE_DISC_BPN_MASK
))
3056 write_reg(pbpctl_dev
,
3059 STATUS_DISC_REG_ADDR
);
3063 status_reg
= read_reg(pbpctl_dev
, STATUS_TAP_REG_ADDR
);
3065 if ((mode
== 0) && (pbpctl_dev
->bp_caps
& BP_CAP
)) {
3066 if (pbpctl_dev
->bp_ext_ver
>= 0x8) {
3068 read_reg(pbpctl_dev
, STATUS_DISC_REG_ADDR
);
3069 if (status_reg1
& WDTE_DISC_BPN_MASK
)
3070 write_reg(pbpctl_dev
,
3072 ~WDTE_DISC_BPN_MASK
,
3073 STATUS_DISC_REG_ADDR
);
3075 if (status_reg
& WDTE_TAP_BPN_MASK
)
3076 write_reg(pbpctl_dev
,
3077 status_reg
& ~WDTE_TAP_BPN_MASK
,
3078 STATUS_TAP_REG_ADDR
);
3081 } else if ((mode
== 1) && (pbpctl_dev
->bp_caps
& TAP_CAP
)) {
3082 if (!(status_reg
& WDTE_TAP_BPN_MASK
))
3083 write_reg(pbpctl_dev
,
3084 status_reg
| WDTE_TAP_BPN_MASK
,
3085 STATUS_TAP_REG_ADDR
);
3086 /*else return BP_NOT_CAP; */
3094 int bypass_fw_ver(struct bpctl_dev
*pbpctl_dev
)
3096 if (is_bypass_fn(pbpctl_dev
))
3097 return read_reg(pbpctl_dev
, VER_REG_ADDR
);
3102 int bypass_sign_check(struct bpctl_dev
*pbpctl_dev
)
3105 if (is_bypass_fn(pbpctl_dev
))
3106 return (((read_reg(pbpctl_dev
, PIC_SIGN_REG_ADDR
)) ==
3107 PIC_SIGN_VALUE
) ? 1 : 0);
3112 static int tx_status(struct bpctl_dev
*pbpctl_dev
)
3115 struct bpctl_dev
*pbpctl_dev_m
;
3116 if ((is_bypass_fn(pbpctl_dev
)) == 1)
3117 pbpctl_dev_m
= pbpctl_dev
;
3119 pbpctl_dev_m
= get_master_port_fn(pbpctl_dev
);
3120 if (pbpctl_dev_m
== NULL
)
3122 if (pbpctl_dev_m
->bp_caps_ex
& DISC_PORT_CAP_EX
) {
3124 ctrl
= BPCTL_READ_REG(pbpctl_dev
, CTRL
);
3125 if (pbpctl_dev
->bp_i80
)
3126 return ((ctrl
& BPCTLI_CTRL_SWDPIN1
) != 0 ? 0 : 1);
3127 if (pbpctl_dev
->bp_540
) {
3128 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
3130 return ((ctrl
& BP10G_SDP1_DATA
) != 0 ? 0 : 1);
3135 if (pbpctl_dev
->bp_caps
& TX_CTL_CAP
) {
3136 if (PEG5_IF_SERIES(pbpctl_dev
->subdevice
)) {
3140 (pbpctl_dev
, BPCTLI_PHY_CONTROL
, &mii_reg
))) {
3141 if (mii_reg
& BPCTLI_MII_CR_POWER_DOWN
)
3150 if (pbpctl_dev
->bp_10g9
) {
3151 return ((BP10G_READ_REG(pbpctl_dev
, ESDP
) &
3152 BP10G_SDP3_DATA
) != 0 ? 0 : 1);
3154 } else if (pbpctl_dev
->bp_fiber5
) {
3155 ctrl
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
3156 if (ctrl
& BPCTLI_CTRL_EXT_SDP6_DATA
)
3159 } else if (pbpctl_dev
->bp_10gb
) {
3160 ctrl
= BP10GB_READ_REG(pbpctl_dev
, MISC_REG_GPIO
);
3161 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_GPIO
,
3162 (ctrl
| BP10GB_GPIO0_OE_P1
) &
3163 ~(BP10GB_GPIO0_SET_P1
|
3164 BP10GB_GPIO0_CLR_P1
));
3166 if ((pbpctl_dev
->func
== 1) || (pbpctl_dev
->func
== 3))
3167 return (((BP10GB_READ_REG
3169 MISC_REG_GPIO
)) & BP10GB_GPIO0_P1
) !=
3172 return (((BP10GB_READ_REG
3174 MISC_REG_GPIO
)) & BP10GB_GPIO0_P0
) !=
3178 if (!pbpctl_dev
->bp_10g
) {
3180 ctrl
= BPCTL_READ_REG(pbpctl_dev
, CTRL
);
3181 if (pbpctl_dev
->bp_i80
)
3182 return ((ctrl
& BPCTLI_CTRL_SWDPIN1
) !=
3184 if (pbpctl_dev
->bp_540
) {
3185 ctrl
= BP10G_READ_REG(pbpctl_dev
, ESDP
);
3187 return ((ctrl
& BP10G_SDP1_DATA
) != 0 ? 0 : 1);
3190 return ((ctrl
& BPCTLI_CTRL_SWDPIN0
) != 0 ? 0 : 1);
3192 return ((BP10G_READ_REG(pbpctl_dev
, ESDP
) &
3193 BP10G_SDP0_DATA
) != 0 ? 0 : 1);
3199 static int bp_force_link_status(struct bpctl_dev
*pbpctl_dev
)
3202 if (DBI_IF_SERIES(pbpctl_dev
->subdevice
)) {
3204 if ((pbpctl_dev
->bp_10g
) || (pbpctl_dev
->bp_10g9
)) {
3205 return ((BP10G_READ_REG(pbpctl_dev
, ESDP
) &
3206 BP10G_SDP1_DIR
) != 0 ? 1 : 0);
3213 int bypass_from_last_read(struct bpctl_dev
*pbpctl_dev
)
3215 uint32_t ctrl_ext
= 0;
3216 struct bpctl_dev
*pbpctl_dev_b
= NULL
;
3218 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
3219 pbpctl_dev_b
= get_status_port_fn(pbpctl_dev
);
3222 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev_b
, CTRL_EXT
);
3223 BPCTL_BP_WRITE_REG(pbpctl_dev_b
, CTRL_EXT
,
3224 (ctrl_ext
& ~BPCTLI_CTRL_EXT_SDP7_DIR
));
3225 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev_b
, CTRL_EXT
);
3226 if (ctrl_ext
& BPCTLI_CTRL_EXT_SDP7_DATA
)
3233 int bypass_status_clear(struct bpctl_dev
*pbpctl_dev
)
3235 struct bpctl_dev
*pbpctl_dev_b
= NULL
;
3237 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
3238 pbpctl_dev_b
= get_status_port_fn(pbpctl_dev
);
3241 send_bypass_clear_pulse(pbpctl_dev_b
, 1);
3247 int bypass_flag_status(struct bpctl_dev
*pbpctl_dev
)
3250 if ((pbpctl_dev
->bp_caps
& BP_CAP
)) {
3251 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
3252 return ((((read_reg(pbpctl_dev
, STATUS_REG_ADDR
)) &
3253 BYPASS_FLAG_MASK
) ==
3254 BYPASS_FLAG_MASK
) ? 1 : 0);
3260 int bypass_flag_status_clear(struct bpctl_dev
*pbpctl_dev
)
3263 if (pbpctl_dev
->bp_caps
& BP_CAP
) {
3264 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
3265 uint32_t status_reg
= 0;
3266 status_reg
= read_reg(pbpctl_dev
, STATUS_REG_ADDR
);
3267 write_reg(pbpctl_dev
, status_reg
& ~BYPASS_FLAG_MASK
,
3275 int bypass_change_status(struct bpctl_dev
*pbpctl_dev
)
3277 int ret
= BP_NOT_CAP
;
3279 if (pbpctl_dev
->bp_caps
& BP_STATUS_CHANGE_CAP
) {
3280 if (pbpctl_dev
->bp_ext_ver
>= 0x8) {
3281 ret
= bypass_flag_status(pbpctl_dev
);
3282 bypass_flag_status_clear(pbpctl_dev
);
3283 } else if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
3284 ret
= bypass_flag_status(pbpctl_dev
);
3285 bypass_flag_status_clear(pbpctl_dev
);
3287 ret
= bypass_from_last_read(pbpctl_dev
);
3288 bypass_status_clear(pbpctl_dev
);
3294 int bypass_off_status(struct bpctl_dev
*pbpctl_dev
)
3297 if (pbpctl_dev
->bp_caps
& BP_CAP
) {
3298 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
3299 return ((((read_reg(pbpctl_dev
, STATUS_REG_ADDR
)) &
3300 BYPASS_OFF_MASK
) == BYPASS_OFF_MASK
) ? 1 : 0);
3306 static int bypass_status(struct bpctl_dev
*pbpctl_dev
)
3309 if (pbpctl_dev
->bp_caps
& BP_CAP
) {
3311 struct bpctl_dev
*pbpctl_dev_b
= NULL
;
3313 pbpctl_dev_b
= get_status_port_fn(pbpctl_dev
);
3317 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
)) {
3319 if (!pbpctl_dev
->bp_status_un
)
3320 return (((BPCTL_READ_REG
3323 BPCTLI_CTRL_EXT_SDP7_DATA
) !=
3328 if (pbpctl_dev
->bp_ext_ver
>= 0x8) {
3330 if (pbpctl_dev
->bp_10g9
) {
3331 ctrl_ext
= BP10G_READ_REG(pbpctl_dev_b
, I2CCTL
);
3332 BP10G_WRITE_REG(pbpctl_dev_b
, I2CCTL
,
3333 (ctrl_ext
| BP10G_I2C_CLK_OUT
));
3334 return ((BP10G_READ_REG(pbpctl_dev_b
, I2CCTL
) &
3335 BP10G_I2C_CLK_IN
) != 0 ? 0 : 1);
3337 } else if (pbpctl_dev
->bp_540
) {
3338 return (((BP10G_READ_REG(pbpctl_dev_b
, ESDP
)) &
3339 BP10G_SDP0_DATA
) != 0 ? 0 : 1);
3342 else if ((pbpctl_dev
->bp_fiber5
)
3343 || (pbpctl_dev
->bp_i80
)) {
3344 return (((BPCTL_READ_REG(pbpctl_dev_b
, CTRL
)) &
3345 BPCTLI_CTRL_SWDPIN0
) != 0 ? 0 : 1);
3346 } else if (pbpctl_dev
->bp_10gb
) {
3348 BP10GB_READ_REG(pbpctl_dev
, MISC_REG_GPIO
);
3349 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_GPIO
,
3350 (ctrl_ext
| BP10GB_GPIO3_OE_P0
)
3351 & ~(BP10GB_GPIO3_SET_P0
|
3352 BP10GB_GPIO3_CLR_P0
));
3354 return (((BP10GB_READ_REG
3356 MISC_REG_GPIO
)) & BP10GB_GPIO3_P0
) !=
3360 else if (!pbpctl_dev
->bp_10g
)
3361 return (((BPCTL_READ_REG
3364 BPCTLI_CTRL_EXT_SDP7_DATA
) !=
3368 ctrl_ext
= BP10G_READ_REG(pbpctl_dev_b
, EODSDP
);
3369 BP10G_WRITE_REG(pbpctl_dev_b
, EODSDP
,
3371 BP10G_SDP7_DATA_OUT
));
3372 return ((BP10G_READ_REG(pbpctl_dev_b
, EODSDP
) &
3373 BP10G_SDP7_DATA_IN
) != 0 ? 0 : 1);
3376 } else if (pbpctl_dev
->media_type
== BP_COPPER
) {
3378 return (((BPCTL_READ_REG(pbpctl_dev_b
, CTRL
)) &
3379 BPCTLI_CTRL_SWDPIN1
) != 0 ? 1 : 0);
3381 if ((bypass_status_clear(pbpctl_dev
)) >= 0)
3382 return bypass_from_last_read(pbpctl_dev
);
3389 int default_pwron_status(struct bpctl_dev
*pbpctl_dev
)
3392 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
3393 if (pbpctl_dev
->bp_caps
& BP_PWUP_CTL_CAP
) {
3394 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
3397 STATUS_REG_ADDR
)) & DFLT_PWRON_MASK
)
3398 == DFLT_PWRON_MASK
) ? 0 : 1);
3400 } /*else if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3401 (pbpctl_dev->bp_caps&BP_PWUP_ON_CAP))
3407 static int default_pwroff_status(struct bpctl_dev
*pbpctl_dev
)
3410 /*if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3411 (pbpctl_dev->bp_caps&BP_PWOFF_ON_CAP))
3413 if ((pbpctl_dev
->bp_caps
& SW_CTL_CAP
)
3414 && (pbpctl_dev
->bp_caps
& BP_PWOFF_CTL_CAP
)) {
3415 return ((((read_reg(pbpctl_dev
, STATUS_REG_ADDR
)) &
3416 DFLT_PWROFF_MASK
) == DFLT_PWROFF_MASK
) ? 0 : 1);
3421 int dis_bypass_cap_status(struct bpctl_dev
*pbpctl_dev
)
3424 if (pbpctl_dev
->bp_caps
& BP_DIS_CAP
) {
3425 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
3426 return ((((read_reg(pbpctl_dev
, STATUS_REG_ADDR
)) &
3427 DIS_BYPASS_CAP_MASK
) ==
3428 DIS_BYPASS_CAP_MASK
) ? 1 : 0);
3434 int cmd_en_status(struct bpctl_dev
*pbpctl_dev
)
3437 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
3438 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
3439 return ((((read_reg(pbpctl_dev
, STATUS_REG_ADDR
)) &
3440 CMND_EN_MASK
) == CMND_EN_MASK
) ? 1 : 0);
3446 int wdt_en_status(struct bpctl_dev
*pbpctl_dev
)
3449 if (pbpctl_dev
->bp_caps
& WD_CTL_CAP
) {
3450 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
3451 return ((((read_reg(pbpctl_dev
, STATUS_REG_ADDR
)) &
3452 WDT_EN_MASK
) == WDT_EN_MASK
) ? 1 : 0);
3458 int wdt_programmed(struct bpctl_dev
*pbpctl_dev
, int *timeout
)
3461 if (pbpctl_dev
->bp_caps
& WD_CTL_CAP
) {
3462 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
3463 if ((read_reg(pbpctl_dev
, STATUS_REG_ADDR
)) &
3466 wdt_val
= read_reg(pbpctl_dev
, WDT_REG_ADDR
);
3467 *timeout
= (1 << wdt_val
) * 100;
3471 int curr_wdt_status
= pbpctl_dev
->wdt_status
;
3472 if (curr_wdt_status
== WDT_STATUS_UNKNOWN
)
3477 0 ? 0 : pbpctl_dev
->bypass_timer_interval
;
3484 int bypass_support(struct bpctl_dev
*pbpctl_dev
)
3488 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
3489 if (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
) {
3491 ((((read_reg(pbpctl_dev
, PRODUCT_CAP_REG_ADDR
)) &
3492 BYPASS_SUPPORT_MASK
) ==
3493 BYPASS_SUPPORT_MASK
) ? 1 : 0);
3494 } else if (pbpctl_dev
->bp_ext_ver
== PXG2BPI_VER
)
3501 int tap_support(struct bpctl_dev
*pbpctl_dev
)
3505 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
3506 if (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
) {
3508 ((((read_reg(pbpctl_dev
, PRODUCT_CAP_REG_ADDR
)) &
3509 TAP_SUPPORT_MASK
) == TAP_SUPPORT_MASK
) ? 1 : 0);
3510 } else if (pbpctl_dev
->bp_ext_ver
== PXG2BPI_VER
)
3517 int normal_support(struct bpctl_dev
*pbpctl_dev
)
3519 int ret
= BP_NOT_CAP
;
3521 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
3522 if (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
) {
3524 ((((read_reg(pbpctl_dev
, PRODUCT_CAP_REG_ADDR
)) &
3525 NORMAL_UNSUPPORT_MASK
) ==
3526 NORMAL_UNSUPPORT_MASK
) ? 0 : 1);
3533 int get_bp_prod_caps(struct bpctl_dev
*pbpctl_dev
)
3535 if ((pbpctl_dev
->bp_caps
& SW_CTL_CAP
) &&
3536 (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
))
3537 return read_reg(pbpctl_dev
, PRODUCT_CAP_REG_ADDR
);
3542 int tap_flag_status(struct bpctl_dev
*pbpctl_dev
)
3545 if (pbpctl_dev
->bp_caps
& TAP_STATUS_CAP
) {
3546 if (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
)
3547 return ((((read_reg(pbpctl_dev
, STATUS_TAP_REG_ADDR
)) &
3548 TAP_FLAG_MASK
) == TAP_FLAG_MASK
) ? 1 : 0);
3554 int tap_flag_status_clear(struct bpctl_dev
*pbpctl_dev
)
3556 uint32_t status_reg
= 0;
3557 if (pbpctl_dev
->bp_caps
& TAP_STATUS_CAP
) {
3558 if (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
) {
3559 status_reg
= read_reg(pbpctl_dev
, STATUS_TAP_REG_ADDR
);
3560 write_reg(pbpctl_dev
, status_reg
& ~TAP_FLAG_MASK
,
3561 STATUS_TAP_REG_ADDR
);
3568 int tap_change_status(struct bpctl_dev
*pbpctl_dev
)
3570 int ret
= BP_NOT_CAP
;
3571 if (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
) {
3572 if (pbpctl_dev
->bp_caps
& TAP_CAP
) {
3573 if (pbpctl_dev
->bp_caps
& BP_CAP
) {
3574 ret
= tap_flag_status(pbpctl_dev
);
3575 tap_flag_status_clear(pbpctl_dev
);
3577 ret
= bypass_from_last_read(pbpctl_dev
);
3578 bypass_status_clear(pbpctl_dev
);
3585 int tap_off_status(struct bpctl_dev
*pbpctl_dev
)
3587 if (pbpctl_dev
->bp_caps
& TAP_CAP
) {
3588 if (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
)
3589 return ((((read_reg(pbpctl_dev
, STATUS_TAP_REG_ADDR
)) &
3590 TAP_OFF_MASK
) == TAP_OFF_MASK
) ? 1 : 0);
3595 int tap_status(struct bpctl_dev
*pbpctl_dev
)
3599 if (pbpctl_dev
->bp_caps
& TAP_CAP
) {
3600 struct bpctl_dev
*pbpctl_dev_b
= NULL
;
3602 pbpctl_dev_b
= get_status_port_fn(pbpctl_dev
);
3606 if (pbpctl_dev
->bp_ext_ver
>= 0x8) {
3607 if (!pbpctl_dev
->bp_10g
)
3608 return (((BPCTL_READ_REG
3611 BPCTLI_CTRL_EXT_SDP6_DATA
) !=
3614 ctrl_ext
= BP10G_READ_REG(pbpctl_dev_b
, EODSDP
);
3615 BP10G_WRITE_REG(pbpctl_dev_b
, EODSDP
,
3617 BP10G_SDP6_DATA_OUT
));
3618 return ((BP10G_READ_REG(pbpctl_dev_b
, EODSDP
) &
3619 BP10G_SDP6_DATA_IN
) != 0 ? 0 : 1);
3622 } else if (pbpctl_dev
->media_type
== BP_COPPER
)
3623 return (((BPCTL_READ_REG(pbpctl_dev
, CTRL
)) &
3624 BPCTLI_CTRL_SWDPIN0
) != 0 ? 1 : 0);
3626 if ((bypass_status_clear(pbpctl_dev
)) >= 0)
3627 return bypass_from_last_read(pbpctl_dev
);
3634 int default_pwron_tap_status(struct bpctl_dev
*pbpctl_dev
)
3636 if (pbpctl_dev
->bp_caps
& TAP_PWUP_CTL_CAP
) {
3637 if (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
)
3638 return ((((read_reg(pbpctl_dev
, STATUS_TAP_REG_ADDR
)) &
3639 DFLT_PWRON_TAP_MASK
) ==
3640 DFLT_PWRON_TAP_MASK
) ? 1 : 0);
3645 int dis_tap_cap_status(struct bpctl_dev
*pbpctl_dev
)
3647 if (pbpctl_dev
->bp_caps
& TAP_PWUP_CTL_CAP
) {
3648 if (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
)
3649 return ((((read_reg(pbpctl_dev
, STATUS_TAP_REG_ADDR
)) &
3650 DIS_TAP_CAP_MASK
) ==
3651 DIS_TAP_CAP_MASK
) ? 1 : 0);
3656 int disc_flag_status(struct bpctl_dev
*pbpctl_dev
)
3659 if (pbpctl_dev
->bp_caps
& DISC_CAP
) {
3660 if (pbpctl_dev
->bp_ext_ver
>= 0x8)
3661 return ((((read_reg(pbpctl_dev
, STATUS_DISC_REG_ADDR
)) &
3662 DISC_FLAG_MASK
) == DISC_FLAG_MASK
) ? 1 : 0);
3668 int disc_flag_status_clear(struct bpctl_dev
*pbpctl_dev
)
3670 uint32_t status_reg
= 0;
3671 if (pbpctl_dev
->bp_caps
& DISC_CAP
) {
3672 if (pbpctl_dev
->bp_ext_ver
>= 0x8) {
3673 status_reg
= read_reg(pbpctl_dev
, STATUS_DISC_REG_ADDR
);
3674 write_reg(pbpctl_dev
, status_reg
& ~DISC_FLAG_MASK
,
3675 STATUS_DISC_REG_ADDR
);
3682 int disc_change_status(struct bpctl_dev
*pbpctl_dev
)
3684 int ret
= BP_NOT_CAP
;
3685 if (pbpctl_dev
->bp_caps
& DISC_CAP
) {
3686 ret
= disc_flag_status(pbpctl_dev
);
3687 disc_flag_status_clear(pbpctl_dev
);
3693 int disc_off_status(struct bpctl_dev
*pbpctl_dev
)
3695 struct bpctl_dev
*pbpctl_dev_b
= NULL
;
3698 if (pbpctl_dev
->bp_caps
& DISC_CAP
) {
3699 pbpctl_dev_b
= get_status_port_fn(pbpctl_dev
);
3702 if (DISCF_IF_SERIES(pbpctl_dev
->subdevice
))
3703 return ((((read_reg(pbpctl_dev
, STATUS_DISC_REG_ADDR
)) &
3704 DISC_OFF_MASK
) == DISC_OFF_MASK
) ? 1 : 0);
3706 if (pbpctl_dev
->bp_i80
) {
3707 return (((BPCTL_READ_REG(pbpctl_dev_b
, CTRL_EXT
)) &
3708 BPCTLI_CTRL_EXT_SDP6_DATA
) != 0 ? 1 : 0);
3711 if (pbpctl_dev
->bp_540
) {
3712 ctrl_ext
= BP10G_READ_REG(pbpctl_dev_b
, ESDP
);
3713 return ((BP10G_READ_REG(pbpctl_dev_b
, ESDP
) &
3714 BP10G_SDP2_DATA
) != 0 ? 1 : 0);
3717 if (pbpctl_dev
->media_type
== BP_COPPER
) {
3720 return ((((read_reg(pbpctl_dev
, STATUS_DISC_REG_ADDR
)) &
3721 DISC_OFF_MASK
) == DISC_OFF_MASK
) ? 1 : 0);
3723 if (!pbpctl_dev
->bp_10g
)
3724 return (((BPCTL_READ_REG(pbpctl_dev_b
, CTRL
)) &
3725 BPCTLI_CTRL_SWDPIN1
) != 0 ? 1 : 0);
3727 return ((BP10G_READ_REG(pbpctl_dev_b
, ESDP
) &
3728 BP10G_SDP1_DATA
) != 0 ? 1 : 0);
3732 if (pbpctl_dev
->bp_10g9
) {
3733 ctrl_ext
= BP10G_READ_REG(pbpctl_dev_b
, I2CCTL
);
3734 BP10G_WRITE_REG(pbpctl_dev_b
, I2CCTL
,
3736 BP10G_I2C_DATA_OUT
));
3737 return ((BP10G_READ_REG(pbpctl_dev_b
, I2CCTL
) &
3738 BP10G_I2C_DATA_IN
) != 0 ? 1 : 0);
3740 } else if (pbpctl_dev
->bp_fiber5
) {
3741 return (((BPCTL_READ_REG(pbpctl_dev_b
, CTRL
)) &
3742 BPCTLI_CTRL_SWDPIN1
) != 0 ? 1 : 0);
3743 } else if (pbpctl_dev
->bp_10gb
) {
3745 BP10GB_READ_REG(pbpctl_dev
, MISC_REG_GPIO
);
3746 BP10GB_WRITE_REG(pbpctl_dev
, MISC_REG_GPIO
,
3747 (ctrl_ext
| BP10GB_GPIO3_OE_P1
)
3748 & ~(BP10GB_GPIO3_SET_P1
|
3749 BP10GB_GPIO3_CLR_P1
));
3751 return (((BP10GB_READ_REG
3753 MISC_REG_GPIO
)) & BP10GB_GPIO3_P1
) !=
3756 if (!pbpctl_dev
->bp_10g
) {
3758 return (((BPCTL_READ_REG
3761 BPCTLI_CTRL_EXT_SDP6_DATA
) !=
3764 ctrl_ext
= BP10G_READ_REG(pbpctl_dev_b
, EODSDP
);
3765 BP10G_WRITE_REG(pbpctl_dev_b
, EODSDP
,
3767 BP10G_SDP6_DATA_OUT
));
3768 return (((BP10G_READ_REG(pbpctl_dev_b
, EODSDP
))
3769 & BP10G_SDP6_DATA_IN
) != 0 ? 1 : 0);
3777 static int disc_status(struct bpctl_dev
*pbpctl_dev
)
3780 if (pbpctl_dev
->bp_caps
& DISC_CAP
) {
3781 ctrl
= disc_off_status(pbpctl_dev
);
3784 return ((ctrl
== 0) ? 1 : 0);
3789 int default_pwron_disc_status(struct bpctl_dev
*pbpctl_dev
)
3791 if (pbpctl_dev
->bp_caps
& DISC_PWUP_CTL_CAP
) {
3792 if (pbpctl_dev
->bp_ext_ver
>= 0x8)
3793 return ((((read_reg(pbpctl_dev
, STATUS_DISC_REG_ADDR
)) &
3794 DFLT_PWRON_DISC_MASK
) ==
3795 DFLT_PWRON_DISC_MASK
) ? 1 : 0);
3800 int dis_disc_cap_status(struct bpctl_dev
*pbpctl_dev
)
3802 if (pbpctl_dev
->bp_caps
& DIS_DISC_CAP
) {
3803 if (pbpctl_dev
->bp_ext_ver
>= 0x8)
3804 return ((((read_reg(pbpctl_dev
, STATUS_DISC_REG_ADDR
)) &
3805 DIS_DISC_CAP_MASK
) ==
3806 DIS_DISC_CAP_MASK
) ? 1 : 0);
3811 int disc_port_status(struct bpctl_dev
*pbpctl_dev
)
3813 int ret
= BP_NOT_CAP
;
3814 struct bpctl_dev
*pbpctl_dev_m
;
3816 if ((is_bypass_fn(pbpctl_dev
)) == 1)
3817 pbpctl_dev_m
= pbpctl_dev
;
3819 pbpctl_dev_m
= get_master_port_fn(pbpctl_dev
);
3820 if (pbpctl_dev_m
== NULL
)
3823 if (pbpctl_dev_m
->bp_caps_ex
& DISC_PORT_CAP_EX
) {
3824 if (is_bypass_fn(pbpctl_dev
) == 1) {
3825 return ((((read_reg(pbpctl_dev
, STATUS_TAP_REG_ADDR
)) &
3826 TX_DISA_MASK
) == TX_DISA_MASK
) ? 1 : 0);
3828 return ((((read_reg(pbpctl_dev
, STATUS_TAP_REG_ADDR
)) &
3829 TX_DISB_MASK
) == TX_DISB_MASK
) ? 1 : 0);
3835 int default_pwron_disc_port_status(struct bpctl_dev
*pbpctl_dev
)
3837 int ret
= BP_NOT_CAP
;
3838 struct bpctl_dev
*pbpctl_dev_m
;
3840 if ((is_bypass_fn(pbpctl_dev
)) == 1)
3841 pbpctl_dev_m
= pbpctl_dev
;
3843 pbpctl_dev_m
= get_master_port_fn(pbpctl_dev
);
3844 if (pbpctl_dev_m
== NULL
)
3847 if (pbpctl_dev_m
->bp_caps_ex
& DISC_PORT_CAP_EX
) {
3848 if (is_bypass_fn(pbpctl_dev
) == 1)
3850 /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
3853 /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
3859 int wdt_exp_mode_status(struct bpctl_dev
*pbpctl_dev
)
3861 if (pbpctl_dev
->bp_caps
& WD_CTL_CAP
) {
3862 if (pbpctl_dev
->bp_ext_ver
<= PXG2BPI_VER
)
3863 return 0; /* bypass mode */
3864 else if (pbpctl_dev
->bp_ext_ver
== PXG2TBPI_VER
)
3865 return 1; /* tap mode */
3866 else if (pbpctl_dev
->bp_ext_ver
>= PXE2TBPI_VER
) {
3867 if (pbpctl_dev
->bp_ext_ver
>= 0x8) {
3870 STATUS_DISC_REG_ADDR
)) &
3871 WDTE_DISC_BPN_MASK
) == WDTE_DISC_BPN_MASK
)
3874 return ((((read_reg(pbpctl_dev
, STATUS_TAP_REG_ADDR
)) &
3875 WDTE_TAP_BPN_MASK
) ==
3876 WDTE_TAP_BPN_MASK
) ? 1 : 0);
3882 int tpl2_flag_status(struct bpctl_dev
*pbpctl_dev
)
3885 if (pbpctl_dev
->bp_caps_ex
& TPL2_CAP_EX
) {
3886 return ((((read_reg(pbpctl_dev
, STATUS_DISC_REG_ADDR
)) &
3887 TPL2_FLAG_MASK
) == TPL2_FLAG_MASK
) ? 1 : 0);
3893 int tpl_hw_status(struct bpctl_dev
*pbpctl_dev
)
3895 struct bpctl_dev
*pbpctl_dev_b
= NULL
;
3897 pbpctl_dev_b
= get_status_port_fn(pbpctl_dev
);
3901 if (TPL_IF_SERIES(pbpctl_dev
->subdevice
))
3902 return (((BPCTL_READ_REG(pbpctl_dev
, CTRL
)) &
3903 BPCTLI_CTRL_SWDPIN0
) != 0 ? 1 : 0);
3908 int bp_wait_at_pwup_status(struct bpctl_dev
*pbpctl_dev
)
3910 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
3911 if (pbpctl_dev
->bp_ext_ver
>= 0x8)
3912 return ((((read_reg(pbpctl_dev
, CONT_CONFIG_REG_ADDR
)) &
3913 WAIT_AT_PWUP_MASK
) ==
3914 WAIT_AT_PWUP_MASK
) ? 1 : 0);
3919 int bp_hw_reset_status(struct bpctl_dev
*pbpctl_dev
)
3922 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
3924 if (pbpctl_dev
->bp_ext_ver
>= 0x8)
3925 return ((((read_reg(pbpctl_dev
, CONT_CONFIG_REG_ADDR
)) &
3926 EN_HW_RESET_MASK
) ==
3927 EN_HW_RESET_MASK
) ? 1 : 0);
3933 int std_nic_status(struct bpctl_dev
*pbpctl_dev
)
3937 if (pbpctl_dev
->bp_caps
& STD_NIC_CAP
) {
3938 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
))
3940 if (pbpctl_dev
->bp_ext_ver
>= BP_FW_EXT_VER8
) {
3941 return ((((read_reg(pbpctl_dev
, STATUS_DISC_REG_ADDR
)) &
3942 STD_NIC_ON_MASK
) == STD_NIC_ON_MASK
) ? 1 : 0);
3945 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
3946 if (pbpctl_dev
->bp_caps
& BP_CAP
) {
3948 read_reg(pbpctl_dev
, STATUS_REG_ADDR
);
3949 if (((!(status_val
& WDT_EN_MASK
))
3950 && ((status_val
& STD_NIC_MASK
) ==
3956 if (pbpctl_dev
->bp_caps
& TAP_CAP
) {
3958 read_reg(pbpctl_dev
, STATUS_TAP_REG_ADDR
);
3959 if ((status_val
& STD_NIC_TAP_MASK
) ==
3965 if (pbpctl_dev
->bp_caps
& TAP_CAP
) {
3966 if ((disc_off_status(pbpctl_dev
)))
3978 /******************************************************/
3979 /**************SW_INIT*********************************/
3980 /******************************************************/
3981 void bypass_caps_init(struct bpctl_dev
*pbpctl_dev
)
3983 u_int32_t ctrl_ext
= 0;
3984 struct bpctl_dev
*pbpctl_dev_m
= NULL
;
3988 if (!(INTEL_IF_SERIES(adapter
->bp_device_block
.subdevice
))) {
3989 ret
= read_reg(pbpctl_dev
, VER_REG_ADDR
);
3990 printk("VER_REG reg1=%x\n", ret
);
3991 ret
= read_reg(pbpctl_dev
, PRODUCT_CAP_REG_ADDR
);
3992 printk("PRODUCT_CAP reg=%x\n", ret
);
3993 ret
= read_reg(pbpctl_dev
, STATUS_TAP_REG_ADDR
);
3994 printk("STATUS_TAP reg1=%x\n", ret
);
3995 ret
= read_reg(pbpctl_dev
, 0x7);
3996 printk("SIG_REG reg1=%x\n", ret
);
3997 ret
= read_reg(pbpctl_dev
, STATUS_REG_ADDR
);
3998 printk("STATUS_REG_ADDR=%x\n", ret
);
3999 ret
= read_reg(pbpctl_dev
, WDT_REG_ADDR
);
4000 printk("WDT_REG_ADDR=%x\n", ret
);
4001 ret
= read_reg(pbpctl_dev
, TMRL_REG_ADDR
);
4002 printk("TMRL_REG_ADDR=%x\n", ret
);
4003 ret
= read_reg(pbpctl_dev
, TMRH_REG_ADDR
);
4004 printk("TMRH_REG_ADDR=%x\n", ret
);
4007 if ((pbpctl_dev
->bp_fiber5
) || (pbpctl_dev
->bp_10g9
)) {
4008 pbpctl_dev
->media_type
= BP_FIBER
;
4009 } else if (pbpctl_dev
->bp_10gb
) {
4010 if (BP10GB_CX4_SERIES(pbpctl_dev
->subdevice
))
4011 pbpctl_dev
->media_type
= BP_CX4
;
4013 pbpctl_dev
->media_type
= BP_FIBER
;
4017 else if (pbpctl_dev
->bp_540
)
4018 pbpctl_dev
->media_type
= BP_NONE
;
4019 else if (!pbpctl_dev
->bp_10g
) {
4021 ctrl_ext
= BPCTL_READ_REG(pbpctl_dev
, CTRL_EXT
);
4022 if ((ctrl_ext
& BPCTLI_CTRL_EXT_LINK_MODE_MASK
) == 0x0)
4023 pbpctl_dev
->media_type
= BP_COPPER
;
4025 pbpctl_dev
->media_type
= BP_FIBER
;
4028 if (BP10G_CX4_SERIES(pbpctl_dev
->subdevice
))
4029 pbpctl_dev
->media_type
= BP_CX4
;
4031 pbpctl_dev
->media_type
= BP_FIBER
;
4034 if (is_bypass_fn(pbpctl_dev
)) {
4036 pbpctl_dev
->bp_caps
|= BP_PWOFF_ON_CAP
;
4037 if (pbpctl_dev
->media_type
== BP_FIBER
)
4038 pbpctl_dev
->bp_caps
|=
4039 (TX_CTL_CAP
| TX_STATUS_CAP
| TPL_CAP
);
4041 if (TPL_IF_SERIES(pbpctl_dev
->subdevice
))
4042 pbpctl_dev
->bp_caps
|= TPL_CAP
;
4044 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
)) {
4045 pbpctl_dev
->bp_caps
|=
4046 (BP_CAP
| BP_STATUS_CAP
| SW_CTL_CAP
|
4047 BP_PWUP_ON_CAP
| BP_PWUP_OFF_CAP
| BP_PWOFF_OFF_CAP
4048 | WD_CTL_CAP
| WD_STATUS_CAP
| STD_NIC_CAP
|
4051 pbpctl_dev
->bp_ext_ver
= OLD_IF_VER
;
4055 if ((pbpctl_dev
->bp_fw_ver
== 0xff) &&
4056 OLD_IF_SERIES(pbpctl_dev
->subdevice
)) {
4058 pbpctl_dev
->bp_caps
|=
4059 (BP_CAP
| BP_STATUS_CAP
| BP_STATUS_CHANGE_CAP
|
4060 SW_CTL_CAP
| BP_PWUP_ON_CAP
| WD_CTL_CAP
|
4061 WD_STATUS_CAP
| WD_TIMEOUT_CAP
);
4063 pbpctl_dev
->bp_ext_ver
= OLD_IF_VER
;
4068 switch (pbpctl_dev
->bp_fw_ver
) {
4071 pbpctl_dev
->bp_ext_ver
=
4073 bp_fw_ver
& EXT_VER_MASK
);
4077 if ((bypass_sign_check(pbpctl_dev
)) !=
4079 pbpctl_dev
->bp_caps
= 0;
4082 pbpctl_dev
->bp_ext_ver
=
4084 bp_fw_ver
& EXT_VER_MASK
);
4089 if (pbpctl_dev
->bp_ext_ver
== PXG2BPI_VER
)
4090 pbpctl_dev
->bp_caps
|=
4091 (BP_CAP
| BP_STATUS_CAP
| BP_STATUS_CHANGE_CAP
|
4092 SW_CTL_CAP
| BP_DIS_CAP
| BP_DIS_STATUS_CAP
|
4093 BP_PWUP_ON_CAP
| BP_PWUP_OFF_CAP
| BP_PWUP_CTL_CAP
4094 | WD_CTL_CAP
| STD_NIC_CAP
| WD_STATUS_CAP
|
4096 else if (pbpctl_dev
->bp_ext_ver
>= PXG2TBPI_VER
) {
4099 pbpctl_dev
->bp_caps
|=
4100 (SW_CTL_CAP
| WD_CTL_CAP
| WD_STATUS_CAP
|
4102 cap_reg
= get_bp_prod_caps(pbpctl_dev
);
4104 if ((cap_reg
& NORMAL_UNSUPPORT_MASK
) ==
4105 NORMAL_UNSUPPORT_MASK
)
4106 pbpctl_dev
->bp_caps
|= NIC_CAP_NEG
;
4108 pbpctl_dev
->bp_caps
|= STD_NIC_CAP
;
4110 if ((normal_support(pbpctl_dev
)) == 1)
4112 pbpctl_dev
->bp_caps
|= STD_NIC_CAP
;
4115 pbpctl_dev
->bp_caps
|= NIC_CAP_NEG
;
4116 if ((cap_reg
& BYPASS_SUPPORT_MASK
) ==
4117 BYPASS_SUPPORT_MASK
) {
4118 pbpctl_dev
->bp_caps
|=
4119 (BP_CAP
| BP_STATUS_CAP
|
4120 BP_STATUS_CHANGE_CAP
| BP_DIS_CAP
|
4121 BP_DIS_STATUS_CAP
| BP_PWUP_ON_CAP
|
4122 BP_PWUP_OFF_CAP
| BP_PWUP_CTL_CAP
);
4123 if (pbpctl_dev
->bp_ext_ver
>= BP_FW_EXT_VER7
)
4124 pbpctl_dev
->bp_caps
|=
4125 BP_PWOFF_ON_CAP
| BP_PWOFF_OFF_CAP
|
4128 if ((cap_reg
& TAP_SUPPORT_MASK
) == TAP_SUPPORT_MASK
) {
4129 pbpctl_dev
->bp_caps
|=
4130 (TAP_CAP
| TAP_STATUS_CAP
|
4131 TAP_STATUS_CHANGE_CAP
| TAP_DIS_CAP
|
4132 TAP_DIS_STATUS_CAP
| TAP_PWUP_ON_CAP
|
4133 TAP_PWUP_OFF_CAP
| TAP_PWUP_CTL_CAP
);
4135 if (pbpctl_dev
->bp_ext_ver
>= BP_FW_EXT_VER8
) {
4136 if ((cap_reg
& DISC_SUPPORT_MASK
) ==
4138 pbpctl_dev
->bp_caps
|=
4139 (DISC_CAP
| DISC_DIS_CAP
|
4141 if ((cap_reg
& TPL2_SUPPORT_MASK
) ==
4142 TPL2_SUPPORT_MASK
) {
4143 pbpctl_dev
->bp_caps_ex
|= TPL2_CAP_EX
;
4144 pbpctl_dev
->bp_caps
|= TPL_CAP
;
4145 pbpctl_dev
->bp_tpl_flag
=
4146 tpl2_flag_status(pbpctl_dev
);
4151 if (pbpctl_dev
->bp_ext_ver
>= BP_FW_EXT_VER9
) {
4152 if ((cap_reg
& DISC_PORT_SUPPORT_MASK
) ==
4153 DISC_PORT_SUPPORT_MASK
) {
4154 pbpctl_dev
->bp_caps_ex
|=
4156 pbpctl_dev
->bp_caps
|=
4157 (TX_CTL_CAP
| TX_STATUS_CAP
);
4163 if (pbpctl_dev
->bp_ext_ver
>= PXG2BPI_VER
) {
4164 if ((read_reg(pbpctl_dev
, STATUS_REG_ADDR
)) &
4166 pbpctl_dev
->wdt_status
= WDT_STATUS_EN
;
4168 pbpctl_dev
->wdt_status
= WDT_STATUS_DIS
;
4171 } else if ((P2BPFI_IF_SERIES(pbpctl_dev
->subdevice
)) ||
4172 (PEGF5_IF_SERIES(pbpctl_dev
->subdevice
)) ||
4173 (PEGF80_IF_SERIES(pbpctl_dev
->subdevice
)) ||
4174 (BP10G9_IF_SERIES(pbpctl_dev
->subdevice
))) {
4175 pbpctl_dev
->bp_caps
|= (TX_CTL_CAP
| TX_STATUS_CAP
);
4177 if ((pbpctl_dev
->subdevice
& 0xa00) == 0xa00)
4178 pbpctl_dev
->bp_caps
|= (TX_CTL_CAP
| TX_STATUS_CAP
);
4179 if (PEG5_IF_SERIES(pbpctl_dev
->subdevice
))
4180 pbpctl_dev
->bp_caps
|= (TX_CTL_CAP
| TX_STATUS_CAP
);
4182 if (BP10GB_IF_SERIES(pbpctl_dev
->subdevice
))
4183 pbpctl_dev
->bp_caps
&= ~(TX_CTL_CAP
| TX_STATUS_CAP
);
4185 pbpctl_dev_m
= get_master_port_fn(pbpctl_dev
);
4186 if (pbpctl_dev_m
!= NULL
) {
4188 if (pbpctl_dev_m
->bp_ext_ver
>= 0x9) {
4189 cap_reg
= get_bp_prod_caps(pbpctl_dev_m
);
4190 if ((cap_reg
& DISC_PORT_SUPPORT_MASK
) ==
4191 DISC_PORT_SUPPORT_MASK
)
4192 pbpctl_dev
->bp_caps
|=
4193 (TX_CTL_CAP
| TX_STATUS_CAP
);
4194 pbpctl_dev
->bp_caps_ex
|= DISC_PORT_CAP_EX
;
4199 int bypass_off_init(struct bpctl_dev
*pbpctl_dev
)
4201 int ret
= cmnd_on(pbpctl_dev
);
4204 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
))
4205 return dis_bypass_cap(pbpctl_dev
);
4206 wdt_off(pbpctl_dev
);
4207 if (pbpctl_dev
->bp_caps
& BP_CAP
)
4208 bypass_off(pbpctl_dev
);
4209 if (pbpctl_dev
->bp_caps
& TAP_CAP
)
4210 tap_off(pbpctl_dev
);
4211 cmnd_off(pbpctl_dev
);
4215 void remove_bypass_wd_auto(struct bpctl_dev
*pbpctl_dev
)
4218 struct bpctl_dev
*pbpctl_dev_sl
= NULL
;
4221 if (pbpctl_dev
->bp_caps
& WD_CTL_CAP
) {
4223 del_timer_sync(&pbpctl_dev
->bp_timer
);
4225 pbpctl_dev_sl
= get_status_port_fn(pbpctl_dev
);
4226 if (pbpctl_dev_sl
&& (pbpctl_dev_sl
->ndev
)) {
4227 if ((pbpctl_dev_sl
->ndev
->netdev_ops
)
4228 && (pbpctl_dev_sl
->old_ops
)) {
4230 pbpctl_dev_sl
->ndev
->netdev_ops
=
4231 pbpctl_dev_sl
->old_ops
;
4232 pbpctl_dev_sl
->old_ops
= NULL
;
4244 int init_bypass_wd_auto(struct bpctl_dev
*pbpctl_dev
)
4246 if (pbpctl_dev
->bp_caps
& WD_CTL_CAP
) {
4247 init_timer(&pbpctl_dev
->bp_timer
);
4248 pbpctl_dev
->bp_timer
.function
= &wd_reset_timer
;
4249 pbpctl_dev
->bp_timer
.data
= (unsigned long)pbpctl_dev
;
4256 int bp_hard_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
4258 struct bpctl_dev
*pbpctl_dev
= NULL
, *pbpctl_dev_m
= NULL
;
4260 struct ethhdr
*eth
= (struct ethhdr
*)skb
->data
;
4263 ((bpctl_dev_arr
[idx_dev
].ndev
!= NULL
) && (idx_dev
< device_num
));
4265 if (bpctl_dev_arr
[idx_dev
].ndev
== dev
) {
4266 pbpctl_dev
= &bpctl_dev_arr
[idx_dev
];
4272 if ((htons(ETH_P_BPTEST
) == eth
->h_proto
)) {
4274 pbpctl_dev_m
= get_master_port_fn(pbpctl_dev
);
4277 if (bypass_status(pbpctl_dev_m
)) {
4278 cmnd_on(pbpctl_dev_m
);
4279 bypass_off(pbpctl_dev_m
);
4280 cmnd_off(pbpctl_dev_m
);
4282 wdt_timer_reload(pbpctl_dev_m
);
4284 dev_kfree_skb_irq(skb
);
4287 return pbpctl_dev
->hard_start_xmit_save(skb
, dev
);
4291 int set_bypass_wd_auto(struct bpctl_dev
*pbpctl_dev
, unsigned int param
)
4293 if (pbpctl_dev
->bp_caps
& WD_CTL_CAP
) {
4294 if (pbpctl_dev
->reset_time
!= param
) {
4295 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
))
4296 pbpctl_dev
->reset_time
=
4298 WDT_AUTO_MIN_INT
) ? WDT_AUTO_MIN_INT
:
4301 pbpctl_dev
->reset_time
= param
;
4303 mod_timer(&pbpctl_dev
->bp_timer
, jiffies
);
4310 int get_bypass_wd_auto(struct bpctl_dev
*pbpctl_dev
)
4312 if (pbpctl_dev
->bp_caps
& WD_CTL_CAP
)
4313 return pbpctl_dev
->reset_time
;
4320 int set_bp_self_test(struct bpctl_dev
*pbpctl_dev
, unsigned int param
)
4322 struct bpctl_dev
*pbpctl_dev_sl
= NULL
;
4324 if (pbpctl_dev
->bp_caps
& WD_CTL_CAP
) {
4325 pbpctl_dev
->bp_self_test_flag
= param
== 0 ? 0 : 1;
4326 pbpctl_dev_sl
= get_status_port_fn(pbpctl_dev
);
4328 if ((pbpctl_dev_sl
->ndev
) && (pbpctl_dev_sl
->ndev
->netdev_ops
)) {
4330 if (pbpctl_dev
->bp_self_test_flag
== 1) {
4332 pbpctl_dev_sl
->old_ops
=
4333 pbpctl_dev_sl
->ndev
->netdev_ops
;
4334 pbpctl_dev_sl
->new_ops
=
4335 *pbpctl_dev_sl
->old_ops
;
4336 pbpctl_dev_sl
->new_ops
.ndo_start_xmit
=
4338 pbpctl_dev_sl
->ndev
->netdev_ops
=
4339 &pbpctl_dev_sl
->new_ops
;
4341 } else if (pbpctl_dev_sl
->old_ops
) {
4342 pbpctl_dev_sl
->ndev
->netdev_ops
=
4343 pbpctl_dev_sl
->old_ops
;
4344 pbpctl_dev_sl
->old_ops
= NULL
;
4349 set_bypass_wd_auto(pbpctl_dev
, param
);
4355 int get_bp_self_test(struct bpctl_dev
*pbpctl_dev
)
4358 if (pbpctl_dev
->bp_caps
& WD_CTL_CAP
) {
4359 if (pbpctl_dev
->bp_self_test_flag
== 1)
4360 return pbpctl_dev
->reset_time
;
4369 /**************************************************************/
4370 /************************* API ********************************/
4371 /**************************************************************/
4373 int is_bypass_fn(struct bpctl_dev
*pbpctl_dev
)
4378 return (((pbpctl_dev
->func
== 0) || (pbpctl_dev
->func
== 2)) ? 1 : 0);
4381 int set_bypass_fn(struct bpctl_dev
*pbpctl_dev
, int bypass_mode
)
4385 if (!(pbpctl_dev
->bp_caps
& BP_CAP
))
4387 ret
= cmnd_on(pbpctl_dev
);
4391 ret
= bypass_off(pbpctl_dev
);
4393 ret
= bypass_on(pbpctl_dev
);
4394 cmnd_off(pbpctl_dev
);
4399 int get_bypass_fn(struct bpctl_dev
*pbpctl_dev
)
4401 return bypass_status(pbpctl_dev
);
4404 int get_bypass_change_fn(struct bpctl_dev
*pbpctl_dev
)
4409 return bypass_change_status(pbpctl_dev
);
4412 int set_dis_bypass_fn(struct bpctl_dev
*pbpctl_dev
, int dis_param
)
4418 if (!(pbpctl_dev
->bp_caps
& BP_DIS_CAP
))
4420 ret
= cmnd_on(pbpctl_dev
);
4424 ret
= dis_bypass_cap(pbpctl_dev
);
4426 ret
= en_bypass_cap(pbpctl_dev
);
4427 cmnd_off(pbpctl_dev
);
4431 int get_dis_bypass_fn(struct bpctl_dev
*pbpctl_dev
)
4436 return dis_bypass_cap_status(pbpctl_dev
);
4439 int set_bypass_pwoff_fn(struct bpctl_dev
*pbpctl_dev
, int bypass_mode
)
4445 if (!(pbpctl_dev
->bp_caps
& BP_PWOFF_CTL_CAP
))
4447 ret
= cmnd_on(pbpctl_dev
);
4451 ret
= bypass_state_pwroff(pbpctl_dev
);
4453 ret
= normal_state_pwroff(pbpctl_dev
);
4454 cmnd_off(pbpctl_dev
);
4458 int get_bypass_pwoff_fn(struct bpctl_dev
*pbpctl_dev
)
4463 return default_pwroff_status(pbpctl_dev
);
4466 int set_bypass_pwup_fn(struct bpctl_dev
*pbpctl_dev
, int bypass_mode
)
4472 if (!(pbpctl_dev
->bp_caps
& BP_PWUP_CTL_CAP
))
4474 ret
= cmnd_on(pbpctl_dev
);
4478 ret
= bypass_state_pwron(pbpctl_dev
);
4480 ret
= normal_state_pwron(pbpctl_dev
);
4481 cmnd_off(pbpctl_dev
);
4485 int get_bypass_pwup_fn(struct bpctl_dev
*pbpctl_dev
)
4490 return default_pwron_status(pbpctl_dev
);
4493 int set_bypass_wd_fn(struct bpctl_dev
*pbpctl_dev
, int timeout
)
4499 if (!(pbpctl_dev
->bp_caps
& WD_CTL_CAP
))
4502 ret
= cmnd_on(pbpctl_dev
);
4506 ret
= wdt_off(pbpctl_dev
);
4508 wdt_on(pbpctl_dev
, timeout
);
4509 ret
= pbpctl_dev
->bypass_timer_interval
;
4511 cmnd_off(pbpctl_dev
);
4515 int get_bypass_wd_fn(struct bpctl_dev
*pbpctl_dev
, int *timeout
)
4520 return wdt_programmed(pbpctl_dev
, timeout
);
4523 int get_wd_expire_time_fn(struct bpctl_dev
*pbpctl_dev
, int *time_left
)
4528 return wdt_timer(pbpctl_dev
, time_left
);
4531 int reset_bypass_wd_timer_fn(struct bpctl_dev
*pbpctl_dev
)
4536 return wdt_timer_reload(pbpctl_dev
);
4539 int get_wd_set_caps_fn(struct bpctl_dev
*pbpctl_dev
)
4543 unsigned int step_value
= TIMEOUT_MAX_STEP
+ 1, bit_cnt
= 0;
4547 if (INTEL_IF_SERIES(pbpctl_dev
->subdevice
))
4550 while ((step_value
>>= 1))
4553 if (is_bypass_fn(pbpctl_dev
)) {
4555 WD_STEP_COUNT_MASK(bit_cnt
) | WDT_STEP_TIME
|
4556 WD_MIN_TIME_MASK(TIMEOUT_UNIT
/ 100);
4563 int set_std_nic_fn(struct bpctl_dev
*pbpctl_dev
, int nic_mode
)
4569 if (!(pbpctl_dev
->bp_caps
& STD_NIC_CAP
))
4572 ret
= cmnd_on(pbpctl_dev
);
4576 ret
= std_nic_on(pbpctl_dev
);
4578 ret
= std_nic_off(pbpctl_dev
);
4579 cmnd_off(pbpctl_dev
);
4583 int get_std_nic_fn(struct bpctl_dev
*pbpctl_dev
)
4588 return std_nic_status(pbpctl_dev
);
4591 int set_tap_fn(struct bpctl_dev
*pbpctl_dev
, int tap_mode
)
4596 if ((pbpctl_dev
->bp_caps
& TAP_CAP
) && ((cmnd_on(pbpctl_dev
)) >= 0)) {
4598 tap_off(pbpctl_dev
);
4601 cmnd_off(pbpctl_dev
);
4607 int get_tap_fn(struct bpctl_dev
*pbpctl_dev
)
4612 return tap_status(pbpctl_dev
);
4615 int set_tap_pwup_fn(struct bpctl_dev
*pbpctl_dev
, int tap_mode
)
4621 if ((pbpctl_dev
->bp_caps
& TAP_PWUP_CTL_CAP
)
4622 && ((cmnd_on(pbpctl_dev
)) >= 0)) {
4624 ret
= tap_state_pwron(pbpctl_dev
);
4626 ret
= normal_state_pwron(pbpctl_dev
);
4627 cmnd_off(pbpctl_dev
);
4633 int get_tap_pwup_fn(struct bpctl_dev
*pbpctl_dev
)
4639 ret
= default_pwron_tap_status(pbpctl_dev
);
4642 return ((ret
== 0) ? 1 : 0);
4645 int get_tap_change_fn(struct bpctl_dev
*pbpctl_dev
)
4650 return tap_change_status(pbpctl_dev
);
4653 int set_dis_tap_fn(struct bpctl_dev
*pbpctl_dev
, int dis_param
)
4659 if ((pbpctl_dev
->bp_caps
& TAP_DIS_CAP
) && ((cmnd_on(pbpctl_dev
)) >= 0)) {
4661 ret
= dis_tap_cap(pbpctl_dev
);
4663 ret
= en_tap_cap(pbpctl_dev
);
4664 cmnd_off(pbpctl_dev
);
4670 int get_dis_tap_fn(struct bpctl_dev
*pbpctl_dev
)
4675 return dis_tap_cap_status(pbpctl_dev
);
4678 int set_disc_fn(struct bpctl_dev
*pbpctl_dev
, int disc_mode
)
4683 if ((pbpctl_dev
->bp_caps
& DISC_CAP
) && ((cmnd_on(pbpctl_dev
)) >= 0)) {
4685 disc_off(pbpctl_dev
);
4687 disc_on(pbpctl_dev
);
4688 cmnd_off(pbpctl_dev
);
4695 int get_disc_fn(struct bpctl_dev
*pbpctl_dev
)
4701 ret
= disc_status(pbpctl_dev
);
4706 int set_disc_pwup_fn(struct bpctl_dev
*pbpctl_dev
, int disc_mode
)
4712 if ((pbpctl_dev
->bp_caps
& DISC_PWUP_CTL_CAP
)
4713 && ((cmnd_on(pbpctl_dev
)) >= 0)) {
4715 ret
= disc_state_pwron(pbpctl_dev
);
4717 ret
= normal_state_pwron(pbpctl_dev
);
4718 cmnd_off(pbpctl_dev
);
4724 int get_disc_pwup_fn(struct bpctl_dev
*pbpctl_dev
)
4730 ret
= default_pwron_disc_status(pbpctl_dev
);
4731 return (ret
== 0 ? 1 : (ret
< 0 ? BP_NOT_CAP
: 0));
4734 int get_disc_change_fn(struct bpctl_dev
*pbpctl_dev
)
4740 ret
= disc_change_status(pbpctl_dev
);
4744 int set_dis_disc_fn(struct bpctl_dev
*pbpctl_dev
, int dis_param
)
4750 if ((pbpctl_dev
->bp_caps
& DISC_DIS_CAP
)
4751 && ((cmnd_on(pbpctl_dev
)) >= 0)) {
4753 ret
= dis_disc_cap(pbpctl_dev
);
4755 ret
= en_disc_cap(pbpctl_dev
);
4756 cmnd_off(pbpctl_dev
);
4762 int get_dis_disc_fn(struct bpctl_dev
*pbpctl_dev
)
4768 ret
= dis_disc_cap_status(pbpctl_dev
);
4773 int set_disc_port_fn(struct bpctl_dev
*pbpctl_dev
, int disc_mode
)
4775 int ret
= BP_NOT_CAP
;
4780 ret
= disc_port_off(pbpctl_dev
);
4782 ret
= disc_port_on(pbpctl_dev
);
4787 int get_disc_port_fn(struct bpctl_dev
*pbpctl_dev
)
4792 return disc_port_status(pbpctl_dev
);
4795 int set_disc_port_pwup_fn(struct bpctl_dev
*pbpctl_dev
, int disc_mode
)
4797 int ret
= BP_NOT_CAP
;
4802 ret
= normal_port_state_pwron(pbpctl_dev
);
4804 ret
= disc_port_state_pwron(pbpctl_dev
);
4809 int get_disc_port_pwup_fn(struct bpctl_dev
*pbpctl_dev
)
4815 ret
= default_pwron_disc_port_status(pbpctl_dev
);
4818 return ((ret
== 0) ? 1 : 0);
4821 int get_wd_exp_mode_fn(struct bpctl_dev
*pbpctl_dev
)
4826 return wdt_exp_mode_status(pbpctl_dev
);
4829 int set_wd_exp_mode_fn(struct bpctl_dev
*pbpctl_dev
, int param
)
4834 return wdt_exp_mode(pbpctl_dev
, param
);
4837 int reset_cont_fn(struct bpctl_dev
*pbpctl_dev
)
4843 ret
= cmnd_on(pbpctl_dev
);
4846 return reset_cont(pbpctl_dev
);
4849 int set_tx_fn(struct bpctl_dev
*pbpctl_dev
, int tx_state
)
4852 struct bpctl_dev
*pbpctl_dev_b
= NULL
;
4856 if ((pbpctl_dev
->bp_caps
& TPL_CAP
) &&
4857 (pbpctl_dev
->bp_caps
& SW_CTL_CAP
)) {
4858 if ((pbpctl_dev
->bp_tpl_flag
))
4861 pbpctl_dev_b
= get_master_port_fn(pbpctl_dev
);
4863 (pbpctl_dev_b
->bp_caps
& TPL_CAP
) &&
4864 (pbpctl_dev_b
->bp_tpl_flag
))
4867 return set_tx(pbpctl_dev
, tx_state
);
4870 int set_bp_force_link_fn(int dev_num
, int tx_state
)
4872 static struct bpctl_dev
*bpctl_dev_curr
;
4874 if ((dev_num
< 0) || (dev_num
> device_num
)
4875 || (bpctl_dev_arr
[dev_num
].pdev
== NULL
))
4877 bpctl_dev_curr
= &bpctl_dev_arr
[dev_num
];
4879 return set_bp_force_link(bpctl_dev_curr
, tx_state
);
4882 int set_wd_autoreset_fn(struct bpctl_dev
*pbpctl_dev
, int param
)
4887 return set_bypass_wd_auto(pbpctl_dev
, param
);
4890 int get_wd_autoreset_fn(struct bpctl_dev
*pbpctl_dev
)
4895 return get_bypass_wd_auto(pbpctl_dev
);
4899 int set_bp_self_test_fn(struct bpctl_dev
*pbpctl_dev
, int param
)
4904 return set_bp_self_test(pbpctl_dev
, param
);
4907 int get_bp_self_test_fn(struct bpctl_dev
*pbpctl_dev
)
4912 return get_bp_self_test(pbpctl_dev
);
4917 int get_bypass_caps_fn(struct bpctl_dev
*pbpctl_dev
)
4922 return pbpctl_dev
->bp_caps
;
4926 int get_bypass_slave_fn(struct bpctl_dev
*pbpctl_dev
, struct bpctl_dev
**pbpctl_dev_out
)
4932 if ((pbpctl_dev
->func
== 0) || (pbpctl_dev
->func
== 2)) {
4934 ((bpctl_dev_arr
[idx_dev
].pdev
!= NULL
)
4935 && (idx_dev
< device_num
)); idx_dev
++) {
4936 if ((bpctl_dev_arr
[idx_dev
].bus
== pbpctl_dev
->bus
)
4937 && (bpctl_dev_arr
[idx_dev
].slot
==
4938 pbpctl_dev
->slot
)) {
4939 if ((pbpctl_dev
->func
== 0)
4940 && (bpctl_dev_arr
[idx_dev
].func
== 1)) {
4942 &bpctl_dev_arr
[idx_dev
];
4945 if ((pbpctl_dev
->func
== 2) &&
4946 (bpctl_dev_arr
[idx_dev
].func
== 3)) {
4948 &bpctl_dev_arr
[idx_dev
];
4958 int is_bypass(struct bpctl_dev
*pbpctl_dev
)
4963 if ((pbpctl_dev
->func
== 0) || (pbpctl_dev
->func
== 2))
4969 int get_tx_fn(struct bpctl_dev
*pbpctl_dev
)
4971 struct bpctl_dev
*pbpctl_dev_b
= NULL
;
4975 if ((pbpctl_dev
->bp_caps
& TPL_CAP
) &&
4976 (pbpctl_dev
->bp_caps
& SW_CTL_CAP
)) {
4977 if ((pbpctl_dev
->bp_tpl_flag
))
4980 pbpctl_dev_b
= get_master_port_fn(pbpctl_dev
);
4982 (pbpctl_dev_b
->bp_caps
& TPL_CAP
) &&
4983 (pbpctl_dev_b
->bp_tpl_flag
))
4986 return tx_status(pbpctl_dev
);
4989 int get_bp_force_link_fn(int dev_num
)
4991 static struct bpctl_dev
*bpctl_dev_curr
;
4993 if ((dev_num
< 0) || (dev_num
> device_num
)
4994 || (bpctl_dev_arr
[dev_num
].pdev
== NULL
))
4996 bpctl_dev_curr
= &bpctl_dev_arr
[dev_num
];
4998 return bp_force_link_status(bpctl_dev_curr
);
5001 static int get_bypass_link_status(struct bpctl_dev
*pbpctl_dev
)
5006 if (pbpctl_dev
->media_type
== BP_FIBER
)
5007 return ((BPCTL_READ_REG(pbpctl_dev
, CTRL
) &
5008 BPCTLI_CTRL_SWDPIN1
));
5010 return ((BPCTL_READ_REG(pbpctl_dev
, STATUS
) &
5015 static void bp_tpl_timer_fn(unsigned long param
)
5017 struct bpctl_dev
*pbpctl_dev
= (struct bpctl_dev
*) param
;
5018 uint32_t link1
, link2
;
5019 struct bpctl_dev
*pbpctl_dev_b
= NULL
;
5021 pbpctl_dev_b
= get_status_port_fn(pbpctl_dev
);
5025 if (!pbpctl_dev
->bp_tpl_flag
) {
5026 set_tx(pbpctl_dev_b
, 1);
5027 set_tx(pbpctl_dev
, 1);
5030 link1
= get_bypass_link_status(pbpctl_dev
);
5032 link2
= get_bypass_link_status(pbpctl_dev_b
);
5033 if ((link1
) && (tx_status(pbpctl_dev
))) {
5034 if ((!link2
) && (tx_status(pbpctl_dev_b
)))
5035 set_tx(pbpctl_dev
, 0);
5036 else if (!tx_status(pbpctl_dev_b
))
5037 set_tx(pbpctl_dev_b
, 1);
5038 } else if ((!link1
) && (tx_status(pbpctl_dev
))) {
5039 if ((link2
) && (tx_status(pbpctl_dev_b
)))
5040 set_tx(pbpctl_dev_b
, 0);
5041 } else if ((link1
) && (!tx_status(pbpctl_dev
))) {
5042 if ((link2
) && (tx_status(pbpctl_dev_b
)))
5043 set_tx(pbpctl_dev
, 1);
5044 } else if ((!link1
) && (!tx_status(pbpctl_dev
))) {
5045 if ((link2
) && (tx_status(pbpctl_dev_b
)))
5046 set_tx(pbpctl_dev
, 1);
5049 mod_timer(&pbpctl_dev
->bp_tpl_timer
, jiffies
+ BP_LINK_MON_DELAY
* HZ
);
5052 void remove_bypass_tpl_auto(struct bpctl_dev
*pbpctl_dev
)
5054 struct bpctl_dev
*pbpctl_dev_b
= NULL
;
5057 pbpctl_dev_b
= get_status_port_fn(pbpctl_dev
);
5059 if (pbpctl_dev
->bp_caps
& TPL_CAP
) {
5060 del_timer_sync(&pbpctl_dev
->bp_tpl_timer
);
5061 pbpctl_dev
->bp_tpl_flag
= 0;
5062 pbpctl_dev_b
= get_status_port_fn(pbpctl_dev
);
5064 set_tx(pbpctl_dev_b
, 1);
5065 set_tx(pbpctl_dev
, 1);
5070 int init_bypass_tpl_auto(struct bpctl_dev
*pbpctl_dev
)
5074 if (pbpctl_dev
->bp_caps
& TPL_CAP
) {
5075 init_timer(&pbpctl_dev
->bp_tpl_timer
);
5076 pbpctl_dev
->bp_tpl_timer
.function
= &bp_tpl_timer_fn
;
5077 pbpctl_dev
->bp_tpl_timer
.data
= (unsigned long)pbpctl_dev
;
5083 int set_bypass_tpl_auto(struct bpctl_dev
*pbpctl_dev
, unsigned int param
)
5087 if (pbpctl_dev
->bp_caps
& TPL_CAP
) {
5088 if ((param
) && (!pbpctl_dev
->bp_tpl_flag
)) {
5089 pbpctl_dev
->bp_tpl_flag
= param
;
5090 mod_timer(&pbpctl_dev
->bp_tpl_timer
, jiffies
+ 1);
5093 if ((!param
) && (pbpctl_dev
->bp_tpl_flag
))
5094 remove_bypass_tpl_auto(pbpctl_dev
);
5101 int get_bypass_tpl_auto(struct bpctl_dev
*pbpctl_dev
)
5105 if (pbpctl_dev
->bp_caps
& TPL_CAP
)
5106 return pbpctl_dev
->bp_tpl_flag
;
5111 int set_tpl_fn(struct bpctl_dev
*pbpctl_dev
, int tpl_mode
)
5114 struct bpctl_dev
*pbpctl_dev_b
= NULL
;
5118 pbpctl_dev_b
= get_status_port_fn(pbpctl_dev
);
5120 if (pbpctl_dev
->bp_caps
& TPL_CAP
) {
5122 pbpctl_dev_b
= get_status_port_fn(pbpctl_dev
);
5124 set_tx(pbpctl_dev_b
, 1);
5125 set_tx(pbpctl_dev
, 1);
5127 if ((TPL_IF_SERIES(pbpctl_dev
->subdevice
)) ||
5128 (pbpctl_dev
->bp_caps_ex
& TPL2_CAP_EX
)) {
5129 pbpctl_dev
->bp_tpl_flag
= tpl_mode
;
5131 tpl_hw_off(pbpctl_dev
);
5133 tpl_hw_on(pbpctl_dev
);
5135 set_bypass_tpl_auto(pbpctl_dev
, tpl_mode
);
5141 int get_tpl_fn(struct bpctl_dev
*pbpctl_dev
)
5143 int ret
= BP_NOT_CAP
;
5147 if (pbpctl_dev
->bp_caps
& TPL_CAP
) {
5148 if (pbpctl_dev
->bp_caps_ex
& TPL2_CAP_EX
)
5149 return tpl2_flag_status(pbpctl_dev
);
5150 ret
= pbpctl_dev
->bp_tpl_flag
;
5155 int set_bp_wait_at_pwup_fn(struct bpctl_dev
*pbpctl_dev
, int tap_mode
)
5160 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
5161 /* bp_lock(pbp_device_block); */
5162 cmnd_on(pbpctl_dev
);
5164 bp_wait_at_pwup_dis(pbpctl_dev
);
5166 bp_wait_at_pwup_en(pbpctl_dev
);
5167 cmnd_off(pbpctl_dev
);
5169 /* bp_unlock(pbp_device_block); */
5175 int get_bp_wait_at_pwup_fn(struct bpctl_dev
*pbpctl_dev
)
5181 /* bp_lock(pbp_device_block); */
5182 ret
= bp_wait_at_pwup_status(pbpctl_dev
);
5183 /* bp_unlock(pbp_device_block); */
5188 int set_bp_hw_reset_fn(struct bpctl_dev
*pbpctl_dev
, int tap_mode
)
5193 if (pbpctl_dev
->bp_caps
& SW_CTL_CAP
) {
5194 /* bp_lock(pbp_device_block); */
5195 cmnd_on(pbpctl_dev
);
5198 bp_hw_reset_dis(pbpctl_dev
);
5200 bp_hw_reset_en(pbpctl_dev
);
5201 cmnd_off(pbpctl_dev
);
5202 /* bp_unlock(pbp_device_block); */
5208 int get_bp_hw_reset_fn(struct bpctl_dev
*pbpctl_dev
)
5214 /* bp_lock(pbp_device_block); */
5215 ret
= bp_hw_reset_status(pbpctl_dev
);
5217 /* bp_unlock(pbp_device_block); */
5223 int get_bypass_info_fn(struct bpctl_dev
*pbpctl_dev
, char *dev_name
,
5228 if (!is_bypass_fn(pbpctl_dev
))
5230 strcpy(dev_name
, pbpctl_dev
->name
);
5231 *add_param
= pbpctl_dev
->bp_fw_ver
;
5235 int get_dev_idx_bsf(int bus
, int slot
, int func
)
5239 ((bpctl_dev_arr
[idx_dev
].pdev
!= NULL
) && (idx_dev
< device_num
));
5241 if ((bus
== bpctl_dev_arr
[idx_dev
].bus
)
5242 && (slot
== bpctl_dev_arr
[idx_dev
].slot
)
5243 && (func
== bpctl_dev_arr
[idx_dev
].func
))
5250 static int get_dev_idx(int ifindex
)
5255 ((bpctl_dev_arr
[idx_dev
].pdev
!= NULL
) && (idx_dev
< device_num
));
5257 if (ifindex
== bpctl_dev_arr
[idx_dev
].ifindex
)
5264 static struct bpctl_dev
*get_dev_idx_p(int ifindex
)
5269 ((bpctl_dev_arr
[idx_dev
].pdev
!= NULL
) && (idx_dev
< device_num
));
5271 if (ifindex
== bpctl_dev_arr
[idx_dev
].ifindex
)
5272 return &bpctl_dev_arr
[idx_dev
];
5278 static void if_scan_init(void)
5280 struct net_device
*dev
;
5282 /* rcu_read_lock(); */
5284 /* rcu_read_lock(); */
5286 for_each_netdev(&init_net
, dev
) {
5289 if (bp_get_dev_idx_bsf(dev
, &idx_dev
))
5295 bpctl_dev_arr
[idx_dev
].ifindex
= dev
->ifindex
;
5296 bpctl_dev_arr
[idx_dev
].ndev
= dev
;
5298 /* rtnl_unlock(); */
5299 /* rcu_read_unlock(); */
5302 static long device_ioctl(struct file
*file
, /* see include/linux/fs.h */
5303 unsigned int ioctl_num
, /* number and param for ioctl */
5304 unsigned long ioctl_param
)
5306 struct bpctl_cmd bpctl_cmd
;
5308 struct bpctl_dev
*pbpctl_dev_out
;
5309 void __user
*argp
= (void __user
*)ioctl_param
;
5311 unsigned long flags
;
5313 static struct bpctl_dev
*pbpctl_dev
;
5315 /* lock_kernel(); */
5316 if (down_interruptible(&bpctl_sema
))
5317 return -ERESTARTSYS
;
5318 /* local_irq_save(flags); */
5319 /* if(!spin_trylock_irqsave(&bpvm_lock)){
5320 local_irq_restore(flags);
5325 /* spin_lock_irqsave(&bpvm_lock, flags); */
5328 * Switch according to the ioctl called
5330 if (ioctl_num
== IOCTL_TX_MSG(IF_SCAN
)) {
5335 if (copy_from_user(&bpctl_cmd
, argp
, sizeof(struct bpctl_cmd
))) {
5341 if (ioctl_num
== IOCTL_TX_MSG(GET_DEV_NUM
)) {
5342 bpctl_cmd
.out_param
[0] = device_num
;
5344 (argp
, (void *)&bpctl_cmd
, sizeof(struct bpctl_cmd
))) {
5353 /* preempt_disable(); */
5354 local_irq_save(flags
);
5355 if (!spin_trylock(&bpvm_lock
)) {
5356 local_irq_restore(flags
);
5361 /* preempt_disable();
5363 spin_lock_irqsave(&bpvm_lock, flags);
5365 if ((bpctl_cmd
.in_param
[5]) ||
5366 (bpctl_cmd
.in_param
[6]) || (bpctl_cmd
.in_param
[7]))
5367 dev_idx
= get_dev_idx_bsf(bpctl_cmd
.in_param
[5],
5368 bpctl_cmd
.in_param
[6],
5369 bpctl_cmd
.in_param
[7]);
5370 else if (bpctl_cmd
.in_param
[1] == 0)
5371 dev_idx
= bpctl_cmd
.in_param
[0];
5373 dev_idx
= get_dev_idx(bpctl_cmd
.in_param
[1]);
5375 if (dev_idx
< 0 || dev_idx
> device_num
) {
5377 preempt_enable(); */
5379 /* preempt_enable();
5380 rcu_read_unlock(); */
5381 spin_unlock_irqrestore(&bpvm_lock
, flags
);
5385 bpctl_cmd
.out_param
[0] = bpctl_dev_arr
[dev_idx
].bus
;
5386 bpctl_cmd
.out_param
[1] = bpctl_dev_arr
[dev_idx
].slot
;
5387 bpctl_cmd
.out_param
[2] = bpctl_dev_arr
[dev_idx
].func
;
5388 bpctl_cmd
.out_param
[3] = bpctl_dev_arr
[dev_idx
].ifindex
;
5390 if ((bpctl_dev_arr
[dev_idx
].bp_10gb
)
5391 && (!(bpctl_dev_arr
[dev_idx
].ifindex
))) {
5392 printk("Please load network driver for %s adapter!\n",
5393 bpctl_dev_arr
[dev_idx
].name
);
5394 bpctl_cmd
.status
= -1;
5396 /* preempt_enable(); */
5397 /* rcu_read_unlock(); */
5398 spin_unlock_irqrestore(&bpvm_lock
, flags
);
5402 if ((bpctl_dev_arr
[dev_idx
].bp_10gb
) && (bpctl_dev_arr
[dev_idx
].ndev
)) {
5403 if (!(bpctl_dev_arr
[dev_idx
].ndev
->flags
& IFF_UP
)) {
5404 if (!(bpctl_dev_arr
[dev_idx
].ndev
->flags
& IFF_UP
)) {
5406 ("Please bring up network interfaces for %s adapter!\n",
5407 bpctl_dev_arr
[dev_idx
].name
);
5408 bpctl_cmd
.status
= -1;
5410 /* preempt_enable(); */
5411 /* rcu_read_unlock(); */
5412 spin_unlock_irqrestore(&bpvm_lock
, flags
);
5419 if ((dev_idx
< 0) || (dev_idx
> device_num
)
5420 || (bpctl_dev_arr
[dev_idx
].pdev
== NULL
)) {
5421 bpctl_cmd
.status
= -1;
5425 pbpctl_dev
= &bpctl_dev_arr
[dev_idx
];
5427 switch (ioctl_num
) {
5428 case IOCTL_TX_MSG(SET_BYPASS_PWOFF
):
5430 set_bypass_pwoff_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5433 case IOCTL_TX_MSG(GET_BYPASS_PWOFF
):
5434 bpctl_cmd
.status
= get_bypass_pwoff_fn(pbpctl_dev
);
5437 case IOCTL_TX_MSG(SET_BYPASS_PWUP
):
5439 set_bypass_pwup_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5442 case IOCTL_TX_MSG(GET_BYPASS_PWUP
):
5443 bpctl_cmd
.status
= get_bypass_pwup_fn(pbpctl_dev
);
5446 case IOCTL_TX_MSG(SET_BYPASS_WD
):
5448 set_bypass_wd_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5451 case IOCTL_TX_MSG(GET_BYPASS_WD
):
5453 get_bypass_wd_fn(pbpctl_dev
, (int *)&(bpctl_cmd
.data
[0]));
5456 case IOCTL_TX_MSG(GET_WD_EXPIRE_TIME
):
5458 get_wd_expire_time_fn(pbpctl_dev
,
5459 (int *)&(bpctl_cmd
.data
[0]));
5462 case IOCTL_TX_MSG(RESET_BYPASS_WD_TIMER
):
5463 bpctl_cmd
.status
= reset_bypass_wd_timer_fn(pbpctl_dev
);
5466 case IOCTL_TX_MSG(GET_WD_SET_CAPS
):
5467 bpctl_cmd
.status
= get_wd_set_caps_fn(pbpctl_dev
);
5470 case IOCTL_TX_MSG(SET_STD_NIC
):
5472 set_std_nic_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5475 case IOCTL_TX_MSG(GET_STD_NIC
):
5476 bpctl_cmd
.status
= get_std_nic_fn(pbpctl_dev
);
5479 case IOCTL_TX_MSG(SET_TAP
):
5481 set_tap_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5484 case IOCTL_TX_MSG(GET_TAP
):
5485 bpctl_cmd
.status
= get_tap_fn(pbpctl_dev
);
5488 case IOCTL_TX_MSG(GET_TAP_CHANGE
):
5489 bpctl_cmd
.status
= get_tap_change_fn(pbpctl_dev
);
5492 case IOCTL_TX_MSG(SET_DIS_TAP
):
5494 set_dis_tap_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5497 case IOCTL_TX_MSG(GET_DIS_TAP
):
5498 bpctl_cmd
.status
= get_dis_tap_fn(pbpctl_dev
);
5501 case IOCTL_TX_MSG(SET_TAP_PWUP
):
5503 set_tap_pwup_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5506 case IOCTL_TX_MSG(GET_TAP_PWUP
):
5507 bpctl_cmd
.status
= get_tap_pwup_fn(pbpctl_dev
);
5510 case IOCTL_TX_MSG(SET_WD_EXP_MODE
):
5512 set_wd_exp_mode_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5515 case IOCTL_TX_MSG(GET_WD_EXP_MODE
):
5516 bpctl_cmd
.status
= get_wd_exp_mode_fn(pbpctl_dev
);
5519 case IOCTL_TX_MSG(GET_DIS_BYPASS
):
5520 bpctl_cmd
.status
= get_dis_bypass_fn(pbpctl_dev
);
5523 case IOCTL_TX_MSG(SET_DIS_BYPASS
):
5525 set_dis_bypass_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5528 case IOCTL_TX_MSG(GET_BYPASS_CHANGE
):
5529 bpctl_cmd
.status
= get_bypass_change_fn(pbpctl_dev
);
5532 case IOCTL_TX_MSG(GET_BYPASS
):
5533 bpctl_cmd
.status
= get_bypass_fn(pbpctl_dev
);
5536 case IOCTL_TX_MSG(SET_BYPASS
):
5538 set_bypass_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5541 case IOCTL_TX_MSG(GET_BYPASS_CAPS
):
5542 bpctl_cmd
.status
= get_bypass_caps_fn(pbpctl_dev
);
5543 /*preempt_enable(); */
5544 /*rcu_read_unlock();*/
5545 spin_unlock_irqrestore(&bpvm_lock
, flags
);
5547 (argp
, (void *)&bpctl_cmd
, sizeof(struct bpctl_cmd
))) {
5548 /*unlock_bpctl(); */
5549 /*preempt_enable(); */
5555 case IOCTL_TX_MSG(GET_BYPASS_SLAVE
):
5557 get_bypass_slave_fn(pbpctl_dev
, &pbpctl_dev_out
);
5558 if (bpctl_cmd
.status
== 1) {
5559 bpctl_cmd
.out_param
[4] = pbpctl_dev_out
->bus
;
5560 bpctl_cmd
.out_param
[5] = pbpctl_dev_out
->slot
;
5561 bpctl_cmd
.out_param
[6] = pbpctl_dev_out
->func
;
5562 bpctl_cmd
.out_param
[7] = pbpctl_dev_out
->ifindex
;
5566 case IOCTL_TX_MSG(IS_BYPASS
):
5567 bpctl_cmd
.status
= is_bypass(pbpctl_dev
);
5569 case IOCTL_TX_MSG(SET_TX
):
5570 bpctl_cmd
.status
= set_tx_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5572 case IOCTL_TX_MSG(GET_TX
):
5573 bpctl_cmd
.status
= get_tx_fn(pbpctl_dev
);
5575 case IOCTL_TX_MSG(SET_WD_AUTORESET
):
5577 set_wd_autoreset_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5580 case IOCTL_TX_MSG(GET_WD_AUTORESET
):
5582 bpctl_cmd
.status
= get_wd_autoreset_fn(pbpctl_dev
);
5584 case IOCTL_TX_MSG(SET_DISC
):
5586 set_disc_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5588 case IOCTL_TX_MSG(GET_DISC
):
5589 bpctl_cmd
.status
= get_disc_fn(pbpctl_dev
);
5591 case IOCTL_TX_MSG(GET_DISC_CHANGE
):
5592 bpctl_cmd
.status
= get_disc_change_fn(pbpctl_dev
);
5594 case IOCTL_TX_MSG(SET_DIS_DISC
):
5596 set_dis_disc_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5598 case IOCTL_TX_MSG(GET_DIS_DISC
):
5599 bpctl_cmd
.status
= get_dis_disc_fn(pbpctl_dev
);
5601 case IOCTL_TX_MSG(SET_DISC_PWUP
):
5603 set_disc_pwup_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5605 case IOCTL_TX_MSG(GET_DISC_PWUP
):
5606 bpctl_cmd
.status
= get_disc_pwup_fn(pbpctl_dev
);
5609 case IOCTL_TX_MSG(GET_BYPASS_INFO
):
5612 get_bypass_info_fn(pbpctl_dev
, (char *)&bpctl_cmd
.data
,
5613 (char *)&bpctl_cmd
.out_param
[4]);
5616 case IOCTL_TX_MSG(SET_TPL
):
5618 set_tpl_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5621 case IOCTL_TX_MSG(GET_TPL
):
5622 bpctl_cmd
.status
= get_tpl_fn(pbpctl_dev
);
5624 case IOCTL_TX_MSG(SET_BP_WAIT_AT_PWUP
):
5626 set_bp_wait_at_pwup_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5629 case IOCTL_TX_MSG(GET_BP_WAIT_AT_PWUP
):
5630 bpctl_cmd
.status
= get_bp_wait_at_pwup_fn(pbpctl_dev
);
5632 case IOCTL_TX_MSG(SET_BP_HW_RESET
):
5634 set_bp_hw_reset_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5637 case IOCTL_TX_MSG(GET_BP_HW_RESET
):
5638 bpctl_cmd
.status
= get_bp_hw_reset_fn(pbpctl_dev
);
5641 case IOCTL_TX_MSG(SET_BP_SELF_TEST
):
5643 set_bp_self_test_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5646 case IOCTL_TX_MSG(GET_BP_SELF_TEST
):
5647 bpctl_cmd
.status
= get_bp_self_test_fn(pbpctl_dev
);
5652 case IOCTL_TX_MSG(SET_DISC_PORT
):
5654 set_disc_port_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5657 case IOCTL_TX_MSG(GET_DISC_PORT
):
5658 bpctl_cmd
.status
= get_disc_port_fn(pbpctl_dev
);
5661 case IOCTL_TX_MSG(SET_DISC_PORT_PWUP
):
5663 set_disc_port_pwup_fn(pbpctl_dev
, bpctl_cmd
.in_param
[2]);
5666 case IOCTL_TX_MSG(GET_DISC_PORT_PWUP
):
5667 bpctl_cmd
.status
= get_disc_port_pwup_fn(pbpctl_dev
);
5670 case IOCTL_TX_MSG(SET_BP_FORCE_LINK
):
5672 set_bp_force_link_fn(dev_idx
, bpctl_cmd
.in_param
[2]);
5675 case IOCTL_TX_MSG(GET_BP_FORCE_LINK
):
5676 bpctl_cmd
.status
= get_bp_force_link_fn(dev_idx
);
5680 /* unlock_bpctl(); */
5683 /* preempt_enable(); */
5684 /* rcu_read_unlock();*/
5685 spin_unlock_irqrestore(&bpvm_lock
, flags
);
5688 /* unlock_bpctl(); */
5689 /* preempt_enable(); */
5691 /* rcu_read_unlock(); */
5692 spin_unlock_irqrestore(&bpvm_lock
, flags
);
5693 if (copy_to_user(argp
, (void *)&bpctl_cmd
, sizeof(struct bpctl_cmd
)))
5697 /* unlock_kernel(); */
5698 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
5700 /* unlock_kernel(); */
5704 static const struct file_operations Fops
= {
5705 .owner
= THIS_MODULE
,
5706 .unlocked_ioctl
= device_ioctl
,
5710 #define PCI_DEVICE(vend, dev) \
5711 .vendor = (vend), .device = (dev), \
5712 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
5715 #define SILICOM_E1000BP_ETHERNET_DEVICE(device_id) {\
5716 PCI_DEVICE(SILICOM_VID, device_id)}
5879 unsigned int vendor
;
5880 unsigned int device
;
5881 unsigned int subvendor
;
5882 unsigned int subdevice
;
5891 {"Silicom Bypass PXG2BPFI-SD series adapter"},
5892 {"Silicom Bypass PXG2BPFIL-SD series adapter"},
5893 {"Silicom Bypass PXG2BPFILX-SD series adapter"},
5894 {"Silicom Bypass PXG2BPFILLX-SD series adapter"},
5895 {"Silicom Bypass PXG2BPI-SD series adapter"},
5896 {"Silicom Bypass PXG2BPIG-SD series adapter"},
5897 {"Silicom Bypass PXG2TBFI-SD series adapter"},
5898 {"Silicom Bypass PXG4BPI-SD series adapter"},
5899 {"Silicom Bypass PXG4BPFI-SD series adapter"},
5900 {"Silicom Bypass PEG4BPI-SD series adapter"},
5901 {"Silicom Bypass PEG2BPI-SD series adapter"},
5902 {"Silicom Bypass PEG4BPIN-SD series adapter"},
5903 {"Silicom Bypass PEG2BPFI-SD series adapter"},
5904 {"Silicom Bypass PEG2BPFI-LX-SD series adapter"},
5905 {"Silicom Bypass PMCX2BPFI-SD series adapter"},
5906 {"Silicom Bypass PMCX2BPFI-N series adapter"},
5907 {"Intel Bypass PEG2BPII series adapter"},
5908 {"Intel Bypass PEG2BPFII series adapter"},
5909 {"Silicom Bypass PXG4BPFILX-SD series adapter"},
5910 {"Silicom Bypass PMCX2BPI-N series adapter"},
5911 {"Silicom Bypass PMCX4BPI-N series adapter"},
5912 {"Silicom Bypass PXG2BISC1-SD series adapter"},
5913 {"Silicom Bypass PEG2TBFI-SD series adapter"},
5914 {"Silicom Bypass PXG2TBI-SD series adapter"},
5915 {"Silicom Bypass PXG4BPFID-SD series adapter"},
5916 {"Silicom Bypass PEG4BPFI-SD series adapter"},
5917 {"Silicom Bypass PEG4BPIPT-SD series adapter"},
5918 {"Silicom Bypass PXG6BPI-SD series adapter"},
5919 {"Silicom Bypass PEG4BPIL-SD series adapter"},
5920 {"Silicom Bypass PMCX2BPI-N2 series adapter"},
5921 {"Silicom Bypass PMCX4BPI-N2 series adapter"},
5922 {"Silicom Bypass PMCX2BPI-SD series adapter"},
5923 {"Silicom Bypass PEG2BPFID-SD series adapter"},
5924 {"Silicom Bypass PEG2BPFIDLX-SD series adapter"},
5925 {"Silicom Bypass PMCX4BPI-SD series adapter"},
5926 {"Silicom Bypass MEG2BPFILN-SD series adapter"},
5927 {"Silicom Bypass MEG2BPFINX-SD series adapter"},
5928 {"Silicom Bypass PEG4BPFILX-SD series adapter"},
5929 {"Silicom Bypass PE10G2BPISR-SD series adapter"},
5930 {"Silicom Bypass PE10G2BPILR-SD series adapter"},
5931 {"Silicom Bypass MHIO8AD-SD series adapter"},
5932 {"Silicom Bypass PE10G2BPICX4-SD series adapter"},
5933 {"Silicom Bypass PEG2BPI5-SD series adapter"},
5934 {"Silicom Bypass PEG6BPI5-SD series adapter"},
5935 {"Silicom Bypass PEG4BPFI5-SD series adapter"},
5936 {"Silicom Bypass PEG4BPFI5LX-SD series adapter"},
5937 {"Silicom Bypass MEG2BPFILXLN-SD series adapter"},
5938 {"Silicom Bypass PEG2BPIX1-SD series adapter"},
5939 {"Silicom Bypass MEG2BPFILXNX-SD series adapter"},
5940 {"Silicom Bypass XE10G2BPIT-SD series adapter"},
5941 {"Silicom Bypass XE10G2BPICX4-SD series adapter"},
5942 {"Silicom Bypass XE10G2BPISR-SD series adapter"},
5943 {"Silicom Bypass XE10G2BPILR-SD series adapter"},
5944 {"Intel Bypass PEG2BPFII0 series adapter"},
5945 {"Silicom Bypass XE10G2BPIXR series adapter"},
5946 {"Silicom Bypass PE10G2DBISR series adapter"},
5947 {"Silicom Bypass PEG2BI5SC6 series adapter"},
5948 {"Silicom Bypass PEG6BPI5FC series adapter"},
5950 {"Silicom Bypass PE10G2BPTCX4 series adapter"},
5951 {"Silicom Bypass PE10G2BPTSR series adapter"},
5952 {"Silicom Bypass PE10G2BPTLR series adapter"},
5953 {"Silicom Bypass PE10G2BPTT series adapter"},
5954 {"Silicom Bypass PEG4BPI6 series adapter"},
5955 {"Silicom Bypass PEG4BPFI6 series adapter"},
5956 {"Silicom Bypass PEG4BPFI6LX series adapter"},
5957 {"Silicom Bypass PEG4BPFI6ZX series adapter"},
5958 {"Silicom Bypass PEG2BPI6 series adapter"},
5959 {"Silicom Bypass PEG2BPFI6 series adapter"},
5960 {"Silicom Bypass PEG2BPFI6LX series adapter"},
5961 {"Silicom Bypass PEG2BPFI6ZX series adapter"},
5962 {"Silicom Bypass PEG2BPFI6FLXM series adapter"},
5963 {"Silicom Bypass PEG4BPI6FC series adapter"},
5964 {"Silicom Bypass PEG4BPFI6FC series adapter"},
5965 {"Silicom Bypass PEG4BPFI6FCLX series adapter"},
5966 {"Silicom Bypass PEG4BPFI6FCZX series adapter"},
5967 {"Silicom Bypass PEG6BPI6 series adapter"},
5968 {"Silicom Bypass PEG2BPI6SC6 series adapter"},
5969 {"Silicom Bypass MEG2BPI6 series adapter"},
5970 {"Silicom Bypass XEG2BPI6 series adapter"},
5971 {"Silicom Bypass MEG4BPI6 series adapter"},
5972 {"Silicom Bypass PEG2BPFI5-SD series adapter"},
5973 {"Silicom Bypass PEG2BPFI5LX-SD series adapter"},
5974 {"Silicom Bypass PXEG4BPFI-SD series adapter"},
5975 {"Silicom Bypass MxEG2BPI6 series adapter"},
5976 {"Silicom Bypass MxEG2BPFI6 series adapter"},
5977 {"Silicom Bypass MxEG2BPFI6LX series adapter"},
5978 {"Silicom Bypass MxEG2BPFI6ZX series adapter"},
5979 {"Silicom Bypass MxEG4BPI6 series adapter"},
5980 {"Silicom Bypass MxEG4BPFI6 series adapter"},
5981 {"Silicom Bypass MxEG4BPFI6LX series adapter"},
5982 {"Silicom Bypass MxEG4BPFI6ZX series adapter"},
5983 {"Silicom Bypass MxEG6BPI6 series adapter"},
5984 {"Silicom Bypass MxE2G4BPi80 series adapter"},
5985 {"Silicom Bypass MxE2G4BPFi80 series adapter"},
5986 {"Silicom Bypass MxE2G4BPFi80LX series adapter"},
5987 {"Silicom Bypass MxE2G4BPFi80ZX series adapter"},
5989 {"Silicom Bypass PE210G2SPI9 series adapter"},
5991 {"Silicom Bypass MxE210G2BPI9CX4 series adapter"},
5992 {"Silicom Bypass MxE210G2BPI9SR series adapter"},
5993 {"Silicom Bypass MxE210G2BPI9LR series adapter"},
5994 {"Silicom Bypass MxE210G2BPI9T series adapter"},
5996 {"Silicom Bypass PE210G2BPI9CX4 series adapter"},
5997 {"Silicom Bypass PE210G2BPI9SR series adapter"},
5998 {"Silicom Bypass PE210G2BPI9LR series adapter"},
5999 {"Silicom Bypass PE210G2BPI9T series adapter"},
6001 {"Silicom Bypass M2EG2BPFI6 series adapter"},
6002 {"Silicom Bypass M2EG2BPFI6LX series adapter"},
6003 {"Silicom Bypass M2EG2BPFI6ZX series adapter"},
6004 {"Silicom Bypass M2EG4BPI6 series adapter"},
6005 {"Silicom Bypass M2EG4BPFI6 series adapter"},
6006 {"Silicom Bypass M2EG4BPFI6LX series adapter"},
6007 {"Silicom Bypass M2EG4BPFI6ZX series adapter"},
6008 {"Silicom Bypass M2EG6BPI6 series adapter"},
6010 {"Silicom Bypass PEG2DBI6 series adapter"},
6011 {"Silicom Bypass PEG2DBFI6 series adapter"},
6012 {"Silicom Bypass PEG2DBFI6LX series adapter"},
6013 {"Silicom Bypass PEG2DBFI6ZX series adapter"},
6015 {"Silicom Bypass PE2G4BPi80 series adapter"},
6016 {"Silicom Bypass PE2G4BPFi80 series adapter"},
6017 {"Silicom Bypass PE2G4BPFi80LX series adapter"},
6018 {"Silicom Bypass PE2G4BPFi80ZX series adapter"},
6020 {"Silicom Bypass PE2G4BPi80L series adapter"},
6021 {"Silicom Bypass MxE2G8BPi80A series adapter"},
6023 {"Silicom Bypass PE2G2BPi35 series adapter"},
6024 {"Silicom Bypass PAC1200BPi35 series adapter"},
6025 {"Silicom Bypass PE2G2BPFi35 series adapter"},
6026 {"Silicom Bypass PE2G2BPFi35LX series adapter"},
6027 {"Silicom Bypass PE2G2BPFi35ZX series adapter"},
6029 {"Silicom Bypass PE2G4BPi35 series adapter"},
6030 {"Silicom Bypass PE2G4BPi35L series adapter"},
6031 {"Silicom Bypass PE2G4BPFi35 series adapter"},
6032 {"Silicom Bypass PE2G4BPFi35LX series adapter"},
6033 {"Silicom Bypass PE2G4BPFi35ZX series adapter"},
6035 {"Silicom Bypass PE2G6BPi35 series adapter"},
6036 {"Silicom Bypass PE2G6BPi35CX series adapter"},
6038 {"Silicom Bypass PE2G2BPi80 series adapter"},
6039 {"Silicom Bypass PE2G2BPFi80 series adapter"},
6040 {"Silicom Bypass PE2G2BPFi80LX series adapter"},
6041 {"Silicom Bypass PE2G2BPFi80ZX series adapter"},
6043 {"Silicom Bypass M2E10G2BPI9CX4 series adapter"},
6044 {"Silicom Bypass M2E10G2BPI9SR series adapter"},
6045 {"Silicom Bypass M2E10G2BPI9LR series adapter"},
6046 {"Silicom Bypass M2E10G2BPI9T series adapter"},
6047 {"Silicom Bypass MxE2G8BPi80 series adapter"},
6048 {"Silicom Bypass PE210G2DBi9SR series adapter"},
6049 {"Silicom Bypass PE210G2DBi9SRRB series adapter"},
6050 {"Silicom Bypass PE210G2DBi9LR series adapter"},
6051 {"Silicom Bypass PE210G2DBi9LRRB series adapter"},
6052 {"Silicom Bypass PE310G4DBi9-SR series adapter"},
6053 {"Silicom Bypass PE310G4BPi9T series adapter"},
6054 {"Silicom Bypass PE310G4BPi9SR series adapter"},
6055 {"Silicom Bypass PE310G4BPi9LR series adapter"},
6056 {"Silicom Bypass PE210G2BPi40T series adapter"},
6060 static struct bpmod_info tx_ctl_pci_tbl
[] = {
6061 {0x8086, 0x107a, SILICOM_SVID
, SILICOM_PXG2BPFI_SSID
, PXG2BPFI
,
6063 {0x8086, 0x107a, SILICOM_SVID
, SILICOM_PXG2BPFIL_SSID
, PXG2BPFIL
,
6065 {0x8086, 0x107a, SILICOM_SVID
, SILICOM_PXG2BPFILX_SSID
, PXG2BPFILX
,
6067 {0x8086, 0x107a, SILICOM_SVID
, SILICOM_PXG2BPFILLX_SSID
, PXG2BPFILLX
,
6069 {0x8086, 0x1010, SILICOM_SVID
, SILICOM_PXGBPI_SSID
, PXGBPI
,
6071 {0x8086, 0x1079, SILICOM_SVID
, SILICOM_PXGBPIG_SSID
, PXGBPIG
,
6073 {0x8086, 0x107a, SILICOM_SVID
, SILICOM_PXG2TBFI_SSID
, PXG2TBFI
,
6075 {0x8086, 0x1079, SILICOM_SVID
, SILICOM_PXG4BPI_SSID
, PXG4BPI
,
6077 {0x8086, 0x107a, SILICOM_SVID
, SILICOM_PXG4BPFI_SSID
, PXG4BPFI
,
6079 {0x8086, 0x107a, SILICOM_SVID
, SILICOM_PXG4BPFILX_SSID
, PXG4BPFILX
,
6081 {0x8086, 0x1079, SILICOM_SVID
, SILICOM_PEG4BPI_SSID
, PEG4BPI
,
6083 {0x8086, 0x105e, SILICOM_SVID
, SILICOM_PEG2BPI_SSID
, PEG2BPI
,
6085 {0x8086, 0x105e, SILICOM_SVID
, SILICOM_PEG4BPIN_SSID
, PEG4BPIN
,
6087 {0x8086, 0x105f, SILICOM_SVID
, SILICOM_PEG2BPFI_SSID
, PEG2BPFI
,
6089 {0x8086, 0x105f, SILICOM_SVID
, SILICOM_PEG2BPFILX_SSID
, PEG2BPFILX
,
6091 {0x8086, 0x107a, SILICOM_SVID
, SILICOM_PMCXG2BPFI_SSID
, PMCXG2BPFI
,
6093 {0x8086, 0x107a, NOKIA_PMCXG2BPFIN_SVID
, NOKIA_PMCXG2BPFIN_SSID
,
6094 PMCXG2BPFIN
, "PMCX2BPFI-N"},
6095 {0x8086, INTEL_PEG4BPII_PID
, 0x8086, INTEL_PEG4BPII_SSID
, PEG4BPII
,
6097 {0x8086, INTEL_PEG4BPIIO_PID
, 0x8086, INTEL_PEG4BPIIO_SSID
, PEG4BPIIO
,
6099 {0x8086, INTEL_PEG4BPFII_PID
, 0x8086, INTEL_PEG4BPFII_SSID
, PEG4BPFII
,
6101 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID
, NOKIA_PMCXG2BPIN_SSID
,
6102 PMCXG2BPIN
, "PMCX2BPI-N"},
6103 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID
, NOKIA_PMCXG4BPIN_SSID
,
6104 PMCXG4BPIN
, "PMCX4BPI-N"},
6105 {0x8086, 0x1079, SILICOM_SVID
, SILICOM_PXG2BISC1_SSID
, PXG2BISC1
,
6107 {0x8086, 0x105f, SILICOM_SVID
, SILICOM_PEG2TBFI_SSID
, PEG2TBFI
,
6109 {0x8086, 0x1079, SILICOM_SVID
, SILICOM_PXG2TBI_SSID
, PXG2TBI
,
6111 {0x8086, 0x107a, SILICOM_SVID
, SILICOM_PXG4BPFID_SSID
, PXG4BPFID
,
6113 {0x8086, 0x105f, SILICOM_SVID
, SILICOM_PEG4BPFI_SSID
, PEG4BPFI
,
6115 {0x8086, 0x105e, SILICOM_SVID
, SILICOM_PEG4BPIPT_SSID
, PEG4BPIPT
,
6117 {0x8086, 0x1079, SILICOM_SVID
, SILICOM_PXG6BPI_SSID
, PXG6BPI
,
6119 {0x8086, 0x10a7, SILICOM_SVID
/*PCI_ANY_ID */ ,
6120 SILICOM_PEG4BPIL_SSID
/*PCI_ANY_ID */ , PEG4BPIL
, "PEG4BPIL-SD"},
6121 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID
, NOKIA_PMCXG2BPIN2_SSID
,
6122 PMCXG2BPIN2
, "PMCX2BPI-N2"},
6123 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID
, NOKIA_PMCXG4BPIN2_SSID
,
6124 PMCXG4BPIN2
, "PMCX4BPI-N2"},
6125 {0x8086, 0x1079, SILICOM_SVID
, SILICOM_PMCX2BPI_SSID
, PMCX2BPI
,
6127 {0x8086, 0x1079, SILICOM_SVID
, SILICOM_PMCX4BPI_SSID
, PMCX4BPI
,
6129 {0x8086, 0x105f, SILICOM_SVID
, SILICOM_PEG2BPFID_SSID
, PEG2BPFID
,
6131 {0x8086, 0x105f, SILICOM_SVID
, SILICOM_PEG2BPFIDLX_SSID
, PEG2BPFIDLX
,
6133 {0x8086, 0x105f, SILICOM_SVID
, SILICOM_MEG2BPFILN_SSID
, MEG2BPFILN
,
6135 {0x8086, 0x105f, SILICOM_SVID
, SILICOM_MEG2BPFINX_SSID
, MEG2BPFINX
,
6137 {0x8086, 0x105f, SILICOM_SVID
, SILICOM_PEG4BPFILX_SSID
, PEG4BPFILX
,
6139 {0x8086, PCI_ANY_ID
, SILICOM_SVID
, SILICOM_PE10G2BPISR_SSID
,
6140 PE10G2BPISR
, "PE10G2BPISR"},
6141 {0x8086, PCI_ANY_ID
, SILICOM_SVID
, SILICOM_PE10G2BPILR_SSID
,
6142 PE10G2BPILR
, "PE10G2BPILR"},
6143 {0x8086, 0x10a9, SILICOM_SVID
, SILICOM_MHIO8AD_SSID
, MHIO8AD
,
6145 {0x8086, PCI_ANY_ID
, SILICOM_SVID
, SILICOM_PE10G2BPICX4_SSID
,
6146 PE10G2BPISR
, "PE10G2BPICX4"},
6147 {0x8086, 0x10a7, SILICOM_SVID
/*PCI_ANY_ID */ ,
6148 SILICOM_PEG2BPI5_SSID
/*PCI_ANY_ID */ , PEG2BPI5
, "PEG2BPI5-SD"},
6149 {0x8086, 0x10a7, SILICOM_SVID
/*PCI_ANY_ID */ ,
6150 SILICOM_PEG6BPI_SSID
/*PCI_ANY_ID */ , PEG6BPI
, "PEG6BPI5"},
6151 {0x8086, 0x10a9, SILICOM_SVID
/*PCI_ANY_ID */ , SILICOM_PEG4BPFI5_SSID
,
6152 PEG4BPFI5
, "PEG4BPFI5"},
6153 {0x8086, 0x10a9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6154 SILICOM_PEG4BPFI5LX_SSID
, PEG4BPFI5LX
, "PEG4BPFI5LX"},
6155 {0x8086, 0x105f, SILICOM_SVID
, SILICOM_MEG2BPFILXLN_SSID
, MEG2BPFILXLN
,
6157 {0x8086, 0x105e, SILICOM_SVID
, SILICOM_PEG2BPIX1_SSID
, PEG2BPIX1
,
6159 {0x8086, 0x105f, SILICOM_SVID
, SILICOM_MEG2BPFILXNX_SSID
, MEG2BPFILXNX
,
6161 {0x8086, PCI_ANY_ID
, SILICOM_SVID
, SILICOM_XE10G2BPIT_SSID
, XE10G2BPIT
,
6163 {0x8086, PCI_ANY_ID
, SILICOM_SVID
, SILICOM_XE10G2BPICX4_SSID
,
6164 XE10G2BPICX4
, "XE10G2BPICX4"},
6165 {0x8086, 0x10C6, SILICOM_SVID
, SILICOM_XE10G2BPISR_SSID
, XE10G2BPISR
,
6167 {0x8086, 0x10C6, SILICOM_SVID
, SILICOM_XE10G2BPILR_SSID
, XE10G2BPILR
,
6169 {0x8086, 0x10C6, NOKIA_XE10G2BPIXR_SVID
, NOKIA_XE10G2BPIXR_SSID
,
6170 XE10G2BPIXR
, "XE10G2BPIXR"},
6171 {0x8086, 0x10C6, SILICOM_SVID
, SILICOM_PE10GDBISR_SSID
, PE10GDBISR
,
6173 {0x8086, 0x10C6, SILICOM_SVID
, SILICOM_PE10GDBILR_SSID
, PE10GDBILR
,
6175 {0x8086, 0x10a7, SILICOM_SVID
/*PCI_ANY_ID */ ,
6176 SILICOM_PEG2BISC6_SSID
/*PCI_ANY_ID */ , PEG2BISC6
, "PEG2BI5SC6"},
6177 {0x8086, 0x10a7, SILICOM_SVID
/*PCI_ANY_ID */ ,
6178 SILICOM_PEG6BPIFC_SSID
/*PCI_ANY_ID */ , PEG6BPIFC
, "PEG6BPI5FC"},
6180 {BROADCOM_VID
, BROADCOM_PE10G2_PID
, SILICOM_SVID
,
6181 SILICOM_PE10G2BPTCX4_SSID
, PE10G2BPTCX4
, "PE10G2BPTCX4"},
6182 {BROADCOM_VID
, BROADCOM_PE10G2_PID
, SILICOM_SVID
,
6183 SILICOM_PE10G2BPTSR_SSID
, PE10G2BPTSR
, "PE10G2BPTSR"},
6184 {BROADCOM_VID
, BROADCOM_PE10G2_PID
, SILICOM_SVID
,
6185 SILICOM_PE10G2BPTLR_SSID
, PE10G2BPTLR
, "PE10G2BPTLR"},
6186 {BROADCOM_VID
, BROADCOM_PE10G2_PID
, SILICOM_SVID
,
6187 SILICOM_PE10G2BPTT_SSID
, PE10G2BPTT
, "PE10G2BPTT"},
6189 /* {BROADCOM_VID, BROADCOM_PE10G2_PID, PCI_ANY_ID, PCI_ANY_ID, PE10G2BPTCX4, "PE10G2BPTCX4"}, */
6191 {0x8086, 0x10c9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6192 SILICOM_PEG4BPI6_SSID
/*PCI_ANY_ID */ , PEG4BPI6
, "PEG4BPI6"},
6193 {0x8086, 0x10e6, SILICOM_SVID
/*PCI_ANY_ID */ ,
6194 SILICOM_PEG4BPFI6_SSID
/*PCI_ANY_ID */ , PEG4BPFI6
, "PEG4BPFI6"},
6195 {0x8086, 0x10e6, SILICOM_SVID
/*PCI_ANY_ID */ ,
6196 SILICOM_PEG4BPFI6LX_SSID
/*PCI_ANY_ID */ , PEG4BPFI6LX
, "PEG4BPFI6LX"},
6197 {0x8086, 0x10e6, SILICOM_SVID
/*PCI_ANY_ID */ ,
6198 SILICOM_PEG4BPFI6ZX_SSID
/*PCI_ANY_ID */ , PEG4BPFI6ZX
, "PEG4BPFI6ZX"},
6199 {0x8086, 0x10c9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6200 SILICOM_PEG2BPI6_SSID
/*PCI_ANY_ID */ , PEG2BPI6
, "PEG2BPI6"},
6201 {0x8086, 0x10e6, SILICOM_SVID
/*PCI_ANY_ID */ ,
6202 SILICOM_PEG2BPFI6_SSID
/*PCI_ANY_ID */ , PEG2BPFI6
, "PEG2BPFI6"},
6203 {0x8086, 0x10e6, SILICOM_SVID
/*PCI_ANY_ID */ ,
6204 SILICOM_PEG2BPFI6LX_SSID
/*PCI_ANY_ID */ , PEG2BPFI6LX
, "PEG2BPFI6LX"},
6205 {0x8086, 0x10e6, SILICOM_SVID
/*PCI_ANY_ID */ ,
6206 SILICOM_PEG2BPFI6ZX_SSID
/*PCI_ANY_ID */ , PEG2BPFI6ZX
, "PEG2BPFI6ZX"},
6207 {0x8086, 0x10e7, SILICOM_SVID
/*PCI_ANY_ID */ ,
6208 SILICOM_PEG2BPFI6FLXM_SSID
/*PCI_ANY_ID */ , PEG2BPFI6FLXM
,
6210 {0x8086, 0x10c9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6211 SILICOM_PEG4BPI6FC_SSID
/*PCI_ANY_ID */ , PEG4BPI6FC
, "PEG4BPI6FC"},
6212 {0x8086, 0x10e6, SILICOM_SVID
/*PCI_ANY_ID */ ,
6213 SILICOM_PEG4BPFI6FC_SSID
/*PCI_ANY_ID */ , PEG4BPFI6FC
, "PEG4BPFI6FC"},
6214 {0x8086, 0x10e6, SILICOM_SVID
/*PCI_ANY_ID */ ,
6215 SILICOM_PEG4BPFI6FCLX_SSID
/*PCI_ANY_ID */ , PEG4BPFI6FCLX
,
6217 {0x8086, 0x10e6, SILICOM_SVID
/*PCI_ANY_ID */ ,
6218 SILICOM_PEG4BPFI6FCZX_SSID
/*PCI_ANY_ID */ , PEG4BPFI6FCZX
,
6220 {0x8086, 0x10c9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6221 SILICOM_PEG6BPI6_SSID
/*PCI_ANY_ID */ , PEG6BPI6
, "PEG6BPI6"},
6222 {0x8086, 0x10c9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6223 SILICOM_PEG2BPI6SC6_SSID
/*PCI_ANY_ID */ , PEG2BPI6SC6
,
6225 {0x8086, 0x10c9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6226 SILICOM_MEG2BPI6_SSID
/*PCI_ANY_ID */ , MEG2BPI6
, "MEG2BPI6"},
6227 {0x8086, 0x10c9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6228 SILICOM_XEG2BPI6_SSID
/*PCI_ANY_ID */ , XEG2BPI6
, "XEG2BPI6"},
6229 {0x8086, 0x10c9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6230 SILICOM_MEG4BPI6_SSID
/*PCI_ANY_ID */ , MEG4BPI6
, "MEG4BPI6"},
6232 {0x8086, 0x10a9, SILICOM_SVID
/*PCI_ANY_ID */ , SILICOM_PEG2BPFI5_SSID
,
6233 PEG2BPFI5
, "PEG2BPFI5"},
6234 {0x8086, 0x10a9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6235 SILICOM_PEG2BPFI5LX_SSID
, PEG2BPFI5LX
, "PEG2BPFI5LX"},
6237 {0x8086, 0x105f, SILICOM_SVID
, SILICOM_PXEG4BPFI_SSID
, PXEG4BPFI
,
6240 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6241 SILICOM_M1EG2BPI6_SSID
/*PCI_ANY_ID */ , M1EG2BPI6
, "MxEG2BPI6"},
6243 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6244 SILICOM_M1EG2BPFI6_SSID
/*PCI_ANY_ID */ , M1EG2BPFI6
, "MxEG2BPFI6"},
6245 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6246 SILICOM_M1EG2BPFI6LX_SSID
/*PCI_ANY_ID */ , M1EG2BPFI6LX
,
6248 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6249 SILICOM_M1EG2BPFI6ZX_SSID
/*PCI_ANY_ID */ , M1EG2BPFI6ZX
,
6252 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6253 SILICOM_M1EG4BPI6_SSID
/*PCI_ANY_ID */ , M1EG4BPI6
, "MxEG4BPI6"},
6255 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6256 SILICOM_M1EG4BPFI6_SSID
/*PCI_ANY_ID */ , M1EG4BPFI6
, "MxEG4BPFI6"},
6257 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6258 SILICOM_M1EG4BPFI6LX_SSID
/*PCI_ANY_ID */ , M1EG4BPFI6LX
,
6260 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6261 SILICOM_M1EG4BPFI6ZX_SSID
/*PCI_ANY_ID */ , M1EG4BPFI6ZX
,
6264 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6265 SILICOM_M1EG6BPI6_SSID
/*PCI_ANY_ID */ , M1EG6BPI6
, "MxEG6BPI6"},
6267 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6268 SILICOM_M1E2G4BPi80_SSID
/*PCI_ANY_ID */ , M1E2G4BPi80
, "MxE2G4BPi80"},
6269 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6270 SILICOM_M1E2G4BPFi80_SSID
/*PCI_ANY_ID */ , M1E2G4BPFi80
,
6272 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6273 SILICOM_M1E2G4BPFi80LX_SSID
/*PCI_ANY_ID */ , M1E2G4BPFi80LX
,
6275 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6276 SILICOM_M1E2G4BPFi80ZX_SSID
/*PCI_ANY_ID */ , M1E2G4BPFi80ZX
,
6279 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6280 SILICOM_M2EG2BPFI6_SSID
/*PCI_ANY_ID */ , M2EG2BPFI6
, "M2EG2BPFI6"},
6281 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6282 SILICOM_M2EG2BPFI6LX_SSID
/*PCI_ANY_ID */ , M2EG2BPFI6LX
,
6284 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6285 SILICOM_M2EG2BPFI6ZX_SSID
/*PCI_ANY_ID */ , M2EG2BPFI6ZX
,
6288 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6289 SILICOM_M2EG4BPI6_SSID
/*PCI_ANY_ID */ , M2EG4BPI6
, "M2EG4BPI6"},
6291 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6292 SILICOM_M2EG4BPFI6_SSID
/*PCI_ANY_ID */ , M2EG4BPFI6
, "M2EG4BPFI6"},
6293 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6294 SILICOM_M2EG4BPFI6LX_SSID
/*PCI_ANY_ID */ , M2EG4BPFI6LX
,
6296 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6297 SILICOM_M2EG4BPFI6ZX_SSID
/*PCI_ANY_ID */ , M2EG4BPFI6ZX
,
6300 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6301 SILICOM_M2EG6BPI6_SSID
/*PCI_ANY_ID */ , M2EG6BPI6
, "M2EG6BPI6"},
6303 {0x8086, 0x10c9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6304 SILICOM_PEG2DBI6_SSID
/*PCI_ANY_ID */ , PEG2DBI6
, "PEG2DBI6"},
6305 {0x8086, 0x10e6, SILICOM_SVID
/*PCI_ANY_ID */ ,
6306 SILICOM_PEG2DBFI6_SSID
/*PCI_ANY_ID */ , PEG2DBFI6
, "PEG2DBFI6"},
6307 {0x8086, 0x10e6, SILICOM_SVID
/*PCI_ANY_ID */ ,
6308 SILICOM_PEG2DBFI6LX_SSID
/*PCI_ANY_ID */ , PEG2DBFI6LX
, "PEG2DBFI6LX"},
6309 {0x8086, 0x10e6, SILICOM_SVID
/*PCI_ANY_ID */ ,
6310 SILICOM_PEG2DBFI6ZX_SSID
/*PCI_ANY_ID */ , PEG2DBFI6ZX
, "PEG2DBFI6ZX"},
6312 {0x8086, 0x10F9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6313 SILICOM_PE210G2DBi9SR_SSID
, PE210G2DBi9SR
, "PE210G2DBi9SR"},
6314 {0x8086, 0x10F9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6315 SILICOM_PE210G2DBi9LR_SSID
, PE210G2DBi9LR
, "PE210G2DBi9LR"},
6316 {0x8086, 0x10F9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6317 SILICOM_PE310G4DBi940SR_SSID
, PE310G4DBi940SR
, "PE310G4DBi9SR"},
6319 {0x8086, 0x10Fb, SILICOM_SVID
/*PCI_ANY_ID */ ,
6320 SILICOM_PE310G4BPi9T_SSID
, PE310G4BPi9T
, "PE310G4BPi9T"},
6321 {0x8086, 0x10Fb, SILICOM_SVID
/*PCI_ANY_ID */ ,
6322 SILICOM_PE310G4BPi9SR_SSID
, PE310G4BPi9SR
, "PE310G4BPi9SR"},
6323 {0x8086, 0x10Fb, SILICOM_SVID
/*PCI_ANY_ID */ ,
6324 SILICOM_PE310G4BPi9LR_SSID
, PE310G4BPi9LR
, "PE310G4BPi9LR"},
6326 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6327 SILICOM_PE2G4BPi80_SSID
/*PCI_ANY_ID */ , PE2G4BPi80
, "PE2G4BPi80"},
6328 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6329 SILICOM_PE2G4BPFi80_SSID
/*PCI_ANY_ID */ , PE2G4BPFi80
, "PE2G4BPFi80"},
6330 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6331 SILICOM_PE2G4BPFi80LX_SSID
/*PCI_ANY_ID */ , PE2G4BPFi80LX
,
6333 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6334 SILICOM_PE2G4BPFi80ZX_SSID
/*PCI_ANY_ID */ , PE2G4BPFi80ZX
,
6337 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6338 SILICOM_PE2G4BPi80L_SSID
/*PCI_ANY_ID */ , PE2G4BPi80L
, "PE2G4BPi80L"},
6340 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6341 SILICOM_M6E2G8BPi80A_SSID
/*PCI_ANY_ID */ , M6E2G8BPi80A
,
6344 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6345 SILICOM_PE2G2BPi35_SSID
/*PCI_ANY_ID */ , PE2G2BPi35
, "PE2G2BPi35"},
6346 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6347 SILICOM_PAC1200BPi35_SSID
/*PCI_ANY_ID */ , PAC1200BPi35
,
6350 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6351 SILICOM_PE2G2BPFi35_SSID
/*PCI_ANY_ID */ , PE2G2BPFi35
, "PE2G2BPFi35"},
6352 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6353 SILICOM_PE2G2BPFi35LX_SSID
/*PCI_ANY_ID */ , PE2G2BPFi35LX
,
6355 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6356 SILICOM_PE2G2BPFi35ZX_SSID
/*PCI_ANY_ID */ , PE2G2BPFi35ZX
,
6359 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6360 SILICOM_PE2G4BPi35_SSID
/*PCI_ANY_ID */ , PE2G4BPi35
, "PE2G4BPi35"},
6362 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6363 SILICOM_PE2G4BPi35L_SSID
/*PCI_ANY_ID */ , PE2G4BPi35L
, "PE2G4BPi35L"},
6365 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6366 SILICOM_PE2G4BPFi35_SSID
/*PCI_ANY_ID */ , PE2G4BPFi35
, "PE2G4BPFi35"},
6367 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6368 SILICOM_PE2G4BPFi35LX_SSID
/*PCI_ANY_ID */ , PE2G4BPFi35LX
,
6370 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6371 SILICOM_PE2G4BPFi35ZX_SSID
/*PCI_ANY_ID */ , PE2G4BPFi35ZX
,
6374 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6375 SILICOM_PE2G6BPi35_SSID
/*PCI_ANY_ID */ , PE2G6BPi35
, "PE2G6BPi35"},
6378 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaa0, PE2G6BPi35CX
,
6380 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaa1, PE2G6BPi35CX
,
6382 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaa2, PE2G6BPi35CX
,
6384 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaa3, PE2G6BPi35CX
,
6386 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaa4, PE2G6BPi35CX
,
6388 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaa5, PE2G6BPi35CX
,
6390 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaa6, PE2G6BPi35CX
,
6392 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaa7, PE2G6BPi35CX
,
6394 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaa8, PE2G6BPi35CX
,
6396 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaa9, PE2G6BPi35CX
,
6398 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaaa, PE2G6BPi35CX
,
6400 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaab, PE2G6BPi35CX
,
6402 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaac, PE2G6BPi35CX
,
6404 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaad, PE2G6BPi35CX
,
6406 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaae, PE2G6BPi35CX
,
6408 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaaf, PE2G6BPi35CX
,
6410 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xab0, PE2G6BPi35CX
,
6412 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xab1, PE2G6BPi35CX
,
6414 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xab2, PE2G6BPi35CX
,
6416 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xab3, PE2G6BPi35CX
,
6418 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xab4, PE2G6BPi35CX
,
6420 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xab5, PE2G6BPi35CX
,
6422 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xab6, PE2G6BPi35CX
,
6424 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xab7, PE2G6BPi35CX
,
6426 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xab8, PE2G6BPi35CX
,
6428 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xab9, PE2G6BPi35CX
,
6430 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xaba, PE2G6BPi35CX
,
6432 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xabb, PE2G6BPi35CX
,
6434 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xabc, PE2G6BPi35CX
,
6436 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xabd, PE2G6BPi35CX
,
6438 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xabe, PE2G6BPi35CX
,
6440 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ , 0xabf, PE2G6BPi35CX
,
6443 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6444 SILICOM_PE2G2BPi80_SSID
/*PCI_ANY_ID */ , PE2G2BPi80
, "PE2G2BPi80"},
6445 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6446 SILICOM_PE2G2BPFi80_SSID
/*PCI_ANY_ID */ , PE2G2BPFi80
, "PE2G2BPFi80"},
6447 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6448 SILICOM_PE2G2BPFi80LX_SSID
/*PCI_ANY_ID */ , PE2G2BPFi80LX
,
6450 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6451 SILICOM_PE2G2BPFi80ZX_SSID
/*PCI_ANY_ID */ , PE2G2BPFi80ZX
,
6454 {0x8086, 0x10c9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6455 SILICOM_MEG2BPI6_SSID
/*PCI_ANY_ID */ , MEG2BPI6
, "MEG2BPI6"},
6456 {0x8086, 0x10c9, SILICOM_SVID
/*PCI_ANY_ID */ ,
6457 SILICOM_XEG2BPI6_SSID
/*PCI_ANY_ID */ , XEG2BPI6
, "XEG2BPI6"},
6460 {0x8086, 0x10fb, 0x8086, INTEL_PE210G2SPI9_SSID
, PE210G2SPI9
,
6463 {0x8086, 0x10fb, SILICOM_SVID
/*PCI_ANY_ID */ ,
6464 SILICOM_M1E10G2BPI9CX4_SSID
/*PCI_ANY_ID */ , M1E10G2BPI9CX4
,
6466 {0x8086, 0x10fb, SILICOM_SVID
/*PCI_ANY_ID */ ,
6467 SILICOM_M1E10G2BPI9SR_SSID
/*PCI_ANY_ID */ , M1E10G2BPI9SR
,
6469 {0x8086, 0x10fb, SILICOM_SVID
/*PCI_ANY_ID */ ,
6470 SILICOM_M1E10G2BPI9LR_SSID
/*PCI_ANY_ID */ , M1E10G2BPI9LR
,
6472 {0x8086, 0x10fb, SILICOM_SVID
/*PCI_ANY_ID */ ,
6473 SILICOM_M1E10G2BPI9T_SSID
/*PCI_ANY_ID */ , M1E10G2BPI9T
,
6476 {0x8086, 0x10fb, SILICOM_SVID
/*PCI_ANY_ID */ ,
6477 SILICOM_M2E10G2BPI9CX4_SSID
/*PCI_ANY_ID */ , M2E10G2BPI9CX4
,
6479 {0x8086, 0x10fb, SILICOM_SVID
/*PCI_ANY_ID */ ,
6480 SILICOM_M2E10G2BPI9SR_SSID
/*PCI_ANY_ID */ , M2E10G2BPI9SR
,
6482 {0x8086, 0x10fb, SILICOM_SVID
/*PCI_ANY_ID */ ,
6483 SILICOM_M2E10G2BPI9LR_SSID
/*PCI_ANY_ID */ , M2E10G2BPI9LR
,
6485 {0x8086, 0x10fb, SILICOM_SVID
/*PCI_ANY_ID */ ,
6486 SILICOM_M2E10G2BPI9T_SSID
/*PCI_ANY_ID */ , M2E10G2BPI9T
,
6489 {0x8086, 0x10fb, SILICOM_SVID
, SILICOM_PE210G2BPI9CX4_SSID
,
6490 PE210G2BPI9CX4
, "PE210G2BPI9CX4"},
6491 {0x8086, 0x10fb, SILICOM_SVID
, SILICOM_PE210G2BPI9SR_SSID
,
6492 PE210G2BPI9SR
, "PE210G2BPI9SR"},
6493 {0x8086, 0x10fb, SILICOM_SVID
, SILICOM_PE210G2BPI9LR_SSID
,
6494 PE210G2BPI9LR
, "PE210G2BPI9LR"},
6495 {0x8086, 0x10fb, SILICOM_SVID
, SILICOM_PE210G2BPI9T_SSID
, PE210G2BPI9T
,
6499 {0x1374, 0x2c, SILICOM_SVID
, SILICOM_PXG4BPI_SSID
, PXG4BPI
,
6502 {0x1374, 0x2d, SILICOM_SVID
, SILICOM_PXG4BPFI_SSID
, PXG4BPFI
,
6505 {0x1374, 0x3f, SILICOM_SVID
, SILICOM_PXG2TBI_SSID
, PXG2TBI
,
6508 {0x1374, 0x3d, SILICOM_SVID
, SILICOM_PXG2BISC1_SSID
, PXG2BISC1
,
6511 {0x1374, 0x40, SILICOM_SVID
, SILICOM_PEG4BPFI_SSID
, PEG4BPFI
,
6515 {0x1374, 0x28, SILICOM_SVID
, 0x28, PXGBPI
, "PXG2BPI-SD"},
6518 {0x8086, PCI_ANY_ID
, SILICOM_SVID
/*PCI_ANY_ID */ ,
6519 SILICOM_M6E2G8BPi80_SSID
/*PCI_ANY_ID */ , M6E2G8BPi80
, "MxE2G8BPi80"},
6520 {0x8086, 0x1528, SILICOM_SVID
/*PCI_ANY_ID */ ,
6521 SILICOM_PE210G2BPi40_SSID
/*PCI_ANY_ID */ , PE210G2BPi40
,
6524 /* required last entry */
6528 static void find_fw(struct bpctl_dev
*dev
)
6530 unsigned long mmio_start
, mmio_len
;
6531 struct pci_dev
*pdev1
= dev
->pdev
;
6533 if ((OLD_IF_SERIES(dev
->subdevice
)) ||
6534 (INTEL_IF_SERIES(dev
->subdevice
)))
6535 dev
->bp_fw_ver
= 0xff;
6537 dev
->bp_fw_ver
= bypass_fw_ver(dev
);
6539 if (dev
->bp_10gb
== 1 && dev
->bp_fw_ver
== 0xff) {
6542 iounmap((void *)dev
->mem_map
);
6543 mmio_start
= pci_resource_start(pdev1
, 0);
6544 mmio_len
= pci_resource_len(pdev1
, 0);
6546 dev
->mem_map
= (unsigned long)
6547 ioremap(mmio_start
, mmio_len
);
6549 dev
->bp_fw_ver
= bypass_fw_ver(dev
);
6550 if (dev
->bp_fw_ver
== 0xa8)
6554 /* dev->bp_fw_ver=0xa8; */
6555 printk("firmware version: 0x%x\n", dev
->bp_fw_ver
);
6558 static int init_one(struct bpctl_dev
*dev
, struct bpmod_info
*info
, struct pci_dev
*pdev1
)
6560 unsigned long mmio_start
, mmio_len
;
6563 mmio_start
= pci_resource_start(pdev1
, 0);
6564 mmio_len
= pci_resource_len(pdev1
, 0);
6566 dev
->desc
= dev_desc
[info
->index
].name
;
6567 dev
->name
= info
->bp_name
;
6568 dev
->device
= info
->device
;
6569 dev
->vendor
= info
->vendor
;
6570 dev
->subdevice
= info
->subdevice
;
6571 dev
->subvendor
= info
->subvendor
;
6572 dev
->func
= PCI_FUNC(pdev1
->devfn
);
6573 dev
->slot
= PCI_SLOT(pdev1
->devfn
);
6574 dev
->bus
= pdev1
->bus
->number
;
6575 dev
->mem_map
= (unsigned long)ioremap(mmio_start
, mmio_len
);
6577 spin_lock_init(&dev
->bypass_wr_lock
);
6579 if (BP10G9_IF_SERIES(dev
->subdevice
))
6581 if (BP10G_IF_SERIES(dev
->subdevice
))
6583 if (PEG540_IF_SERIES(dev
->subdevice
))
6585 if (PEGF5_IF_SERIES(dev
->subdevice
))
6587 if (PEG80_IF_SERIES(dev
->subdevice
))
6589 if (PEGF80_IF_SERIES(dev
->subdevice
))
6591 if ((dev
->subdevice
& 0xa00) == 0xa00)
6593 if (BP10GB_IF_SERIES(dev
->subdevice
)) {
6594 if (dev
->ifindex
== 0) {
6595 unregister_chrdev(major_num
, DEVICE_NAME
);
6596 printk("Please load network driver for %s adapter!\n",
6601 if (dev
->ndev
&& !(dev
->ndev
->flags
& IFF_UP
)) {
6602 unregister_chrdev(major_num
, DEVICE_NAME
);
6603 printk("Please bring up network interfaces for %s adapter!\n",
6610 if (!dev
->bp_10g9
) {
6611 if (is_bypass_fn(dev
)) {
6612 printk(KERN_INFO
"%s found, ",
6616 dev
->wdt_status
= WDT_STATUS_UNKNOWN
;
6617 dev
->reset_time
= 0;
6618 atomic_set(&dev
->wdt_busy
, 0);
6619 dev
->bp_status_un
= 1;
6621 bypass_caps_init(dev
);
6623 init_bypass_wd_auto(dev
);
6624 init_bypass_tpl_auto(dev
);
6625 if (NOKIA_SERIES(dev
->subdevice
))
6629 dev
->bp_tx_data
= kzalloc(BPTEST_DATA_LEN
, GFP_KERNEL
);
6630 if (dev
->bp_tx_data
) {
6631 memset(dev
->bp_tx_data
, 0xff, 6);
6632 memset(dev
->bp_tx_data
+ 6, 0x0, 1);
6633 memset(dev
->bp_tx_data
+ 7, 0xaa, 5);
6634 *(__be16
*)(dev
->bp_tx_data
+ 12) = htons(ETH_P_BPTEST
);
6636 printk("bp_ctl: Memory allocation error!\n");
6642 * Initialize the module - Register the character device
6645 static int __init
bypass_init_module(void)
6647 int ret_val
, idx
, idx_dev
= 0;
6648 struct pci_dev
*pdev1
= NULL
;
6649 struct bpctl_dev
*dev
;
6651 printk(BP_MOD_DESCR
" v" BP_MOD_VER
"\n");
6652 ret_val
= register_chrdev(major_num
, DEVICE_NAME
, &Fops
);
6654 printk("%s failed with %d\n", DEVICE_NAME
, ret_val
);
6657 major_num
= ret_val
; /* dynamic */
6658 for (idx
= 0; tx_ctl_pci_tbl
[idx
].vendor
; idx
++) {
6659 while ((pdev1
= pci_get_subsys(tx_ctl_pci_tbl
[idx
].vendor
,
6660 tx_ctl_pci_tbl
[idx
].device
,
6661 tx_ctl_pci_tbl
[idx
].subvendor
,
6662 tx_ctl_pci_tbl
[idx
].subdevice
,
6669 printk("No such device\n");
6670 unregister_chrdev(major_num
, DEVICE_NAME
);
6674 bpctl_dev_arr
= kmalloc((device_num
) * sizeof(struct bpctl_dev
), GFP_KERNEL
);
6676 if (!bpctl_dev_arr
) {
6677 printk("Allocation error\n");
6678 unregister_chrdev(major_num
, DEVICE_NAME
);
6681 memset(bpctl_dev_arr
, 0, ((device_num
) * sizeof(struct bpctl_dev
)));
6684 dev
= bpctl_dev_arr
;
6685 for (idx
= 0; tx_ctl_pci_tbl
[idx
].vendor
; idx
++) {
6686 while ((pdev1
= pci_get_subsys(tx_ctl_pci_tbl
[idx
].vendor
,
6687 tx_ctl_pci_tbl
[idx
].device
,
6688 tx_ctl_pci_tbl
[idx
].subvendor
,
6689 tx_ctl_pci_tbl
[idx
].subdevice
,
6691 if (init_one(dev
, &tx_ctl_pci_tbl
[idx
], pdev1
) < 0)
6698 sema_init(&bpctl_sema
, 1);
6699 spin_lock_init(&bpvm_lock
);
6702 struct bpctl_dev
*pbpctl_dev_c
= NULL
;
6703 for (idx_dev
= 0, dev
= bpctl_dev_arr
;
6704 idx_dev
< device_num
&& dev
->pdev
;
6707 pbpctl_dev_c
= get_status_port_fn(dev
);
6708 if (is_bypass_fn(dev
)) {
6709 printk(KERN_INFO
"%s found, ",
6711 dev
->bp_fw_ver
= bypass_fw_ver(dev
);
6712 printk("firmware version: 0x%x\n",
6715 dev
->wdt_status
= WDT_STATUS_UNKNOWN
;
6716 dev
->reset_time
= 0;
6717 atomic_set(&dev
->wdt_busy
, 0);
6718 dev
->bp_status_un
= 1;
6720 bypass_caps_init(dev
);
6722 init_bypass_wd_auto(dev
);
6723 init_bypass_tpl_auto(dev
);
6730 register_netdevice_notifier(&bp_notifier_block
);
6731 #ifdef BP_PROC_SUPPORT
6734 /* unsigned long flags; */
6735 /* rcu_read_lock(); */
6737 for (i
= 0; i
< device_num
; i
++) {
6738 if (bpctl_dev_arr
[i
].ifindex
) {
6739 /* spin_lock_irqsave(&bpvm_lock, flags); */
6740 bypass_proc_remove_dev_sd(&bpctl_dev_arr
[i
]);
6741 bypass_proc_create_dev_sd(&bpctl_dev_arr
[i
]);
6742 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
6746 /* rcu_read_unlock(); */
6754 * Cleanup - unregister the appropriate file from /proc
6756 static void __exit
bypass_cleanup_module(void)
6759 unregister_netdevice_notifier(&bp_notifier_block
);
6761 for (i
= 0; i
< device_num
; i
++) {
6762 /* unsigned long flags; */
6763 #ifdef BP_PROC_SUPPORT
6764 /* spin_lock_irqsave(&bpvm_lock, flags);
6766 bypass_proc_remove_dev_sd(&bpctl_dev_arr
[i
]);
6767 /* spin_unlock_irqrestore(&bpvm_lock, flags);
6768 rcu_read_unlock(); */
6770 remove_bypass_wd_auto(&bpctl_dev_arr
[i
]);
6771 bpctl_dev_arr
[i
].reset_time
= 0;
6773 remove_bypass_tpl_auto(&bpctl_dev_arr
[i
]);
6776 /* unmap all devices */
6777 for (i
= 0; i
< device_num
; i
++) {
6779 kfree(bpctl_dev_arr
[i
].bp_tx_data
);
6781 iounmap((void *)(bpctl_dev_arr
[i
].mem_map
));
6784 /* free all devices space */
6785 kfree(bpctl_dev_arr
);
6788 * Unregister the device
6790 unregister_chrdev(major_num
, DEVICE_NAME
);
6793 module_init(bypass_init_module
);
6794 module_exit(bypass_cleanup_module
);
6796 int is_bypass_sd(int ifindex
)
6798 return is_bypass(get_dev_idx_p(ifindex
));
6800 EXPORT_SYMBOL(is_bypass_sd
);
6802 int set_bypass_sd(int ifindex
, int bypass_mode
)
6805 return set_bypass_fn(get_dev_idx_p(ifindex
), bypass_mode
);
6807 EXPORT_SYMBOL(set_bypass_sd
);
6809 int get_bypass_sd(int ifindex
)
6812 return get_bypass_fn(get_dev_idx_p(ifindex
));
6814 EXPORT_SYMBOL(get_bypass_sd
);
6816 int get_bypass_change_sd(int ifindex
)
6819 return get_bypass_change_fn(get_dev_idx_p(ifindex
));
6821 EXPORT_SYMBOL(get_bypass_change_sd
);
6823 int set_dis_bypass_sd(int ifindex
, int dis_param
)
6825 return set_dis_bypass_fn(get_dev_idx_p(ifindex
), dis_param
);
6827 EXPORT_SYMBOL(set_dis_bypass_sd
);
6829 int get_dis_bypass_sd(int ifindex
)
6832 return get_dis_bypass_fn(get_dev_idx_p(ifindex
));
6834 EXPORT_SYMBOL(get_dis_bypass_sd
);
6836 int set_bypass_pwoff_sd(int ifindex
, int bypass_mode
)
6838 return set_bypass_pwoff_fn(get_dev_idx_p(ifindex
), bypass_mode
);
6841 EXPORT_SYMBOL(set_bypass_pwoff_sd
);
6843 int get_bypass_pwoff_sd(int ifindex
)
6845 return get_bypass_pwoff_fn(get_dev_idx_p(ifindex
));
6848 EXPORT_SYMBOL(get_bypass_pwoff_sd
);
6850 int set_bypass_pwup_sd(int ifindex
, int bypass_mode
)
6852 return set_bypass_pwup_fn(get_dev_idx_p(ifindex
), bypass_mode
);
6855 EXPORT_SYMBOL(set_bypass_pwup_sd
);
6857 int get_bypass_pwup_sd(int ifindex
)
6859 return get_bypass_pwup_fn(get_dev_idx_p(ifindex
));
6862 EXPORT_SYMBOL(get_bypass_pwup_sd
);
6864 int set_bypass_wd_sd(int if_index
, int ms_timeout
, int *ms_timeout_set
)
6866 if ((is_bypass(get_dev_idx_p(if_index
))) <= 0)
6868 *ms_timeout_set
= set_bypass_wd_fn(get_dev_idx_p(if_index
), ms_timeout
);
6871 EXPORT_SYMBOL(set_bypass_wd_sd
);
6873 int get_bypass_wd_sd(int ifindex
, int *timeout
)
6875 return get_bypass_wd_fn(get_dev_idx_p(ifindex
), timeout
);
6878 EXPORT_SYMBOL(get_bypass_wd_sd
);
6880 int get_wd_expire_time_sd(int ifindex
, int *time_left
)
6882 return get_wd_expire_time_fn(get_dev_idx_p(ifindex
), time_left
);
6884 EXPORT_SYMBOL(get_wd_expire_time_sd
);
6886 int reset_bypass_wd_timer_sd(int ifindex
)
6888 return reset_bypass_wd_timer_fn(get_dev_idx_p(ifindex
));
6891 EXPORT_SYMBOL(reset_bypass_wd_timer_sd
);
6893 int get_wd_set_caps_sd(int ifindex
)
6895 return get_wd_set_caps_fn(get_dev_idx_p(ifindex
));
6898 EXPORT_SYMBOL(get_wd_set_caps_sd
);
6900 int set_std_nic_sd(int ifindex
, int nic_mode
)
6902 return set_std_nic_fn(get_dev_idx_p(ifindex
), nic_mode
);
6905 EXPORT_SYMBOL(set_std_nic_sd
);
6907 int get_std_nic_sd(int ifindex
)
6909 return get_std_nic_fn(get_dev_idx_p(ifindex
));
6912 EXPORT_SYMBOL(get_std_nic_sd
);
6914 int set_tap_sd(int ifindex
, int tap_mode
)
6916 return set_tap_fn(get_dev_idx_p(ifindex
), tap_mode
);
6919 EXPORT_SYMBOL(set_tap_sd
);
6921 int get_tap_sd(int ifindex
)
6923 return get_tap_fn(get_dev_idx_p(ifindex
));
6926 EXPORT_SYMBOL(get_tap_sd
);
6928 int set_tap_pwup_sd(int ifindex
, int tap_mode
)
6930 return set_tap_pwup_fn(get_dev_idx_p(ifindex
), tap_mode
);
6933 EXPORT_SYMBOL(set_tap_pwup_sd
);
6935 int get_tap_pwup_sd(int ifindex
)
6937 return get_tap_pwup_fn(get_dev_idx_p(ifindex
));
6940 EXPORT_SYMBOL(get_tap_pwup_sd
);
6942 int get_tap_change_sd(int ifindex
)
6944 return get_tap_change_fn(get_dev_idx_p(ifindex
));
6947 EXPORT_SYMBOL(get_tap_change_sd
);
6949 int set_dis_tap_sd(int ifindex
, int dis_param
)
6951 return set_dis_tap_fn(get_dev_idx_p(ifindex
), dis_param
);
6954 EXPORT_SYMBOL(set_dis_tap_sd
);
6956 int get_dis_tap_sd(int ifindex
)
6958 return get_dis_tap_fn(get_dev_idx_p(ifindex
));
6961 EXPORT_SYMBOL(get_dis_tap_sd
);
6963 int set_bp_disc_sd(int ifindex
, int disc_mode
)
6965 return set_disc_fn(get_dev_idx_p(ifindex
), disc_mode
);
6968 EXPORT_SYMBOL(set_bp_disc_sd
);
6970 int get_bp_disc_sd(int ifindex
)
6972 return get_disc_fn(get_dev_idx_p(ifindex
));
6975 EXPORT_SYMBOL(get_bp_disc_sd
);
6977 int set_bp_disc_pwup_sd(int ifindex
, int disc_mode
)
6979 return set_disc_pwup_fn(get_dev_idx_p(ifindex
), disc_mode
);
6982 EXPORT_SYMBOL(set_bp_disc_pwup_sd
);
6984 int get_bp_disc_pwup_sd(int ifindex
)
6986 return get_disc_pwup_fn(get_dev_idx_p(ifindex
));
6989 EXPORT_SYMBOL(get_bp_disc_pwup_sd
);
6991 int get_bp_disc_change_sd(int ifindex
)
6993 return get_disc_change_fn(get_dev_idx_p(ifindex
));
6996 EXPORT_SYMBOL(get_bp_disc_change_sd
);
6998 int set_bp_dis_disc_sd(int ifindex
, int dis_param
)
7000 return set_dis_disc_fn(get_dev_idx_p(ifindex
), dis_param
);
7003 EXPORT_SYMBOL(set_bp_dis_disc_sd
);
7005 int get_bp_dis_disc_sd(int ifindex
)
7007 return get_dis_disc_fn(get_dev_idx_p(ifindex
));
7010 EXPORT_SYMBOL(get_bp_dis_disc_sd
);
7012 int get_wd_exp_mode_sd(int ifindex
)
7014 return get_wd_exp_mode_fn(get_dev_idx_p(ifindex
));
7016 EXPORT_SYMBOL(get_wd_exp_mode_sd
);
7018 int set_wd_exp_mode_sd(int ifindex
, int param
)
7020 return set_wd_exp_mode_fn(get_dev_idx_p(ifindex
), param
);
7023 EXPORT_SYMBOL(set_wd_exp_mode_sd
);
7025 int reset_cont_sd(int ifindex
)
7027 return reset_cont_fn(get_dev_idx_p(ifindex
));
7031 int set_tx_sd(int ifindex
, int tx_state
)
7033 return set_tx_fn(get_dev_idx_p(ifindex
), tx_state
);
7036 EXPORT_SYMBOL(set_tx_sd
);
7038 int set_tpl_sd(int ifindex
, int tpl_state
)
7040 return set_tpl_fn(get_dev_idx_p(ifindex
), tpl_state
);
7043 EXPORT_SYMBOL(set_tpl_sd
);
7045 int set_bp_hw_reset_sd(int ifindex
, int status
)
7047 return set_bp_hw_reset_fn(get_dev_idx_p(ifindex
), status
);
7050 EXPORT_SYMBOL(set_bp_hw_reset_sd
);
7052 int set_wd_autoreset_sd(int ifindex
, int param
)
7054 return set_wd_autoreset_fn(get_dev_idx_p(ifindex
), param
);
7057 EXPORT_SYMBOL(set_wd_autoreset_sd
);
7059 int get_wd_autoreset_sd(int ifindex
)
7061 return get_wd_autoreset_fn(get_dev_idx_p(ifindex
));
7064 EXPORT_SYMBOL(get_wd_autoreset_sd
);
7066 int get_bypass_caps_sd(int ifindex
)
7068 return get_bypass_caps_fn(get_dev_idx_p(ifindex
));
7070 EXPORT_SYMBOL(get_bypass_caps_sd
);
7072 int get_bypass_slave_sd(int ifindex
)
7074 struct bpctl_dev
*pbpctl_dev_out
;
7075 int ret
= get_bypass_slave_fn(get_dev_idx_p(ifindex
), &pbpctl_dev_out
);
7077 return pbpctl_dev_out
->ifindex
;
7081 EXPORT_SYMBOL(get_bypass_slave_sd
);
7083 int get_tx_sd(int ifindex
)
7085 return get_tx_fn(get_dev_idx_p(ifindex
));
7088 EXPORT_SYMBOL(get_tx_sd
);
7090 int get_tpl_sd(int ifindex
)
7092 return get_tpl_fn(get_dev_idx_p(ifindex
));
7095 EXPORT_SYMBOL(get_tpl_sd
);
7097 int get_bp_hw_reset_sd(int ifindex
)
7099 return get_bp_hw_reset_fn(get_dev_idx_p(ifindex
));
7102 EXPORT_SYMBOL(get_bp_hw_reset_sd
);
7104 int get_bypass_info_sd(int ifindex
, struct bp_info
*bp_info
)
7106 return get_bypass_info_fn(get_dev_idx_p(ifindex
), bp_info
->prod_name
, &bp_info
->fw_ver
);
7108 EXPORT_SYMBOL(get_bypass_info_sd
);
7110 int bp_if_scan_sd(void)
7115 EXPORT_SYMBOL(bp_if_scan_sd
);
7117 #define BP_PROC_DIR "bypass"
7119 static struct proc_dir_entry
*bp_procfs_dir
;
7121 int bp_proc_create(void)
7123 bp_procfs_dir
= proc_mkdir(BP_PROC_DIR
, init_net
.proc_net
);
7124 if (bp_procfs_dir
== (struct proc_dir_entry
*)0) {
7126 "Could not create procfs nicinfo directory %s\n",
7133 static int procfs_add(char *proc_name
, const struct file_operations
*fops
,
7134 struct bpctl_dev
*dev
)
7136 struct bypass_pfs_sd
*pfs
= &dev
->bypass_pfs_set
;
7137 if (!proc_create_data(proc_name
, 0644, pfs
->bypass_entry
, fops
, dev
))
7142 #define RO_FOPS(name) \
7143 static int name##_open(struct inode *inode, struct file *file) \
7145 return single_open(file, show_##name, PDE_DATA(inode));\
7147 static const struct file_operations name##_ops = { \
7148 .open = name##_open, \
7150 .llseek = seq_lseek, \
7151 .release = single_release, \
7154 #define RW_FOPS(name) \
7155 static int name##_open(struct inode *inode, struct file *file) \
7157 return single_open(file, show_##name, PDE_DATA(inode));\
7159 static const struct file_operations name##_ops = { \
7160 .open = name##_open, \
7162 .write = name##_write, \
7163 .llseek = seq_lseek, \
7164 .release = single_release, \
7167 static int show_bypass_info(struct seq_file
*m
, void *v
)
7169 struct bpctl_dev
*dev
= m
->private;
7171 seq_printf(m
, "Name\t\t\t%s\n", dev
->name
);
7172 seq_printf(m
, "Firmware version\t0x%x\n", dev
->bp_fw_ver
);
7175 RO_FOPS(bypass_info
)
7177 static int show_bypass_slave(struct seq_file
*m
, void *v
)
7179 struct bpctl_dev
*dev
= m
->private;
7180 struct bpctl_dev
*slave
= get_status_port_fn(dev
);
7184 seq_puts(m
, "fail\n");
7185 else if (slave
->ndev
)
7186 seq_printf(m
, "%s\n", slave
->ndev
->name
);
7189 RO_FOPS(bypass_slave
)
7191 static int show_bypass_caps(struct seq_file
*m
, void *v
)
7193 struct bpctl_dev
*dev
= m
->private;
7194 int ret
= get_bypass_caps_fn(dev
);
7195 if (ret
== BP_NOT_CAP
)
7196 seq_puts(m
, "-1\n");
7198 seq_printf(m
, "0x%x\n", ret
);
7201 RO_FOPS(bypass_caps
)
7203 static int show_wd_set_caps(struct seq_file
*m
, void *v
)
7205 struct bpctl_dev
*dev
= m
->private;
7206 int ret
= get_wd_set_caps_fn(dev
);
7207 if (ret
== BP_NOT_CAP
)
7208 seq_puts(m
, "-1\n");
7210 seq_printf(m
, "0x%x\n", ret
);
7213 RO_FOPS(wd_set_caps
)
7215 static int user_on_off(const void __user
*buffer
, size_t count
)
7221 if (count
> (sizeof(kbuf
) - 1))
7224 if (copy_from_user(&kbuf
, buffer
, count
))
7228 length
= strlen(kbuf
);
7229 if (kbuf
[length
- 1] == '\n')
7230 kbuf
[--length
] = '\0';
7232 if (strcmp(kbuf
, "on") == 0)
7234 if (strcmp(kbuf
, "off") == 0)
7239 static ssize_t
bypass_write(struct file
*file
, const char __user
*buffer
,
7240 size_t count
, loff_t
*pos
)
7242 int bypass_param
= user_on_off(buffer
, count
);
7243 if (bypass_param
< 0)
7246 set_bypass_fn(PDE_DATA(file_inode(file
)), bypass_param
);
7249 static int show_bypass(struct seq_file
*m
, void *v
)
7251 struct bpctl_dev
*dev
= m
->private;
7252 int ret
= get_bypass_fn(dev
);
7253 if (ret
== BP_NOT_CAP
)
7254 seq_puts(m
, "fail\n");
7256 seq_puts(m
, "on\n");
7258 seq_puts(m
, "off\n");
7263 static ssize_t
tap_write(struct file
*file
, const char __user
*buffer
,
7264 size_t count
, loff_t
*pos
)
7266 int tap_param
= user_on_off(buffer
, count
);
7270 set_tap_fn(PDE_DATA(file_inode(file
)), tap_param
);
7273 static int show_tap(struct seq_file
*m
, void *v
)
7275 struct bpctl_dev
*dev
= m
->private;
7276 int ret
= get_tap_fn(dev
);
7277 if (ret
== BP_NOT_CAP
)
7278 seq_puts(m
, "fail\n");
7280 seq_puts(m
, "on\n");
7282 seq_puts(m
, "off\n");
7287 static ssize_t
disc_write(struct file
*file
, const char __user
*buffer
,
7288 size_t count
, loff_t
*pos
)
7290 int tap_param
= user_on_off(buffer
, count
);
7294 set_disc_fn(PDE_DATA(file_inode(file
)), tap_param
);
7297 static int show_disc(struct seq_file
*m
, void *v
)
7299 struct bpctl_dev
*dev
= m
->private;
7300 int ret
= get_disc_fn(dev
);
7301 if (ret
== BP_NOT_CAP
)
7302 seq_puts(m
, "fail\n");
7304 seq_puts(m
, "on\n");
7306 seq_puts(m
, "off\n");
7311 static int show_bypass_change(struct seq_file
*m
, void *v
)
7313 struct bpctl_dev
*dev
= m
->private;
7314 int ret
= get_bypass_change_fn(dev
);
7316 seq_puts(m
, "on\n");
7318 seq_puts(m
, "off\n");
7320 seq_puts(m
, "fail\n");
7323 RO_FOPS(bypass_change
)
7325 static int show_tap_change(struct seq_file
*m
, void *v
)
7327 struct bpctl_dev
*dev
= m
->private;
7328 int ret
= get_tap_change_fn(dev
);
7330 seq_puts(m
, "on\n");
7332 seq_puts(m
, "off\n");
7334 seq_puts(m
, "fail\n");
7339 static int show_disc_change(struct seq_file
*m
, void *v
)
7341 struct bpctl_dev
*dev
= m
->private;
7342 int ret
= get_disc_change_fn(dev
);
7344 seq_puts(m
, "on\n");
7346 seq_puts(m
, "off\n");
7348 seq_puts(m
, "fail\n");
7351 RO_FOPS(disc_change
)
7353 static ssize_t
bypass_wd_write(struct file
*file
, const char __user
*buffer
,
7354 size_t count
, loff_t
*pos
)
7356 struct bpctl_dev
*dev
= PDE_DATA(file_inode(file
));
7358 int ret
= kstrtoint_from_user(buffer
, count
, 10, &timeout
);
7361 set_bypass_wd_fn(dev
, timeout
);
7364 static int show_bypass_wd(struct seq_file
*m
, void *v
)
7366 struct bpctl_dev
*dev
= m
->private;
7367 int ret
= 0, timeout
= 0;
7369 ret
= get_bypass_wd_fn(dev
, &timeout
);
7370 if (ret
== BP_NOT_CAP
)
7371 seq_puts(m
, "fail\n");
7372 else if (timeout
== -1)
7373 seq_puts(m
, "unknown\n");
7374 else if (timeout
== 0)
7375 seq_puts(m
, "disable\n");
7377 seq_printf(m
, "%d\n", timeout
);
7382 static int show_wd_expire_time(struct seq_file
*m
, void *v
)
7384 struct bpctl_dev
*dev
= m
->private;
7385 int ret
= 0, timeout
= 0;
7386 ret
= get_wd_expire_time_fn(dev
, &timeout
);
7387 if (ret
== BP_NOT_CAP
)
7388 seq_puts(m
, "fail\n");
7389 else if (timeout
== -1)
7390 seq_puts(m
, "expire\n");
7391 else if (timeout
== 0)
7392 seq_puts(m
, "disable\n");
7394 seq_printf(m
, "%d\n", timeout
);
7397 RO_FOPS(wd_expire_time
)
7399 static ssize_t
tpl_write(struct file
*file
, const char __user
*buffer
,
7400 size_t count
, loff_t
*pos
)
7402 struct bpctl_dev
*dev
= PDE_DATA(file_inode(file
));
7403 int tpl_param
= user_on_off(buffer
, count
);
7407 set_tpl_fn(dev
, tpl_param
);
7410 static int show_tpl(struct seq_file
*m
, void *v
)
7412 struct bpctl_dev
*dev
= m
->private;
7413 int ret
= get_tpl_fn(dev
);
7414 if (ret
== BP_NOT_CAP
)
7415 seq_puts(m
, "fail\n");
7417 seq_puts(m
, "on\n");
7419 seq_puts(m
, "off\n");
7425 static ssize_t
wait_at_pwup_write(struct file
*file
, const char __user
*buffer
,
7426 size_t count
, loff_t
*pos
)
7428 struct bpctl_dev
*dev
= PDE_DATA(file_inode(file
));
7429 int tpl_param
= user_on_off(buffer
, count
);
7433 set_bp_wait_at_pwup_fn(dev
, tpl_param
);
7436 static int show_wait_at_pwup(struct seq_file
*m
, void *v
)
7438 struct bpctl_dev
*dev
= m
->private;
7439 int ret
= get_bp_wait_at_pwup_fn(dev
);
7440 if (ret
== BP_NOT_CAP
)
7441 seq_puts(m
, "fail\n");
7443 seq_puts(m
, "on\n");
7445 seq_puts(m
, "off\n");
7448 RW_FOPS(wait_at_pwup
)
7450 static ssize_t
hw_reset_write(struct file
*file
, const char __user
*buffer
,
7451 size_t count
, loff_t
*pos
)
7453 struct bpctl_dev
*dev
= PDE_DATA(file_inode(file
));
7454 int tpl_param
= user_on_off(buffer
, count
);
7458 set_bp_hw_reset_fn(dev
, tpl_param
);
7461 static int show_hw_reset(struct seq_file
*m
, void *v
)
7463 struct bpctl_dev
*dev
= m
->private;
7464 int ret
= get_bp_hw_reset_fn(dev
);
7465 if (ret
== BP_NOT_CAP
)
7466 seq_puts(m
, "fail\n");
7468 seq_puts(m
, "on\n");
7470 seq_puts(m
, "off\n");
7475 #endif /*PMC_WAIT_FLAG */
7477 static int show_reset_bypass_wd(struct seq_file
*m
, void *v
)
7479 struct bpctl_dev
*dev
= m
->private;
7480 int ret
= reset_bypass_wd_timer_fn(dev
);
7481 if (ret
== BP_NOT_CAP
)
7482 seq_puts(m
, "fail\n");
7484 seq_puts(m
, "disable\n");
7486 seq_puts(m
, "success\n");
7489 RO_FOPS(reset_bypass_wd
)
7491 static ssize_t
dis_bypass_write(struct file
*file
, const char __user
*buffer
,
7492 size_t count
, loff_t
*pos
)
7494 int bypass_param
= user_on_off(buffer
, count
);
7495 if (bypass_param
< 0)
7498 set_dis_bypass_fn(PDE_DATA(file_inode(file
)), bypass_param
);
7501 static int show_dis_bypass(struct seq_file
*m
, void *v
)
7503 struct bpctl_dev
*dev
= m
->private;
7504 int ret
= get_dis_bypass_fn(dev
);
7505 if (ret
== BP_NOT_CAP
)
7506 seq_puts(m
, "fail\n");
7508 seq_puts(m
, "off\n");
7510 seq_puts(m
, "on\n");
7515 static ssize_t
dis_tap_write(struct file
*file
, const char __user
*buffer
,
7516 size_t count
, loff_t
*pos
)
7518 int tap_param
= user_on_off(buffer
, count
);
7522 set_dis_tap_fn(PDE_DATA(file_inode(file
)), tap_param
);
7525 static int show_dis_tap(struct seq_file
*m
, void *v
)
7527 struct bpctl_dev
*dev
= m
->private;
7528 int ret
= get_dis_tap_fn(dev
);
7529 if (ret
== BP_NOT_CAP
)
7530 seq_puts(m
, "fail\n");
7532 seq_puts(m
, "off\n");
7534 seq_puts(m
, "on\n");
7539 static ssize_t
dis_disc_write(struct file
*file
, const char __user
*buffer
,
7540 size_t count
, loff_t
*pos
)
7542 int tap_param
= user_on_off(buffer
, count
);
7546 set_dis_disc_fn(PDE_DATA(file_inode(file
)), tap_param
);
7549 static int show_dis_disc(struct seq_file
*m
, void *v
)
7551 struct bpctl_dev
*dev
= m
->private;
7552 int ret
= get_dis_disc_fn(dev
);
7553 if (ret
== BP_NOT_CAP
)
7554 seq_puts(m
, "fail\n");
7556 seq_puts(m
, "off\n");
7558 seq_puts(m
, "on\n");
7563 static ssize_t
bypass_pwup_write(struct file
*file
, const char __user
*buffer
,
7564 size_t count
, loff_t
*pos
)
7566 int bypass_param
= user_on_off(buffer
, count
);
7567 if (bypass_param
< 0)
7570 set_bypass_pwup_fn(PDE_DATA(file_inode(file
)), bypass_param
);
7573 static int show_bypass_pwup(struct seq_file
*m
, void *v
)
7575 struct bpctl_dev
*dev
= m
->private;
7576 int ret
= get_bypass_pwup_fn(dev
);
7577 if (ret
== BP_NOT_CAP
)
7578 seq_puts(m
, "fail\n");
7580 seq_puts(m
, "off\n");
7582 seq_puts(m
, "on\n");
7585 RW_FOPS(bypass_pwup
)
7587 static ssize_t
bypass_pwoff_write(struct file
*file
, const char __user
*buffer
,
7588 size_t count
, loff_t
*pos
)
7590 int bypass_param
= user_on_off(buffer
, count
);
7591 if (bypass_param
< 0)
7594 set_bypass_pwoff_fn(PDE_DATA(file_inode(file
)), bypass_param
);
7597 static int show_bypass_pwoff(struct seq_file
*m
, void *v
)
7599 struct bpctl_dev
*dev
= m
->private;
7600 int ret
= get_bypass_pwoff_fn(dev
);
7601 if (ret
== BP_NOT_CAP
)
7602 seq_puts(m
, "fail\n");
7604 seq_puts(m
, "off\n");
7606 seq_puts(m
, "on\n");
7609 RW_FOPS(bypass_pwoff
)
7611 static ssize_t
tap_pwup_write(struct file
*file
, const char __user
*buffer
,
7612 size_t count
, loff_t
*pos
)
7614 int tap_param
= user_on_off(buffer
, count
);
7618 set_tap_pwup_fn(PDE_DATA(file_inode(file
)), tap_param
);
7621 static int show_tap_pwup(struct seq_file
*m
, void *v
)
7623 struct bpctl_dev
*dev
= m
->private;
7624 int ret
= get_tap_pwup_fn(dev
);
7625 if (ret
== BP_NOT_CAP
)
7626 seq_puts(m
, "fail\n");
7628 seq_puts(m
, "off\n");
7630 seq_puts(m
, "on\n");
7635 static ssize_t
disc_pwup_write(struct file
*file
, const char __user
*buffer
,
7636 size_t count
, loff_t
*pos
)
7638 int tap_param
= user_on_off(buffer
, count
);
7642 set_disc_pwup_fn(PDE_DATA(file_inode(file
)), tap_param
);
7645 static int show_disc_pwup(struct seq_file
*m
, void *v
)
7647 struct bpctl_dev
*dev
= m
->private;
7648 int ret
= get_disc_pwup_fn(dev
);
7649 if (ret
== BP_NOT_CAP
)
7650 seq_puts(m
, "fail\n");
7652 seq_puts(m
, "off\n");
7654 seq_puts(m
, "on\n");
7659 static ssize_t
std_nic_write(struct file
*file
, const char __user
*buffer
,
7660 size_t count
, loff_t
*pos
)
7662 int bypass_param
= user_on_off(buffer
, count
);
7663 if (bypass_param
< 0)
7666 set_std_nic_fn(PDE_DATA(file_inode(file
)), bypass_param
);
7669 static int show_std_nic(struct seq_file
*m
, void *v
)
7671 struct bpctl_dev
*dev
= m
->private;
7672 int ret
= get_std_nic_fn(dev
);
7673 if (ret
== BP_NOT_CAP
)
7674 seq_puts(m
, "fail\n");
7676 seq_puts(m
, "off\n");
7678 seq_puts(m
, "on\n");
7683 static ssize_t
wd_exp_mode_write(struct file
*file
, const char __user
*buffer
,
7684 size_t count
, loff_t
*pos
)
7687 int bypass_param
= 0, length
= 0;
7689 if (count
> (sizeof(kbuf
) - 1))
7692 if (copy_from_user(&kbuf
, buffer
, count
))
7696 length
= strlen(kbuf
);
7697 if (kbuf
[length
- 1] == '\n')
7698 kbuf
[--length
] = '\0';
7700 if (strcmp(kbuf
, "tap") == 0)
7702 else if (strcmp(kbuf
, "bypass") == 0)
7704 else if (strcmp(kbuf
, "disc") == 0)
7707 set_wd_exp_mode_fn(PDE_DATA(file_inode(file
)), bypass_param
);
7711 static int show_wd_exp_mode(struct seq_file
*m
, void *v
)
7713 struct bpctl_dev
*dev
= m
->private;
7714 int ret
= get_wd_exp_mode_fn(dev
);
7716 seq_puts(m
, "tap\n");
7718 seq_puts(m
, "bypass\n");
7720 seq_puts(m
, "disc\n");
7722 seq_puts(m
, "fail\n");
7725 RW_FOPS(wd_exp_mode
)
7727 static ssize_t
wd_autoreset_write(struct file
*file
, const char __user
*buffer
,
7728 size_t count
, loff_t
*pos
)
7731 int ret
= kstrtoint_from_user(buffer
, count
, 10, &timeout
);
7734 set_wd_autoreset_fn(PDE_DATA(file_inode(file
)), timeout
);
7737 static int show_wd_autoreset(struct seq_file
*m
, void *v
)
7739 struct bpctl_dev
*dev
= m
->private;
7740 int ret
= get_wd_autoreset_fn(dev
);
7742 seq_printf(m
, "%d\n", ret
);
7744 seq_puts(m
, "fail\n");
7747 RW_FOPS(wd_autoreset
)
7749 int bypass_proc_create_dev_sd(struct bpctl_dev
*pbp_device_block
)
7751 struct bypass_pfs_sd
*current_pfs
= &(pbp_device_block
->bypass_pfs_set
);
7752 static struct proc_dir_entry
*procfs_dir
;
7755 if (!pbp_device_block
->ndev
)
7757 sprintf(current_pfs
->dir_name
, "bypass_%s",
7758 pbp_device_block
->ndev
->name
);
7763 /* create device proc dir */
7764 procfs_dir
= proc_mkdir(current_pfs
->dir_name
, bp_procfs_dir
);
7766 printk(KERN_DEBUG
"Could not create procfs directory %s\n",
7767 current_pfs
->dir_name
);
7770 current_pfs
->bypass_entry
= procfs_dir
;
7772 #define ENTRY(x) (ret |= procfs_add(#x, &x##_ops, pbp_device_block))
7775 if (pbp_device_block
->bp_caps
& SW_CTL_CAP
) {
7776 /* Create set param proc's */
7777 ENTRY(bypass_slave
);
7781 ENTRY(wd_expire_time
);
7782 ENTRY(reset_bypass_wd
);
7784 if (pbp_device_block
->bp_caps
& BP_CAP
) {
7788 ENTRY(bypass_pwoff
);
7789 ENTRY(bypass_change
);
7791 if (pbp_device_block
->bp_caps
& TAP_CAP
) {
7797 if (pbp_device_block
->bp_caps
& DISC_CAP
) {
7805 ENTRY(wd_autoreset
);
7808 ENTRY(wait_at_pwup
);
7814 printk(KERN_DEBUG
"Create proc entry failed\n");
7819 int bypass_proc_remove_dev_sd(struct bpctl_dev
*pbp_device_block
)
7822 struct bypass_pfs_sd
*current_pfs
= &pbp_device_block
->bypass_pfs_set
;
7823 remove_proc_subtree(current_pfs
->dir_name
, bp_procfs_dir
);
7824 current_pfs
->bypass_entry
= NULL
;