2 * Support for the Tundra TSI148 VME-PCI Bridge Chip
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/proc_fs.h>
22 #include <linux/pci.h>
23 #include <linux/poll.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/interrupt.h>
26 #include <linux/spinlock.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
31 #include <asm/uaccess.h>
34 #include "../vme_bridge.h"
35 #include "vme_tsi148.h"
37 static int __init
tsi148_init(void);
38 static int tsi148_probe(struct pci_dev
*, const struct pci_device_id
*);
39 static void tsi148_remove(struct pci_dev
*);
40 static void __exit
tsi148_exit(void);
43 int tsi148_slave_set(struct vme_slave_resource
*, int, unsigned long long,
44 unsigned long long, dma_addr_t
, vme_address_t
, vme_cycle_t
);
45 int tsi148_slave_get(struct vme_slave_resource
*, int *, unsigned long long *,
46 unsigned long long *, dma_addr_t
*, vme_address_t
*, vme_cycle_t
*);
48 int tsi148_master_get(struct vme_master_resource
*, int *, unsigned long long *,
49 unsigned long long *, vme_address_t
*, vme_cycle_t
*, vme_width_t
*);
50 int tsi148_master_set(struct vme_master_resource
*, int, unsigned long long,
51 unsigned long long, vme_address_t
, vme_cycle_t
, vme_width_t
);
52 ssize_t
tsi148_master_read(struct vme_master_resource
*, void *, size_t,
54 ssize_t
tsi148_master_write(struct vme_master_resource
*, void *, size_t,
56 unsigned int tsi148_master_rmw(struct vme_master_resource
*, unsigned int,
57 unsigned int, unsigned int, loff_t
);
58 int tsi148_dma_list_add (struct vme_dma_list
*, struct vme_dma_attr
*,
59 struct vme_dma_attr
*, size_t);
60 int tsi148_dma_list_exec(struct vme_dma_list
*);
61 int tsi148_dma_list_empty(struct vme_dma_list
*);
62 int tsi148_generate_irq(int, int);
64 /* Module parameter */
68 static char driver_name
[] = "vme_tsi148";
70 static const struct pci_device_id tsi148_ids
[] = {
71 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA
, PCI_DEVICE_ID_TUNDRA_TSI148
) },
75 static struct pci_driver tsi148_driver
= {
77 .id_table
= tsi148_ids
,
78 .probe
= tsi148_probe
,
79 .remove
= tsi148_remove
,
82 static void reg_join(unsigned int high
, unsigned int low
,
83 unsigned long long *variable
)
85 *variable
= (unsigned long long)high
<< 32;
86 *variable
|= (unsigned long long)low
;
89 static void reg_split(unsigned long long variable
, unsigned int *high
,
92 *low
= (unsigned int)variable
& 0xFFFFFFFF;
93 *high
= (unsigned int)(variable
>> 32);
99 static u32
tsi148_DMA_irqhandler(struct tsi148_driver
*bridge
,
104 if (channel_mask
& TSI148_LCSR_INTS_DMA0S
) {
105 wake_up(&(bridge
->dma_queue
[0]));
106 serviced
|= TSI148_LCSR_INTC_DMA0C
;
108 if (channel_mask
& TSI148_LCSR_INTS_DMA1S
) {
109 wake_up(&(bridge
->dma_queue
[1]));
110 serviced
|= TSI148_LCSR_INTC_DMA1C
;
117 * Wake up location monitor queue
119 static u32
tsi148_LM_irqhandler(struct tsi148_driver
*bridge
, u32 stat
)
124 for (i
= 0; i
< 4; i
++) {
125 if(stat
& TSI148_LCSR_INTS_LMS
[i
]) {
126 /* We only enable interrupts if the callback is set */
127 bridge
->lm_callback
[i
](i
);
128 serviced
|= TSI148_LCSR_INTC_LMC
[i
];
136 * Wake up mail box queue.
138 * XXX This functionality is not exposed up though API.
140 static u32
tsi148_MB_irqhandler(struct vme_bridge
*tsi148_bridge
, u32 stat
)
145 struct tsi148_driver
*bridge
;
147 bridge
= tsi148_bridge
->driver_priv
;
149 for (i
= 0; i
< 4; i
++) {
150 if(stat
& TSI148_LCSR_INTS_MBS
[i
]) {
151 val
= ioread32be(bridge
->base
+ TSI148_GCSR_MBOX
[i
]);
152 dev_err(tsi148_bridge
->parent
, "VME Mailbox %d received"
154 serviced
|= TSI148_LCSR_INTC_MBC
[i
];
162 * Display error & status message when PERR (PCI) exception interrupt occurs.
164 static u32
tsi148_PERR_irqhandler(struct vme_bridge
*tsi148_bridge
)
166 struct tsi148_driver
*bridge
;
168 bridge
= tsi148_bridge
->driver_priv
;
170 dev_err(tsi148_bridge
->parent
, "PCI Exception at address: 0x%08x:%08x, "
171 "attributes: %08x\n",
172 ioread32be(bridge
->base
+ TSI148_LCSR_EDPAU
),
173 ioread32be(bridge
->base
+ TSI148_LCSR_EDPAL
),
174 ioread32be(bridge
->base
+ TSI148_LCSR_EDPAT
));
176 dev_err(tsi148_bridge
->parent
, "PCI-X attribute reg: %08x, PCI-X split "
177 "completion reg: %08x\n",
178 ioread32be(bridge
->base
+ TSI148_LCSR_EDPXA
),
179 ioread32be(bridge
->base
+ TSI148_LCSR_EDPXS
));
181 iowrite32be(TSI148_LCSR_EDPAT_EDPCL
, bridge
->base
+ TSI148_LCSR_EDPAT
);
183 return TSI148_LCSR_INTC_PERRC
;
187 * Save address and status when VME error interrupt occurs.
189 static u32
tsi148_VERR_irqhandler(struct vme_bridge
*tsi148_bridge
)
191 unsigned int error_addr_high
, error_addr_low
;
192 unsigned long long error_addr
;
194 struct vme_bus_error
*error
;
195 struct tsi148_driver
*bridge
;
197 bridge
= tsi148_bridge
->driver_priv
;
199 error_addr_high
= ioread32be(bridge
->base
+ TSI148_LCSR_VEAU
);
200 error_addr_low
= ioread32be(bridge
->base
+ TSI148_LCSR_VEAL
);
201 error_attrib
= ioread32be(bridge
->base
+ TSI148_LCSR_VEAT
);
203 reg_join(error_addr_high
, error_addr_low
, &error_addr
);
205 /* Check for exception register overflow (we have lost error data) */
206 if(error_attrib
& TSI148_LCSR_VEAT_VEOF
) {
207 dev_err(tsi148_bridge
->parent
, "VME Bus Exception Overflow "
211 error
= (struct vme_bus_error
*)kmalloc(sizeof (struct vme_bus_error
),
214 error
->address
= error_addr
;
215 error
->attributes
= error_attrib
;
216 list_add_tail(&(error
->list
), &(tsi148_bridge
->vme_errors
));
218 dev_err(tsi148_bridge
->parent
, "Unable to alloc memory for "
219 "VMEbus Error reporting\n");
220 dev_err(tsi148_bridge
->parent
, "VME Bus Error at address: "
221 "0x%llx, attributes: %08x\n", error_addr
, error_attrib
);
225 iowrite32be(TSI148_LCSR_VEAT_VESCL
, bridge
->base
+ TSI148_LCSR_VEAT
);
227 return TSI148_LCSR_INTC_VERRC
;
231 * Wake up IACK queue.
233 static u32
tsi148_IACK_irqhandler(struct tsi148_driver
*bridge
)
235 wake_up(&(bridge
->iack_queue
));
237 return TSI148_LCSR_INTC_IACKC
;
241 * Calling VME bus interrupt callback if provided.
243 static u32
tsi148_VIRQ_irqhandler(struct vme_bridge
*tsi148_bridge
,
246 int vec
, i
, serviced
= 0;
247 struct tsi148_driver
*bridge
;
249 bridge
= tsi148_bridge
->driver_priv
;
251 for (i
= 7; i
> 0; i
--) {
252 if (stat
& (1 << i
)) {
254 * Note: Even though the registers are defined
255 * as 32-bits in the spec, we only want to issue
256 * 8-bit IACK cycles on the bus, read from offset
259 vec
= ioread8(bridge
->base
+ TSI148_LCSR_VIACK
[i
] + 3);
261 vme_irq_handler(tsi148_bridge
, i
, vec
);
263 serviced
|= (1 << i
);
271 * Top level interrupt handler. Clears appropriate interrupt status bits and
272 * then calls appropriate sub handler(s).
274 static irqreturn_t
tsi148_irqhandler(int irq
, void *ptr
)
276 u32 stat
, enable
, serviced
= 0;
277 struct vme_bridge
*tsi148_bridge
;
278 struct tsi148_driver
*bridge
;
282 bridge
= tsi148_bridge
->driver_priv
;
284 /* Determine which interrupts are unmasked and set */
285 enable
= ioread32be(bridge
->base
+ TSI148_LCSR_INTEO
);
286 stat
= ioread32be(bridge
->base
+ TSI148_LCSR_INTS
);
288 /* Only look at unmasked interrupts */
291 if (unlikely(!stat
)) {
295 /* Call subhandlers as appropriate */
297 if (stat
& (TSI148_LCSR_INTS_DMA1S
| TSI148_LCSR_INTS_DMA0S
))
298 serviced
|= tsi148_DMA_irqhandler(bridge
, stat
);
300 /* Location monitor irqs */
301 if (stat
& (TSI148_LCSR_INTS_LM3S
| TSI148_LCSR_INTS_LM2S
|
302 TSI148_LCSR_INTS_LM1S
| TSI148_LCSR_INTS_LM0S
))
303 serviced
|= tsi148_LM_irqhandler(bridge
, stat
);
306 if (stat
& (TSI148_LCSR_INTS_MB3S
| TSI148_LCSR_INTS_MB2S
|
307 TSI148_LCSR_INTS_MB1S
| TSI148_LCSR_INTS_MB0S
))
308 serviced
|= tsi148_MB_irqhandler(tsi148_bridge
, stat
);
311 if (stat
& TSI148_LCSR_INTS_PERRS
)
312 serviced
|= tsi148_PERR_irqhandler(tsi148_bridge
);
315 if (stat
& TSI148_LCSR_INTS_VERRS
)
316 serviced
|= tsi148_VERR_irqhandler(tsi148_bridge
);
319 if (stat
& TSI148_LCSR_INTS_IACKS
)
320 serviced
|= tsi148_IACK_irqhandler(bridge
);
323 if (stat
& (TSI148_LCSR_INTS_IRQ7S
| TSI148_LCSR_INTS_IRQ6S
|
324 TSI148_LCSR_INTS_IRQ5S
| TSI148_LCSR_INTS_IRQ4S
|
325 TSI148_LCSR_INTS_IRQ3S
| TSI148_LCSR_INTS_IRQ2S
|
326 TSI148_LCSR_INTS_IRQ1S
))
327 serviced
|= tsi148_VIRQ_irqhandler(tsi148_bridge
, stat
);
329 /* Clear serviced interrupts */
330 iowrite32be(serviced
, bridge
->base
+ TSI148_LCSR_INTC
);
335 static int tsi148_irq_init(struct vme_bridge
*tsi148_bridge
)
339 struct pci_dev
*pdev
;
340 struct tsi148_driver
*bridge
;
342 pdev
= container_of(tsi148_bridge
->parent
, struct pci_dev
, dev
);
344 bridge
= tsi148_bridge
->driver_priv
;
346 /* Initialise list for VME bus errors */
347 INIT_LIST_HEAD(&(tsi148_bridge
->vme_errors
));
349 mutex_init(&(tsi148_bridge
->irq_mtx
));
351 result
= request_irq(pdev
->irq
,
354 driver_name
, tsi148_bridge
);
356 dev_err(tsi148_bridge
->parent
, "Can't get assigned pci irq "
357 "vector %02X\n", pdev
->irq
);
361 /* Enable and unmask interrupts */
362 tmp
= TSI148_LCSR_INTEO_DMA1EO
| TSI148_LCSR_INTEO_DMA0EO
|
363 TSI148_LCSR_INTEO_MB3EO
| TSI148_LCSR_INTEO_MB2EO
|
364 TSI148_LCSR_INTEO_MB1EO
| TSI148_LCSR_INTEO_MB0EO
|
365 TSI148_LCSR_INTEO_PERREO
| TSI148_LCSR_INTEO_VERREO
|
366 TSI148_LCSR_INTEO_IACKEO
;
368 /* This leaves the following interrupts masked.
369 * TSI148_LCSR_INTEO_VIEEO
370 * TSI148_LCSR_INTEO_SYSFLEO
371 * TSI148_LCSR_INTEO_ACFLEO
374 /* Don't enable Location Monitor interrupts here - they will be
375 * enabled when the location monitors are properly configured and
376 * a callback has been attached.
377 * TSI148_LCSR_INTEO_LM0EO
378 * TSI148_LCSR_INTEO_LM1EO
379 * TSI148_LCSR_INTEO_LM2EO
380 * TSI148_LCSR_INTEO_LM3EO
383 /* Don't enable VME interrupts until we add a handler, else the board
384 * will respond to it and we don't want that unless it knows how to
385 * properly deal with it.
386 * TSI148_LCSR_INTEO_IRQ7EO
387 * TSI148_LCSR_INTEO_IRQ6EO
388 * TSI148_LCSR_INTEO_IRQ5EO
389 * TSI148_LCSR_INTEO_IRQ4EO
390 * TSI148_LCSR_INTEO_IRQ3EO
391 * TSI148_LCSR_INTEO_IRQ2EO
392 * TSI148_LCSR_INTEO_IRQ1EO
395 iowrite32be(tmp
, bridge
->base
+ TSI148_LCSR_INTEO
);
396 iowrite32be(tmp
, bridge
->base
+ TSI148_LCSR_INTEN
);
401 static void tsi148_irq_exit(struct tsi148_driver
*bridge
, struct pci_dev
*pdev
)
403 /* Turn off interrupts */
404 iowrite32be(0x0, bridge
->base
+ TSI148_LCSR_INTEO
);
405 iowrite32be(0x0, bridge
->base
+ TSI148_LCSR_INTEN
);
407 /* Clear all interrupts */
408 iowrite32be(0xFFFFFFFF, bridge
->base
+ TSI148_LCSR_INTC
);
410 /* Detach interrupt handler */
411 free_irq(pdev
->irq
, pdev
);
415 * Check to see if an IACk has been received, return true (1) or false (0).
417 int tsi148_iack_received(struct tsi148_driver
*bridge
)
421 tmp
= ioread32be(bridge
->base
+ TSI148_LCSR_VICR
);
423 if (tmp
& TSI148_LCSR_VICR_IRQS
)
430 * Configure VME interrupt
432 void tsi148_irq_set(struct vme_bridge
*tsi148_bridge
, int level
,
435 struct pci_dev
*pdev
;
437 struct tsi148_driver
*bridge
;
439 bridge
= tsi148_bridge
->driver_priv
;
441 /* We need to do the ordering differently for enabling and disabling */
443 tmp
= ioread32be(bridge
->base
+ TSI148_LCSR_INTEN
);
444 tmp
&= ~TSI148_LCSR_INTEN_IRQEN
[level
- 1];
445 iowrite32be(tmp
, bridge
->base
+ TSI148_LCSR_INTEN
);
447 tmp
= ioread32be(bridge
->base
+ TSI148_LCSR_INTEO
);
448 tmp
&= ~TSI148_LCSR_INTEO_IRQEO
[level
- 1];
449 iowrite32be(tmp
, bridge
->base
+ TSI148_LCSR_INTEO
);
452 pdev
= container_of(tsi148_bridge
->parent
,
453 struct pci_dev
, dev
);
455 synchronize_irq(pdev
->irq
);
458 tmp
= ioread32be(bridge
->base
+ TSI148_LCSR_INTEO
);
459 tmp
|= TSI148_LCSR_INTEO_IRQEO
[level
- 1];
460 iowrite32be(tmp
, bridge
->base
+ TSI148_LCSR_INTEO
);
462 tmp
= ioread32be(bridge
->base
+ TSI148_LCSR_INTEN
);
463 tmp
|= TSI148_LCSR_INTEN_IRQEN
[level
- 1];
464 iowrite32be(tmp
, bridge
->base
+ TSI148_LCSR_INTEN
);
469 * Generate a VME bus interrupt at the requested level & vector. Wait for
470 * interrupt to be acked.
472 int tsi148_irq_generate(struct vme_bridge
*tsi148_bridge
, int level
, int statid
)
475 struct tsi148_driver
*bridge
;
477 bridge
= tsi148_bridge
->driver_priv
;
479 mutex_lock(&(bridge
->vme_int
));
481 /* Read VICR register */
482 tmp
= ioread32be(bridge
->base
+ TSI148_LCSR_VICR
);
485 tmp
= (tmp
& ~TSI148_LCSR_VICR_STID_M
) |
486 (statid
& TSI148_LCSR_VICR_STID_M
);
487 iowrite32be(tmp
, bridge
->base
+ TSI148_LCSR_VICR
);
489 /* Assert VMEbus IRQ */
490 tmp
= tmp
| TSI148_LCSR_VICR_IRQL
[level
];
491 iowrite32be(tmp
, bridge
->base
+ TSI148_LCSR_VICR
);
493 /* XXX Consider implementing a timeout? */
494 wait_event_interruptible(bridge
->iack_queue
,
495 tsi148_iack_received(bridge
));
497 mutex_unlock(&(bridge
->vme_int
));
503 * Find the first error in this address range
505 static struct vme_bus_error
*tsi148_find_error(struct vme_bridge
*tsi148_bridge
,
506 vme_address_t aspace
, unsigned long long address
, size_t count
)
508 struct list_head
*err_pos
;
509 struct vme_bus_error
*vme_err
, *valid
= NULL
;
510 unsigned long long bound
;
512 bound
= address
+ count
;
515 * XXX We are currently not looking at the address space when parsing
516 * for errors. This is because parsing the Address Modifier Codes
517 * is going to be quite resource intensive to do properly. We
518 * should be OK just looking at the addresses and this is certainly
519 * much better than what we had before.
522 /* Iterate through errors */
523 list_for_each(err_pos
, &(tsi148_bridge
->vme_errors
)) {
524 vme_err
= list_entry(err_pos
, struct vme_bus_error
, list
);
525 if((vme_err
->address
>= address
) && (vme_err
->address
< bound
)){
535 * Clear errors in the provided address range.
537 static void tsi148_clear_errors(struct vme_bridge
*tsi148_bridge
,
538 vme_address_t aspace
, unsigned long long address
, size_t count
)
540 struct list_head
*err_pos
, *temp
;
541 struct vme_bus_error
*vme_err
;
542 unsigned long long bound
;
544 bound
= address
+ count
;
547 * XXX We are currently not looking at the address space when parsing
548 * for errors. This is because parsing the Address Modifier Codes
549 * is going to be quite resource intensive to do properly. We
550 * should be OK just looking at the addresses and this is certainly
551 * much better than what we had before.
554 /* Iterate through errors */
555 list_for_each_safe(err_pos
, temp
, &(tsi148_bridge
->vme_errors
)) {
556 vme_err
= list_entry(err_pos
, struct vme_bus_error
, list
);
558 if((vme_err
->address
>= address
) && (vme_err
->address
< bound
)){
566 * Initialize a slave window with the requested attributes.
568 int tsi148_slave_set(struct vme_slave_resource
*image
, int enabled
,
569 unsigned long long vme_base
, unsigned long long size
,
570 dma_addr_t pci_base
, vme_address_t aspace
, vme_cycle_t cycle
)
572 unsigned int i
, addr
= 0, granularity
= 0;
573 unsigned int temp_ctl
= 0;
574 unsigned int vme_base_low
, vme_base_high
;
575 unsigned int vme_bound_low
, vme_bound_high
;
576 unsigned int pci_offset_low
, pci_offset_high
;
577 unsigned long long vme_bound
, pci_offset
;
578 struct vme_bridge
*tsi148_bridge
;
579 struct tsi148_driver
*bridge
;
581 tsi148_bridge
= image
->parent
;
582 bridge
= tsi148_bridge
->driver_priv
;
589 addr
|= TSI148_LCSR_ITAT_AS_A16
;
592 granularity
= 0x1000;
593 addr
|= TSI148_LCSR_ITAT_AS_A24
;
596 granularity
= 0x10000;
597 addr
|= TSI148_LCSR_ITAT_AS_A32
;
600 granularity
= 0x10000;
601 addr
|= TSI148_LCSR_ITAT_AS_A64
;
609 dev_err(tsi148_bridge
->parent
, "Invalid address space\n");
614 /* Convert 64-bit variables to 2x 32-bit variables */
615 reg_split(vme_base
, &vme_base_high
, &vme_base_low
);
618 * Bound address is a valid address for the window, adjust
621 vme_bound
= vme_base
+ size
- granularity
;
622 reg_split(vme_bound
, &vme_bound_high
, &vme_bound_low
);
623 pci_offset
= (unsigned long long)pci_base
- vme_base
;
624 reg_split(pci_offset
, &pci_offset_high
, &pci_offset_low
);
626 if (vme_base_low
& (granularity
- 1)) {
627 dev_err(tsi148_bridge
->parent
, "Invalid VME base alignment\n");
630 if (vme_bound_low
& (granularity
- 1)) {
631 dev_err(tsi148_bridge
->parent
, "Invalid VME bound alignment\n");
634 if (pci_offset_low
& (granularity
- 1)) {
635 dev_err(tsi148_bridge
->parent
, "Invalid PCI Offset "
640 /* Disable while we are mucking around */
641 temp_ctl
= ioread32be(bridge
->base
+ TSI148_LCSR_IT
[i
] +
642 TSI148_LCSR_OFFSET_ITAT
);
643 temp_ctl
&= ~TSI148_LCSR_ITAT_EN
;
644 iowrite32be(temp_ctl
, bridge
->base
+ TSI148_LCSR_IT
[i
] +
645 TSI148_LCSR_OFFSET_ITAT
);
648 iowrite32be(vme_base_high
, bridge
->base
+ TSI148_LCSR_IT
[i
] +
649 TSI148_LCSR_OFFSET_ITSAU
);
650 iowrite32be(vme_base_low
, bridge
->base
+ TSI148_LCSR_IT
[i
] +
651 TSI148_LCSR_OFFSET_ITSAL
);
652 iowrite32be(vme_bound_high
, bridge
->base
+ TSI148_LCSR_IT
[i
] +
653 TSI148_LCSR_OFFSET_ITEAU
);
654 iowrite32be(vme_bound_low
, bridge
->base
+ TSI148_LCSR_IT
[i
] +
655 TSI148_LCSR_OFFSET_ITEAL
);
656 iowrite32be(pci_offset_high
, bridge
->base
+ TSI148_LCSR_IT
[i
] +
657 TSI148_LCSR_OFFSET_ITOFU
);
658 iowrite32be(pci_offset_low
, bridge
->base
+ TSI148_LCSR_IT
[i
] +
659 TSI148_LCSR_OFFSET_ITOFL
);
661 /* Setup 2eSST speeds */
662 temp_ctl
&= ~TSI148_LCSR_ITAT_2eSSTM_M
;
663 switch (cycle
& (VME_2eSST160
| VME_2eSST267
| VME_2eSST320
)) {
665 temp_ctl
|= TSI148_LCSR_ITAT_2eSSTM_160
;
668 temp_ctl
|= TSI148_LCSR_ITAT_2eSSTM_267
;
671 temp_ctl
|= TSI148_LCSR_ITAT_2eSSTM_320
;
675 /* Setup cycle types */
676 temp_ctl
&= ~(0x1F << 7);
678 temp_ctl
|= TSI148_LCSR_ITAT_BLT
;
679 if (cycle
& VME_MBLT
)
680 temp_ctl
|= TSI148_LCSR_ITAT_MBLT
;
681 if (cycle
& VME_2eVME
)
682 temp_ctl
|= TSI148_LCSR_ITAT_2eVME
;
683 if (cycle
& VME_2eSST
)
684 temp_ctl
|= TSI148_LCSR_ITAT_2eSST
;
685 if (cycle
& VME_2eSSTB
)
686 temp_ctl
|= TSI148_LCSR_ITAT_2eSSTB
;
688 /* Setup address space */
689 temp_ctl
&= ~TSI148_LCSR_ITAT_AS_M
;
693 if (cycle
& VME_SUPER
)
694 temp_ctl
|= TSI148_LCSR_ITAT_SUPR
;
695 if (cycle
& VME_USER
)
696 temp_ctl
|= TSI148_LCSR_ITAT_NPRIV
;
697 if (cycle
& VME_PROG
)
698 temp_ctl
|= TSI148_LCSR_ITAT_PGM
;
699 if (cycle
& VME_DATA
)
700 temp_ctl
|= TSI148_LCSR_ITAT_DATA
;
702 /* Write ctl reg without enable */
703 iowrite32be(temp_ctl
, bridge
->base
+ TSI148_LCSR_IT
[i
] +
704 TSI148_LCSR_OFFSET_ITAT
);
707 temp_ctl
|= TSI148_LCSR_ITAT_EN
;
709 iowrite32be(temp_ctl
, bridge
->base
+ TSI148_LCSR_IT
[i
] +
710 TSI148_LCSR_OFFSET_ITAT
);
716 * Get slave window configuration.
718 int tsi148_slave_get(struct vme_slave_resource
*image
, int *enabled
,
719 unsigned long long *vme_base
, unsigned long long *size
,
720 dma_addr_t
*pci_base
, vme_address_t
*aspace
, vme_cycle_t
*cycle
)
722 unsigned int i
, granularity
= 0, ctl
= 0;
723 unsigned int vme_base_low
, vme_base_high
;
724 unsigned int vme_bound_low
, vme_bound_high
;
725 unsigned int pci_offset_low
, pci_offset_high
;
726 unsigned long long vme_bound
, pci_offset
;
727 struct tsi148_driver
*bridge
;
729 bridge
= image
->parent
->driver_priv
;
734 ctl
= ioread32be(bridge
->base
+ TSI148_LCSR_IT
[i
] +
735 TSI148_LCSR_OFFSET_ITAT
);
737 vme_base_high
= ioread32be(bridge
->base
+ TSI148_LCSR_IT
[i
] +
738 TSI148_LCSR_OFFSET_ITSAU
);
739 vme_base_low
= ioread32be(bridge
->base
+ TSI148_LCSR_IT
[i
] +
740 TSI148_LCSR_OFFSET_ITSAL
);
741 vme_bound_high
= ioread32be(bridge
->base
+ TSI148_LCSR_IT
[i
] +
742 TSI148_LCSR_OFFSET_ITEAU
);
743 vme_bound_low
= ioread32be(bridge
->base
+ TSI148_LCSR_IT
[i
] +
744 TSI148_LCSR_OFFSET_ITEAL
);
745 pci_offset_high
= ioread32be(bridge
->base
+ TSI148_LCSR_IT
[i
] +
746 TSI148_LCSR_OFFSET_ITOFU
);
747 pci_offset_low
= ioread32be(bridge
->base
+ TSI148_LCSR_IT
[i
] +
748 TSI148_LCSR_OFFSET_ITOFL
);
750 /* Convert 64-bit variables to 2x 32-bit variables */
751 reg_join(vme_base_high
, vme_base_low
, vme_base
);
752 reg_join(vme_bound_high
, vme_bound_low
, &vme_bound
);
753 reg_join(pci_offset_high
, pci_offset_low
, &pci_offset
);
755 *pci_base
= (dma_addr_t
)vme_base
+ pci_offset
;
761 if (ctl
& TSI148_LCSR_ITAT_EN
)
764 if ((ctl
& TSI148_LCSR_ITAT_AS_M
) == TSI148_LCSR_ITAT_AS_A16
) {
768 if ((ctl
& TSI148_LCSR_ITAT_AS_M
) == TSI148_LCSR_ITAT_AS_A24
) {
769 granularity
= 0x1000;
772 if ((ctl
& TSI148_LCSR_ITAT_AS_M
) == TSI148_LCSR_ITAT_AS_A32
) {
773 granularity
= 0x10000;
776 if ((ctl
& TSI148_LCSR_ITAT_AS_M
) == TSI148_LCSR_ITAT_AS_A64
) {
777 granularity
= 0x10000;
781 /* Need granularity before we set the size */
782 *size
= (unsigned long long)((vme_bound
- *vme_base
) + granularity
);
785 if ((ctl
& TSI148_LCSR_ITAT_2eSSTM_M
) == TSI148_LCSR_ITAT_2eSSTM_160
)
786 *cycle
|= VME_2eSST160
;
787 if ((ctl
& TSI148_LCSR_ITAT_2eSSTM_M
) == TSI148_LCSR_ITAT_2eSSTM_267
)
788 *cycle
|= VME_2eSST267
;
789 if ((ctl
& TSI148_LCSR_ITAT_2eSSTM_M
) == TSI148_LCSR_ITAT_2eSSTM_320
)
790 *cycle
|= VME_2eSST320
;
792 if (ctl
& TSI148_LCSR_ITAT_BLT
)
794 if (ctl
& TSI148_LCSR_ITAT_MBLT
)
796 if (ctl
& TSI148_LCSR_ITAT_2eVME
)
798 if (ctl
& TSI148_LCSR_ITAT_2eSST
)
800 if (ctl
& TSI148_LCSR_ITAT_2eSSTB
)
801 *cycle
|= VME_2eSSTB
;
803 if (ctl
& TSI148_LCSR_ITAT_SUPR
)
805 if (ctl
& TSI148_LCSR_ITAT_NPRIV
)
807 if (ctl
& TSI148_LCSR_ITAT_PGM
)
809 if (ctl
& TSI148_LCSR_ITAT_DATA
)
816 * Allocate and map PCI Resource
818 static int tsi148_alloc_resource(struct vme_master_resource
*image
,
819 unsigned long long size
)
821 unsigned long long existing_size
;
823 struct pci_dev
*pdev
;
824 struct vme_bridge
*tsi148_bridge
;
826 tsi148_bridge
= image
->parent
;
828 pdev
= container_of(tsi148_bridge
->parent
, struct pci_dev
, dev
);
830 existing_size
= (unsigned long long)(image
->bus_resource
.end
-
831 image
->bus_resource
.start
);
833 /* If the existing size is OK, return */
834 if ((size
!= 0) && (existing_size
== (size
- 1)))
837 if (existing_size
!= 0) {
838 iounmap(image
->kern_base
);
839 image
->kern_base
= NULL
;
840 if (image
->bus_resource
.name
!= NULL
)
841 kfree(image
->bus_resource
.name
);
842 release_resource(&(image
->bus_resource
));
843 memset(&(image
->bus_resource
), 0, sizeof(struct resource
));
846 /* Exit here if size is zero */
851 if (image
->bus_resource
.name
== NULL
) {
852 image
->bus_resource
.name
= kmalloc(VMENAMSIZ
+3, GFP_KERNEL
);
853 if (image
->bus_resource
.name
== NULL
) {
854 dev_err(tsi148_bridge
->parent
, "Unable to allocate "
855 "memory for resource name\n");
861 sprintf((char *)image
->bus_resource
.name
, "%s.%d", tsi148_bridge
->name
,
864 image
->bus_resource
.start
= 0;
865 image
->bus_resource
.end
= (unsigned long)size
;
866 image
->bus_resource
.flags
= IORESOURCE_MEM
;
868 retval
= pci_bus_alloc_resource(pdev
->bus
,
869 &(image
->bus_resource
), size
, size
, PCIBIOS_MIN_MEM
,
872 dev_err(tsi148_bridge
->parent
, "Failed to allocate mem "
873 "resource for window %d size 0x%lx start 0x%lx\n",
874 image
->number
, (unsigned long)size
,
875 (unsigned long)image
->bus_resource
.start
);
879 image
->kern_base
= ioremap_nocache(
880 image
->bus_resource
.start
, size
);
881 if (image
->kern_base
== NULL
) {
882 dev_err(tsi148_bridge
->parent
, "Failed to remap resource\n");
889 iounmap(image
->kern_base
);
890 image
->kern_base
= NULL
;
892 release_resource(&(image
->bus_resource
));
894 kfree(image
->bus_resource
.name
);
895 memset(&(image
->bus_resource
), 0, sizeof(struct resource
));
901 * Free and unmap PCI Resource
903 static void tsi148_free_resource(struct vme_master_resource
*image
)
905 iounmap(image
->kern_base
);
906 image
->kern_base
= NULL
;
907 release_resource(&(image
->bus_resource
));
908 kfree(image
->bus_resource
.name
);
909 memset(&(image
->bus_resource
), 0, sizeof(struct resource
));
913 * Set the attributes of an outbound window.
915 int tsi148_master_set( struct vme_master_resource
*image
, int enabled
,
916 unsigned long long vme_base
, unsigned long long size
,
917 vme_address_t aspace
, vme_cycle_t cycle
, vme_width_t dwidth
)
921 unsigned int temp_ctl
= 0;
922 unsigned int pci_base_low
, pci_base_high
;
923 unsigned int pci_bound_low
, pci_bound_high
;
924 unsigned int vme_offset_low
, vme_offset_high
;
925 unsigned long long pci_bound
, vme_offset
, pci_base
;
926 struct vme_bridge
*tsi148_bridge
;
927 struct tsi148_driver
*bridge
;
929 tsi148_bridge
= image
->parent
;
931 bridge
= tsi148_bridge
->driver_priv
;
933 /* Verify input data */
934 if (vme_base
& 0xFFFF) {
935 dev_err(tsi148_bridge
->parent
, "Invalid VME Window "
941 if ((size
== 0) && (enabled
!= 0)) {
942 dev_err(tsi148_bridge
->parent
, "Size must be non-zero for "
943 "enabled windows\n");
948 spin_lock(&(image
->lock
));
950 /* Let's allocate the resource here rather than further up the stack as
951 * it avoids pushing loads of bus dependant stuff up the stack. If size
952 * is zero, any existing resource will be freed.
954 retval
= tsi148_alloc_resource(image
, size
);
956 spin_unlock(&(image
->lock
));
957 dev_err(tsi148_bridge
->parent
, "Unable to allocate memory for "
967 pci_base
= (unsigned long long)image
->bus_resource
.start
;
970 * Bound address is a valid address for the window, adjust
971 * according to window granularity.
973 pci_bound
= pci_base
+ (size
- 0x10000);
974 vme_offset
= vme_base
- pci_base
;
977 /* Convert 64-bit variables to 2x 32-bit variables */
978 reg_split(pci_base
, &pci_base_high
, &pci_base_low
);
979 reg_split(pci_bound
, &pci_bound_high
, &pci_bound_low
);
980 reg_split(vme_offset
, &vme_offset_high
, &vme_offset_low
);
982 if (pci_base_low
& 0xFFFF) {
983 spin_unlock(&(image
->lock
));
984 dev_err(tsi148_bridge
->parent
, "Invalid PCI base alignment\n");
988 if (pci_bound_low
& 0xFFFF) {
989 spin_unlock(&(image
->lock
));
990 dev_err(tsi148_bridge
->parent
, "Invalid PCI bound alignment\n");
994 if (vme_offset_low
& 0xFFFF) {
995 spin_unlock(&(image
->lock
));
996 dev_err(tsi148_bridge
->parent
, "Invalid VME Offset "
1004 /* Disable while we are mucking around */
1005 temp_ctl
= ioread32be(bridge
->base
+ TSI148_LCSR_OT
[i
] +
1006 TSI148_LCSR_OFFSET_OTAT
);
1007 temp_ctl
&= ~TSI148_LCSR_OTAT_EN
;
1008 iowrite32be(temp_ctl
, bridge
->base
+ TSI148_LCSR_OT
[i
] +
1009 TSI148_LCSR_OFFSET_OTAT
);
1011 /* Setup 2eSST speeds */
1012 temp_ctl
&= ~TSI148_LCSR_OTAT_2eSSTM_M
;
1013 switch (cycle
& (VME_2eSST160
| VME_2eSST267
| VME_2eSST320
)) {
1015 temp_ctl
|= TSI148_LCSR_OTAT_2eSSTM_160
;
1018 temp_ctl
|= TSI148_LCSR_OTAT_2eSSTM_267
;
1021 temp_ctl
|= TSI148_LCSR_OTAT_2eSSTM_320
;
1025 /* Setup cycle types */
1026 if (cycle
& VME_BLT
) {
1027 temp_ctl
&= ~TSI148_LCSR_OTAT_TM_M
;
1028 temp_ctl
|= TSI148_LCSR_OTAT_TM_BLT
;
1030 if (cycle
& VME_MBLT
) {
1031 temp_ctl
&= ~TSI148_LCSR_OTAT_TM_M
;
1032 temp_ctl
|= TSI148_LCSR_OTAT_TM_MBLT
;
1034 if (cycle
& VME_2eVME
) {
1035 temp_ctl
&= ~TSI148_LCSR_OTAT_TM_M
;
1036 temp_ctl
|= TSI148_LCSR_OTAT_TM_2eVME
;
1038 if (cycle
& VME_2eSST
) {
1039 temp_ctl
&= ~TSI148_LCSR_OTAT_TM_M
;
1040 temp_ctl
|= TSI148_LCSR_OTAT_TM_2eSST
;
1042 if (cycle
& VME_2eSSTB
) {
1043 dev_warn(tsi148_bridge
->parent
, "Currently not setting "
1044 "Broadcast Select Registers\n");
1045 temp_ctl
&= ~TSI148_LCSR_OTAT_TM_M
;
1046 temp_ctl
|= TSI148_LCSR_OTAT_TM_2eSSTB
;
1049 /* Setup data width */
1050 temp_ctl
&= ~TSI148_LCSR_OTAT_DBW_M
;
1053 temp_ctl
|= TSI148_LCSR_OTAT_DBW_16
;
1056 temp_ctl
|= TSI148_LCSR_OTAT_DBW_32
;
1059 spin_unlock(&(image
->lock
));
1060 dev_err(tsi148_bridge
->parent
, "Invalid data width\n");
1065 /* Setup address space */
1066 temp_ctl
&= ~TSI148_LCSR_OTAT_AMODE_M
;
1069 temp_ctl
|= TSI148_LCSR_OTAT_AMODE_A16
;
1072 temp_ctl
|= TSI148_LCSR_OTAT_AMODE_A24
;
1075 temp_ctl
|= TSI148_LCSR_OTAT_AMODE_A32
;
1078 temp_ctl
|= TSI148_LCSR_OTAT_AMODE_A64
;
1081 temp_ctl
|= TSI148_LCSR_OTAT_AMODE_CRCSR
;
1084 temp_ctl
|= TSI148_LCSR_OTAT_AMODE_USER1
;
1087 temp_ctl
|= TSI148_LCSR_OTAT_AMODE_USER2
;
1090 temp_ctl
|= TSI148_LCSR_OTAT_AMODE_USER3
;
1093 temp_ctl
|= TSI148_LCSR_OTAT_AMODE_USER4
;
1096 spin_unlock(&(image
->lock
));
1097 dev_err(tsi148_bridge
->parent
, "Invalid address space\n");
1103 temp_ctl
&= ~(3<<4);
1104 if (cycle
& VME_SUPER
)
1105 temp_ctl
|= TSI148_LCSR_OTAT_SUP
;
1106 if (cycle
& VME_PROG
)
1107 temp_ctl
|= TSI148_LCSR_OTAT_PGM
;
1110 iowrite32be(pci_base_high
, bridge
->base
+ TSI148_LCSR_OT
[i
] +
1111 TSI148_LCSR_OFFSET_OTSAU
);
1112 iowrite32be(pci_base_low
, bridge
->base
+ TSI148_LCSR_OT
[i
] +
1113 TSI148_LCSR_OFFSET_OTSAL
);
1114 iowrite32be(pci_bound_high
, bridge
->base
+ TSI148_LCSR_OT
[i
] +
1115 TSI148_LCSR_OFFSET_OTEAU
);
1116 iowrite32be(pci_bound_low
, bridge
->base
+ TSI148_LCSR_OT
[i
] +
1117 TSI148_LCSR_OFFSET_OTEAL
);
1118 iowrite32be(vme_offset_high
, bridge
->base
+ TSI148_LCSR_OT
[i
] +
1119 TSI148_LCSR_OFFSET_OTOFU
);
1120 iowrite32be(vme_offset_low
, bridge
->base
+ TSI148_LCSR_OT
[i
] +
1121 TSI148_LCSR_OFFSET_OTOFL
);
1123 /* Write ctl reg without enable */
1124 iowrite32be(temp_ctl
, bridge
->base
+ TSI148_LCSR_OT
[i
] +
1125 TSI148_LCSR_OFFSET_OTAT
);
1128 temp_ctl
|= TSI148_LCSR_OTAT_EN
;
1130 iowrite32be(temp_ctl
, bridge
->base
+ TSI148_LCSR_OT
[i
] +
1131 TSI148_LCSR_OFFSET_OTAT
);
1133 spin_unlock(&(image
->lock
));
1139 tsi148_free_resource(image
);
1147 * Set the attributes of an outbound window.
1149 * XXX Not parsing prefetch information.
1151 int __tsi148_master_get( struct vme_master_resource
*image
, int *enabled
,
1152 unsigned long long *vme_base
, unsigned long long *size
,
1153 vme_address_t
*aspace
, vme_cycle_t
*cycle
, vme_width_t
*dwidth
)
1155 unsigned int i
, ctl
;
1156 unsigned int pci_base_low
, pci_base_high
;
1157 unsigned int pci_bound_low
, pci_bound_high
;
1158 unsigned int vme_offset_low
, vme_offset_high
;
1160 unsigned long long pci_base
, pci_bound
, vme_offset
;
1161 struct tsi148_driver
*bridge
;
1163 bridge
= image
->parent
->driver_priv
;
1167 ctl
= ioread32be(bridge
->base
+ TSI148_LCSR_OT
[i
] +
1168 TSI148_LCSR_OFFSET_OTAT
);
1170 pci_base_high
= ioread32be(bridge
->base
+ TSI148_LCSR_OT
[i
] +
1171 TSI148_LCSR_OFFSET_OTSAU
);
1172 pci_base_low
= ioread32be(bridge
->base
+ TSI148_LCSR_OT
[i
] +
1173 TSI148_LCSR_OFFSET_OTSAL
);
1174 pci_bound_high
= ioread32be(bridge
->base
+ TSI148_LCSR_OT
[i
] +
1175 TSI148_LCSR_OFFSET_OTEAU
);
1176 pci_bound_low
= ioread32be(bridge
->base
+ TSI148_LCSR_OT
[i
] +
1177 TSI148_LCSR_OFFSET_OTEAL
);
1178 vme_offset_high
= ioread32be(bridge
->base
+ TSI148_LCSR_OT
[i
] +
1179 TSI148_LCSR_OFFSET_OTOFU
);
1180 vme_offset_low
= ioread32be(bridge
->base
+ TSI148_LCSR_OT
[i
] +
1181 TSI148_LCSR_OFFSET_OTOFL
);
1183 /* Convert 64-bit variables to 2x 32-bit variables */
1184 reg_join(pci_base_high
, pci_base_low
, &pci_base
);
1185 reg_join(pci_bound_high
, pci_bound_low
, &pci_bound
);
1186 reg_join(vme_offset_high
, vme_offset_low
, &vme_offset
);
1188 *vme_base
= pci_base
+ vme_offset
;
1189 *size
= (unsigned long long)(pci_bound
- pci_base
) + 0x10000;
1196 if (ctl
& TSI148_LCSR_OTAT_EN
)
1199 /* Setup address space */
1200 if ((ctl
& TSI148_LCSR_OTAT_AMODE_M
) == TSI148_LCSR_OTAT_AMODE_A16
)
1202 if ((ctl
& TSI148_LCSR_OTAT_AMODE_M
) == TSI148_LCSR_OTAT_AMODE_A24
)
1204 if ((ctl
& TSI148_LCSR_OTAT_AMODE_M
) == TSI148_LCSR_OTAT_AMODE_A32
)
1206 if ((ctl
& TSI148_LCSR_OTAT_AMODE_M
) == TSI148_LCSR_OTAT_AMODE_A64
)
1208 if ((ctl
& TSI148_LCSR_OTAT_AMODE_M
) == TSI148_LCSR_OTAT_AMODE_CRCSR
)
1209 *aspace
|= VME_CRCSR
;
1210 if ((ctl
& TSI148_LCSR_OTAT_AMODE_M
) == TSI148_LCSR_OTAT_AMODE_USER1
)
1211 *aspace
|= VME_USER1
;
1212 if ((ctl
& TSI148_LCSR_OTAT_AMODE_M
) == TSI148_LCSR_OTAT_AMODE_USER2
)
1213 *aspace
|= VME_USER2
;
1214 if ((ctl
& TSI148_LCSR_OTAT_AMODE_M
) == TSI148_LCSR_OTAT_AMODE_USER3
)
1215 *aspace
|= VME_USER3
;
1216 if ((ctl
& TSI148_LCSR_OTAT_AMODE_M
) == TSI148_LCSR_OTAT_AMODE_USER4
)
1217 *aspace
|= VME_USER4
;
1219 /* Setup 2eSST speeds */
1220 if ((ctl
& TSI148_LCSR_OTAT_2eSSTM_M
) == TSI148_LCSR_OTAT_2eSSTM_160
)
1221 *cycle
|= VME_2eSST160
;
1222 if ((ctl
& TSI148_LCSR_OTAT_2eSSTM_M
) == TSI148_LCSR_OTAT_2eSSTM_267
)
1223 *cycle
|= VME_2eSST267
;
1224 if ((ctl
& TSI148_LCSR_OTAT_2eSSTM_M
) == TSI148_LCSR_OTAT_2eSSTM_320
)
1225 *cycle
|= VME_2eSST320
;
1227 /* Setup cycle types */
1228 if ((ctl
& TSI148_LCSR_OTAT_TM_M
) == TSI148_LCSR_OTAT_TM_SCT
)
1230 if ((ctl
& TSI148_LCSR_OTAT_TM_M
) == TSI148_LCSR_OTAT_TM_BLT
)
1232 if ((ctl
& TSI148_LCSR_OTAT_TM_M
) == TSI148_LCSR_OTAT_TM_MBLT
)
1234 if ((ctl
& TSI148_LCSR_OTAT_TM_M
) == TSI148_LCSR_OTAT_TM_2eVME
)
1235 *cycle
|= VME_2eVME
;
1236 if ((ctl
& TSI148_LCSR_OTAT_TM_M
) == TSI148_LCSR_OTAT_TM_2eSST
)
1237 *cycle
|= VME_2eSST
;
1238 if ((ctl
& TSI148_LCSR_OTAT_TM_M
) == TSI148_LCSR_OTAT_TM_2eSSTB
)
1239 *cycle
|= VME_2eSSTB
;
1241 if (ctl
& TSI148_LCSR_OTAT_SUP
)
1242 *cycle
|= VME_SUPER
;
1246 if (ctl
& TSI148_LCSR_OTAT_PGM
)
1251 /* Setup data width */
1252 if ((ctl
& TSI148_LCSR_OTAT_DBW_M
) == TSI148_LCSR_OTAT_DBW_16
)
1254 if ((ctl
& TSI148_LCSR_OTAT_DBW_M
) == TSI148_LCSR_OTAT_DBW_32
)
1261 int tsi148_master_get( struct vme_master_resource
*image
, int *enabled
,
1262 unsigned long long *vme_base
, unsigned long long *size
,
1263 vme_address_t
*aspace
, vme_cycle_t
*cycle
, vme_width_t
*dwidth
)
1267 spin_lock(&(image
->lock
));
1269 retval
= __tsi148_master_get(image
, enabled
, vme_base
, size
, aspace
,
1272 spin_unlock(&(image
->lock
));
1277 ssize_t
tsi148_master_read(struct vme_master_resource
*image
, void *buf
,
1278 size_t count
, loff_t offset
)
1280 int retval
, enabled
;
1281 unsigned long long vme_base
, size
;
1282 vme_address_t aspace
;
1285 struct vme_bus_error
*vme_err
= NULL
;
1286 struct vme_bridge
*tsi148_bridge
;
1288 tsi148_bridge
= image
->parent
;
1290 spin_lock(&(image
->lock
));
1292 memcpy_fromio(buf
, image
->kern_base
+ offset
, (unsigned int)count
);
1298 __tsi148_master_get(image
, &enabled
, &vme_base
, &size
, &aspace
, &cycle
,
1301 vme_err
= tsi148_find_error(tsi148_bridge
, aspace
, vme_base
+ offset
,
1303 if(vme_err
!= NULL
) {
1304 dev_err(image
->parent
->parent
, "First VME read error detected "
1305 "an at address 0x%llx\n", vme_err
->address
);
1306 retval
= vme_err
->address
- (vme_base
+ offset
);
1307 /* Clear down save errors in this address range */
1308 tsi148_clear_errors(tsi148_bridge
, aspace
, vme_base
+ offset
,
1313 spin_unlock(&(image
->lock
));
1319 ssize_t
tsi148_master_write(struct vme_master_resource
*image
, void *buf
,
1320 size_t count
, loff_t offset
)
1322 int retval
= 0, enabled
;
1323 unsigned long long vme_base
, size
;
1324 vme_address_t aspace
;
1328 struct vme_bus_error
*vme_err
= NULL
;
1329 struct vme_bridge
*tsi148_bridge
;
1330 struct tsi148_driver
*bridge
;
1332 tsi148_bridge
= image
->parent
;
1334 bridge
= tsi148_bridge
->driver_priv
;
1336 spin_lock(&(image
->lock
));
1338 memcpy_toio(image
->kern_base
+ offset
, buf
, (unsigned int)count
);
1342 * Writes are posted. We need to do a read on the VME bus to flush out
1343 * all of the writes before we check for errors. We can't guarentee
1344 * that reading the data we have just written is safe. It is believed
1345 * that there isn't any read, write re-ordering, so we can read any
1346 * location in VME space, so lets read the Device ID from the tsi148's
1347 * own registers as mapped into CR/CSR space.
1349 * We check for saved errors in the written address range/space.
1356 * Get window info first, to maximise the time that the buffers may
1357 * fluch on their own
1359 __tsi148_master_get(image
, &enabled
, &vme_base
, &size
, &aspace
, &cycle
,
1362 ioread16(bridge
->flush_image
->kern_base
+ 0x7F000);
1364 vme_err
= tsi148_find_error(tsi148_bridge
, aspace
, vme_base
+ offset
,
1366 if(vme_err
!= NULL
) {
1367 dev_warn(tsi148_bridge
->parent
, "First VME write error detected"
1368 " an at address 0x%llx\n", vme_err
->address
);
1369 retval
= vme_err
->address
- (vme_base
+ offset
);
1370 /* Clear down save errors in this address range */
1371 tsi148_clear_errors(tsi148_bridge
, aspace
, vme_base
+ offset
,
1376 spin_unlock(&(image
->lock
));
1382 * Perform an RMW cycle on the VME bus.
1384 * Requires a previously configured master window, returns final value.
1386 unsigned int tsi148_master_rmw(struct vme_master_resource
*image
,
1387 unsigned int mask
, unsigned int compare
, unsigned int swap
,
1390 unsigned long long pci_addr
;
1391 unsigned int pci_addr_high
, pci_addr_low
;
1394 struct tsi148_driver
*bridge
;
1396 bridge
= image
->parent
->driver_priv
;
1398 /* Find the PCI address that maps to the desired VME address */
1401 /* Locking as we can only do one of these at a time */
1402 mutex_lock(&(bridge
->vme_rmw
));
1405 spin_lock(&(image
->lock
));
1407 pci_addr_high
= ioread32be(bridge
->base
+ TSI148_LCSR_OT
[i
] +
1408 TSI148_LCSR_OFFSET_OTSAU
);
1409 pci_addr_low
= ioread32be(bridge
->base
+ TSI148_LCSR_OT
[i
] +
1410 TSI148_LCSR_OFFSET_OTSAL
);
1412 reg_join(pci_addr_high
, pci_addr_low
, &pci_addr
);
1413 reg_split(pci_addr
+ offset
, &pci_addr_high
, &pci_addr_low
);
1415 /* Configure registers */
1416 iowrite32be(mask
, bridge
->base
+ TSI148_LCSR_RMWEN
);
1417 iowrite32be(compare
, bridge
->base
+ TSI148_LCSR_RMWC
);
1418 iowrite32be(swap
, bridge
->base
+ TSI148_LCSR_RMWS
);
1419 iowrite32be(pci_addr_high
, bridge
->base
+ TSI148_LCSR_RMWAU
);
1420 iowrite32be(pci_addr_low
, bridge
->base
+ TSI148_LCSR_RMWAL
);
1423 tmp
= ioread32be(bridge
->base
+ TSI148_LCSR_VMCTRL
);
1424 tmp
|= TSI148_LCSR_VMCTRL_RMWEN
;
1425 iowrite32be(tmp
, bridge
->base
+ TSI148_LCSR_VMCTRL
);
1427 /* Kick process off with a read to the required address. */
1428 result
= ioread32be(image
->kern_base
+ offset
);
1431 tmp
= ioread32be(bridge
->base
+ TSI148_LCSR_VMCTRL
);
1432 tmp
&= ~TSI148_LCSR_VMCTRL_RMWEN
;
1433 iowrite32be(tmp
, bridge
->base
+ TSI148_LCSR_VMCTRL
);
1435 spin_unlock(&(image
->lock
));
1437 mutex_unlock(&(bridge
->vme_rmw
));
1442 static int tsi148_dma_set_vme_src_attributes(struct device
*dev
, u32
*attr
,
1443 vme_address_t aspace
, vme_cycle_t cycle
, vme_width_t dwidth
)
1445 /* Setup 2eSST speeds */
1446 switch (cycle
& (VME_2eSST160
| VME_2eSST267
| VME_2eSST320
)) {
1448 *attr
|= TSI148_LCSR_DSAT_2eSSTM_160
;
1451 *attr
|= TSI148_LCSR_DSAT_2eSSTM_267
;
1454 *attr
|= TSI148_LCSR_DSAT_2eSSTM_320
;
1458 /* Setup cycle types */
1459 if (cycle
& VME_SCT
) {
1460 *attr
|= TSI148_LCSR_DSAT_TM_SCT
;
1462 if (cycle
& VME_BLT
) {
1463 *attr
|= TSI148_LCSR_DSAT_TM_BLT
;
1465 if (cycle
& VME_MBLT
) {
1466 *attr
|= TSI148_LCSR_DSAT_TM_MBLT
;
1468 if (cycle
& VME_2eVME
) {
1469 *attr
|= TSI148_LCSR_DSAT_TM_2eVME
;
1471 if (cycle
& VME_2eSST
) {
1472 *attr
|= TSI148_LCSR_DSAT_TM_2eSST
;
1474 if (cycle
& VME_2eSSTB
) {
1475 dev_err(dev
, "Currently not setting Broadcast Select "
1477 *attr
|= TSI148_LCSR_DSAT_TM_2eSSTB
;
1480 /* Setup data width */
1483 *attr
|= TSI148_LCSR_DSAT_DBW_16
;
1486 *attr
|= TSI148_LCSR_DSAT_DBW_32
;
1489 dev_err(dev
, "Invalid data width\n");
1493 /* Setup address space */
1496 *attr
|= TSI148_LCSR_DSAT_AMODE_A16
;
1499 *attr
|= TSI148_LCSR_DSAT_AMODE_A24
;
1502 *attr
|= TSI148_LCSR_DSAT_AMODE_A32
;
1505 *attr
|= TSI148_LCSR_DSAT_AMODE_A64
;
1508 *attr
|= TSI148_LCSR_DSAT_AMODE_CRCSR
;
1511 *attr
|= TSI148_LCSR_DSAT_AMODE_USER1
;
1514 *attr
|= TSI148_LCSR_DSAT_AMODE_USER2
;
1517 *attr
|= TSI148_LCSR_DSAT_AMODE_USER3
;
1520 *attr
|= TSI148_LCSR_DSAT_AMODE_USER4
;
1523 dev_err(dev
, "Invalid address space\n");
1528 if (cycle
& VME_SUPER
)
1529 *attr
|= TSI148_LCSR_DSAT_SUP
;
1530 if (cycle
& VME_PROG
)
1531 *attr
|= TSI148_LCSR_DSAT_PGM
;
1536 static int tsi148_dma_set_vme_dest_attributes(struct device
*dev
, u32
*attr
,
1537 vme_address_t aspace
, vme_cycle_t cycle
, vme_width_t dwidth
)
1539 /* Setup 2eSST speeds */
1540 switch (cycle
& (VME_2eSST160
| VME_2eSST267
| VME_2eSST320
)) {
1542 *attr
|= TSI148_LCSR_DDAT_2eSSTM_160
;
1545 *attr
|= TSI148_LCSR_DDAT_2eSSTM_267
;
1548 *attr
|= TSI148_LCSR_DDAT_2eSSTM_320
;
1552 /* Setup cycle types */
1553 if (cycle
& VME_SCT
) {
1554 *attr
|= TSI148_LCSR_DDAT_TM_SCT
;
1556 if (cycle
& VME_BLT
) {
1557 *attr
|= TSI148_LCSR_DDAT_TM_BLT
;
1559 if (cycle
& VME_MBLT
) {
1560 *attr
|= TSI148_LCSR_DDAT_TM_MBLT
;
1562 if (cycle
& VME_2eVME
) {
1563 *attr
|= TSI148_LCSR_DDAT_TM_2eVME
;
1565 if (cycle
& VME_2eSST
) {
1566 *attr
|= TSI148_LCSR_DDAT_TM_2eSST
;
1568 if (cycle
& VME_2eSSTB
) {
1569 dev_err(dev
, "Currently not setting Broadcast Select "
1571 *attr
|= TSI148_LCSR_DDAT_TM_2eSSTB
;
1574 /* Setup data width */
1577 *attr
|= TSI148_LCSR_DDAT_DBW_16
;
1580 *attr
|= TSI148_LCSR_DDAT_DBW_32
;
1583 dev_err(dev
, "Invalid data width\n");
1587 /* Setup address space */
1590 *attr
|= TSI148_LCSR_DDAT_AMODE_A16
;
1593 *attr
|= TSI148_LCSR_DDAT_AMODE_A24
;
1596 *attr
|= TSI148_LCSR_DDAT_AMODE_A32
;
1599 *attr
|= TSI148_LCSR_DDAT_AMODE_A64
;
1602 *attr
|= TSI148_LCSR_DDAT_AMODE_CRCSR
;
1605 *attr
|= TSI148_LCSR_DDAT_AMODE_USER1
;
1608 *attr
|= TSI148_LCSR_DDAT_AMODE_USER2
;
1611 *attr
|= TSI148_LCSR_DDAT_AMODE_USER3
;
1614 *attr
|= TSI148_LCSR_DDAT_AMODE_USER4
;
1617 dev_err(dev
, "Invalid address space\n");
1622 if (cycle
& VME_SUPER
)
1623 *attr
|= TSI148_LCSR_DDAT_SUP
;
1624 if (cycle
& VME_PROG
)
1625 *attr
|= TSI148_LCSR_DDAT_PGM
;
1631 * Add a link list descriptor to the list
1633 int tsi148_dma_list_add (struct vme_dma_list
*list
, struct vme_dma_attr
*src
,
1634 struct vme_dma_attr
*dest
, size_t count
)
1636 struct tsi148_dma_entry
*entry
, *prev
;
1637 u32 address_high
, address_low
;
1638 struct vme_dma_pattern
*pattern_attr
;
1639 struct vme_dma_pci
*pci_attr
;
1640 struct vme_dma_vme
*vme_attr
;
1641 dma_addr_t desc_ptr
;
1643 struct vme_bridge
*tsi148_bridge
;
1645 tsi148_bridge
= list
->parent
->parent
;
1647 /* Descriptor must be aligned on 64-bit boundaries */
1648 entry
= (struct tsi148_dma_entry
*)kmalloc(
1649 sizeof(struct tsi148_dma_entry
), GFP_KERNEL
);
1650 if (entry
== NULL
) {
1651 dev_err(tsi148_bridge
->parent
, "Failed to allocate memory for "
1652 "dma resource structure\n");
1657 /* Test descriptor alignment */
1658 if ((unsigned long)&(entry
->descriptor
) & 0x7) {
1659 dev_err(tsi148_bridge
->parent
, "Descriptor not aligned to 8 "
1660 "byte boundary as required: %p\n",
1661 &(entry
->descriptor
));
1666 /* Given we are going to fill out the structure, we probably don't
1667 * need to zero it, but better safe than sorry for now.
1669 memset(&(entry
->descriptor
), 0, sizeof(struct tsi148_dma_descriptor
));
1671 /* Fill out source part */
1672 switch (src
->type
) {
1673 case VME_DMA_PATTERN
:
1674 pattern_attr
= (struct vme_dma_pattern
*)src
->private;
1676 entry
->descriptor
.dsal
= pattern_attr
->pattern
;
1677 entry
->descriptor
.dsat
= TSI148_LCSR_DSAT_TYP_PAT
;
1678 /* Default behaviour is 32 bit pattern */
1679 if (pattern_attr
->type
& VME_DMA_PATTERN_BYTE
) {
1680 entry
->descriptor
.dsat
|= TSI148_LCSR_DSAT_PSZ
;
1682 /* It seems that the default behaviour is to increment */
1683 if ((pattern_attr
->type
& VME_DMA_PATTERN_INCREMENT
) == 0) {
1684 entry
->descriptor
.dsat
|= TSI148_LCSR_DSAT_NIN
;
1688 pci_attr
= (struct vme_dma_pci
*)src
->private;
1690 reg_split((unsigned long long)pci_attr
->address
, &address_high
,
1692 entry
->descriptor
.dsau
= address_high
;
1693 entry
->descriptor
.dsal
= address_low
;
1694 entry
->descriptor
.dsat
= TSI148_LCSR_DSAT_TYP_PCI
;
1697 vme_attr
= (struct vme_dma_vme
*)src
->private;
1699 reg_split((unsigned long long)vme_attr
->address
, &address_high
,
1701 entry
->descriptor
.dsau
= address_high
;
1702 entry
->descriptor
.dsal
= address_low
;
1703 entry
->descriptor
.dsat
= TSI148_LCSR_DSAT_TYP_VME
;
1705 retval
= tsi148_dma_set_vme_src_attributes(
1706 tsi148_bridge
->parent
, &(entry
->descriptor
.dsat
),
1707 vme_attr
->aspace
, vme_attr
->cycle
, vme_attr
->dwidth
);
1712 dev_err(tsi148_bridge
->parent
, "Invalid source type\n");
1718 /* Assume last link - this will be over-written by adding another */
1719 entry
->descriptor
.dnlau
= 0;
1720 entry
->descriptor
.dnlal
= TSI148_LCSR_DNLAL_LLA
;
1723 /* Fill out destination part */
1724 switch (dest
->type
) {
1726 pci_attr
= (struct vme_dma_pci
*)dest
->private;
1728 reg_split((unsigned long long)pci_attr
->address
, &address_high
,
1730 entry
->descriptor
.ddau
= address_high
;
1731 entry
->descriptor
.ddal
= address_low
;
1732 entry
->descriptor
.ddat
= TSI148_LCSR_DDAT_TYP_PCI
;
1735 vme_attr
= (struct vme_dma_vme
*)dest
->private;
1737 reg_split((unsigned long long)vme_attr
->address
, &address_high
,
1739 entry
->descriptor
.ddau
= address_high
;
1740 entry
->descriptor
.ddal
= address_low
;
1741 entry
->descriptor
.ddat
= TSI148_LCSR_DDAT_TYP_VME
;
1743 retval
= tsi148_dma_set_vme_dest_attributes(
1744 tsi148_bridge
->parent
, &(entry
->descriptor
.ddat
),
1745 vme_attr
->aspace
, vme_attr
->cycle
, vme_attr
->dwidth
);
1750 dev_err(tsi148_bridge
->parent
, "Invalid destination type\n");
1756 /* Fill out count */
1757 entry
->descriptor
.dcnt
= (u32
)count
;
1760 list_add_tail(&(entry
->list
), &(list
->entries
));
1762 /* Fill out previous descriptors "Next Address" */
1763 if(entry
->list
.prev
!= &(list
->entries
)){
1764 prev
= list_entry(entry
->list
.prev
, struct tsi148_dma_entry
,
1766 /* We need the bus address for the pointer */
1767 desc_ptr
= virt_to_bus(&(entry
->descriptor
));
1768 reg_split(desc_ptr
, &(prev
->descriptor
.dnlau
),
1769 &(prev
->descriptor
.dnlal
));
1783 * Check to see if the provided DMA channel is busy.
1785 static int tsi148_dma_busy(struct vme_bridge
*tsi148_bridge
, int channel
)
1788 struct tsi148_driver
*bridge
;
1790 bridge
= tsi148_bridge
->driver_priv
;
1792 tmp
= ioread32be(bridge
->base
+ TSI148_LCSR_DMA
[channel
] +
1793 TSI148_LCSR_OFFSET_DSTA
);
1795 if (tmp
& TSI148_LCSR_DSTA_BSY
)
1803 * Execute a previously generated link list
1805 * XXX Need to provide control register configuration.
1807 int tsi148_dma_list_exec(struct vme_dma_list
*list
)
1809 struct vme_dma_resource
*ctrlr
;
1810 int channel
, retval
= 0;
1811 struct tsi148_dma_entry
*entry
;
1812 dma_addr_t bus_addr
;
1813 u32 bus_addr_high
, bus_addr_low
;
1814 u32 val
, dctlreg
= 0;
1815 struct vme_bridge
*tsi148_bridge
;
1816 struct tsi148_driver
*bridge
;
1818 ctrlr
= list
->parent
;
1820 tsi148_bridge
= ctrlr
->parent
;
1822 bridge
= tsi148_bridge
->driver_priv
;
1824 mutex_lock(&(ctrlr
->mtx
));
1826 channel
= ctrlr
->number
;
1828 if (! list_empty(&(ctrlr
->running
))) {
1830 * XXX We have an active DMA transfer and currently haven't
1831 * sorted out the mechanism for "pending" DMA transfers.
1834 /* Need to add to pending here */
1835 mutex_unlock(&(ctrlr
->mtx
));
1838 list_add(&(list
->list
), &(ctrlr
->running
));
1841 /* Get first bus address and write into registers */
1842 entry
= list_first_entry(&(list
->entries
), struct tsi148_dma_entry
,
1845 bus_addr
= virt_to_bus(&(entry
->descriptor
));
1847 mutex_unlock(&(ctrlr
->mtx
));
1849 reg_split(bus_addr
, &bus_addr_high
, &bus_addr_low
);
1851 iowrite32be(bus_addr_high
, bridge
->base
+
1852 TSI148_LCSR_DMA
[channel
] + TSI148_LCSR_OFFSET_DNLAU
);
1853 iowrite32be(bus_addr_low
, bridge
->base
+
1854 TSI148_LCSR_DMA
[channel
] + TSI148_LCSR_OFFSET_DNLAL
);
1856 /* Start the operation */
1857 iowrite32be(dctlreg
| TSI148_LCSR_DCTL_DGO
, bridge
->base
+
1858 TSI148_LCSR_DMA
[channel
] + TSI148_LCSR_OFFSET_DCTL
);
1860 wait_event_interruptible(bridge
->dma_queue
[channel
],
1861 tsi148_dma_busy(ctrlr
->parent
, channel
));
1863 * Read status register, this register is valid until we kick off a
1866 val
= ioread32be(bridge
->base
+ TSI148_LCSR_DMA
[channel
] +
1867 TSI148_LCSR_OFFSET_DSTA
);
1869 if (val
& TSI148_LCSR_DSTA_VBE
) {
1870 dev_err(tsi148_bridge
->parent
, "DMA Error. DSTA=%08X\n", val
);
1874 /* Remove list from running list */
1875 mutex_lock(&(ctrlr
->mtx
));
1876 list_del(&(list
->list
));
1877 mutex_unlock(&(ctrlr
->mtx
));
1883 * Clean up a previously generated link list
1885 * We have a separate function, don't assume that the chain can't be reused.
1887 int tsi148_dma_list_empty(struct vme_dma_list
*list
)
1889 struct list_head
*pos
, *temp
;
1890 struct tsi148_dma_entry
*entry
;
1892 /* detach and free each entry */
1893 list_for_each_safe(pos
, temp
, &(list
->entries
)) {
1895 entry
= list_entry(pos
, struct tsi148_dma_entry
, list
);
1903 * All 4 location monitors reside at the same base - this is therefore a
1904 * system wide configuration.
1906 * This does not enable the LM monitor - that should be done when the first
1907 * callback is attached and disabled when the last callback is removed.
1909 int tsi148_lm_set(struct vme_lm_resource
*lm
, unsigned long long lm_base
,
1910 vme_address_t aspace
, vme_cycle_t cycle
)
1912 u32 lm_base_high
, lm_base_low
, lm_ctl
= 0;
1914 struct vme_bridge
*tsi148_bridge
;
1915 struct tsi148_driver
*bridge
;
1917 tsi148_bridge
= lm
->parent
;
1919 bridge
= tsi148_bridge
->driver_priv
;
1921 mutex_lock(&(lm
->mtx
));
1923 /* If we already have a callback attached, we can't move it! */
1924 for (i
= 0; i
< lm
->monitors
; i
++) {
1925 if (bridge
->lm_callback
[i
] != NULL
) {
1926 mutex_unlock(&(lm
->mtx
));
1927 dev_err(tsi148_bridge
->parent
, "Location monitor "
1928 "callback attached, can't reset\n");
1935 lm_ctl
|= TSI148_LCSR_LMAT_AS_A16
;
1938 lm_ctl
|= TSI148_LCSR_LMAT_AS_A24
;
1941 lm_ctl
|= TSI148_LCSR_LMAT_AS_A32
;
1944 lm_ctl
|= TSI148_LCSR_LMAT_AS_A64
;
1947 mutex_unlock(&(lm
->mtx
));
1948 dev_err(tsi148_bridge
->parent
, "Invalid address space\n");
1953 if (cycle
& VME_SUPER
)
1954 lm_ctl
|= TSI148_LCSR_LMAT_SUPR
;
1955 if (cycle
& VME_USER
)
1956 lm_ctl
|= TSI148_LCSR_LMAT_NPRIV
;
1957 if (cycle
& VME_PROG
)
1958 lm_ctl
|= TSI148_LCSR_LMAT_PGM
;
1959 if (cycle
& VME_DATA
)
1960 lm_ctl
|= TSI148_LCSR_LMAT_DATA
;
1962 reg_split(lm_base
, &lm_base_high
, &lm_base_low
);
1964 iowrite32be(lm_base_high
, bridge
->base
+ TSI148_LCSR_LMBAU
);
1965 iowrite32be(lm_base_low
, bridge
->base
+ TSI148_LCSR_LMBAL
);
1966 iowrite32be(lm_ctl
, bridge
->base
+ TSI148_LCSR_LMAT
);
1968 mutex_unlock(&(lm
->mtx
));
1973 /* Get configuration of the callback monitor and return whether it is enabled
1976 int tsi148_lm_get(struct vme_lm_resource
*lm
, unsigned long long *lm_base
,
1977 vme_address_t
*aspace
, vme_cycle_t
*cycle
)
1979 u32 lm_base_high
, lm_base_low
, lm_ctl
, enabled
= 0;
1980 struct tsi148_driver
*bridge
;
1982 bridge
= lm
->parent
->driver_priv
;
1984 mutex_lock(&(lm
->mtx
));
1986 lm_base_high
= ioread32be(bridge
->base
+ TSI148_LCSR_LMBAU
);
1987 lm_base_low
= ioread32be(bridge
->base
+ TSI148_LCSR_LMBAL
);
1988 lm_ctl
= ioread32be(bridge
->base
+ TSI148_LCSR_LMAT
);
1990 reg_join(lm_base_high
, lm_base_low
, lm_base
);
1992 if (lm_ctl
& TSI148_LCSR_LMAT_EN
)
1995 if ((lm_ctl
& TSI148_LCSR_LMAT_AS_M
) == TSI148_LCSR_LMAT_AS_A16
) {
1998 if ((lm_ctl
& TSI148_LCSR_LMAT_AS_M
) == TSI148_LCSR_LMAT_AS_A24
) {
2001 if ((lm_ctl
& TSI148_LCSR_LMAT_AS_M
) == TSI148_LCSR_LMAT_AS_A32
) {
2004 if ((lm_ctl
& TSI148_LCSR_LMAT_AS_M
) == TSI148_LCSR_LMAT_AS_A64
) {
2008 if (lm_ctl
& TSI148_LCSR_LMAT_SUPR
)
2009 *cycle
|= VME_SUPER
;
2010 if (lm_ctl
& TSI148_LCSR_LMAT_NPRIV
)
2012 if (lm_ctl
& TSI148_LCSR_LMAT_PGM
)
2014 if (lm_ctl
& TSI148_LCSR_LMAT_DATA
)
2017 mutex_unlock(&(lm
->mtx
));
2023 * Attach a callback to a specific location monitor.
2025 * Callback will be passed the monitor triggered.
2027 int tsi148_lm_attach(struct vme_lm_resource
*lm
, int monitor
,
2028 void (*callback
)(int))
2031 struct vme_bridge
*tsi148_bridge
;
2032 struct tsi148_driver
*bridge
;
2034 tsi148_bridge
= lm
->parent
;
2036 bridge
= tsi148_bridge
->driver_priv
;
2038 mutex_lock(&(lm
->mtx
));
2040 /* Ensure that the location monitor is configured - need PGM or DATA */
2041 lm_ctl
= ioread32be(bridge
->base
+ TSI148_LCSR_LMAT
);
2042 if ((lm_ctl
& (TSI148_LCSR_LMAT_PGM
| TSI148_LCSR_LMAT_DATA
)) == 0) {
2043 mutex_unlock(&(lm
->mtx
));
2044 dev_err(tsi148_bridge
->parent
, "Location monitor not properly "
2049 /* Check that a callback isn't already attached */
2050 if (bridge
->lm_callback
[monitor
] != NULL
) {
2051 mutex_unlock(&(lm
->mtx
));
2052 dev_err(tsi148_bridge
->parent
, "Existing callback attached\n");
2056 /* Attach callback */
2057 bridge
->lm_callback
[monitor
] = callback
;
2059 /* Enable Location Monitor interrupt */
2060 tmp
= ioread32be(bridge
->base
+ TSI148_LCSR_INTEN
);
2061 tmp
|= TSI148_LCSR_INTEN_LMEN
[monitor
];
2062 iowrite32be(tmp
, bridge
->base
+ TSI148_LCSR_INTEN
);
2064 tmp
= ioread32be(bridge
->base
+ TSI148_LCSR_INTEO
);
2065 tmp
|= TSI148_LCSR_INTEO_LMEO
[monitor
];
2066 iowrite32be(tmp
, bridge
->base
+ TSI148_LCSR_INTEO
);
2068 /* Ensure that global Location Monitor Enable set */
2069 if ((lm_ctl
& TSI148_LCSR_LMAT_EN
) == 0) {
2070 lm_ctl
|= TSI148_LCSR_LMAT_EN
;
2071 iowrite32be(lm_ctl
, bridge
->base
+ TSI148_LCSR_LMAT
);
2074 mutex_unlock(&(lm
->mtx
));
2080 * Detach a callback function forn a specific location monitor.
2082 int tsi148_lm_detach(struct vme_lm_resource
*lm
, int monitor
)
2085 struct tsi148_driver
*bridge
;
2087 bridge
= lm
->parent
->driver_priv
;
2089 mutex_lock(&(lm
->mtx
));
2091 /* Disable Location Monitor and ensure previous interrupts are clear */
2092 lm_en
= ioread32be(bridge
->base
+ TSI148_LCSR_INTEN
);
2093 lm_en
&= ~TSI148_LCSR_INTEN_LMEN
[monitor
];
2094 iowrite32be(lm_en
, bridge
->base
+ TSI148_LCSR_INTEN
);
2096 tmp
= ioread32be(bridge
->base
+ TSI148_LCSR_INTEO
);
2097 tmp
&= ~TSI148_LCSR_INTEO_LMEO
[monitor
];
2098 iowrite32be(tmp
, bridge
->base
+ TSI148_LCSR_INTEO
);
2100 iowrite32be(TSI148_LCSR_INTC_LMC
[monitor
],
2101 bridge
->base
+ TSI148_LCSR_INTC
);
2103 /* Detach callback */
2104 bridge
->lm_callback
[monitor
] = NULL
;
2106 /* If all location monitors disabled, disable global Location Monitor */
2107 if ((lm_en
& (TSI148_LCSR_INTS_LM0S
| TSI148_LCSR_INTS_LM1S
|
2108 TSI148_LCSR_INTS_LM2S
| TSI148_LCSR_INTS_LM3S
)) == 0) {
2109 tmp
= ioread32be(bridge
->base
+ TSI148_LCSR_LMAT
);
2110 tmp
&= ~TSI148_LCSR_LMAT_EN
;
2111 iowrite32be(tmp
, bridge
->base
+ TSI148_LCSR_LMAT
);
2114 mutex_unlock(&(lm
->mtx
));
2120 * Determine Geographical Addressing
2122 int tsi148_slot_get(struct vme_bridge
*tsi148_bridge
)
2125 struct tsi148_driver
*bridge
;
2127 bridge
= tsi148_bridge
->driver_priv
;
2130 slot
= ioread32be(bridge
->base
+ TSI148_LCSR_VSTAT
);
2131 slot
= slot
& TSI148_LCSR_VSTAT_GA_M
;
2138 static int __init
tsi148_init(void)
2140 return pci_register_driver(&tsi148_driver
);
2144 * Configure CR/CSR space
2146 * Access to the CR/CSR can be configured at power-up. The location of the
2147 * CR/CSR registers in the CR/CSR address space is determined by the boards
2148 * Auto-ID or Geographic address. This function ensures that the window is
2149 * enabled at an offset consistent with the boards geopgraphic address.
2151 * Each board has a 512kB window, with the highest 4kB being used for the
2152 * boards registers, this means there is a fix length 508kB window which must
2153 * be mapped onto PCI memory.
2155 static int tsi148_crcsr_init(struct vme_bridge
*tsi148_bridge
,
2156 struct pci_dev
*pdev
)
2158 u32 cbar
, crat
, vstat
;
2159 u32 crcsr_bus_high
, crcsr_bus_low
;
2161 struct tsi148_driver
*bridge
;
2163 bridge
= tsi148_bridge
->driver_priv
;
2165 /* Allocate mem for CR/CSR image */
2166 bridge
->crcsr_kernel
= pci_alloc_consistent(pdev
, VME_CRCSR_BUF_SIZE
,
2167 &(bridge
->crcsr_bus
));
2168 if (bridge
->crcsr_kernel
== NULL
) {
2169 dev_err(tsi148_bridge
->parent
, "Failed to allocate memory for "
2174 memset(bridge
->crcsr_kernel
, 0, VME_CRCSR_BUF_SIZE
);
2176 reg_split(bridge
->crcsr_bus
, &crcsr_bus_high
, &crcsr_bus_low
);
2178 iowrite32be(crcsr_bus_high
, bridge
->base
+ TSI148_LCSR_CROU
);
2179 iowrite32be(crcsr_bus_low
, bridge
->base
+ TSI148_LCSR_CROL
);
2181 /* Ensure that the CR/CSR is configured at the correct offset */
2182 cbar
= ioread32be(bridge
->base
+ TSI148_CBAR
);
2183 cbar
= (cbar
& TSI148_CRCSR_CBAR_M
)>>3;
2185 vstat
= tsi148_slot_get(tsi148_bridge
);
2187 if (cbar
!= vstat
) {
2189 dev_info(tsi148_bridge
->parent
, "Setting CR/CSR offset\n");
2190 iowrite32be(cbar
<<3, bridge
->base
+ TSI148_CBAR
);
2192 dev_info(tsi148_bridge
->parent
, "CR/CSR Offset: %d\n", cbar
);
2194 crat
= ioread32be(bridge
->base
+ TSI148_LCSR_CRAT
);
2195 if (crat
& TSI148_LCSR_CRAT_EN
) {
2196 dev_info(tsi148_bridge
->parent
, "Enabling CR/CSR space\n");
2197 iowrite32be(crat
| TSI148_LCSR_CRAT_EN
,
2198 bridge
->base
+ TSI148_LCSR_CRAT
);
2200 dev_info(tsi148_bridge
->parent
, "CR/CSR already enabled\n");
2202 /* If we want flushed, error-checked writes, set up a window
2203 * over the CR/CSR registers. We read from here to safely flush
2204 * through VME writes.
2207 retval
= tsi148_master_set(bridge
->flush_image
, 1,
2208 (vstat
* 0x80000), 0x80000, VME_CRCSR
, VME_SCT
,
2211 dev_err(tsi148_bridge
->parent
, "Configuring flush image"
2219 static void tsi148_crcsr_exit(struct vme_bridge
*tsi148_bridge
,
2220 struct pci_dev
*pdev
)
2223 struct tsi148_driver
*bridge
;
2225 bridge
= tsi148_bridge
->driver_priv
;
2227 /* Turn off CR/CSR space */
2228 crat
= ioread32be(bridge
->base
+ TSI148_LCSR_CRAT
);
2229 iowrite32be(crat
& ~TSI148_LCSR_CRAT_EN
,
2230 bridge
->base
+ TSI148_LCSR_CRAT
);
2233 iowrite32be(0, bridge
->base
+ TSI148_LCSR_CROU
);
2234 iowrite32be(0, bridge
->base
+ TSI148_LCSR_CROL
);
2236 pci_free_consistent(pdev
, VME_CRCSR_BUF_SIZE
, bridge
->crcsr_kernel
,
2240 static int tsi148_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2242 int retval
, i
, master_num
;
2244 struct list_head
*pos
= NULL
;
2245 struct vme_bridge
*tsi148_bridge
;
2246 struct tsi148_driver
*tsi148_device
;
2247 struct vme_master_resource
*master_image
;
2248 struct vme_slave_resource
*slave_image
;
2249 struct vme_dma_resource
*dma_ctrlr
;
2250 struct vme_lm_resource
*lm
;
2252 /* If we want to support more than one of each bridge, we need to
2253 * dynamically generate this so we get one per device
2255 tsi148_bridge
= (struct vme_bridge
*)kmalloc(sizeof(struct vme_bridge
),
2257 if (tsi148_bridge
== NULL
) {
2258 dev_err(&pdev
->dev
, "Failed to allocate memory for device "
2264 memset(tsi148_bridge
, 0, sizeof(struct vme_bridge
));
2266 tsi148_device
= kmalloc(sizeof(struct tsi148_driver
), GFP_KERNEL
);
2267 if (tsi148_device
== NULL
) {
2268 dev_err(&pdev
->dev
, "Failed to allocate memory for device "
2274 memset(tsi148_device
, 0, sizeof(struct tsi148_driver
));
2276 tsi148_bridge
->driver_priv
= tsi148_device
;
2278 /* Enable the device */
2279 retval
= pci_enable_device(pdev
);
2281 dev_err(&pdev
->dev
, "Unable to enable device\n");
2286 retval
= pci_request_regions(pdev
, driver_name
);
2288 dev_err(&pdev
->dev
, "Unable to reserve resources\n");
2292 /* map registers in BAR 0 */
2293 tsi148_device
->base
= ioremap_nocache(pci_resource_start(pdev
, 0),
2295 if (!tsi148_device
->base
) {
2296 dev_err(&pdev
->dev
, "Unable to remap CRG region\n");
2301 /* Check to see if the mapping worked out */
2302 data
= ioread32(tsi148_device
->base
+ TSI148_PCFS_ID
) & 0x0000FFFF;
2303 if (data
!= PCI_VENDOR_ID_TUNDRA
) {
2304 dev_err(&pdev
->dev
, "CRG region check failed\n");
2309 /* Initialize wait queues & mutual exclusion flags */
2310 init_waitqueue_head(&(tsi148_device
->dma_queue
[0]));
2311 init_waitqueue_head(&(tsi148_device
->dma_queue
[1]));
2312 init_waitqueue_head(&(tsi148_device
->iack_queue
));
2313 mutex_init(&(tsi148_device
->vme_int
));
2314 mutex_init(&(tsi148_device
->vme_rmw
));
2316 tsi148_bridge
->parent
= &(pdev
->dev
);
2317 strcpy(tsi148_bridge
->name
, driver_name
);
2320 retval
= tsi148_irq_init(tsi148_bridge
);
2322 dev_err(&pdev
->dev
, "Chip Initialization failed.\n");
2326 /* If we are going to flush writes, we need to read from the VME bus.
2327 * We need to do this safely, thus we read the devices own CR/CSR
2328 * register. To do this we must set up a window in CR/CSR space and
2329 * hence have one less master window resource available.
2331 master_num
= TSI148_MAX_MASTER
;
2335 tsi148_device
->flush_image
= (struct vme_master_resource
*)
2336 kmalloc(sizeof(struct vme_master_resource
), GFP_KERNEL
);
2337 if (tsi148_device
->flush_image
== NULL
) {
2338 dev_err(&pdev
->dev
, "Failed to allocate memory for "
2339 "flush resource structure\n");
2343 tsi148_device
->flush_image
->parent
= tsi148_bridge
;
2344 spin_lock_init(&(tsi148_device
->flush_image
->lock
));
2345 tsi148_device
->flush_image
->locked
= 1;
2346 tsi148_device
->flush_image
->number
= master_num
;
2347 tsi148_device
->flush_image
->address_attr
= VME_A16
| VME_A24
|
2349 tsi148_device
->flush_image
->cycle_attr
= VME_SCT
| VME_BLT
|
2350 VME_MBLT
| VME_2eVME
| VME_2eSST
| VME_2eSSTB
|
2351 VME_2eSST160
| VME_2eSST267
| VME_2eSST320
| VME_SUPER
|
2352 VME_USER
| VME_PROG
| VME_DATA
;
2353 tsi148_device
->flush_image
->width_attr
= VME_D16
| VME_D32
;
2354 memset(&(tsi148_device
->flush_image
->bus_resource
), 0,
2355 sizeof(struct resource
));
2356 tsi148_device
->flush_image
->kern_base
= NULL
;
2359 /* Add master windows to list */
2360 INIT_LIST_HEAD(&(tsi148_bridge
->master_resources
));
2361 for (i
= 0; i
< master_num
; i
++) {
2362 master_image
= (struct vme_master_resource
*)kmalloc(
2363 sizeof(struct vme_master_resource
), GFP_KERNEL
);
2364 if (master_image
== NULL
) {
2365 dev_err(&pdev
->dev
, "Failed to allocate memory for "
2366 "master resource structure\n");
2370 master_image
->parent
= tsi148_bridge
;
2371 spin_lock_init(&(master_image
->lock
));
2372 master_image
->locked
= 0;
2373 master_image
->number
= i
;
2374 master_image
->address_attr
= VME_A16
| VME_A24
| VME_A32
|
2376 master_image
->cycle_attr
= VME_SCT
| VME_BLT
| VME_MBLT
|
2377 VME_2eVME
| VME_2eSST
| VME_2eSSTB
| VME_2eSST160
|
2378 VME_2eSST267
| VME_2eSST320
| VME_SUPER
| VME_USER
|
2379 VME_PROG
| VME_DATA
;
2380 master_image
->width_attr
= VME_D16
| VME_D32
;
2381 memset(&(master_image
->bus_resource
), 0,
2382 sizeof(struct resource
));
2383 master_image
->kern_base
= NULL
;
2384 list_add_tail(&(master_image
->list
),
2385 &(tsi148_bridge
->master_resources
));
2388 /* Add slave windows to list */
2389 INIT_LIST_HEAD(&(tsi148_bridge
->slave_resources
));
2390 for (i
= 0; i
< TSI148_MAX_SLAVE
; i
++) {
2391 slave_image
= (struct vme_slave_resource
*)kmalloc(
2392 sizeof(struct vme_slave_resource
), GFP_KERNEL
);
2393 if (slave_image
== NULL
) {
2394 dev_err(&pdev
->dev
, "Failed to allocate memory for "
2395 "slave resource structure\n");
2399 slave_image
->parent
= tsi148_bridge
;
2400 mutex_init(&(slave_image
->mtx
));
2401 slave_image
->locked
= 0;
2402 slave_image
->number
= i
;
2403 slave_image
->address_attr
= VME_A16
| VME_A24
| VME_A32
|
2404 VME_A64
| VME_CRCSR
| VME_USER1
| VME_USER2
|
2405 VME_USER3
| VME_USER4
;
2406 slave_image
->cycle_attr
= VME_SCT
| VME_BLT
| VME_MBLT
|
2407 VME_2eVME
| VME_2eSST
| VME_2eSSTB
| VME_2eSST160
|
2408 VME_2eSST267
| VME_2eSST320
| VME_SUPER
| VME_USER
|
2409 VME_PROG
| VME_DATA
;
2410 list_add_tail(&(slave_image
->list
),
2411 &(tsi148_bridge
->slave_resources
));
2414 /* Add dma engines to list */
2415 INIT_LIST_HEAD(&(tsi148_bridge
->dma_resources
));
2416 for (i
= 0; i
< TSI148_MAX_DMA
; i
++) {
2417 dma_ctrlr
= (struct vme_dma_resource
*)kmalloc(
2418 sizeof(struct vme_dma_resource
), GFP_KERNEL
);
2419 if (dma_ctrlr
== NULL
) {
2420 dev_err(&pdev
->dev
, "Failed to allocate memory for "
2421 "dma resource structure\n");
2425 dma_ctrlr
->parent
= tsi148_bridge
;
2426 mutex_init(&(dma_ctrlr
->mtx
));
2427 dma_ctrlr
->locked
= 0;
2428 dma_ctrlr
->number
= i
;
2429 dma_ctrlr
->route_attr
= VME_DMA_VME_TO_MEM
|
2430 VME_DMA_MEM_TO_VME
| VME_DMA_VME_TO_VME
|
2431 VME_DMA_MEM_TO_MEM
| VME_DMA_PATTERN_TO_VME
|
2432 VME_DMA_PATTERN_TO_MEM
;
2433 INIT_LIST_HEAD(&(dma_ctrlr
->pending
));
2434 INIT_LIST_HEAD(&(dma_ctrlr
->running
));
2435 list_add_tail(&(dma_ctrlr
->list
),
2436 &(tsi148_bridge
->dma_resources
));
2439 /* Add location monitor to list */
2440 INIT_LIST_HEAD(&(tsi148_bridge
->lm_resources
));
2441 lm
= kmalloc(sizeof(struct vme_lm_resource
), GFP_KERNEL
);
2443 dev_err(&pdev
->dev
, "Failed to allocate memory for "
2444 "location monitor resource structure\n");
2448 lm
->parent
= tsi148_bridge
;
2449 mutex_init(&(lm
->mtx
));
2453 list_add_tail(&(lm
->list
), &(tsi148_bridge
->lm_resources
));
2455 tsi148_bridge
->slave_get
= tsi148_slave_get
;
2456 tsi148_bridge
->slave_set
= tsi148_slave_set
;
2457 tsi148_bridge
->master_get
= tsi148_master_get
;
2458 tsi148_bridge
->master_set
= tsi148_master_set
;
2459 tsi148_bridge
->master_read
= tsi148_master_read
;
2460 tsi148_bridge
->master_write
= tsi148_master_write
;
2461 tsi148_bridge
->master_rmw
= tsi148_master_rmw
;
2462 tsi148_bridge
->dma_list_add
= tsi148_dma_list_add
;
2463 tsi148_bridge
->dma_list_exec
= tsi148_dma_list_exec
;
2464 tsi148_bridge
->dma_list_empty
= tsi148_dma_list_empty
;
2465 tsi148_bridge
->irq_set
= tsi148_irq_set
;
2466 tsi148_bridge
->irq_generate
= tsi148_irq_generate
;
2467 tsi148_bridge
->lm_set
= tsi148_lm_set
;
2468 tsi148_bridge
->lm_get
= tsi148_lm_get
;
2469 tsi148_bridge
->lm_attach
= tsi148_lm_attach
;
2470 tsi148_bridge
->lm_detach
= tsi148_lm_detach
;
2471 tsi148_bridge
->slot_get
= tsi148_slot_get
;
2473 data
= ioread32be(tsi148_device
->base
+ TSI148_LCSR_VSTAT
);
2474 dev_info(&pdev
->dev
, "Board is%s the VME system controller\n",
2475 (data
& TSI148_LCSR_VSTAT_SCONS
)? "" : " not");
2477 dev_info(&pdev
->dev
, "VME geographical address is %d\n",
2478 data
& TSI148_LCSR_VSTAT_GA_M
);
2480 dev_info(&pdev
->dev
, "VME geographical address is set to %d\n",
2483 dev_info(&pdev
->dev
, "VME Write and flush and error check is %s\n",
2484 err_chk
? "enabled" : "disabled");
2486 if (tsi148_crcsr_init(tsi148_bridge
, pdev
))
2487 dev_err(&pdev
->dev
, "CR/CSR configuration failed.\n");
2490 retval
= vme_register_bridge(tsi148_bridge
);
2492 dev_err(&pdev
->dev
, "Chip Registration failed.\n");
2496 pci_set_drvdata(pdev
, tsi148_bridge
);
2498 /* Clear VME bus "board fail", and "power-up reset" lines */
2499 data
= ioread32be(tsi148_device
->base
+ TSI148_LCSR_VSTAT
);
2500 data
&= ~TSI148_LCSR_VSTAT_BRDFL
;
2501 data
|= TSI148_LCSR_VSTAT_CPURST
;
2502 iowrite32be(data
, tsi148_device
->base
+ TSI148_LCSR_VSTAT
);
2506 vme_unregister_bridge(tsi148_bridge
);
2508 tsi148_crcsr_exit(tsi148_bridge
, pdev
);
2511 /* resources are stored in link list */
2512 list_for_each(pos
, &(tsi148_bridge
->lm_resources
)) {
2513 lm
= list_entry(pos
, struct vme_lm_resource
, list
);
2518 /* resources are stored in link list */
2519 list_for_each(pos
, &(tsi148_bridge
->dma_resources
)) {
2520 dma_ctrlr
= list_entry(pos
, struct vme_dma_resource
, list
);
2525 /* resources are stored in link list */
2526 list_for_each(pos
, &(tsi148_bridge
->slave_resources
)) {
2527 slave_image
= list_entry(pos
, struct vme_slave_resource
, list
);
2532 /* resources are stored in link list */
2533 list_for_each(pos
, &(tsi148_bridge
->master_resources
)) {
2534 master_image
= list_entry(pos
, struct vme_master_resource
, list
);
2536 kfree(master_image
);
2539 tsi148_irq_exit(tsi148_device
, pdev
);
2542 iounmap(tsi148_device
->base
);
2544 pci_release_regions(pdev
);
2546 pci_disable_device(pdev
);
2548 kfree(tsi148_device
);
2550 kfree(tsi148_bridge
);
2556 static void tsi148_remove(struct pci_dev
*pdev
)
2558 struct list_head
*pos
= NULL
;
2559 struct vme_master_resource
*master_image
;
2560 struct vme_slave_resource
*slave_image
;
2561 struct vme_dma_resource
*dma_ctrlr
;
2563 struct tsi148_driver
*bridge
;
2564 struct vme_bridge
*tsi148_bridge
= pci_get_drvdata(pdev
);
2566 bridge
= tsi148_bridge
->driver_priv
;
2569 dev_dbg(&pdev
->dev
, "Driver is being unloaded.\n");
2572 * Shutdown all inbound and outbound windows.
2574 for (i
= 0; i
< 8; i
++) {
2575 iowrite32be(0, bridge
->base
+ TSI148_LCSR_IT
[i
] +
2576 TSI148_LCSR_OFFSET_ITAT
);
2577 iowrite32be(0, bridge
->base
+ TSI148_LCSR_OT
[i
] +
2578 TSI148_LCSR_OFFSET_OTAT
);
2582 * Shutdown Location monitor.
2584 iowrite32be(0, bridge
->base
+ TSI148_LCSR_LMAT
);
2589 iowrite32be(0, bridge
->base
+ TSI148_LCSR_CSRAT
);
2592 * Clear error status.
2594 iowrite32be(0xFFFFFFFF, bridge
->base
+ TSI148_LCSR_EDPAT
);
2595 iowrite32be(0xFFFFFFFF, bridge
->base
+ TSI148_LCSR_VEAT
);
2596 iowrite32be(0x07000700, bridge
->base
+ TSI148_LCSR_PSTAT
);
2599 * Remove VIRQ interrupt (if any)
2601 if (ioread32be(bridge
->base
+ TSI148_LCSR_VICR
) & 0x800)
2602 iowrite32be(0x8000, bridge
->base
+ TSI148_LCSR_VICR
);
2605 * Map all Interrupts to PCI INTA
2607 iowrite32be(0x0, bridge
->base
+ TSI148_LCSR_INTM1
);
2608 iowrite32be(0x0, bridge
->base
+ TSI148_LCSR_INTM2
);
2610 tsi148_irq_exit(bridge
, pdev
);
2612 vme_unregister_bridge(tsi148_bridge
);
2614 tsi148_crcsr_exit(tsi148_bridge
, pdev
);
2616 /* resources are stored in link list */
2617 list_for_each(pos
, &(tsi148_bridge
->dma_resources
)) {
2618 dma_ctrlr
= list_entry(pos
, struct vme_dma_resource
, list
);
2623 /* resources are stored in link list */
2624 list_for_each(pos
, &(tsi148_bridge
->slave_resources
)) {
2625 slave_image
= list_entry(pos
, struct vme_slave_resource
, list
);
2630 /* resources are stored in link list */
2631 list_for_each(pos
, &(tsi148_bridge
->master_resources
)) {
2632 master_image
= list_entry(pos
, struct vme_master_resource
,
2635 kfree(master_image
);
2638 tsi148_irq_exit(bridge
, pdev
);
2640 iounmap(bridge
->base
);
2642 pci_release_regions(pdev
);
2644 pci_disable_device(pdev
);
2646 kfree(tsi148_bridge
->driver_priv
);
2648 kfree(tsi148_bridge
);
2651 static void __exit
tsi148_exit(void)
2653 pci_unregister_driver(&tsi148_driver
);
2656 MODULE_PARM_DESC(err_chk
, "Check for VME errors on reads and writes");
2657 module_param(err_chk
, bool, 0);
2659 MODULE_PARM_DESC(geoid
, "Override geographical addressing");
2660 module_param(geoid
, int, 0);
2662 MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2663 MODULE_LICENSE("GPL");
2665 module_init(tsi148_init
);
2666 module_exit(tsi148_exit
);