2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 * Purpose: Implement functions to access baseband
29 * BBuGetFrameTime - Calculate data frame transmitting time
30 * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal parameter for baseband Tx
31 * BBbReadEmbedded - Embedded read baseband register via MAC
32 * BBbWriteEmbedded - Embedded write baseband register via MAC
33 * BBbIsRegBitsOn - Test if baseband register bits on
34 * BBbIsRegBitsOff - Test if baseband register bits off
35 * BBbVT3253Init - VIA VT3253 baseband chip init code
36 * BBvReadAllRegs - Read All Baseband Registers
37 * BBvLoopbackOn - Turn on BaseBand Loopback mode
38 * BBvLoopbackOff - Turn off BaseBand Loopback mode
41 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
42 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
43 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and BBvCalculateParameter().
44 * cancel the setting of MAC_REG_SOFTPWRCTL on BBbVT3253Init().
46 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
47 * Modified BBvLoopbackOn & BBvLoopbackOff().
59 /*--------------------- Static Definitions -------------------------*/
60 //static int msglevel =MSG_LEVEL_DEBUG;
61 static int msglevel
= MSG_LEVEL_INFO
;
63 /*--------------------- Static Classes ----------------------------*/
65 /*--------------------- Static Variables --------------------------*/
67 /*--------------------- Static Functions --------------------------*/
69 /*--------------------- Export Variables --------------------------*/
71 /*--------------------- Static Definitions -------------------------*/
73 /*--------------------- Static Classes ----------------------------*/
75 /*--------------------- Static Variables --------------------------*/
77 #define CB_VT3253_INIT_FOR_RFMD 446
78 unsigned char byVT3253InitTab_RFMD
[CB_VT3253_INIT_FOR_RFMD
][2] = {
527 #define CB_VT3253B0_INIT_FOR_RFMD 256
528 unsigned char byVT3253B0_RFMD
[CB_VT3253B0_INIT_FOR_RFMD
][2] = {
787 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
789 unsigned char byVT3253B0_AGC4_RFMD2959
[CB_VT3253B0_AGC_FOR_RFMD2959
][2] = {
987 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
989 unsigned char byVT3253B0_AIROHA2230
[CB_VT3253B0_INIT_FOR_AIROHA2230
][2] = {
1098 {0x6c, 0x00}, //RobertYu:20050125, request by JJSue
1248 #define CB_VT3253B0_INIT_FOR_UW2451 256
1250 unsigned char byVT3253B0_UW2451
[CB_VT3253B0_INIT_FOR_UW2451
][2] = {
1359 {0x6c, 0x00}, //RobertYu:20050125, request by JJSue
1509 #define CB_VT3253B0_AGC 193
1511 unsigned char byVT3253B0_AGC
[CB_VT3253B0_AGC
][2] = {
1707 const unsigned short awcFrameTime
[MAX_RATE
] =
1708 {10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216};
1710 /*--------------------- Static Functions --------------------------*/
1714 s_ulGetRatio(PSDevice pDevice
);
1728 if (pDevice
->dwRxAntennaSel
== 0) {
1729 pDevice
->dwRxAntennaSel
= 1;
1730 if (pDevice
->bTxRxAntInv
== true)
1731 BBvSetRxAntennaMode(pDevice
->PortOffset
, ANT_A
);
1733 BBvSetRxAntennaMode(pDevice
->PortOffset
, ANT_B
);
1735 pDevice
->dwRxAntennaSel
= 0;
1736 if (pDevice
->bTxRxAntInv
== true)
1737 BBvSetRxAntennaMode(pDevice
->PortOffset
, ANT_B
);
1739 BBvSetRxAntennaMode(pDevice
->PortOffset
, ANT_A
);
1741 if (pDevice
->dwTxAntennaSel
== 0) {
1742 pDevice
->dwTxAntennaSel
= 1;
1743 BBvSetTxAntennaMode(pDevice
->PortOffset
, ANT_B
);
1745 pDevice
->dwTxAntennaSel
= 0;
1746 BBvSetTxAntennaMode(pDevice
->PortOffset
, ANT_A
);
1750 /*--------------------- Export Variables --------------------------*/
1752 * Description: Calculate data frame transmitting time
1756 * byPreambleType - Preamble Type
1757 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1758 * cbFrameLength - Baseband Type
1762 * Return Value: FrameTime
1767 unsigned char byPreambleType
,
1768 unsigned char byPktType
,
1769 unsigned int cbFrameLength
,
1770 unsigned short wRate
1773 unsigned int uFrameTime
;
1774 unsigned int uPreamble
;
1776 unsigned int uRateIdx
= (unsigned int) wRate
;
1777 unsigned int uRate
= 0;
1779 if (uRateIdx
> RATE_54M
) {
1784 uRate
= (unsigned int)awcFrameTime
[uRateIdx
];
1786 if (uRateIdx
<= 3) { //CCK mode
1788 if (byPreambleType
== 1) {//Short
1793 uFrameTime
= (cbFrameLength
* 80) / uRate
; //?????
1794 uTmp
= (uFrameTime
* uRate
) / 80;
1795 if (cbFrameLength
!= uTmp
) {
1799 return uPreamble
+ uFrameTime
;
1801 uFrameTime
= (cbFrameLength
* 8 + 22) / uRate
; //????????
1802 uTmp
= ((uFrameTime
* uRate
) - 22) / 8;
1803 if (cbFrameLength
!= uTmp
) {
1806 uFrameTime
= uFrameTime
* 4; //???????
1807 if (byPktType
!= PK_TYPE_11A
) {
1808 uFrameTime
+= 6; //??????
1810 return 20 + uFrameTime
; //??????
1815 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1819 * pDevice - Device Structure
1820 * cbFrameLength - Tx Frame Length
1823 * pwPhyLen - pointer to Phy Length field
1824 * pbyPhySrv - pointer to Phy Service field
1825 * pbyPhySgn - pointer to Phy Signal field
1827 * Return Value: none
1831 BBvCalculateParameter(
1833 unsigned int cbFrameLength
,
1834 unsigned short wRate
,
1835 unsigned char byPacketType
,
1836 unsigned short *pwPhyLen
,
1837 unsigned char *pbyPhySrv
,
1838 unsigned char *pbyPhySgn
1841 unsigned int cbBitCount
;
1842 unsigned int cbUsCount
= 0;
1845 unsigned char byPreambleType
= pDevice
->byPreambleType
;
1846 bool bCCK
= pDevice
->bCCK
;
1848 cbBitCount
= cbFrameLength
* 8;
1853 cbUsCount
= cbBitCount
;
1858 cbUsCount
= cbBitCount
/ 2;
1859 if (byPreambleType
== 1)
1861 else // long preamble
1868 cbUsCount
= (cbBitCount
* 10) / 55;
1869 cbTmp
= (cbUsCount
* 55) / 10;
1870 if (cbTmp
!= cbBitCount
)
1872 if (byPreambleType
== 1)
1874 else // long preamble
1882 cbUsCount
= cbBitCount
/ 11;
1883 cbTmp
= cbUsCount
* 11;
1884 if (cbTmp
!= cbBitCount
) {
1886 if ((cbBitCount
- cbTmp
) <= 3)
1889 if (byPreambleType
== 1)
1891 else // long preamble
1896 if (byPacketType
== PK_TYPE_11A
) {//11a, 5GHZ
1897 *pbyPhySgn
= 0x9B; //1001 1011
1898 } else {//11g, 2.4GHZ
1899 *pbyPhySgn
= 0x8B; //1000 1011
1904 if (byPacketType
== PK_TYPE_11A
) {//11a, 5GHZ
1905 *pbyPhySgn
= 0x9F; //1001 1111
1906 } else {//11g, 2.4GHZ
1907 *pbyPhySgn
= 0x8F; //1000 1111
1912 if (byPacketType
== PK_TYPE_11A
) {//11a, 5GHZ
1913 *pbyPhySgn
= 0x9A; //1001 1010
1914 } else {//11g, 2.4GHZ
1915 *pbyPhySgn
= 0x8A; //1000 1010
1920 if (byPacketType
== PK_TYPE_11A
) {//11a, 5GHZ
1921 *pbyPhySgn
= 0x9E; //1001 1110
1922 } else {//11g, 2.4GHZ
1923 *pbyPhySgn
= 0x8E; //1000 1110
1928 if (byPacketType
== PK_TYPE_11A
) {//11a, 5GHZ
1929 *pbyPhySgn
= 0x99; //1001 1001
1930 } else {//11g, 2.4GHZ
1931 *pbyPhySgn
= 0x89; //1000 1001
1936 if (byPacketType
== PK_TYPE_11A
) {//11a, 5GHZ
1937 *pbyPhySgn
= 0x9D; //1001 1101
1938 } else {//11g, 2.4GHZ
1939 *pbyPhySgn
= 0x8D; //1000 1101
1944 if (byPacketType
== PK_TYPE_11A
) {//11a, 5GHZ
1945 *pbyPhySgn
= 0x98; //1001 1000
1946 } else {//11g, 2.4GHZ
1947 *pbyPhySgn
= 0x88; //1000 1000
1952 if (byPacketType
== PK_TYPE_11A
) {//11a, 5GHZ
1953 *pbyPhySgn
= 0x9C; //1001 1100
1954 } else {//11g, 2.4GHZ
1955 *pbyPhySgn
= 0x8C; //1000 1100
1960 if (byPacketType
== PK_TYPE_11A
) {//11a, 5GHZ
1961 *pbyPhySgn
= 0x9C; //1001 1100
1962 } else {//11g, 2.4GHZ
1963 *pbyPhySgn
= 0x8C; //1000 1100
1968 if (byPacketType
== PK_TYPE_11B
) {
1971 *pbyPhySrv
= *pbyPhySrv
| 0x80;
1972 *pwPhyLen
= (unsigned short)cbUsCount
;
1975 *pwPhyLen
= (unsigned short)cbFrameLength
;
1980 * Description: Read a byte from BASEBAND, by embedded programming
1984 * dwIoBase - I/O base address
1985 * byBBAddr - address of register in Baseband
1987 * pbyData - data read
1989 * Return Value: true if succeeded; false if failed.
1992 bool BBbReadEmbedded(unsigned long dwIoBase
, unsigned char byBBAddr
, unsigned char *pbyData
)
1995 unsigned char byValue
;
1998 VNSvOutPortB(dwIoBase
+ MAC_REG_BBREGADR
, byBBAddr
);
2001 MACvRegBitsOn(dwIoBase
, MAC_REG_BBREGCTL
, BBREGCTL_REGR
);
2002 // W_MAX_TIMEOUT is the timeout period
2003 for (ww
= 0; ww
< W_MAX_TIMEOUT
; ww
++) {
2004 VNSvInPortB(dwIoBase
+ MAC_REG_BBREGCTL
, &byValue
);
2005 if (byValue
& BBREGCTL_DONE
)
2010 VNSvInPortB(dwIoBase
+ MAC_REG_BBREGDATA
, pbyData
);
2012 if (ww
== W_MAX_TIMEOUT
) {
2014 DBG_PRT(MSG_LEVEL_DEBUG
, KERN_INFO
" DBG_PORT80(0x30)\n");
2021 * Description: Write a Byte to BASEBAND, by embedded programming
2025 * dwIoBase - I/O base address
2026 * byBBAddr - address of register in Baseband
2027 * byData - data to write
2031 * Return Value: true if succeeded; false if failed.
2034 bool BBbWriteEmbedded(unsigned long dwIoBase
, unsigned char byBBAddr
, unsigned char byData
)
2037 unsigned char byValue
;
2040 VNSvOutPortB(dwIoBase
+ MAC_REG_BBREGADR
, byBBAddr
);
2042 VNSvOutPortB(dwIoBase
+ MAC_REG_BBREGDATA
, byData
);
2044 // turn on BBREGCTL_REGW
2045 MACvRegBitsOn(dwIoBase
, MAC_REG_BBREGCTL
, BBREGCTL_REGW
);
2046 // W_MAX_TIMEOUT is the timeout period
2047 for (ww
= 0; ww
< W_MAX_TIMEOUT
; ww
++) {
2048 VNSvInPortB(dwIoBase
+ MAC_REG_BBREGCTL
, &byValue
);
2049 if (byValue
& BBREGCTL_DONE
)
2053 if (ww
== W_MAX_TIMEOUT
) {
2055 DBG_PRT(MSG_LEVEL_DEBUG
, KERN_INFO
" DBG_PORT80(0x31)\n");
2062 * Description: Test if all bits are set for the Baseband register
2066 * dwIoBase - I/O base address
2067 * byBBAddr - address of register in Baseband
2068 * byTestBits - TestBits
2072 * Return Value: true if all TestBits are set; false otherwise.
2075 bool BBbIsRegBitsOn(unsigned long dwIoBase
, unsigned char byBBAddr
, unsigned char byTestBits
)
2077 unsigned char byOrgData
;
2079 BBbReadEmbedded(dwIoBase
, byBBAddr
, &byOrgData
);
2080 return (byOrgData
& byTestBits
) == byTestBits
;
2084 * Description: Test if all bits are clear for the Baseband register
2088 * dwIoBase - I/O base address
2089 * byBBAddr - address of register in Baseband
2090 * byTestBits - TestBits
2094 * Return Value: true if all TestBits are clear; false otherwise.
2097 bool BBbIsRegBitsOff(unsigned long dwIoBase
, unsigned char byBBAddr
, unsigned char byTestBits
)
2099 unsigned char byOrgData
;
2101 BBbReadEmbedded(dwIoBase
, byBBAddr
, &byOrgData
);
2102 return (byOrgData
& byTestBits
) == 0;
2106 * Description: VIA VT3253 Baseband chip init function
2110 * dwIoBase - I/O base address
2111 * byRevId - Revision ID
2112 * byRFType - RF type
2116 * Return Value: true if succeeded; false if failed.
2120 bool BBbVT3253Init(PSDevice pDevice
)
2122 bool bResult
= true;
2124 unsigned long dwIoBase
= pDevice
->PortOffset
;
2125 unsigned char byRFType
= pDevice
->byRFType
;
2126 unsigned char byLocalID
= pDevice
->byLocalID
;
2128 if (byRFType
== RF_RFMD2959
) {
2129 if (byLocalID
<= REV_ID_VT3253_A1
) {
2130 for (ii
= 0; ii
< CB_VT3253_INIT_FOR_RFMD
; ii
++) {
2131 bResult
&= BBbWriteEmbedded(dwIoBase
, byVT3253InitTab_RFMD
[ii
][0], byVT3253InitTab_RFMD
[ii
][1]);
2134 for (ii
= 0; ii
< CB_VT3253B0_INIT_FOR_RFMD
; ii
++) {
2135 bResult
&= BBbWriteEmbedded(dwIoBase
, byVT3253B0_RFMD
[ii
][0], byVT3253B0_RFMD
[ii
][1]);
2137 for (ii
= 0; ii
< CB_VT3253B0_AGC_FOR_RFMD2959
; ii
++) {
2138 bResult
&= BBbWriteEmbedded(dwIoBase
, byVT3253B0_AGC4_RFMD2959
[ii
][0], byVT3253B0_AGC4_RFMD2959
[ii
][1]);
2140 VNSvOutPortD(dwIoBase
+ MAC_REG_ITRTMSET
, 0x23);
2141 MACvRegBitsOn(dwIoBase
, MAC_REG_PAPEDELAY
, BIT0
);
2143 pDevice
->abyBBVGA
[0] = 0x18;
2144 pDevice
->abyBBVGA
[1] = 0x0A;
2145 pDevice
->abyBBVGA
[2] = 0x0;
2146 pDevice
->abyBBVGA
[3] = 0x0;
2147 pDevice
->ldBmThreshold
[0] = -70;
2148 pDevice
->ldBmThreshold
[1] = -50;
2149 pDevice
->ldBmThreshold
[2] = 0;
2150 pDevice
->ldBmThreshold
[3] = 0;
2151 } else if ((byRFType
== RF_AIROHA
) || (byRFType
== RF_AL2230S
)) {
2152 for (ii
= 0; ii
< CB_VT3253B0_INIT_FOR_AIROHA2230
; ii
++) {
2153 bResult
&= BBbWriteEmbedded(dwIoBase
, byVT3253B0_AIROHA2230
[ii
][0], byVT3253B0_AIROHA2230
[ii
][1]);
2155 for (ii
= 0; ii
< CB_VT3253B0_AGC
; ii
++) {
2156 bResult
&= BBbWriteEmbedded(dwIoBase
, byVT3253B0_AGC
[ii
][0], byVT3253B0_AGC
[ii
][1]);
2158 pDevice
->abyBBVGA
[0] = 0x1C;
2159 pDevice
->abyBBVGA
[1] = 0x10;
2160 pDevice
->abyBBVGA
[2] = 0x0;
2161 pDevice
->abyBBVGA
[3] = 0x0;
2162 pDevice
->ldBmThreshold
[0] = -70;
2163 pDevice
->ldBmThreshold
[1] = -48;
2164 pDevice
->ldBmThreshold
[2] = 0;
2165 pDevice
->ldBmThreshold
[3] = 0;
2166 } else if (byRFType
== RF_UW2451
) {
2167 for (ii
= 0; ii
< CB_VT3253B0_INIT_FOR_UW2451
; ii
++) {
2168 bResult
&= BBbWriteEmbedded(dwIoBase
, byVT3253B0_UW2451
[ii
][0], byVT3253B0_UW2451
[ii
][1]);
2170 for (ii
= 0; ii
< CB_VT3253B0_AGC
; ii
++) {
2171 bResult
&= BBbWriteEmbedded(dwIoBase
, byVT3253B0_AGC
[ii
][0], byVT3253B0_AGC
[ii
][1]);
2173 VNSvOutPortB(dwIoBase
+ MAC_REG_ITRTMSET
, 0x23);
2174 MACvRegBitsOn(dwIoBase
, MAC_REG_PAPEDELAY
, BIT0
);
2176 pDevice
->abyBBVGA
[0] = 0x14;
2177 pDevice
->abyBBVGA
[1] = 0x0A;
2178 pDevice
->abyBBVGA
[2] = 0x0;
2179 pDevice
->abyBBVGA
[3] = 0x0;
2180 pDevice
->ldBmThreshold
[0] = -60;
2181 pDevice
->ldBmThreshold
[1] = -50;
2182 pDevice
->ldBmThreshold
[2] = 0;
2183 pDevice
->ldBmThreshold
[3] = 0;
2184 } else if (byRFType
== RF_UW2452
) {
2185 for (ii
= 0; ii
< CB_VT3253B0_INIT_FOR_UW2451
; ii
++) {
2186 bResult
&= BBbWriteEmbedded(dwIoBase
, byVT3253B0_UW2451
[ii
][0], byVT3253B0_UW2451
[ii
][1]);
2188 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2189 //bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);
2190 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2191 //bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);
2192 // Select VC1/VC2, CR215 = 0x02->0x06
2193 bResult
&= BBbWriteEmbedded(dwIoBase
, 0xd7, 0x06);
2195 //{{RobertYu:20050125, request by Jack
2196 bResult
&= BBbWriteEmbedded(dwIoBase
, 0x90, 0x20);
2197 bResult
&= BBbWriteEmbedded(dwIoBase
, 0x97, 0xeb);
2200 //{{RobertYu:20050221, request by Jack
2201 bResult
&= BBbWriteEmbedded(dwIoBase
, 0xa6, 0x00);
2202 bResult
&= BBbWriteEmbedded(dwIoBase
, 0xa8, 0x30);
2204 bResult
&= BBbWriteEmbedded(dwIoBase
, 0xb0, 0x58);
2206 for (ii
= 0; ii
< CB_VT3253B0_AGC
; ii
++) {
2207 bResult
&= BBbWriteEmbedded(dwIoBase
, byVT3253B0_AGC
[ii
][0], byVT3253B0_AGC
[ii
][1]);
2210 pDevice
->abyBBVGA
[0] = 0x14;
2211 pDevice
->abyBBVGA
[1] = 0x0A;
2212 pDevice
->abyBBVGA
[2] = 0x0;
2213 pDevice
->abyBBVGA
[3] = 0x0;
2214 pDevice
->ldBmThreshold
[0] = -60;
2215 pDevice
->ldBmThreshold
[1] = -50;
2216 pDevice
->ldBmThreshold
[2] = 0;
2217 pDevice
->ldBmThreshold
[3] = 0;
2220 } else if (byRFType
== RF_VT3226
) {
2221 for (ii
= 0; ii
< CB_VT3253B0_INIT_FOR_AIROHA2230
; ii
++) {
2222 bResult
&= BBbWriteEmbedded(dwIoBase
, byVT3253B0_AIROHA2230
[ii
][0], byVT3253B0_AIROHA2230
[ii
][1]);
2224 for (ii
= 0; ii
< CB_VT3253B0_AGC
; ii
++) {
2225 bResult
&= BBbWriteEmbedded(dwIoBase
, byVT3253B0_AGC
[ii
][0], byVT3253B0_AGC
[ii
][1]);
2227 pDevice
->abyBBVGA
[0] = 0x1C;
2228 pDevice
->abyBBVGA
[1] = 0x10;
2229 pDevice
->abyBBVGA
[2] = 0x0;
2230 pDevice
->abyBBVGA
[3] = 0x0;
2231 pDevice
->ldBmThreshold
[0] = -70;
2232 pDevice
->ldBmThreshold
[1] = -48;
2233 pDevice
->ldBmThreshold
[2] = 0;
2234 pDevice
->ldBmThreshold
[3] = 0;
2235 // Fix VT3226 DFC system timing issue
2236 MACvSetRFLE_LatchBase(dwIoBase
);
2237 //{{ RobertYu: 20050104
2238 } else if (byRFType
== RF_AIROHA7230
) {
2239 for (ii
= 0; ii
< CB_VT3253B0_INIT_FOR_AIROHA2230
; ii
++) {
2240 bResult
&= BBbWriteEmbedded(dwIoBase
, byVT3253B0_AIROHA2230
[ii
][0], byVT3253B0_AIROHA2230
[ii
][1]);
2243 //{{ RobertYu:20050223, request by JerryChung
2244 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2245 //bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);
2246 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2247 //bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);
2248 // Select VC1/VC2, CR215 = 0x02->0x06
2249 bResult
&= BBbWriteEmbedded(dwIoBase
, 0xd7, 0x06);
2252 for (ii
= 0; ii
< CB_VT3253B0_AGC
; ii
++) {
2253 bResult
&= BBbWriteEmbedded(dwIoBase
, byVT3253B0_AGC
[ii
][0], byVT3253B0_AGC
[ii
][1]);
2255 pDevice
->abyBBVGA
[0] = 0x1C;
2256 pDevice
->abyBBVGA
[1] = 0x10;
2257 pDevice
->abyBBVGA
[2] = 0x0;
2258 pDevice
->abyBBVGA
[3] = 0x0;
2259 pDevice
->ldBmThreshold
[0] = -70;
2260 pDevice
->ldBmThreshold
[1] = -48;
2261 pDevice
->ldBmThreshold
[2] = 0;
2262 pDevice
->ldBmThreshold
[3] = 0;
2266 pDevice
->bUpdateBBVGA
= false;
2267 pDevice
->abyBBVGA
[0] = 0x1C;
2270 if (byLocalID
> REV_ID_VT3253_A1
) {
2271 BBbWriteEmbedded(dwIoBase
, 0x04, 0x7F);
2272 BBbWriteEmbedded(dwIoBase
, 0x0D, 0x01);
2279 * Description: Read All Baseband Registers
2283 * dwIoBase - I/O base address
2284 * pbyBBRegs - Point to struct that stores Baseband Registers
2288 * Return Value: none
2291 void BBvReadAllRegs(unsigned long dwIoBase
, unsigned char *pbyBBRegs
)
2294 unsigned char byBase
= 1;
2295 for (ii
= 0; ii
< BB_MAX_CONTEXT_SIZE
; ii
++) {
2296 BBbReadEmbedded(dwIoBase
, (unsigned char)(ii
*byBase
), pbyBBRegs
);
2297 pbyBBRegs
+= byBase
;
2302 * Description: Turn on BaseBand Loopback mode
2306 * dwIoBase - I/O base address
2307 * bCCK - If CCK is set
2311 * Return Value: none
2315 void BBvLoopbackOn(PSDevice pDevice
)
2317 unsigned char byData
;
2318 unsigned long dwIoBase
= pDevice
->PortOffset
;
2321 BBbReadEmbedded(dwIoBase
, 0xC9, &pDevice
->byBBCRc9
);//CR201
2322 BBbWriteEmbedded(dwIoBase
, 0xC9, 0);
2323 BBbReadEmbedded(dwIoBase
, 0x4D, &pDevice
->byBBCR4d
);//CR77
2324 BBbWriteEmbedded(dwIoBase
, 0x4D, 0x90);
2326 //CR 88 = 0x02(CCK), 0x03(OFDM)
2327 BBbReadEmbedded(dwIoBase
, 0x88, &pDevice
->byBBCR88
);//CR136
2329 if (pDevice
->uConnectionRate
<= RATE_11M
) { //CCK
2330 // Enable internal digital loopback: CR33 |= 0000 0001
2331 BBbReadEmbedded(dwIoBase
, 0x21, &byData
);//CR33
2332 BBbWriteEmbedded(dwIoBase
, 0x21, (unsigned char)(byData
| 0x01));//CR33
2334 BBbWriteEmbedded(dwIoBase
, 0x9A, 0); //CR154
2336 BBbWriteEmbedded(dwIoBase
, 0x88, 0x02);//CR239
2338 // Enable internal digital loopback:CR154 |= 0000 0001
2339 BBbReadEmbedded(dwIoBase
, 0x9A, &byData
);//CR154
2340 BBbWriteEmbedded(dwIoBase
, 0x9A, (unsigned char)(byData
| 0x01));//CR154
2342 BBbWriteEmbedded(dwIoBase
, 0x21, 0); //CR33
2344 BBbWriteEmbedded(dwIoBase
, 0x88, 0x03);//CR239
2348 BBbWriteEmbedded(dwIoBase
, 0x0E, 0);//CR14
2351 BBbReadEmbedded(pDevice
->PortOffset
, 0x09, &pDevice
->byBBCR09
);
2352 BBbWriteEmbedded(pDevice
->PortOffset
, 0x09, (unsigned char)(pDevice
->byBBCR09
& 0xDE));
2356 * Description: Turn off BaseBand Loopback mode
2360 * pDevice - Device Structure
2365 * Return Value: none
2368 void BBvLoopbackOff(PSDevice pDevice
)
2370 unsigned char byData
;
2371 unsigned long dwIoBase
= pDevice
->PortOffset
;
2373 BBbWriteEmbedded(dwIoBase
, 0xC9, pDevice
->byBBCRc9
);//CR201
2374 BBbWriteEmbedded(dwIoBase
, 0x88, pDevice
->byBBCR88
);//CR136
2375 BBbWriteEmbedded(dwIoBase
, 0x09, pDevice
->byBBCR09
);//CR136
2376 BBbWriteEmbedded(dwIoBase
, 0x4D, pDevice
->byBBCR4d
);//CR77
2378 if (pDevice
->uConnectionRate
<= RATE_11M
) { // CCK
2379 // Set the CR33 Bit2 to disable internal Loopback.
2380 BBbReadEmbedded(dwIoBase
, 0x21, &byData
);//CR33
2381 BBbWriteEmbedded(dwIoBase
, 0x21, (unsigned char)(byData
& 0xFE));//CR33
2383 BBbReadEmbedded(dwIoBase
, 0x9A, &byData
);//CR154
2384 BBbWriteEmbedded(dwIoBase
, 0x9A, (unsigned char)(byData
& 0xFE));//CR154
2386 BBbReadEmbedded(dwIoBase
, 0x0E, &byData
);//CR14
2387 BBbWriteEmbedded(dwIoBase
, 0x0E, (unsigned char)(byData
| 0x80));//CR14
2391 * Description: Set ShortSlotTime mode
2395 * pDevice - Device Structure
2399 * Return Value: none
2403 BBvSetShortSlotTime(PSDevice pDevice
)
2405 unsigned char byBBRxConf
= 0;
2406 unsigned char byBBVGA
= 0;
2408 BBbReadEmbedded(pDevice
->PortOffset
, 0x0A, &byBBRxConf
);//CR10
2410 if (pDevice
->bShortSlotTime
) {
2411 byBBRxConf
&= 0xDF;//1101 1111
2413 byBBRxConf
|= 0x20;//0010 0000
2416 // patch for 3253B0 Baseband with Cardbus module
2417 BBbReadEmbedded(pDevice
->PortOffset
, 0xE7, &byBBVGA
);
2418 if (byBBVGA
== pDevice
->abyBBVGA
[0]) {
2419 byBBRxConf
|= 0x20;//0010 0000
2422 BBbWriteEmbedded(pDevice
->PortOffset
, 0x0A, byBBRxConf
);//CR10
2425 void BBvSetVGAGainOffset(PSDevice pDevice
, unsigned char byData
)
2427 unsigned char byBBRxConf
= 0;
2429 BBbWriteEmbedded(pDevice
->PortOffset
, 0xE7, byData
);
2431 BBbReadEmbedded(pDevice
->PortOffset
, 0x0A, &byBBRxConf
);//CR10
2432 // patch for 3253B0 Baseband with Cardbus module
2433 if (byData
== pDevice
->abyBBVGA
[0])
2434 byBBRxConf
|= 0x20;//0010 0000
2435 else if (pDevice
->bShortSlotTime
)
2436 byBBRxConf
&= 0xDF;//1101 1111
2438 byBBRxConf
|= 0x20;//0010 0000
2439 pDevice
->byBBVGACurrent
= byData
;
2440 BBbWriteEmbedded(pDevice
->PortOffset
, 0x0A, byBBRxConf
);//CR10
2444 * Description: Baseband SoftwareReset
2448 * dwIoBase - I/O base address
2452 * Return Value: none
2456 BBvSoftwareReset(unsigned long dwIoBase
)
2458 BBbWriteEmbedded(dwIoBase
, 0x50, 0x40);
2459 BBbWriteEmbedded(dwIoBase
, 0x50, 0);
2460 BBbWriteEmbedded(dwIoBase
, 0x9C, 0x01);
2461 BBbWriteEmbedded(dwIoBase
, 0x9C, 0);
2465 * Description: Baseband Power Save Mode ON
2469 * dwIoBase - I/O base address
2473 * Return Value: none
2477 BBvPowerSaveModeON(unsigned long dwIoBase
)
2479 unsigned char byOrgData
;
2481 BBbReadEmbedded(dwIoBase
, 0x0D, &byOrgData
);
2483 BBbWriteEmbedded(dwIoBase
, 0x0D, byOrgData
);
2487 * Description: Baseband Power Save Mode OFF
2491 * dwIoBase - I/O base address
2495 * Return Value: none
2499 BBvPowerSaveModeOFF(unsigned long dwIoBase
)
2501 unsigned char byOrgData
;
2503 BBbReadEmbedded(dwIoBase
, 0x0D, &byOrgData
);
2504 byOrgData
&= ~(BIT0
);
2505 BBbWriteEmbedded(dwIoBase
, 0x0D, byOrgData
);
2509 * Description: Set Tx Antenna mode
2513 * pDevice - Device Structure
2514 * byAntennaMode - Antenna Mode
2518 * Return Value: none
2523 BBvSetTxAntennaMode(unsigned long dwIoBase
, unsigned char byAntennaMode
)
2525 unsigned char byBBTxConf
;
2527 BBbReadEmbedded(dwIoBase
, 0x09, &byBBTxConf
);//CR09
2528 if (byAntennaMode
== ANT_DIVERSITY
) {
2529 // bit 1 is diversity
2531 } else if (byAntennaMode
== ANT_A
) {
2533 byBBTxConf
&= 0xF9; // 1111 1001
2534 } else if (byAntennaMode
== ANT_B
) {
2535 byBBTxConf
&= 0xFD; // 1111 1101
2538 BBbWriteEmbedded(dwIoBase
, 0x09, byBBTxConf
);//CR09
2542 * Description: Set Rx Antenna mode
2546 * pDevice - Device Structure
2547 * byAntennaMode - Antenna Mode
2551 * Return Value: none
2556 BBvSetRxAntennaMode(unsigned long dwIoBase
, unsigned char byAntennaMode
)
2558 unsigned char byBBRxConf
;
2560 BBbReadEmbedded(dwIoBase
, 0x0A, &byBBRxConf
);//CR10
2561 if (byAntennaMode
== ANT_DIVERSITY
) {
2564 } else if (byAntennaMode
== ANT_A
) {
2565 byBBRxConf
&= 0xFC; // 1111 1100
2566 } else if (byAntennaMode
== ANT_B
) {
2567 byBBRxConf
&= 0xFE; // 1111 1110
2570 BBbWriteEmbedded(dwIoBase
, 0x0A, byBBRxConf
);//CR10
2574 * Description: BBvSetDeepSleep
2578 * pDevice - Device Structure
2582 * Return Value: none
2586 BBvSetDeepSleep(unsigned long dwIoBase
, unsigned char byLocalID
)
2588 BBbWriteEmbedded(dwIoBase
, 0x0C, 0x17);//CR12
2589 BBbWriteEmbedded(dwIoBase
, 0x0D, 0xB9);//CR13
2593 BBvExitDeepSleep(unsigned long dwIoBase
, unsigned char byLocalID
)
2595 BBbWriteEmbedded(dwIoBase
, 0x0C, 0x00);//CR12
2596 BBbWriteEmbedded(dwIoBase
, 0x0D, 0x01);//CR13
2601 s_ulGetRatio(PSDevice pDevice
)
2603 unsigned long ulRatio
= 0;
2604 unsigned long ulMaxPacket
;
2605 unsigned long ulPacketNum
;
2607 //This is a thousand-ratio
2608 ulMaxPacket
= pDevice
->uNumSQ3
[RATE_54M
];
2609 if (pDevice
->uNumSQ3
[RATE_54M
] != 0) {
2610 ulPacketNum
= pDevice
->uNumSQ3
[RATE_54M
];
2611 ulRatio
= (ulPacketNum
* 1000 / pDevice
->uDiversityCnt
);
2612 ulRatio
+= TOP_RATE_54M
;
2614 if (pDevice
->uNumSQ3
[RATE_48M
] > ulMaxPacket
) {
2615 ulPacketNum
= pDevice
->uNumSQ3
[RATE_54M
] + pDevice
->uNumSQ3
[RATE_48M
];
2616 ulRatio
= (ulPacketNum
* 1000 / pDevice
->uDiversityCnt
);
2617 ulRatio
+= TOP_RATE_48M
;
2618 ulMaxPacket
= pDevice
->uNumSQ3
[RATE_48M
];
2620 if (pDevice
->uNumSQ3
[RATE_36M
] > ulMaxPacket
) {
2621 ulPacketNum
= pDevice
->uNumSQ3
[RATE_54M
] + pDevice
->uNumSQ3
[RATE_48M
] +
2622 pDevice
->uNumSQ3
[RATE_36M
];
2623 ulRatio
= (ulPacketNum
* 1000 / pDevice
->uDiversityCnt
);
2624 ulRatio
+= TOP_RATE_36M
;
2625 ulMaxPacket
= pDevice
->uNumSQ3
[RATE_36M
];
2627 if (pDevice
->uNumSQ3
[RATE_24M
] > ulMaxPacket
) {
2628 ulPacketNum
= pDevice
->uNumSQ3
[RATE_54M
] + pDevice
->uNumSQ3
[RATE_48M
] +
2629 pDevice
->uNumSQ3
[RATE_36M
] + pDevice
->uNumSQ3
[RATE_24M
];
2630 ulRatio
= (ulPacketNum
* 1000 / pDevice
->uDiversityCnt
);
2631 ulRatio
+= TOP_RATE_24M
;
2632 ulMaxPacket
= pDevice
->uNumSQ3
[RATE_24M
];
2634 if (pDevice
->uNumSQ3
[RATE_18M
] > ulMaxPacket
) {
2635 ulPacketNum
= pDevice
->uNumSQ3
[RATE_54M
] + pDevice
->uNumSQ3
[RATE_48M
] +
2636 pDevice
->uNumSQ3
[RATE_36M
] + pDevice
->uNumSQ3
[RATE_24M
] +
2637 pDevice
->uNumSQ3
[RATE_18M
];
2638 ulRatio
= (ulPacketNum
* 1000 / pDevice
->uDiversityCnt
);
2639 ulRatio
+= TOP_RATE_18M
;
2640 ulMaxPacket
= pDevice
->uNumSQ3
[RATE_18M
];
2642 if (pDevice
->uNumSQ3
[RATE_12M
] > ulMaxPacket
) {
2643 ulPacketNum
= pDevice
->uNumSQ3
[RATE_54M
] + pDevice
->uNumSQ3
[RATE_48M
] +
2644 pDevice
->uNumSQ3
[RATE_36M
] + pDevice
->uNumSQ3
[RATE_24M
] +
2645 pDevice
->uNumSQ3
[RATE_18M
] + pDevice
->uNumSQ3
[RATE_12M
];
2646 ulRatio
= (ulPacketNum
* 1000 / pDevice
->uDiversityCnt
);
2647 ulRatio
+= TOP_RATE_12M
;
2648 ulMaxPacket
= pDevice
->uNumSQ3
[RATE_12M
];
2650 if (pDevice
->uNumSQ3
[RATE_11M
] > ulMaxPacket
) {
2651 ulPacketNum
= pDevice
->uDiversityCnt
- pDevice
->uNumSQ3
[RATE_1M
] -
2652 pDevice
->uNumSQ3
[RATE_2M
] - pDevice
->uNumSQ3
[RATE_5M
] -
2653 pDevice
->uNumSQ3
[RATE_6M
] - pDevice
->uNumSQ3
[RATE_9M
];
2654 ulRatio
= (ulPacketNum
* 1000 / pDevice
->uDiversityCnt
);
2655 ulRatio
+= TOP_RATE_11M
;
2656 ulMaxPacket
= pDevice
->uNumSQ3
[RATE_11M
];
2658 if (pDevice
->uNumSQ3
[RATE_9M
] > ulMaxPacket
) {
2659 ulPacketNum
= pDevice
->uDiversityCnt
- pDevice
->uNumSQ3
[RATE_1M
] -
2660 pDevice
->uNumSQ3
[RATE_2M
] - pDevice
->uNumSQ3
[RATE_5M
] -
2661 pDevice
->uNumSQ3
[RATE_6M
];
2662 ulRatio
= (ulPacketNum
* 1000 / pDevice
->uDiversityCnt
);
2663 ulRatio
+= TOP_RATE_9M
;
2664 ulMaxPacket
= pDevice
->uNumSQ3
[RATE_9M
];
2666 if (pDevice
->uNumSQ3
[RATE_6M
] > ulMaxPacket
) {
2667 ulPacketNum
= pDevice
->uDiversityCnt
- pDevice
->uNumSQ3
[RATE_1M
] -
2668 pDevice
->uNumSQ3
[RATE_2M
] - pDevice
->uNumSQ3
[RATE_5M
];
2669 ulRatio
= (ulPacketNum
* 1000 / pDevice
->uDiversityCnt
);
2670 ulRatio
+= TOP_RATE_6M
;
2671 ulMaxPacket
= pDevice
->uNumSQ3
[RATE_6M
];
2673 if (pDevice
->uNumSQ3
[RATE_5M
] > ulMaxPacket
) {
2674 ulPacketNum
= pDevice
->uDiversityCnt
- pDevice
->uNumSQ3
[RATE_1M
] -
2675 pDevice
->uNumSQ3
[RATE_2M
];
2676 ulRatio
= (ulPacketNum
* 1000 / pDevice
->uDiversityCnt
);
2677 ulRatio
+= TOP_RATE_55M
;
2678 ulMaxPacket
= pDevice
->uNumSQ3
[RATE_5M
];
2680 if (pDevice
->uNumSQ3
[RATE_2M
] > ulMaxPacket
) {
2681 ulPacketNum
= pDevice
->uDiversityCnt
- pDevice
->uNumSQ3
[RATE_1M
];
2682 ulRatio
= (ulPacketNum
* 1000 / pDevice
->uDiversityCnt
);
2683 ulRatio
+= TOP_RATE_2M
;
2684 ulMaxPacket
= pDevice
->uNumSQ3
[RATE_2M
];
2686 if (pDevice
->uNumSQ3
[RATE_1M
] > ulMaxPacket
) {
2687 ulPacketNum
= pDevice
->uDiversityCnt
;
2688 ulRatio
= (ulPacketNum
* 1000 / pDevice
->uDiversityCnt
);
2689 ulRatio
+= TOP_RATE_1M
;
2696 BBvClearAntDivSQ3Value(PSDevice pDevice
)
2700 pDevice
->uDiversityCnt
= 0;
2701 for (ii
= 0; ii
< MAX_RATE
; ii
++) {
2702 pDevice
->uNumSQ3
[ii
] = 0;
2707 * Description: Antenna Diversity
2711 * pDevice - Device Structure
2712 * byRSR - RSR from received packet
2713 * bySQ3 - SQ3 value from received packet
2717 * Return Value: none
2722 BBvAntennaDiversity(PSDevice pDevice
, unsigned char byRxRate
, unsigned char bySQ3
)
2724 if ((byRxRate
>= MAX_RATE
) || (pDevice
->wAntDiversityMaxRate
>= MAX_RATE
)) {
2727 pDevice
->uDiversityCnt
++;
2729 pDevice
->uNumSQ3
[byRxRate
]++;
2731 if (pDevice
->byAntennaState
== 0) {
2732 if (pDevice
->uDiversityCnt
> pDevice
->ulDiversityNValue
) {
2733 DBG_PRT(MSG_LEVEL_DEBUG
, KERN_INFO
"ulDiversityNValue=[%d],54M-[%d]\n",
2734 (int)pDevice
->ulDiversityNValue
, (int)pDevice
->uNumSQ3
[(int)pDevice
->wAntDiversityMaxRate
]);
2736 if (pDevice
->uNumSQ3
[pDevice
->wAntDiversityMaxRate
] < pDevice
->uDiversityCnt
/2) {
2737 pDevice
->ulRatio_State0
= s_ulGetRatio(pDevice
);
2738 DBG_PRT(MSG_LEVEL_DEBUG
, KERN_INFO
"SQ3_State0, rate = [%08x]\n", (int)pDevice
->ulRatio_State0
);
2740 if (pDevice
->byTMax
== 0)
2742 DBG_PRT(MSG_LEVEL_DEBUG
, KERN_INFO
"1.[%08x], uNumSQ3[%d]=%d, %d\n",
2743 (int)pDevice
->ulRatio_State0
, (int)pDevice
->wAntDiversityMaxRate
,
2744 (int)pDevice
->uNumSQ3
[(int)pDevice
->wAntDiversityMaxRate
], (int)pDevice
->uDiversityCnt
);
2746 s_vChangeAntenna(pDevice
);
2747 pDevice
->byAntennaState
= 1;
2748 del_timer(&pDevice
->TimerSQ3Tmax3
);
2749 del_timer(&pDevice
->TimerSQ3Tmax2
);
2750 pDevice
->TimerSQ3Tmax1
.expires
= RUN_AT(pDevice
->byTMax
* HZ
);
2751 add_timer(&pDevice
->TimerSQ3Tmax1
);
2754 pDevice
->TimerSQ3Tmax3
.expires
= RUN_AT(pDevice
->byTMax3
* HZ
);
2755 add_timer(&pDevice
->TimerSQ3Tmax3
);
2757 BBvClearAntDivSQ3Value(pDevice
);
2760 } else { //byAntennaState == 1
2762 if (pDevice
->uDiversityCnt
> pDevice
->ulDiversityMValue
) {
2763 del_timer(&pDevice
->TimerSQ3Tmax1
);
2765 pDevice
->ulRatio_State1
= s_ulGetRatio(pDevice
);
2766 DBG_PRT(MSG_LEVEL_DEBUG
, KERN_INFO
"RX:SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2767 (int)pDevice
->ulRatio_State0
, (int)pDevice
->ulRatio_State1
);
2769 if (pDevice
->ulRatio_State1
< pDevice
->ulRatio_State0
) {
2770 DBG_PRT(MSG_LEVEL_DEBUG
, KERN_INFO
"2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2771 (int)pDevice
->ulRatio_State0
, (int)pDevice
->ulRatio_State1
,
2772 (int)pDevice
->wAntDiversityMaxRate
,
2773 (int)pDevice
->uNumSQ3
[(int)pDevice
->wAntDiversityMaxRate
], (int)pDevice
->uDiversityCnt
);
2775 s_vChangeAntenna(pDevice
);
2776 pDevice
->TimerSQ3Tmax3
.expires
= RUN_AT(pDevice
->byTMax3
* HZ
);
2777 pDevice
->TimerSQ3Tmax2
.expires
= RUN_AT(pDevice
->byTMax2
* HZ
);
2778 add_timer(&pDevice
->TimerSQ3Tmax3
);
2779 add_timer(&pDevice
->TimerSQ3Tmax2
);
2781 pDevice
->byAntennaState
= 0;
2782 BBvClearAntDivSQ3Value(pDevice
);
2790 * Timer for SQ3 antenna diversity
2797 * Return Value: none
2803 void *hDeviceContext
2806 PSDevice pDevice
= (PSDevice
)hDeviceContext
;
2808 DBG_PRT(MSG_LEVEL_DEBUG
, KERN_INFO
"TimerSQ3CallBack...");
2809 spin_lock_irq(&pDevice
->lock
);
2811 DBG_PRT(MSG_LEVEL_DEBUG
, KERN_INFO
"3.[%08x][%08x], %d\n", (int)pDevice
->ulRatio_State0
, (int)pDevice
->ulRatio_State1
, (int)pDevice
->uDiversityCnt
);
2813 s_vChangeAntenna(pDevice
);
2814 pDevice
->byAntennaState
= 0;
2815 BBvClearAntDivSQ3Value(pDevice
);
2817 pDevice
->TimerSQ3Tmax3
.expires
= RUN_AT(pDevice
->byTMax3
* HZ
);
2818 pDevice
->TimerSQ3Tmax2
.expires
= RUN_AT(pDevice
->byTMax2
* HZ
);
2819 add_timer(&pDevice
->TimerSQ3Tmax3
);
2820 add_timer(&pDevice
->TimerSQ3Tmax2
);
2822 spin_unlock_irq(&pDevice
->lock
);
2829 * Timer for SQ3 antenna diversity
2834 * hDeviceContext - Pointer to the adapter
2840 * Return Value: none
2845 TimerState1CallBack(
2846 void *hDeviceContext
2849 PSDevice pDevice
= (PSDevice
)hDeviceContext
;
2851 DBG_PRT(MSG_LEVEL_DEBUG
, KERN_INFO
"TimerState1CallBack...");
2853 spin_lock_irq(&pDevice
->lock
);
2854 if (pDevice
->uDiversityCnt
< pDevice
->ulDiversityMValue
/100) {
2855 s_vChangeAntenna(pDevice
);
2856 pDevice
->TimerSQ3Tmax3
.expires
= RUN_AT(pDevice
->byTMax3
* HZ
);
2857 pDevice
->TimerSQ3Tmax2
.expires
= RUN_AT(pDevice
->byTMax2
* HZ
);
2858 add_timer(&pDevice
->TimerSQ3Tmax3
);
2859 add_timer(&pDevice
->TimerSQ3Tmax2
);
2861 pDevice
->ulRatio_State1
= s_ulGetRatio(pDevice
);
2862 DBG_PRT(MSG_LEVEL_DEBUG
, KERN_INFO
"SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2863 (int)pDevice
->ulRatio_State0
, (int)pDevice
->ulRatio_State1
);
2865 if (pDevice
->ulRatio_State1
< pDevice
->ulRatio_State0
) {
2866 DBG_PRT(MSG_LEVEL_DEBUG
, KERN_INFO
"2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2867 (int)pDevice
->ulRatio_State0
, (int)pDevice
->ulRatio_State1
,
2868 (int)pDevice
->wAntDiversityMaxRate
,
2869 (int)pDevice
->uNumSQ3
[(int)pDevice
->wAntDiversityMaxRate
], (int)pDevice
->uDiversityCnt
);
2871 s_vChangeAntenna(pDevice
);
2873 pDevice
->TimerSQ3Tmax3
.expires
= RUN_AT(pDevice
->byTMax3
* HZ
);
2874 pDevice
->TimerSQ3Tmax2
.expires
= RUN_AT(pDevice
->byTMax2
* HZ
);
2875 add_timer(&pDevice
->TimerSQ3Tmax3
);
2876 add_timer(&pDevice
->TimerSQ3Tmax2
);
2879 pDevice
->byAntennaState
= 0;
2880 BBvClearAntDivSQ3Value(pDevice
);
2881 spin_unlock_irq(&pDevice
->lock
);