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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
[mirror_ubuntu-artful-kernel.git] / drivers / staging / vt6655 / rf.c
1 /*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * File: rf.c
16 *
17 * Purpose: rf function code
18 *
19 * Author: Jerry Chen
20 *
21 * Date: Feb. 19, 2004
22 *
23 * Functions:
24 * IFRFbWriteEmbedded - Embedded write RF register via MAC
25 *
26 * Revision History:
27 * RobertYu 2005
28 * chester 2008
29 *
30 */
31
32 #include "mac.h"
33 #include "srom.h"
34 #include "rf.h"
35 #include "baseband.h"
36
37 #define BY_AL2230_REG_LEN 23 /* 24bit */
38 #define CB_AL2230_INIT_SEQ 15
39 #define SWITCH_CHANNEL_DELAY_AL2230 200 /* us */
40 #define AL2230_PWR_IDX_LEN 64
41
42 #define BY_AL7230_REG_LEN 23 /* 24bit */
43 #define CB_AL7230_INIT_SEQ 16
44 #define SWITCH_CHANNEL_DELAY_AL7230 200 /* us */
45 #define AL7230_PWR_IDX_LEN 64
46
47 static const unsigned long dwAL2230InitTable[CB_AL2230_INIT_SEQ] = {
48 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
49 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
50 0x01A00200 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
51 0x00FFF300 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
52 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
53 0x0F4DC500 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
54 0x0805B600 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
55 0x0146C700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
56 0x00068800 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
57 0x0403B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
58 0x00DBBA00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
59 0x00099B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
60 0x0BDFFC00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
61 0x00000D00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
62 0x00580F00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW
63 };
64
65 static const unsigned long dwAL2230ChannelTable0[CB_MAX_CHANNEL] = {
66 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
67 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
68 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
69 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
70 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
71 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
72 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
73 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
74 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
75 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
76 0x03E7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */
77 0x03E7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */
78 0x03F7C000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */
79 0x03E7C000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 14, Tf = 2412M */
80 };
81
82 static const unsigned long dwAL2230ChannelTable1[CB_MAX_CHANNEL] = {
83 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
84 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
85 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
86 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
87 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
88 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
89 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
90 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
91 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
92 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
93 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */
94 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */
95 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */
96 0x06666100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 14, Tf = 2412M */
97 };
98
99 static unsigned long dwAL2230PowerTable[AL2230_PWR_IDX_LEN] = {
100 0x04040900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
101 0x04041900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
102 0x04042900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
103 0x04043900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
104 0x04044900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
105 0x04045900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
106 0x04046900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
107 0x04047900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
108 0x04048900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
109 0x04049900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
110 0x0404A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
111 0x0404B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
112 0x0404C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
113 0x0404D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
114 0x0404E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
115 0x0404F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
116 0x04050900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
117 0x04051900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
118 0x04052900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
119 0x04053900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
120 0x04054900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
121 0x04055900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
122 0x04056900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
123 0x04057900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
124 0x04058900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
125 0x04059900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
126 0x0405A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
127 0x0405B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
128 0x0405C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
129 0x0405D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
130 0x0405E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
131 0x0405F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
132 0x04060900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
133 0x04061900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
134 0x04062900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
135 0x04063900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
136 0x04064900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
137 0x04065900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
138 0x04066900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
139 0x04067900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
140 0x04068900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
141 0x04069900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
142 0x0406A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
143 0x0406B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
144 0x0406C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
145 0x0406D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
146 0x0406E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
147 0x0406F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
148 0x04070900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
149 0x04071900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
150 0x04072900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
151 0x04073900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
152 0x04074900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
153 0x04075900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
154 0x04076900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
155 0x04077900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
156 0x04078900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
157 0x04079900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
158 0x0407A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
159 0x0407B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
160 0x0407C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
161 0x0407D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
162 0x0407E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW,
163 0x0407F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW
164 };
165
166 /* 40MHz reference frequency
167 * Need to Pull PLLON(PE3) low when writing channel registers through 3-wire.
168 */
169 static const unsigned long dwAL7230InitTable[CB_AL7230_INIT_SEQ] = {
170 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel1 // Need modify for 11a */
171 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel1 // Need modify for 11a */
172 0x841FF200 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 451FE2 */
173 0x3FDFA300 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 5FDFA3 */
174 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* 11b/g // Need modify for 11a */
175 /* RoberYu:20050113, Rev0.47 Regsiter Setting Guide */
176 0x802B5500 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 8D1B55 */
177 0x56AF3600 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
178 0xCE020700 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 860207 */
179 0x6EBC0800 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
180 0x221BB900 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
181 0xE0000A00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: E0600A */
182 0x08031B00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) */
183 /* RoberYu:20050113, Rev0.47 Regsiter Setting Guide */
184 0x000A3C00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 00143C */
185 0xFFFFFD00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
186 0x00000E00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
187 0x1ABA8F00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* Need modify for 11a: 12BACF */
188 };
189
190 static const unsigned long dwAL7230InitTableAMode[CB_AL7230_INIT_SEQ] = {
191 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel184 // Need modify for 11b/g */
192 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel184 // Need modify for 11b/g */
193 0x451FE200 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */
194 0x5FDFA300 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */
195 0x67F78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* 11a // Need modify for 11b/g */
196 0x853F5500 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g, RoberYu:20050113 */
197 0x56AF3600 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
198 0xCE020700 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */
199 0x6EBC0800 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
200 0x221BB900 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
201 0xE0600A00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */
202 0x08031B00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) */
203 0x00147C00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */
204 0xFFFFFD00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
205 0x00000E00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
206 0x12BACF00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* Need modify for 11b/g */
207 };
208
209 static const unsigned long dwAL7230ChannelTable0[CB_MAX_CHANNEL] = {
210 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
211 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
212 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
213 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
214 0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
215 0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
216 0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
217 0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49 */
218 0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49 */
219 0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49 */
220 0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49 */
221 0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49 */
222 0x0037C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49 */
223 0x0037C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */
224
225 /* 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) */
226 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */
227 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */
228 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */
229 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */
230 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */
231 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */
232 0x0FF53000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */
233 0x0FF53000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */
234
235 /* 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
236 * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
237 */
238
239 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 5035MHz (23) */
240 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 5040MHz (24) */
241 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 5045MHz (25) */
242 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 5055MHz (26) */
243 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 5060MHz (27) */
244 0x0FF55000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 16, Tf = 5080MHz (28) */
245 0x0FF56000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 34, Tf = 5170MHz (29) */
246 0x0FF56000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 36, Tf = 5180MHz (30) */
247 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49 */
248 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 40, Tf = 5200MHz (32) */
249 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 42, Tf = 5210MHz (33) */
250 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 44, Tf = 5220MHz (34) */
251 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 46, Tf = 5230MHz (35) */
252 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 48, Tf = 5240MHz (36) */
253 0x0FF58000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 52, Tf = 5260MHz (37) */
254 0x0FF58000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 56, Tf = 5280MHz (38) */
255 0x0FF58000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 60, Tf = 5300MHz (39) */
256 0x0FF59000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 64, Tf = 5320MHz (40) */
257
258 0x0FF5C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */
259 0x0FF5C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */
260 0x0FF5C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */
261 0x0FF5D000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */
262 0x0FF5D000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */
263 0x0FF5D000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */
264 0x0FF5E000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */
265 0x0FF5E000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */
266 0x0FF5E000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */
267 0x0FF5F000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */
268 0x0FF5F000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */
269 0x0FF60000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */
270 0x0FF60000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */
271 0x0FF60000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */
272 0x0FF61000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */
273 0x0FF61000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 165, Tf = 5825MHz (56) */
274 };
275
276 static const unsigned long dwAL7230ChannelTable1[CB_MAX_CHANNEL] = {
277 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
278 0x1B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
279 0x03333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
280 0x0B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
281 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
282 0x1B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
283 0x03333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
284 0x0B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
285 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
286 0x1B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
287 0x03333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */
288 0x0B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */
289 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */
290 0x06666100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */
291
292 /* 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) */
293 0x1D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */
294 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */
295 0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */
296 0x08000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */
297 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */
298 0x0D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */
299 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */
300 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */
301
302 /* 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
303 * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
304 */
305 0x1D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 5035MHz (23) */
306 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 5040MHz (24) */
307 0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 5045MHz (25) */
308 0x08000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 5055MHz (26) */
309 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 5060MHz (27) */
310 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 16, Tf = 5080MHz (28) */
311 0x05555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 34, Tf = 5170MHz (29) */
312 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 36, Tf = 5180MHz (30) */
313 0x10000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 38, Tf = 5190MHz (31) */
314 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 40, Tf = 5200MHz (32) */
315 0x1AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 42, Tf = 5210MHz (33) */
316 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 44, Tf = 5220MHz (34) */
317 0x05555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 46, Tf = 5230MHz (35) */
318 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 48, Tf = 5240MHz (36) */
319 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 52, Tf = 5260MHz (37) */
320 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 56, Tf = 5280MHz (38) */
321 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 60, Tf = 5300MHz (39) */
322 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 64, Tf = 5320MHz (40) */
323 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */
324 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */
325 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */
326 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */
327 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */
328 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */
329 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */
330 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */
331 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */
332 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */
333 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */
334 0x18000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */
335 0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */
336 0x0D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */
337 0x18000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */
338 0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 165, Tf = 5825MHz (56) */
339 };
340
341 static const unsigned long dwAL7230ChannelTable2[CB_MAX_CHANNEL] = {
342 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
343 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
344 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
345 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
346 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
347 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
348 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
349 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
350 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
351 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
352 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */
353 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */
354 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */
355 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */
356
357 /* 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) */
358 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */
359 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */
360 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */
361 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */
362 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */
363 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */
364 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */
365 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */
366
367 /* 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
368 * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56)
369 */
370 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 5035MHz (23) */
371 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 5040MHz (24) */
372 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 5045MHz (25) */
373 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 5055MHz (26) */
374 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 5060MHz (27) */
375 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 16, Tf = 5080MHz (28) */
376 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 34, Tf = 5170MHz (29) */
377 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 36, Tf = 5180MHz (30) */
378 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 38, Tf = 5190MHz (31) */
379 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 40, Tf = 5200MHz (32) */
380 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 42, Tf = 5210MHz (33) */
381 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 44, Tf = 5220MHz (34) */
382 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 46, Tf = 5230MHz (35) */
383 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 48, Tf = 5240MHz (36) */
384 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 52, Tf = 5260MHz (37) */
385 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 56, Tf = 5280MHz (38) */
386 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 60, Tf = 5300MHz (39) */
387 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 64, Tf = 5320MHz (40) */
388 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */
389 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */
390 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */
391 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */
392 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */
393 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */
394 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */
395 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */
396 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */
397 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */
398 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */
399 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */
400 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */
401 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */
402 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */
403 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 165, Tf = 5825MHz (56) */
404 };
405
406 /*
407 * Description: AIROHA IFRF chip init function
408 *
409 * Parameters:
410 * In:
411 * iobase - I/O base address
412 * Out:
413 * none
414 *
415 * Return Value: true if succeeded; false if failed.
416 *
417 */
418 static bool s_bAL7230Init(struct vnt_private *priv)
419 {
420 void __iomem *iobase = priv->PortOffset;
421 int ii;
422 bool ret;
423
424 ret = true;
425
426 /* 3-wire control for normal mode */
427 VNSvOutPortB(iobase + MAC_REG_SOFTPWRCTL, 0);
428
429 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI |
430 SOFTPWRCTL_TXPEINV));
431 BBvPowerSaveModeOFF(priv); /* RobertYu:20050106, have DC value for Calibration */
432
433 for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
434 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[ii]);
435
436 /* PLL On */
437 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
438
439 /* Calibration */
440 MACvTimer0MicroSDelay(priv, 150);/* 150us */
441 /* TXDCOC:active, RCK:disable */
442 ret &= IFRFbWriteEmbedded(priv, (0x9ABA8F00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW));
443 MACvTimer0MicroSDelay(priv, 30);/* 30us */
444 /* TXDCOC:disable, RCK:active */
445 ret &= IFRFbWriteEmbedded(priv, (0x3ABA8F00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW));
446 MACvTimer0MicroSDelay(priv, 30);/* 30us */
447 /* TXDCOC:disable, RCK:disable */
448 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[CB_AL7230_INIT_SEQ-1]);
449
450 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 |
451 SOFTPWRCTL_SWPE2 |
452 SOFTPWRCTL_SWPECTI |
453 SOFTPWRCTL_TXPEINV));
454
455 BBvPowerSaveModeON(priv); /* RobertYu:20050106 */
456
457 /* PE1: TX_ON, PE2: RX_ON, PE3: PLLON */
458 /* 3-wire control for power saving mode */
459 VNSvOutPortB(iobase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); /* 1100 0000 */
460
461 return ret;
462 }
463
464 /* Need to Pull PLLON low when writing channel registers through
465 * 3-wire interface
466 */
467 static bool s_bAL7230SelectChannel(struct vnt_private *priv, unsigned char byChannel)
468 {
469 void __iomem *iobase = priv->PortOffset;
470 bool ret;
471
472 ret = true;
473
474 /* PLLON Off */
475 MACvWordRegBitsOff(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
476
477 ret &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable0[byChannel - 1]);
478 ret &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable1[byChannel - 1]);
479 ret &= IFRFbWriteEmbedded(priv, dwAL7230ChannelTable2[byChannel - 1]);
480
481 /* PLLOn On */
482 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
483
484 /* Set Channel[7] = 0 to tell H/W channel is changing now. */
485 VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel & 0x7F));
486 MACvTimer0MicroSDelay(priv, SWITCH_CHANNEL_DELAY_AL7230);
487 /* Set Channel[7] = 1 to tell H/W channel change is done. */
488 VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel | 0x80));
489
490 return ret;
491 }
492
493 /*
494 * Description: Write to IF/RF, by embedded programming
495 *
496 * Parameters:
497 * In:
498 * iobase - I/O base address
499 * dwData - data to write
500 * Out:
501 * none
502 *
503 * Return Value: true if succeeded; false if failed.
504 *
505 */
506 bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData)
507 {
508 void __iomem *iobase = priv->PortOffset;
509 unsigned short ww;
510 unsigned long dwValue;
511
512 VNSvOutPortD(iobase + MAC_REG_IFREGCTL, dwData);
513
514 /* W_MAX_TIMEOUT is the timeout period */
515 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
516 VNSvInPortD(iobase + MAC_REG_IFREGCTL, &dwValue);
517 if (dwValue & IFREGCTL_DONE)
518 break;
519 }
520
521 if (ww == W_MAX_TIMEOUT)
522 return false;
523
524 return true;
525 }
526
527 /*
528 * Description: AIROHA IFRF chip init function
529 *
530 * Parameters:
531 * In:
532 * iobase - I/O base address
533 * Out:
534 * none
535 *
536 * Return Value: true if succeeded; false if failed.
537 *
538 */
539 static bool RFbAL2230Init(struct vnt_private *priv)
540 {
541 void __iomem *iobase = priv->PortOffset;
542 int ii;
543 bool ret;
544
545 ret = true;
546
547 /* 3-wire control for normal mode */
548 VNSvOutPortB(iobase + MAC_REG_SOFTPWRCTL, 0);
549
550 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI |
551 SOFTPWRCTL_TXPEINV));
552 /* PLL Off */
553 MACvWordRegBitsOff(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
554
555 /* patch abnormal AL2230 frequency output */
556 IFRFbWriteEmbedded(priv, (0x07168700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
557
558 for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++)
559 ret &= IFRFbWriteEmbedded(priv, dwAL2230InitTable[ii]);
560 MACvTimer0MicroSDelay(priv, 30); /* delay 30 us */
561
562 /* PLL On */
563 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3);
564
565 MACvTimer0MicroSDelay(priv, 150);/* 150us */
566 ret &= IFRFbWriteEmbedded(priv, (0x00d80f00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
567 MACvTimer0MicroSDelay(priv, 30);/* 30us */
568 ret &= IFRFbWriteEmbedded(priv, (0x00780f00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
569 MACvTimer0MicroSDelay(priv, 30);/* 30us */
570 ret &= IFRFbWriteEmbedded(priv, dwAL2230InitTable[CB_AL2230_INIT_SEQ-1]);
571
572 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 |
573 SOFTPWRCTL_SWPE2 |
574 SOFTPWRCTL_SWPECTI |
575 SOFTPWRCTL_TXPEINV));
576
577 /* 3-wire control for power saving mode */
578 VNSvOutPortB(iobase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); /* 1100 0000 */
579
580 return ret;
581 }
582
583 static bool RFbAL2230SelectChannel(struct vnt_private *priv, unsigned char byChannel)
584 {
585 void __iomem *iobase = priv->PortOffset;
586 bool ret;
587
588 ret = true;
589
590 ret &= IFRFbWriteEmbedded(priv, dwAL2230ChannelTable0[byChannel - 1]);
591 ret &= IFRFbWriteEmbedded(priv, dwAL2230ChannelTable1[byChannel - 1]);
592
593 /* Set Channel[7] = 0 to tell H/W channel is changing now. */
594 VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel & 0x7F));
595 MACvTimer0MicroSDelay(priv, SWITCH_CHANNEL_DELAY_AL2230);
596 /* Set Channel[7] = 1 to tell H/W channel change is done. */
597 VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel | 0x80));
598
599 return ret;
600 }
601
602 /*
603 * Description: RF init function
604 *
605 * Parameters:
606 * In:
607 * byBBType
608 * byRFType
609 * Out:
610 * none
611 *
612 * Return Value: true if succeeded; false if failed.
613 *
614 */
615 bool RFbInit(struct vnt_private *priv)
616 {
617 bool ret = true;
618
619 switch (priv->byRFType) {
620 case RF_AIROHA:
621 case RF_AL2230S:
622 priv->byMaxPwrLevel = AL2230_PWR_IDX_LEN;
623 ret = RFbAL2230Init(priv);
624 break;
625 case RF_AIROHA7230:
626 priv->byMaxPwrLevel = AL7230_PWR_IDX_LEN;
627 ret = s_bAL7230Init(priv);
628 break;
629 case RF_NOTHING:
630 ret = true;
631 break;
632 default:
633 ret = false;
634 break;
635 }
636 return ret;
637 }
638
639 /*
640 * Description: Select channel
641 *
642 * Parameters:
643 * In:
644 * byRFType
645 * byChannel - Channel number
646 * Out:
647 * none
648 *
649 * Return Value: true if succeeded; false if failed.
650 *
651 */
652 bool RFbSelectChannel(struct vnt_private *priv, unsigned char byRFType,
653 u16 byChannel)
654 {
655 bool ret = true;
656
657 switch (byRFType) {
658 case RF_AIROHA:
659 case RF_AL2230S:
660 ret = RFbAL2230SelectChannel(priv, byChannel);
661 break;
662 /*{{ RobertYu: 20050104 */
663 case RF_AIROHA7230:
664 ret = s_bAL7230SelectChannel(priv, byChannel);
665 break;
666 /*}} RobertYu */
667 case RF_NOTHING:
668 ret = true;
669 break;
670 default:
671 ret = false;
672 break;
673 }
674 return ret;
675 }
676
677 /*
678 * Description: Write WakeProgSyn
679 *
680 * Parameters:
681 * In:
682 * iobase - I/O base address
683 * uChannel - channel number
684 * bySleepCnt - SleepProgSyn count
685 *
686 * Return Value: None.
687 *
688 */
689 bool RFvWriteWakeProgSyn(struct vnt_private *priv, unsigned char byRFType,
690 u16 uChannel)
691 {
692 void __iomem *iobase = priv->PortOffset;
693 int ii;
694 unsigned char byInitCount = 0;
695 unsigned char bySleepCount = 0;
696
697 VNSvOutPortW(iobase + MAC_REG_MISCFFNDEX, 0);
698 switch (byRFType) {
699 case RF_AIROHA:
700 case RF_AL2230S:
701
702 if (uChannel > CB_MAX_CHANNEL_24G)
703 return false;
704
705 /* Init Reg + Channel Reg (2) */
706 byInitCount = CB_AL2230_INIT_SEQ + 2;
707 bySleepCount = 0;
708 if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount))
709 return false;
710
711 for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++)
712 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230InitTable[ii]);
713
714 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel-1]);
715 ii++;
716 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel-1]);
717 break;
718
719 /* Need to check, PLLON need to be low for channel setting */
720 case RF_AIROHA7230:
721 /* Init Reg + Channel Reg (3) */
722 byInitCount = CB_AL7230_INIT_SEQ + 3;
723 bySleepCount = 0;
724 if (byInitCount > (MISCFIFO_SYNDATASIZE - bySleepCount))
725 return false;
726
727 if (uChannel <= CB_MAX_CHANNEL_24G) {
728 for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
729 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTable[ii]);
730 } else {
731 for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
732 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTableAMode[ii]);
733 }
734
735 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel-1]);
736 ii++;
737 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable1[uChannel-1]);
738 ii++;
739 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable2[uChannel-1]);
740 break;
741
742 case RF_NOTHING:
743 return true;
744
745 default:
746 return false;
747 }
748
749 MACvSetMISCFifo(priv, MISCFIFO_SYNINFO_IDX, (unsigned long)MAKEWORD(bySleepCount, byInitCount));
750
751 return true;
752 }
753
754 /*
755 * Description: Set Tx power
756 *
757 * Parameters:
758 * In:
759 * iobase - I/O base address
760 * dwRFPowerTable - RF Tx Power Setting
761 * Out:
762 * none
763 *
764 * Return Value: true if succeeded; false if failed.
765 *
766 */
767 bool RFbSetPower(
768 struct vnt_private *priv,
769 unsigned int rate,
770 u16 uCH
771 )
772 {
773 bool ret = true;
774 unsigned char byPwr = 0;
775 unsigned char byDec = 0;
776
777 if (priv->dwDiagRefCount != 0)
778 return true;
779
780 if ((uCH < 1) || (uCH > CB_MAX_CHANNEL))
781 return false;
782
783 switch (rate) {
784 case RATE_1M:
785 case RATE_2M:
786 case RATE_5M:
787 case RATE_11M:
788 if (uCH > CB_MAX_CHANNEL_24G)
789 return false;
790
791 byPwr = priv->abyCCKPwrTbl[uCH];
792 break;
793 case RATE_6M:
794 case RATE_9M:
795 case RATE_12M:
796 case RATE_18M:
797 byPwr = priv->abyOFDMPwrTbl[uCH];
798 if (priv->byRFType == RF_UW2452)
799 byDec = byPwr + 14;
800 else
801 byDec = byPwr + 10;
802
803 if (byDec >= priv->byMaxPwrLevel)
804 byDec = priv->byMaxPwrLevel-1;
805
806 byPwr = byDec;
807 break;
808 case RATE_24M:
809 case RATE_36M:
810 case RATE_48M:
811 case RATE_54M:
812 byPwr = priv->abyOFDMPwrTbl[uCH];
813 break;
814 }
815
816 if (priv->byCurPwr == byPwr)
817 return true;
818
819 ret = RFbRawSetPower(priv, byPwr, rate);
820 if (ret)
821 priv->byCurPwr = byPwr;
822
823 return ret;
824 }
825
826 /*
827 * Description: Set Tx power
828 *
829 * Parameters:
830 * In:
831 * iobase - I/O base address
832 * dwRFPowerTable - RF Tx Power Setting
833 * Out:
834 * none
835 *
836 * Return Value: true if succeeded; false if failed.
837 *
838 */
839
840 bool RFbRawSetPower(
841 struct vnt_private *priv,
842 unsigned char byPwr,
843 unsigned int rate
844 )
845 {
846 bool ret = true;
847 unsigned long dwMax7230Pwr = 0;
848
849 if (byPwr >= priv->byMaxPwrLevel)
850 return false;
851
852 switch (priv->byRFType) {
853 case RF_AIROHA:
854 ret &= IFRFbWriteEmbedded(priv, dwAL2230PowerTable[byPwr]);
855 if (rate <= RATE_11M)
856 ret &= IFRFbWriteEmbedded(priv, 0x0001B400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
857 else
858 ret &= IFRFbWriteEmbedded(priv, 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
859
860 break;
861
862 case RF_AL2230S:
863 ret &= IFRFbWriteEmbedded(priv, dwAL2230PowerTable[byPwr]);
864 if (rate <= RATE_11M) {
865 ret &= IFRFbWriteEmbedded(priv, 0x040C1400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
866 ret &= IFRFbWriteEmbedded(priv, 0x00299B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
867 } else {
868 ret &= IFRFbWriteEmbedded(priv, 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
869 ret &= IFRFbWriteEmbedded(priv, 0x00099B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW);
870 }
871
872 break;
873
874 case RF_AIROHA7230:
875 /* 0x080F1B00 for 3 wire control TxGain(D10)
876 * and 0x31 as TX Gain value
877 */
878 dwMax7230Pwr = 0x080C0B00 | ((byPwr) << 12) |
879 (BY_AL7230_REG_LEN << 3) | IFREGCTL_REGW;
880
881 ret &= IFRFbWriteEmbedded(priv, dwMax7230Pwr);
882 break;
883
884 default:
885 break;
886 }
887 return ret;
888 }
889
890 /*
891 *
892 * Routine Description:
893 * Translate RSSI to dBm
894 *
895 * Parameters:
896 * In:
897 * priv - The adapter to be translated
898 * byCurrRSSI - RSSI to be translated
899 * Out:
900 * pdwdbm - Translated dbm number
901 *
902 * Return Value: none
903 *
904 */
905 void
906 RFvRSSITodBm(
907 struct vnt_private *priv,
908 unsigned char byCurrRSSI,
909 long *pldBm
910 )
911 {
912 unsigned char byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03);
913 long b = (byCurrRSSI & 0x3F);
914 long a = 0;
915 unsigned char abyAIROHARF[4] = {0, 18, 0, 40};
916
917 switch (priv->byRFType) {
918 case RF_AIROHA:
919 case RF_AL2230S:
920 case RF_AIROHA7230:
921 a = abyAIROHARF[byIdx];
922 break;
923 default:
924 break;
925 }
926
927 *pldBm = -1 * (a + b * 2);
928 }
929
930 /* Post processing for the 11b/g and 11a.
931 * for save time on changing Reg2,3,5,7,10,12,15
932 */
933 bool RFbAL7230SelectChannelPostProcess(struct vnt_private *priv,
934 u16 byOldChannel,
935 u16 byNewChannel)
936 {
937 bool ret;
938
939 ret = true;
940
941 /* if change between 11 b/g and 11a need to update the following
942 * register
943 * Channel Index 1~14
944 */
945 if ((byOldChannel <= CB_MAX_CHANNEL_24G) && (byNewChannel > CB_MAX_CHANNEL_24G)) {
946 /* Change from 2.4G to 5G [Reg] */
947 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[2]);
948 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[3]);
949 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[5]);
950 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[7]);
951 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[10]);
952 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[12]);
953 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTableAMode[15]);
954 } else if ((byOldChannel > CB_MAX_CHANNEL_24G) && (byNewChannel <= CB_MAX_CHANNEL_24G)) {
955 /* Change from 5G to 2.4G [Reg] */
956 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[2]);
957 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[3]);
958 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[5]);
959 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[7]);
960 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[10]);
961 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[12]);
962 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[15]);
963 }
964
965 return ret;
966 }
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