2 OMAP3430 ZOOM MDK astoria interface defs(cyasmemmap.h)
3 ## ===========================
4 ## Copyright (C) 2010 Cypress Semiconductor
6 ## This program is free software; you can redistribute it and/or
7 ## modify it under the terms of the GNU General Public License
8 ## as published by the Free Software Foundation; either version 2
9 ## of the License, or (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin Street, Fifth Floor
19 ## Boston, MA 02110-1301, USA.
20 ## ===========================
22 /* include does not seem to work
23 * moving for patch submission
24 #include <mach/gpmc.h>
27 #include <linux/../../arch/arm/plat-omap/include/plat/gpmc.h>
28 #include <linux/../../arch/arm/plat-omap/include/plat/mux.h>
30 #ifndef _INCLUDED_CYASMEMMAP_H_
31 #define _INCLUDED_CYASMEMMAP_H_
33 /* defines copied from OMAP kernel branch */
35 #define OMAP2_PULL_UP (1 << 4)
36 #define OMAP2_PULL_ENA (1 << 3)
37 #define OMAP34XX_MUX_MODE0 0
38 #define OMAP34XX_MUX_MODE4 4
39 #define OMAP3_INPUT_EN (1 << 8)
40 #define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
44 * for OMAP3430 <-> astoria : ADmux mode, 8 bit data path
45 * WB Signal- OMAP3430 signal COMMENTS
46 * --------------------------- --------------------
47 * CS_L -GPMC_nCS4_GPIO_53 ZOOM I SOM board
48 * signal: up_nCS_A_EXT
49 * AD[7:0]-upD[7:0] buffered on the
53 * INT# -GPMC_nWP_GPIO_62
54 * DACK -N/C not connected
57 * R/B -GPMC_WAIT2_GPIO_64
58 * -------------------------------------------
59 * The address range for nCS1B is 0x06000000 - 0x07FF FFFF.
76 #define AST_WAKEUP 167
81 * NOTE THIS PIN IS USED AS WP for OMAP NAND
86 * as an I/O, it is actually controlled by GPMC
95 /* register and its bit fields */
96 #define GPMC_PREFETCH_CONFIG1 0x01E0
98 /*32 bytes for 16 bit pnand mode*/
99 #define PFE_THRESHOLD 31
103 * PF_ACCESSMODE - 0 - read mode, 1 - write mode
104 * PF_DMAMODE - 0 - default only intr line signal will be generated
105 * PF_SYNCHROMODE - default 0 - engin will start access as soon as
106 * ctrl re STARTENGINE is set
107 * PF_WAITPINSEL - FOR synchro mode selects WAIT pin whch edge
109 * PF_EN_ENGINE - 1- ENABLES ENGINE, but it needs to be started after
110 * that C ctrl reg bit 0
111 * PF_FIFO_THRESHOLD - FIFO threshold in number of BUS(8 or 16) words
112 * PF_WEIGHTED_PRIO - NUM of cycles granted to PFE if RND_ROBIN
113 * prioritization is enabled
114 * PF_ROUND_ROBIN - if enabled, gives priority to other CS, but
115 * reserves NUM of cycles for PFE's turn
116 * PF_ENGIN_CS_SEL - GPMC CS assotiated with PFE function
118 #define PF_ACCESSMODE (0 << 0)
119 #define PF_DMAMODE (0 << 2)
120 #define PF_SYNCHROMODE (0 << 3)
121 #define PF_WAITPINSEL (0x0 << 4)
122 #define PF_EN_ENGINE (1 << 7)
123 #define PF_FIFO_THRESHOLD (PFE_THRESHOLD << 8)
124 #define PF_WEIGHTED_PRIO (0x0 << 16)
125 #define PF_ROUND_ROBIN (0 << 23)
126 #define PF_ENGIN_CS_SEL (AST_GPMC_CS << 24)
127 #define PF_EN_OPTIM_ACC (0 << 27)
128 #define PF_CYCLEOPTIM (0x0 << 28)
130 #define GPMC_PREFETCH_CONFIG1_VAL (PF_ACCESSMODE | \
131 PF_DMAMODE | PF_SYNCHROMODE | \
132 PF_WAITPINSEL | PF_EN_ENGINE | \
133 PF_FIFO_THRESHOLD | PF_FIFO_THRESHOLD | \
134 PF_WEIGHTED_PRIO | PF_ROUND_ROBIN | \
135 PF_ENGIN_CS_SEL | PF_EN_OPTIM_ACC | \
138 /* register and its bit fields */
139 #define GPMC_PREFETCH_CONFIG2 0x01E4
142 * 14 bit field NOTE this counts is also
143 * is in number of BUS(8 or 16) words
145 #define PF_TRANSFERCOUNT (0x000)
148 /* register and its bit fields */
149 #define GPMC_PREFETCH_CONTROL 0x01EC
151 * bit fields , ONLY BIT 0 is implemented
152 * PFWE engin must be programmed with this bit = 0
154 #define PFPW_STARTENGINE (1 << 0)
156 /* register and its bit fields */
157 #define GPMC_PREFETCH_STATUS 0x01F0
160 #define PFE_FIFO_THRESHOLD (1 << 16)
163 * GPMC posted write/prefetch engine end
168 * chip select number on GPMC ( 0..7 )
170 #define AST_GPMC_CS 4
179 * Physical address above the NAND flash
180 * we use CS For mapping in OMAP3430 RAM space use 0x0600 0000
182 #define CYAS_DEV_BASE_ADDR (0x20000000)
184 #define CYAS_DEV_MAX_ADDR (0xFF)
185 #define CYAS_DEV_ADDR_RANGE (CYAS_DEV_MAX_ADDR << 1)
187 #ifdef p_s_r_a_m_INTERFACE
188 /* in CRAM or PSRAM mode OMAP A1..An wires-> Astoria, there is no A0 line */
189 #define CYAS_DEV_CALC_ADDR(cyas_addr) (cyas_addr << 1)
190 #define CYAS_DEV_CALC_EP_ADDR(ep) (ep << 1)
193 * For pNAND interface it depends on NAND emulation mode
194 * SBD/LBD etc we use NON-LNA_LBD mode, so it goes like this:
195 * forlbd <CMD><CA0,CA1,RA0,RA1,RA2> <CMD>,
196 * where CA1 address must have bits 2,3 = "11"
197 * ep is mapped into RA1 bits {4:0}
199 #define CYAS_DEV_CALC_ADDR(cyas_addr) (cyas_addr | 0x0c00)
200 #define CYAS_DEV_CALC_EP_ADDR(ep) ep
204 *OMAP3430 i/o access macros
206 #define IORD32(addr) (*(volatile u32 *)(addr))
207 #define IOWR32(addr, val) (*(volatile u32 *)(addr) = val)
209 #define IORD16(addr) (*(volatile u16 *)(addr))
210 #define IOWR16(addr, val) (*(volatile u16 *)(addr) = val)
212 #define IORD8(addr) (*(volatile u8 *)(addr))
213 #define IOWR8(addr, val) (*(volatile u8 *)(addr) = val)
216 * local defines for accessing to OMAP GPIO ***
218 #define CTLPADCONF_BASE_ADDR 0x48002000
219 #define CTLPADCONF_SIZE 0x1000
221 #define GPIO1_BASE_ADDR 0x48310000
222 #define GPIO2_BASE_ADDR 0x49050000
223 #define GPIO3_BASE_ADDR 0x49052000
224 #define GPIO4_BASE_ADDR 0x49054000
225 #define GPIO5_BASE_ADDR 0x49056000
226 #define GPIO6_BASE_ADDR 0x49058000
227 #define GPIO_SPACE_SIZE 0x1000
231 * OMAP3430 GPMC timing for pNAND interface
233 #define GPMC_BASE 0x6E000000
234 #define GPMC_REGION_SIZE 0x1000
235 #define GPMC_CONFIG_REG (0x50)
238 * bit 0 in the GPMC_CONFIG_REG
240 #define NAND_FORCE_POSTED_WRITE_B 1
243 * WAIT2STATUS, must be (1 << 10)
245 #define AS_WAIT_PIN_MASK (1 << 10)
249 * GPMC_CONFIG(reg number [1..7] [for chip sel CS[0..7])
251 #define GPMC_CFG_REG(N, CS) ((0x60 + (4*(N-1))) + (0x30*CS))
254 *gpmc nand registers for CS4
256 #define AST_GPMC_NAND_CMD (0x7c + (0x30*AST_GPMC_CS))
257 #define AST_GPMC_NAND_ADDR (0x80 + (0x30*AST_GPMC_CS))
258 #define AST_GPMC_NAND_DATA (0x84 + (0x30*AST_GPMC_CS))
260 #define GPMC_STAT_REG (0x54)
261 #define GPMC_ERR_TYPE (0x48)
264 * we get "gpmc_base" from kernel
266 #define GPMC_VMA(offset) (gpmc_base + offset)
269 * GPMC CS space VMA start address
271 #define GPMC_CS_VMA(offset) (gpmc_data_vma + offset)
274 * PAD_CFG mux space VMA
276 #define PADCFG_VMA(offset) (iomux_vma + offset)
279 * CONFIG1: by default, sngle access, async r/w RD_MULTIPLE[30]
280 * WR_MULTIPLE[28]; GPMC_FCL_DIV[1:0]
282 #define GPMC_FCLK_DIV ((0) << 0)
285 * ADDITIONAL DIVIDER FOR ALL TIMING PARAMS
287 #define TIME_GRAN_SCALE ((0) << 4)
290 * for use by gpmc_set_timings api, measured in ns, not clocks
292 #define WB_GPMC_BUSCYC_t (7 * 6)
293 #define WB_GPMC_CS_t_o_n (0)
294 #define WB_GPMC_ADV_t_o_n (0)
295 #define WB_GPMC_OE_t_o_n (0)
296 #define WB_GPMC_OE_t_o_f_f (5 * 6)
297 #define WB_GPMC_WE_t_o_n (1 * 6)
298 #define WB_GPMC_WE_t_o_f_f (5 * 6)
299 #define WB_GPMC_RDS_ADJ (2 * 6)
300 #define WB_GPMC_RD_t_a_c_c (WB_GPMC_OE_t_o_f_f + WB_GPMC_RDS_ADJ)
301 #define WB_GPMC_WR_t_a_c_c (WB_GPMC_BUSCYC_t)
309 * GPMC_CONFIG7[cs] register bit fields
310 * AS_CS_MASK - 3 bit mask for A26,A25,A24,
311 * AS_CS_BADDR - 6 BIT VALUE A29 ...A24
312 * CSVALID_B - CSVALID bit on GPMC_CONFIG7[cs] register
314 #define AS_CS_MASK (0X7 << 8)
315 #define AS_CS_BADDR 0x02
316 #define CSVALID_B (1 << 6)
319 * DEFINE OMAP34XX GPIO OFFSETS (should have been defined in kernel /arch
320 * these are offsets from the BASE_ADDRESS of the GPIO BLOCK
322 #define GPIO_REVISION 0x000
323 #define GPIO_SYSCONFIG 0x010
324 #define GPIO_SYSSTATUS1 0x014
325 #define GPIO_IRQSTATUS1 0x018
326 #define GPIO_IRQENABLE1 0x01C
327 #define GPIO_IRQSTATUS2 0x028
328 #define GPIO_CTRL 0x030
329 #define GPIO_OE 0x034
330 #define GPIO_DATA_IN 0x038
331 #define GPIO_DATA_OUT 0x03C
332 #define GPIO_LEVELDETECT0 0x040
333 #define GPIO_LEVELDETECT1 0x044
334 #define GPIO_RISINGDETECT 0x048
335 #define GPIO_FALLINGDETECT 0x04c
336 #define GPIO_CLEAR_DATAOUT 0x090
337 #define GPIO_SET_DATAOUT 0x094
347 * GPIO phy to translation VMA table
349 static io2vma_tab_t gpio_vma_tab
[6] = {
350 {"GPIO1_BASE_ADDR", GPIO1_BASE_ADDR
, 0 , GPIO_SPACE_SIZE
},
351 {"GPIO2_BASE_ADDR", GPIO2_BASE_ADDR
, 0 , GPIO_SPACE_SIZE
},
352 {"GPIO3_BASE_ADDR", GPIO3_BASE_ADDR
, 0 , GPIO_SPACE_SIZE
},
353 {"GPIO4_BASE_ADDR", GPIO4_BASE_ADDR
, 0 , GPIO_SPACE_SIZE
},
354 {"GPIO5_BASE_ADDR", GPIO5_BASE_ADDR
, 0 , GPIO_SPACE_SIZE
},
355 {"GPIO6_BASE_ADDR", GPIO6_BASE_ADDR
, 0 , GPIO_SPACE_SIZE
}
358 * name - USER signal name assigned to the pin ( for printks)
359 * mux_func - enum index NAME for the pad_cfg function
360 * pin_num - pin_number if mux_func is GPIO, if not a GPIO it is -1
361 * mux_ptr - pointer to the corresponding pad_cfg_reg
362 * (used for pad release )
363 * mux_save - preserve here original PAD_CNF value for this
364 * pin (used for pad release)
365 * dir - if GPIO: 0 - OUT , 1 - IN
366 * dir_save - save original pin direction
367 * drv - initial drive level "0" or "1"
368 * drv_save - save original pin drive level
369 * valid - 1 if successfuly configured
385 * need to ensure that enums are in sync with the
386 * omap_mux_pin_cfg table, these enums designate
387 * functions that OMAP pads can be configured to
390 B23_OMAP3430_GPIO_167
,
391 D23_OMAP3430_GPIO_126
,
393 H1_OMAP3430_GPMC_n_w_p
,
394 T8_OMAP3430_GPMC_n_c_s4
,
396 R25_OMAP3430_GPIO_156
,
397 R27_OMAP3430_GPIO_128
,
401 G3_OMAP3430_n_b_e0_CLE
,
410 * number of GPIOS we plan to grab
415 * user_pads_init() reads(and saves) from/to this table
416 * used in conjunction with omap_3430_mux_t table in .h file
417 * because the way it's done in the kernel code
418 * TODO: implement restore of the the original cfg and i/o regs
421 static user_pad_cfg_t user_pad_cfg
[] = {
423 * name,pad_func,pin_num, mux_ptr, mux_sav, dir,
424 * dir_sav, drv, drv_save, valid
426 {"AST_WAKEUP", B23_OMAP3430_GPIO_167
, 167, NULL
, 0,
427 DIR_OUT
, 0, DRV_HI
, 0, 0},
428 {"AST_RESET", D23_OMAP3430_GPIO_126
, 126, NULL
, 0,
429 DIR_OUT
, 0, DRV_HI
, 0, 0},
430 {"AST__rn_b", K8_GPMC_WAIT2
, 64, NULL
, 0,
431 DIR_INP
, 0, 0, 0, 0},
432 {"AST_INTR", H1_OMAP3430_GPIO_62
, 62, NULL
, 0,
433 DIR_INP
, 0, DRV_HI
, 0, 0},
434 {"AST_CS", T8_OMAP3430_GPMC_n_c_s4
, 55, NULL
, 0,
435 DIR_OUT
, 0, DRV_HI
, 0, 0},
436 {"LED_0", R25_OMAP3430_GPIO_156
, 156, NULL
, 0,
437 DIR_OUT
, 0, DRV_LO
, 0, 0},
438 {"LED_1", R27_OMAP3430_GPIO_128
, 128, NULL
, 0,
439 DIR_OUT
, 0, DRV_LO
, 0, 0},
440 {"AST_CLE", G3_OMAP3430_n_b_e0_CLE
, 60, NULL
, 0,
441 DIR_OUT
, 0, DRV_LO
, 0, 0},
443 * Z terminator, must always be present
444 * for sanity check, don't remove
449 #define GPIO_BANK(pin) (pin >> 5)
451 #define GPIO_REG_VMA(pin_num, offset) \
452 (gpio_vma_tab[GPIO_BANK(pin_num)].virt_addr + offset)
455 * OMAP GPIO_REG 32 BIT MASK for a bit or
456 * flag in gpio_No[0..191] apply it to a 32 bit
457 * location to set clear or check on a corresponding
460 #define GPIO_REG_MASK(pin_num) (1 << \
461 (pin_num - (GPIO_BANK(pin_num) * REG_WIDTH)))
464 * OMAP GPIO registers bitwise access macros
467 #define OMAP_GPIO_BIT(pin_num, reg) \
468 ((*((u32 *)GPIO_REG_VMA(pin_num, reg)) \
469 & GPIO_REG_MASK(pin_num)) ? 1 : 0)
471 #define RD_OMAP_GPIO_BIT(pin_num, v) OMAP_GPIO_BIT(pin_num, reg)
474 *these are superfast set/clr bitbang macro, 48ns cyc tyme
476 #define OMAP_SET_GPIO(pin_num) \
477 (*(u32 *)GPIO_REG_VMA(pin_num, GPIO_SET_DATAOUT) \
478 = GPIO_REG_MASK(pin_num))
479 #define OMAP_CLR_GPIO(pin_num) \
480 (*(u32 *)GPIO_REG_VMA(pin_num, GPIO_CLEAR_DATAOUT) \
481 = GPIO_REG_MASK(pin_num))
483 #define WR_OMAP_GPIO_BIT(pin_num, v) \
484 (v ? (*(u32 *)GPIO_REG_VMA(pin_num, \
485 GPIO_SET_DATAOUT) = GPIO_REG_MASK(pin_num)) \
486 : (*(u32 *)GPIO_REG_VMA(pin_num, \
487 GPIO_CLEAR_DATAOUT) = GPIO_REG_MASK(pin_num)))
490 * Note this pin cfg mimicks similar implementation
491 * in linux kernel, which unfortunately doesn't allow
492 * us to dynamically insert new custom GPIO mux
493 * configurations all REG definitions used in this
494 * applications. to add a new pad_cfg function, insert
495 * a new ENUM and new pin_cfg entry in omap_mux_pin_cfg[]
498 * offset - note this is a word offset since the
499 * SCM regs are 16 bit packed in one 32 bit word
500 * mux_val - just enough to describe pins used
509 * "OUTIN" is configuration when DATA reg drives the
510 * pin but the level at the pin can be sensed
512 #define PAD_AS_OUTIN (OMAP34XX_MUX_MODE4 | \
513 OMAP34XX_PIN_OUTPUT | OMAP34XX_PIN_INPUT)
515 omap_3430_mux_t omap_mux_pin_cfg
[] = {
517 * B23_OMAP3430_GPIO_167 - GPIO func to PAD 167 WB wakeup
518 * D23_OMAP3430_GPIO_126 - drive GPIO_126 ( AST RESET)
519 * H1_OMAP3430_GPIO_62 - need a pullup on this pin
520 * H1_OMAP3430_GPMC_n_w_p - GPMC NAND CTRL n_w_p out
521 * T8_OMAP3430_GPMC_n_c_s4" - T8 is controlled b_y GPMC NAND ctrl
522 * R25_OMAP3430_GPIO_156 - OMAPZOOM drive LED_0
523 * R27_OMAP3430_GPIO_128 - OMAPZOOM drive LED_1
524 * K8_OMAP3430_GPIO_64 - OMAPZOOM drive LED_2
525 * K8_GPMC_WAIT2 - GPMC WAIT2 function on PAD K8
526 * G3_OMAP3430_GPIO_60 - OMAPZOOM drive LED_3
527 * G3_OMAP3430_n_b_e0_CLE -GPMC NAND ctrl CLE signal
530 {"B23_OMAP3430_GPIO_167", 0x0130, (OMAP34XX_MUX_MODE4
)},
531 {"D23_OMAP3430_GPIO_126", 0x0132, (OMAP34XX_MUX_MODE4
)},
532 {"H1_OMAP3430_GPIO_62", 0x00CA, (OMAP34XX_MUX_MODE4
|
533 OMAP3_INPUT_EN
| OMAP34XX_PIN_INPUT_PULLUP
) },
534 {"H1_OMAP3430_GPMC_n_w_p", 0x00CA, (OMAP34XX_MUX_MODE0
)},
535 {"T8_OMAP3430_GPMC_n_c_s4", 0x00B6, (OMAP34XX_MUX_MODE0
) },
536 {"T8_OMAP3430_GPIO_55", 0x00B6, (OMAP34XX_MUX_MODE4
) },
537 {"R25_OMAP3430_GPIO_156", 0x018C, (OMAP34XX_MUX_MODE4
) },
538 {"R27_OMAP3430_GPIO_128", 0x0154, (OMAP34XX_MUX_MODE4
) },
539 {"K8_OMAP3430_GPIO_64", 0x00d0, (OMAP34XX_MUX_MODE4
) },
540 {"K8_GPMC_WAIT2", 0x00d0, (OMAP34XX_MUX_MODE0
) },
541 {"G3_OMAP3430_GPIO_60", 0x00C6, (OMAP34XX_MUX_MODE4
|
543 {"G3_OMAP3430_n_b_e0_CLE", 0x00C6, (OMAP34XX_MUX_MODE0
)},
544 {"C6_GPMC_WAIT3", 0x00d2, (OMAP34XX_MUX_MODE0
)},
545 {"C6_OMAP3430_GPIO_65", 0x00d2, (OMAP34XX_MUX_MODE4
|
547 {"J1_OMAP3430_GPIO_61", 0x00C8, (OMAP34XX_MUX_MODE4
|
548 OMAP3_INPUT_EN
| OMAP34XX_PIN_INPUT_PULLUP
)},
550 * don't remove, used for sanity check.
556 #endif /* _INCLUDED_CYASMEMMAP_H_ */