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git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - drivers/staging/wilc1000/wilc_spi.c
1 /* ////////////////////////////////////////////////////////////////////////// */
3 /* Copyright (c) Atmel Corporation. All rights reserved. */
5 /* Module Name: wilc_spi.c */
8 /* //////////////////////////////////////////////////////////////////////////// */
10 #include "wilc_wlan_if.h"
11 #include "wilc_wlan.h"
13 extern unsigned int int_clrd
;
16 * #include <linux/kernel.h>
17 * #include <linux/string.h>
21 int (*spi_tx
)(uint8_t *, uint32_t);
22 int (*spi_rx
)(uint8_t *, uint32_t);
23 int (*spi_trx
)(uint8_t *, uint8_t *, uint32_t);
24 int (*spi_max_speed
)(void);
25 wilc_debug_func dPrint
;
31 static wilc_spi_t g_spi
;
33 static int spi_read(uint32_t, uint8_t *, uint32_t);
34 static int spi_write(uint32_t, uint8_t *, uint32_t);
36 /********************************************
40 ********************************************/
42 static const uint8_t crc7_syndrome_table
[256] = {
43 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
44 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
45 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
46 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
47 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
48 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
49 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
50 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
51 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
52 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
53 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
54 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
55 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
56 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
57 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
58 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
59 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
60 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
61 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
62 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
63 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
64 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
65 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
66 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
67 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
68 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
69 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
70 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
71 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
72 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
73 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
74 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
77 static uint8_t crc7_byte(uint8_t crc
, uint8_t data
)
79 return crc7_syndrome_table
[(crc
<< 1) ^ data
];
82 static uint8_t crc7(uint8_t crc
, const uint8_t *buffer
, uint32_t len
)
85 crc
= crc7_byte(crc
, *buffer
++);
89 /********************************************
91 * Spi protocol Function
93 ********************************************/
95 #define CMD_DMA_WRITE 0xc1
96 #define CMD_DMA_READ 0xc2
97 #define CMD_INTERNAL_WRITE 0xc3
98 #define CMD_INTERNAL_READ 0xc4
99 #define CMD_TERMINATE 0xc5
100 #define CMD_REPEAT 0xc6
101 #define CMD_DMA_EXT_WRITE 0xc7
102 #define CMD_DMA_EXT_READ 0xc8
103 #define CMD_SINGLE_WRITE 0xc9
104 #define CMD_SINGLE_READ 0xca
105 #define CMD_RESET 0xcf
112 #define DATA_PKT_SZ_256 256
113 #define DATA_PKT_SZ_512 512
114 #define DATA_PKT_SZ_1K 1024
115 #define DATA_PKT_SZ_4K (4 * 1024)
116 #define DATA_PKT_SZ_8K (8 * 1024)
117 #define DATA_PKT_SZ DATA_PKT_SZ_8K
119 static int spi_cmd(uint8_t cmd
, uint32_t adr
, uint32_t data
, uint32_t sz
, uint8_t clockless
)
127 case CMD_SINGLE_READ
: /* single word (4 bytes) read */
128 bc
[1] = (uint8_t)(adr
>> 16);
129 bc
[2] = (uint8_t)(adr
>> 8);
130 bc
[3] = (uint8_t)adr
;
134 case CMD_INTERNAL_READ
: /* internal register read */
135 bc
[1] = (uint8_t)(adr
>> 8);
138 bc
[2] = (uint8_t)adr
;
143 case CMD_TERMINATE
: /* termination */
150 case CMD_REPEAT
: /* repeat */
157 case CMD_RESET
: /* reset */
164 case CMD_DMA_WRITE
: /* dma write */
165 case CMD_DMA_READ
: /* dma read */
166 bc
[1] = (uint8_t)(adr
>> 16);
167 bc
[2] = (uint8_t)(adr
>> 8);
168 bc
[3] = (uint8_t)adr
;
169 bc
[4] = (uint8_t)(sz
>> 8);
170 bc
[5] = (uint8_t)(sz
);
174 case CMD_DMA_EXT_WRITE
: /* dma extended write */
175 case CMD_DMA_EXT_READ
: /* dma extended read */
176 bc
[1] = (uint8_t)(adr
>> 16);
177 bc
[2] = (uint8_t)(adr
>> 8);
178 bc
[3] = (uint8_t)adr
;
179 bc
[4] = (uint8_t)(sz
>> 16);
180 bc
[5] = (uint8_t)(sz
>> 8);
181 bc
[6] = (uint8_t)(sz
);
185 case CMD_INTERNAL_WRITE
: /* internal register write */
186 bc
[1] = (uint8_t)(adr
>> 8);
189 bc
[2] = (uint8_t)(adr
);
190 bc
[3] = (uint8_t)(data
>> 24);
191 bc
[4] = (uint8_t)(data
>> 16);
192 bc
[5] = (uint8_t)(data
>> 8);
193 bc
[6] = (uint8_t)(data
);
197 case CMD_SINGLE_WRITE
: /* single word write */
198 bc
[1] = (uint8_t)(adr
>> 16);
199 bc
[2] = (uint8_t)(adr
>> 8);
200 bc
[3] = (uint8_t)(adr
);
201 bc
[4] = (uint8_t)(data
>> 24);
202 bc
[5] = (uint8_t)(data
>> 16);
203 bc
[6] = (uint8_t)(data
>> 8);
204 bc
[7] = (uint8_t)(data
);
215 bc
[len
- 1] = (crc7(0x7f, (const uint8_t *)&bc
[0], len
- 1)) << 1;
219 if (!g_spi
.spi_tx(bc
, len
)) {
220 PRINT_ER("[wilc spi]: Failed cmd write, bus error...\n");
228 static int spi_cmd_rsp(uint8_t cmd
)
234 * Command/Control response
236 if ((cmd
== CMD_RESET
) ||
237 (cmd
== CMD_TERMINATE
) ||
238 (cmd
== CMD_REPEAT
)) {
239 if (!g_spi
.spi_rx(&rsp
, 1)) {
245 if (!g_spi
.spi_rx(&rsp
, 1)) {
246 PRINT_ER("[wilc spi]: Failed cmd response read, bus error...\n");
252 PRINT_ER("[wilc spi]: Failed cmd response, cmd (%02x), resp (%02x)\n", cmd
, rsp
);
260 if (!g_spi
.spi_rx(&rsp
, 1)) {
261 PRINT_ER("[wilc spi]: Failed cmd state read, bus error...\n");
267 PRINT_ER("[wilc spi]: Failed cmd state response state (%02x)\n", rsp
);
276 static int spi_cmd_complete(uint8_t cmd
, uint32_t adr
, uint8_t *b
, uint32_t sz
, uint8_t clockless
)
278 uint8_t wb
[32], rb
[32];
287 case CMD_SINGLE_READ
: /* single word (4 bytes) read */
288 wb
[1] = (uint8_t)(adr
>> 16);
289 wb
[2] = (uint8_t)(adr
>> 8);
290 wb
[3] = (uint8_t)adr
;
294 case CMD_INTERNAL_READ
: /* internal register read */
295 wb
[1] = (uint8_t)(adr
>> 8);
298 wb
[2] = (uint8_t)adr
;
303 case CMD_TERMINATE
: /* termination */
310 case CMD_REPEAT
: /* repeat */
317 case CMD_RESET
: /* reset */
324 case CMD_DMA_WRITE
: /* dma write */
325 case CMD_DMA_READ
: /* dma read */
326 wb
[1] = (uint8_t)(adr
>> 16);
327 wb
[2] = (uint8_t)(adr
>> 8);
328 wb
[3] = (uint8_t)adr
;
329 wb
[4] = (uint8_t)(sz
>> 8);
330 wb
[5] = (uint8_t)(sz
);
334 case CMD_DMA_EXT_WRITE
: /* dma extended write */
335 case CMD_DMA_EXT_READ
: /* dma extended read */
336 wb
[1] = (uint8_t)(adr
>> 16);
337 wb
[2] = (uint8_t)(adr
>> 8);
338 wb
[3] = (uint8_t)adr
;
339 wb
[4] = (uint8_t)(sz
>> 16);
340 wb
[5] = (uint8_t)(sz
>> 8);
341 wb
[6] = (uint8_t)(sz
);
345 case CMD_INTERNAL_WRITE
: /* internal register write */
346 wb
[1] = (uint8_t)(adr
>> 8);
349 wb
[2] = (uint8_t)(adr
);
357 case CMD_SINGLE_WRITE
: /* single word write */
358 wb
[1] = (uint8_t)(adr
>> 16);
359 wb
[2] = (uint8_t)(adr
>> 8);
360 wb
[3] = (uint8_t)(adr
);
373 if (result
!= N_OK
) {
377 if (!g_spi
.crc_off
) {
378 wb
[len
- 1] = (crc7(0x7f, (const uint8_t *)&wb
[0], len
- 1)) << 1;
383 #define NUM_SKIP_BYTES (1)
384 #define NUM_RSP_BYTES (2)
385 #define NUM_DATA_HDR_BYTES (1)
386 #define NUM_DATA_BYTES (4)
387 #define NUM_CRC_BYTES (2)
388 #define NUM_DUMMY_BYTES (3)
389 if ((cmd
== CMD_RESET
) ||
390 (cmd
== CMD_TERMINATE
) ||
391 (cmd
== CMD_REPEAT
)) {
392 len2
= len
+ (NUM_SKIP_BYTES
+ NUM_RSP_BYTES
+ NUM_DUMMY_BYTES
);
393 } else if ((cmd
== CMD_INTERNAL_READ
) || (cmd
== CMD_SINGLE_READ
)) {
394 if (!g_spi
.crc_off
) {
395 len2
= len
+ (NUM_RSP_BYTES
+ NUM_DATA_HDR_BYTES
+ NUM_DATA_BYTES
396 + NUM_CRC_BYTES
+ NUM_DUMMY_BYTES
);
398 len2
= len
+ (NUM_RSP_BYTES
+ NUM_DATA_HDR_BYTES
+ NUM_DATA_BYTES
402 len2
= len
+ (NUM_RSP_BYTES
+ NUM_DUMMY_BYTES
);
404 #undef NUM_DUMMY_BYTES
406 if (len2
> (sizeof(wb
) / sizeof(wb
[0]))) {
407 PRINT_ER("[wilc spi]: spi buffer size too small (%d) (%zu)\n",
408 len2
, (sizeof(wb
) / sizeof(wb
[0])));
412 /* zero spi write buffers. */
413 for (wix
= len
; wix
< len2
; wix
++) {
418 if (!g_spi
.spi_trx(wb
, rb
, len2
)) {
419 PRINT_ER("[wilc spi]: Failed cmd write, bus error...\n");
425 * Command/Control response
427 if ((cmd
== CMD_RESET
) ||
428 (cmd
== CMD_TERMINATE
) ||
429 (cmd
== CMD_REPEAT
)) {
430 rix
++; /* skip 1 byte */
435 /* if(rsp == cmd) break; */
436 /* } while(&rptr[1] <= &rb[len2]); */
439 PRINT_ER("[wilc spi]: Failed cmd response, cmd (%02x)"
440 ", resp (%02x)\n", cmd
, rsp
);
450 PRINT_ER("[wilc spi]: Failed cmd state response "
451 "state (%02x)\n", rsp
);
456 if ((cmd
== CMD_INTERNAL_READ
) || (cmd
== CMD_SINGLE_READ
)
457 || (cmd
== CMD_DMA_READ
) || (cmd
== CMD_DMA_EXT_READ
)) {
459 /* uint16_t crc1, crc2; */
462 * Data Respnose header
466 /* ensure there is room in buffer later to read data and crc */
473 if (((rsp
>> 4) & 0xf) == 0xf)
478 PRINT_ER("[wilc spi]: Error, data read "
479 "response (%02x)\n", rsp
);
484 if ((cmd
== CMD_INTERNAL_READ
) || (cmd
== CMD_SINGLE_READ
)) {
488 if ((rix
+ 3) < len2
) {
494 PRINT_ER("[wilc spi]: buffer overrun when reading data.\n");
499 if (!g_spi
.crc_off
) {
503 if ((rix
+ 1) < len2
) {
507 PRINT_ER("[wilc spi]: buffer overrun when reading crc.\n");
512 } else if ((cmd
== CMD_DMA_READ
) || (cmd
== CMD_DMA_EXT_READ
)) {
515 /* some data may be read in response to dummy bytes. */
516 for (ix
= 0; (rix
< len2
) && (ix
< sz
); ) {
525 if (sz
<= (DATA_PKT_SZ
- ix
)) {
528 nbytes
= DATA_PKT_SZ
- ix
;
534 if (!g_spi
.spi_rx(&b
[ix
], nbytes
)) {
535 PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
543 if (!g_spi
.crc_off
) {
544 if (!g_spi
.spi_rx(crc
, 2)) {
545 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
556 /* if any data in left unread, then read the rest using normal DMA code.*/
560 if (sz
<= DATA_PKT_SZ
) {
563 nbytes
= DATA_PKT_SZ
;
567 * read data response only on the next DMA cycles not
568 * the first DMA since data response header is already
569 * handled above for the first DMA.
572 * Data Respnose header
576 if (!g_spi
.spi_rx(&rsp
, 1)) {
577 PRINT_ER("[wilc spi]: Failed data response read, bus error...\n");
581 if (((rsp
>> 4) & 0xf) == 0xf)
585 if (result
== N_FAIL
)
592 if (!g_spi
.spi_rx(&b
[ix
], nbytes
)) {
593 PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
601 if (!g_spi
.crc_off
) {
602 if (!g_spi
.spi_rx(crc
, 2)) {
603 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
618 static int spi_data_read(uint8_t *b
, uint32_t sz
)
620 int retry
, ix
, nbytes
;
630 if (sz
<= DATA_PKT_SZ
)
633 nbytes
= DATA_PKT_SZ
;
636 * Data Respnose header
640 if (!g_spi
.spi_rx(&rsp
, 1)) {
641 PRINT_ER("[wilc spi]: Failed data response read, bus error...\n");
645 if (((rsp
>> 4) & 0xf) == 0xf)
649 if (result
== N_FAIL
)
653 PRINT_ER("[wilc spi]: Failed data response read...(%02x)\n", rsp
);
661 if (!g_spi
.spi_rx(&b
[ix
], nbytes
)) {
662 PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
670 if (!g_spi
.crc_off
) {
671 if (!g_spi
.spi_rx(crc
, 2)) {
672 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
686 static int spi_data_write(uint8_t *b
, uint32_t sz
)
690 uint8_t cmd
, order
, crc
[2] = {0};
698 if (sz
<= DATA_PKT_SZ
)
701 nbytes
= DATA_PKT_SZ
;
708 if (sz
<= DATA_PKT_SZ
)
714 if (sz
<= DATA_PKT_SZ
)
720 if (!g_spi
.spi_tx(&cmd
, 1)) {
721 PRINT_ER("[wilc spi]: Failed data block cmd write, bus error...\n");
729 if (!g_spi
.spi_tx(&b
[ix
], nbytes
)) {
730 PRINT_ER("[wilc spi]: Failed data block write, bus error...\n");
738 if (!g_spi
.crc_off
) {
739 if (!g_spi
.spi_tx(crc
, 2)) {
740 PRINT_ER("[wilc spi]: Failed data block crc write, bus error...\n");
747 * No need to wait for response
757 /********************************************
759 * Spi Internal Read/Write Function
761 ********************************************/
763 static int spi_internal_write(uint32_t adr
, uint32_t dat
)
767 #if defined USE_OLD_SPI_SW
771 result
= spi_cmd(CMD_INTERNAL_WRITE
, adr
, dat
, 4, 0);
772 if (result
!= N_OK
) {
773 PRINT_ER("[wilc spi]: Failed internal write cmd...\n");
777 result
= spi_cmd_rsp(CMD_INTERNAL_WRITE
, 0);
778 if (result
!= N_OK
) {
779 PRINT_ER("[wilc spi]: Failed internal write cmd response...\n");
784 dat
= BYTE_SWAP(dat
);
786 result
= spi_cmd_complete(CMD_INTERNAL_WRITE
, adr
, (uint8_t *)&dat
, 4, 0);
787 if (result
!= N_OK
) {
788 PRINT_ER("[wilc spi]: Failed internal write cmd...\n");
795 static int spi_internal_read(uint32_t adr
, uint32_t *data
)
799 #if defined USE_OLD_SPI_SW
800 result
= spi_cmd(CMD_INTERNAL_READ
, adr
, 0, 4, 0);
801 if (result
!= N_OK
) {
802 PRINT_ER("[wilc spi]: Failed internal read cmd...\n");
806 result
= spi_cmd_rsp(CMD_INTERNAL_READ
, 0);
807 if (result
!= N_OK
) {
808 PRINT_ER("[wilc spi]: Failed internal read cmd response...\n");
815 result
= spi_data_read((uint8_t *)data
, 4);
816 if (result
!= N_OK
) {
817 PRINT_ER("[wilc spi]: Failed internal read data...\n");
821 result
= spi_cmd_complete(CMD_INTERNAL_READ
, adr
, (uint8_t *)data
, 4, 0);
822 if (result
!= N_OK
) {
823 PRINT_ER("[wilc spi]: Failed internal read cmd...\n");
830 *data
= BYTE_SWAP(*data
);
836 /********************************************
840 ********************************************/
842 static int spi_write_reg(uint32_t addr
, uint32_t data
)
845 uint8_t cmd
= CMD_SINGLE_WRITE
;
846 uint8_t clockless
= 0;
849 #if defined USE_OLD_SPI_SW
851 result
= spi_cmd(cmd
, addr
, data
, 4, 0);
852 if (result
!= N_OK
) {
853 PRINT_ER("[wilc spi]: Failed cmd, write reg (%08x)...\n", addr
);
857 result
= spi_cmd_rsp(cmd
, 0);
858 if (result
!= N_OK
) {
859 PRINT_ER("[wilc spi]: Failed cmd response, write reg (%08x)...\n", addr
);
867 data
= BYTE_SWAP(data
);
870 /* Clockless register*/
871 cmd
= CMD_INTERNAL_WRITE
;
875 result
= spi_cmd_complete(cmd
, addr
, (uint8_t *)&data
, 4, clockless
);
876 if (result
!= N_OK
) {
877 PRINT_ER("[wilc spi]: Failed cmd, write reg (%08x)...\n", addr
);
885 static int spi_write(uint32_t addr
, uint8_t *buf
, uint32_t size
)
888 uint8_t cmd
= CMD_DMA_EXT_WRITE
;
891 * has to be greated than 4
896 #if defined USE_OLD_SPI_SW
900 result
= spi_cmd(cmd
, addr
, 0, size
, 0);
901 if (result
!= N_OK
) {
902 PRINT_ER("[wilc spi]: Failed cmd, write block (%08x)...\n", addr
);
906 result
= spi_cmd_rsp(cmd
, 0);
907 if (result
!= N_OK
) {
908 PRINT_ER("[wilc spi ]: Failed cmd response, write block (%08x)...\n", addr
);
912 result
= spi_cmd_complete(cmd
, addr
, NULL
, size
, 0);
913 if (result
!= N_OK
) {
914 PRINT_ER("[wilc spi]: Failed cmd, write block (%08x)...\n", addr
);
922 result
= spi_data_write(buf
, size
);
923 if (result
!= N_OK
) {
924 PRINT_ER("[wilc spi]: Failed block data write...\n");
930 static int spi_read_reg(uint32_t addr
, uint32_t *data
)
933 uint8_t cmd
= CMD_SINGLE_READ
;
934 uint8_t clockless
= 0;
936 #if defined USE_OLD_SPI_SW
937 result
= spi_cmd(cmd
, addr
, 0, 4, 0);
938 if (result
!= N_OK
) {
939 PRINT_ER("[wilc spi]: Failed cmd, read reg (%08x)...\n", addr
);
942 result
= spi_cmd_rsp(cmd
, 0);
943 if (result
!= N_OK
) {
944 PRINT_ER("[wilc spi]: Failed cmd response, read reg (%08x)...\n", addr
);
948 result
= spi_data_read((uint8_t *)data
, 4);
949 if (result
!= N_OK
) {
950 PRINT_ER("[wilc spi]: Failed data read...\n");
955 /* PRINT_ER("***** read addr %d\n\n", addr); */
956 /* Clockless register*/
957 cmd
= CMD_INTERNAL_READ
;
961 result
= spi_cmd_complete(cmd
, addr
, (uint8_t *)data
, 4, clockless
);
962 if (result
!= N_OK
) {
963 PRINT_ER("[wilc spi]: Failed cmd, read reg (%08x)...\n", addr
);
970 *data
= BYTE_SWAP(*data
);
976 static int spi_read(uint32_t addr
, uint8_t *buf
, uint32_t size
)
978 uint8_t cmd
= CMD_DMA_EXT_READ
;
984 #if defined USE_OLD_SPI_SW
988 result
= spi_cmd(cmd
, addr
, 0, size
, 0);
989 if (result
!= N_OK
) {
990 PRINT_ER("[wilc spi]: Failed cmd, read block (%08x)...\n", addr
);
994 result
= spi_cmd_rsp(cmd
, 0);
995 if (result
!= N_OK
) {
996 PRINT_ER("[wilc spi]: Failed cmd response, read block (%08x)...\n", addr
);
1003 result
= spi_data_read(buf
, size
);
1004 if (result
!= N_OK
) {
1005 PRINT_ER("[wilc spi]: Failed block data read...\n");
1009 result
= spi_cmd_complete(cmd
, addr
, buf
, size
, 0);
1010 if (result
!= N_OK
) {
1011 PRINT_ER("[wilc spi]: Failed cmd, read block (%08x)...\n", addr
);
1020 /********************************************
1024 ********************************************/
1026 static int spi_clear_int(void)
1029 if (!spi_read_reg(WILC_HOST_RX_CTRL_0
, ®
)) {
1030 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_HOST_RX_CTRL_0
);
1034 spi_write_reg(WILC_HOST_RX_CTRL_0
, reg
);
1039 static int spi_deinit(void *pv
)
1047 static int spi_sync(void)
1053 * interrupt pin mux select
1055 ret
= spi_read_reg(WILC_PIN_MUX_0
, ®
);
1057 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0
);
1061 ret
= spi_write_reg(WILC_PIN_MUX_0
, reg
);
1063 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0
);
1070 ret
= spi_read_reg(WILC_INTR_ENABLE
, ®
);
1072 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE
);
1076 ret
= spi_write_reg(WILC_INTR_ENABLE
, reg
);
1078 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE
);
1085 static int spi_init(wilc_wlan_inp_t
*inp
, wilc_debug_func func
)
1094 if (!spi_read_reg(0x1000, &chipid
)) {
1095 PRINT_ER("[wilc spi]: Fail cmd read chip id...\n");
1101 memset(&g_spi
, 0, sizeof(wilc_spi_t
));
1103 g_spi
.dPrint
= func
;
1104 g_spi
.os_context
= inp
->os_context
.os_private
;
1105 if (inp
->io_func
.io_init
) {
1106 if (!inp
->io_func
.io_init(g_spi
.os_context
)) {
1107 PRINT_ER("[wilc spi]: Failed io init bus...\n");
1113 g_spi
.spi_tx
= inp
->io_func
.u
.spi
.spi_tx
;
1114 g_spi
.spi_rx
= inp
->io_func
.u
.spi
.spi_rx
;
1115 g_spi
.spi_trx
= inp
->io_func
.u
.spi
.spi_trx
;
1116 g_spi
.spi_max_speed
= inp
->io_func
.u
.spi
.spi_max_speed
;
1119 * configure protocol
1123 /* TODO: We can remove the CRC trials if there is a definite way to reset */
1124 /* the SPI to it's initial value. */
1125 if (!spi_internal_read(WILC_SPI_PROTOCOL_OFFSET
, ®
)) {
1126 /* Read failed. Try with CRC off. This might happen when module
1127 * is removed but chip isn't reset*/
1129 PRINT_ER("[wilc spi]: Failed internal read protocol with CRC on, retyring with CRC off...\n");
1130 if (!spi_internal_read(WILC_SPI_PROTOCOL_OFFSET
, ®
)) {
1131 /* Reaad failed with both CRC on and off, something went bad */
1132 PRINT_ER("[wilc spi]: Failed internal read protocol...\n");
1136 if (g_spi
.crc_off
== 0) {
1137 reg
&= ~0xc; /* disable crc checking */
1140 if (!spi_internal_write(WILC_SPI_PROTOCOL_OFFSET
, reg
)) {
1141 PRINT_ER("[wilc spi %d]: Failed internal write protocol reg...\n", __LINE__
);
1149 * make sure can read back chip id correctly
1151 if (!spi_read_reg(0x1000, &chipid
)) {
1152 PRINT_ER("[wilc spi]: Fail cmd read chip id...\n");
1155 /* PRINT_ER("[wilc spi]: chipid (%08x)\n", chipid); */
1157 g_spi
.has_thrpt_enh
= 1;
1164 static void spi_max_bus_speed(void)
1166 g_spi
.spi_max_speed();
1169 static void spi_default_bus_speed(void)
1173 static int spi_read_size(uint32_t *size
)
1176 if (g_spi
.has_thrpt_enh
) {
1177 ret
= spi_internal_read(0xe840 - WILC_SPI_REG_BASE
, size
);
1178 *size
= *size
& IRQ_DMA_WD_CNT_MASK
;
1183 ret
= spi_read_reg(WILC_VMM_TO_HOST_SIZE
, &byte_cnt
);
1185 PRINT_ER("[wilc spi]: Failed read WILC_VMM_TO_HOST_SIZE ...\n");
1188 tmp
= (byte_cnt
>> 2) & IRQ_DMA_WD_CNT_MASK
;
1200 static int spi_read_int(uint32_t *int_status
)
1203 if (g_spi
.has_thrpt_enh
) {
1204 ret
= spi_internal_read(0xe840 - WILC_SPI_REG_BASE
, int_status
);
1209 ret
= spi_read_reg(WILC_VMM_TO_HOST_SIZE
, &byte_cnt
);
1211 PRINT_ER("[wilc spi]: Failed read WILC_VMM_TO_HOST_SIZE ...\n");
1214 tmp
= (byte_cnt
>> 2) & IRQ_DMA_WD_CNT_MASK
;
1225 spi_read_reg(0x1a90, &irq_flags
);
1226 tmp
|= ((irq_flags
>> 27) << IRG_FLAGS_OFFSET
);
1228 if (g_spi
.nint
> 5) {
1229 spi_read_reg(0x1a94, &irq_flags
);
1230 tmp
|= (((irq_flags
>> 0) & 0x7) << (IRG_FLAGS_OFFSET
+ 5));
1234 uint32_t unkmown_mask
;
1236 unkmown_mask
= ~((1ul << g_spi
.nint
) - 1);
1238 if ((tmp
>> IRG_FLAGS_OFFSET
) & unkmown_mask
) {
1239 PRINT_ER("[wilc spi]: Unexpected interrupt (2): j=%d, tmp=%x, mask=%x\n", j
, tmp
, unkmown_mask
);
1244 } while (happended
);
1255 static int spi_clear_int_ext(uint32_t val
)
1259 if (g_spi
.has_thrpt_enh
) {
1260 ret
= spi_internal_write(0xe844 - WILC_SPI_REG_BASE
, val
);
1263 flags
= val
& ((1 << MAX_NUM_INT
) - 1);
1268 for (i
= 0; i
< g_spi
.nint
; i
++) {
1269 /* No matter what you write 1 or 0, it will clear interrupt. */
1271 ret
= spi_write_reg(0x10c8 + i
* 4, 1);
1277 PRINT_ER("[wilc spi]: Failed spi_write_reg, set reg %x ...\n", 0x10c8 + i
* 4);
1280 for (i
= g_spi
.nint
; i
< MAX_NUM_INT
; i
++) {
1282 PRINT_ER("[wilc spi]: Unexpected interrupt cleared %d...\n", i
);
1291 /* select VMM table 0 */
1292 if ((val
& SEL_VMM_TBL0
) == SEL_VMM_TBL0
)
1293 tbl_ctl
|= (1 << 0);
1294 /* select VMM table 1 */
1295 if ((val
& SEL_VMM_TBL1
) == SEL_VMM_TBL1
)
1296 tbl_ctl
|= (1 << 1);
1298 ret
= spi_write_reg(WILC_VMM_TBL_CTL
, tbl_ctl
);
1300 PRINT_ER("[wilc spi]: fail write reg vmm_tbl_ctl...\n");
1304 if ((val
& EN_VMM
) == EN_VMM
) {
1306 * enable vmm transfer.
1308 ret
= spi_write_reg(WILC_VMM_CORE_CTL
, 1);
1310 PRINT_ER("[wilc spi]: fail write reg vmm_core_ctl...\n");
1320 static int spi_sync_ext(int nint
/* how mant interrupts to enable. */)
1325 if (nint
> MAX_NUM_INT
) {
1326 PRINT_ER("[wilc spi]: Too many interupts (%d)...\n", nint
);
1333 * interrupt pin mux select
1335 ret
= spi_read_reg(WILC_PIN_MUX_0
, ®
);
1337 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0
);
1341 ret
= spi_write_reg(WILC_PIN_MUX_0
, reg
);
1343 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0
);
1350 ret
= spi_read_reg(WILC_INTR_ENABLE
, ®
);
1352 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE
);
1356 for (i
= 0; (i
< 5) && (nint
> 0); i
++, nint
--) {
1357 reg
|= (1 << (27 + i
));
1359 ret
= spi_write_reg(WILC_INTR_ENABLE
, reg
);
1361 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE
);
1365 ret
= spi_read_reg(WILC_INTR2_ENABLE
, ®
);
1367 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR2_ENABLE
);
1371 for (i
= 0; (i
< 3) && (nint
> 0); i
++, nint
--) {
1375 ret
= spi_read_reg(WILC_INTR2_ENABLE
, ®
);
1377 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR2_ENABLE
);
1384 /********************************************
1386 * Global spi HIF function table
1388 ********************************************/
1389 wilc_hif_func_t hif_spi
= {
1405 spi_default_bus_speed
,