drivers/staging/xgifb/vb_init.c

   1 #include <linux/delay.h>
   2 #include <linux/vmalloc.h>
   3
   4 #include "XGIfb.h"
   5 #include "vb_def.h"
   6 #include "vb_util.h"
   7 #include "vb_setmode.h"
   8 #include "vb_init.h"
   9 static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
  10         { 16, 0x45},
  11         {  8, 0x35},
  12         {  4, 0x31},
  13         {  2, 0x21} };
  14
  15 static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
  16         { 128, 0x5D},
  17         { 64, 0x59},
  18         { 64, 0x4D},
  19         { 32, 0x55},
  20         { 32, 0x49},
  21         { 32, 0x3D},
  22         { 16, 0x51},
  23         { 16, 0x45},
  24         { 16, 0x39},
  25         {  8, 0x41},
  26         {  8, 0x35},
  27         {  4, 0x31} };
  28
  29 #define XGIFB_ROM_SIZE  65536
  30
  31 static unsigned char
  32 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
  33                        struct vb_device_info *pVBInfo)
  34 {
  35         unsigned char data, temp;
  36
  37         if (HwDeviceExtension->jChipType < XG20) {
  38                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
  39                 if (data == 0)
  40                         data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
  41                                    0x02) >> 1;
  42                 return data;
  43         } else if (HwDeviceExtension->jChipType == XG27) {
  44                 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
  45                 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
  46                 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
  47                         data = 0; /* DDR */
  48                 else
  49                         data = 1; /* DDRII */
  50                 return data;
  51         } else if (HwDeviceExtension->jChipType == XG21) {
  52                 /* Independent GPIO control */
  53                 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
  54                 usleep_range(800, 1800);
  55                 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
  56                 /* GPIOF 0:DVI 1:DVO */
  57                 data = xgifb_reg_get(pVBInfo->P3d4, 0x48);
  58                 /*
  59                  * HOTPLUG_SUPPORT
  60                  * for current XG20 & XG21, GPIOH is floating, driver will
  61                  * fix DDR temporarily
  62                  */
  63                 /* DVI read GPIOH */
  64                 data &= 0x01; /* 1=DDRII, 0=DDR */
  65                 /* ~HOTPLUG_SUPPORT */
  66                 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
  67                 return data;
  68         }
  69         data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
  70
  71         if (data == 1)
  72                 data++;
  73
  74         return data;
  75 }
  76
  77 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
  78                                  struct vb_device_info *pVBInfo)
  79 {
  80         xgifb_reg_set(P3c4, 0x18, 0x01);
  81         xgifb_reg_set(P3c4, 0x19, 0x20);
  82         xgifb_reg_set(P3c4, 0x16, 0x00);
  83         xgifb_reg_set(P3c4, 0x16, 0x80);
  84
  85         usleep_range(3, 1003);
  86         xgifb_reg_set(P3c4, 0x18, 0x00);
  87         xgifb_reg_set(P3c4, 0x19, 0x20);
  88         xgifb_reg_set(P3c4, 0x16, 0x00);
  89         xgifb_reg_set(P3c4, 0x16, 0x80);
  90
  91         usleep_range(60, 1060);
  92         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
  93         xgifb_reg_set(P3c4, 0x19, 0x01);
  94         xgifb_reg_set(P3c4, 0x16, 0x03);
  95         xgifb_reg_set(P3c4, 0x16, 0x83);
  96         usleep_range(1, 1001);
  97         xgifb_reg_set(P3c4, 0x1B, 0x03);
  98         usleep_range(500, 1500);
  99         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
 100         xgifb_reg_set(P3c4, 0x19, 0x00);
 101         xgifb_reg_set(P3c4, 0x16, 0x03);
 102         xgifb_reg_set(P3c4, 0x16, 0x83);
 103         xgifb_reg_set(P3c4, 0x1B, 0x00);
 104 }
 105
 106 static void XGINew_SetMemoryClock(struct vb_device_info *pVBInfo)
 107 {
 108         xgifb_reg_set(pVBInfo->P3c4,
 109                       0x28,
 110                       pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
 111         xgifb_reg_set(pVBInfo->P3c4,
 112                       0x29,
 113                       pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
 114         xgifb_reg_set(pVBInfo->P3c4,
 115                       0x2A,
 116                       pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
 117
 118         xgifb_reg_set(pVBInfo->P3c4,
 119                       0x2E,
 120                       XGI340_ECLKData[pVBInfo->ram_type].SR2E);
 121         xgifb_reg_set(pVBInfo->P3c4,
 122                       0x2F,
 123                       XGI340_ECLKData[pVBInfo->ram_type].SR2F);
 124         xgifb_reg_set(pVBInfo->P3c4,
 125                       0x30,
 126                       XGI340_ECLKData[pVBInfo->ram_type].SR30);
 127 }
 128
 129 static void XGINew_DDRII_Bootup_XG27(
 130                         struct xgi_hw_device_info *HwDeviceExtension,
 131                         unsigned long P3c4, struct vb_device_info *pVBInfo)
 132 {
 133         unsigned long P3d4 = P3c4 + 0x10;
 134
 135         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 136         XGINew_SetMemoryClock(pVBInfo);
 137
 138         /* Set Double Frequency */
 139         xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
 140
 141         usleep_range(200, 1200);
 142
 143         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
 144         xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
 145         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 146         usleep_range(15, 1015);
 147         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 148         usleep_range(15, 1015);
 149
 150         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
 151         xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
 152         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 153         usleep_range(15, 1015);
 154         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 155         usleep_range(15, 1015);
 156
 157         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
 158         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 159         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 160         usleep_range(30, 1030);
 161         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 162         usleep_range(15, 1015);
 163
 164         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
 165         xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
 166         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 167         usleep_range(30, 1030);
 168         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 169         xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
 170
 171         xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
 172         usleep_range(60, 1060);
 173         xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
 174
 175         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
 176         xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
 177         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 178
 179         usleep_range(30, 1030);
 180         xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
 181         usleep_range(15, 1015);
 182
 183         xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
 184         xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
 185         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 186         usleep_range(30, 1030);
 187         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 188         usleep_range(15, 1015);
 189
 190         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
 191         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 192         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 193         usleep_range(30, 1030);
 194         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 195         usleep_range(15, 1015);
 196
 197         /* Set SR1B refresh control 000:close; 010:open */
 198         xgifb_reg_set(P3c4, 0x1B, 0x04);
 199         usleep_range(200, 1200);
 200 }
 201
 202 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
 203                                  unsigned long P3c4,
 204                                  struct vb_device_info *pVBInfo)
 205 {
 206         unsigned long P3d4 = P3c4 + 0x10;
 207
 208         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 209         XGINew_SetMemoryClock(pVBInfo);
 210
 211         xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
 212
 213         usleep_range(200, 1200);
 214         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
 215         xgifb_reg_set(P3c4, 0x19, 0x80);
 216         xgifb_reg_set(P3c4, 0x16, 0x05);
 217         xgifb_reg_set(P3c4, 0x16, 0x85);
 218
 219         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
 220         xgifb_reg_set(P3c4, 0x19, 0xC0);
 221         xgifb_reg_set(P3c4, 0x16, 0x05);
 222         xgifb_reg_set(P3c4, 0x16, 0x85);
 223
 224         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
 225         xgifb_reg_set(P3c4, 0x19, 0x40);
 226         xgifb_reg_set(P3c4, 0x16, 0x05);
 227         xgifb_reg_set(P3c4, 0x16, 0x85);
 228
 229         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 230         xgifb_reg_set(P3c4, 0x19, 0x02);
 231         xgifb_reg_set(P3c4, 0x16, 0x05);
 232         xgifb_reg_set(P3c4, 0x16, 0x85);
 233
 234         usleep_range(15, 1015);
 235         xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
 236         usleep_range(30, 1030);
 237         xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
 238         usleep_range(100, 1100);
 239
 240         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 241         xgifb_reg_set(P3c4, 0x19, 0x00);
 242         xgifb_reg_set(P3c4, 0x16, 0x05);
 243         xgifb_reg_set(P3c4, 0x16, 0x85);
 244
 245         usleep_range(200, 1200);
 246 }
 247
 248 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
 249                                   struct vb_device_info *pVBInfo)
 250 {
 251         xgifb_reg_set(P3c4, 0x18, 0x01);
 252         xgifb_reg_set(P3c4, 0x19, 0x40);
 253         xgifb_reg_set(P3c4, 0x16, 0x00);
 254         xgifb_reg_set(P3c4, 0x16, 0x80);
 255         usleep_range(60, 1060);
 256
 257         xgifb_reg_set(P3c4, 0x18, 0x00);
 258         xgifb_reg_set(P3c4, 0x19, 0x40);
 259         xgifb_reg_set(P3c4, 0x16, 0x00);
 260         xgifb_reg_set(P3c4, 0x16, 0x80);
 261         usleep_range(60, 1060);
 262         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
 263         xgifb_reg_set(P3c4, 0x19, 0x01);
 264         xgifb_reg_set(P3c4, 0x16, 0x03);
 265         xgifb_reg_set(P3c4, 0x16, 0x83);
 266         usleep_range(1, 1001);
 267         xgifb_reg_set(P3c4, 0x1B, 0x03);
 268         usleep_range(500, 1500);
 269         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
 270         xgifb_reg_set(P3c4, 0x19, 0x00);
 271         xgifb_reg_set(P3c4, 0x16, 0x03);
 272         xgifb_reg_set(P3c4, 0x16, 0x83);
 273         xgifb_reg_set(P3c4, 0x1B, 0x00);
 274 }
 275
 276 static void XGINew_DDR1x_DefaultRegister(
 277                 struct xgi_hw_device_info *HwDeviceExtension,
 278                 unsigned long Port, struct vb_device_info *pVBInfo)
 279 {
 280         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 281
 282         if (HwDeviceExtension->jChipType >= XG20) {
 283                 XGINew_SetMemoryClock(pVBInfo);
 284                 xgifb_reg_set(P3d4,
 285                               0x82,
 286                               pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
 287                 xgifb_reg_set(P3d4,
 288                               0x85,
 289                               pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 290                 xgifb_reg_set(P3d4,
 291                               0x86,
 292                               pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
 293
 294                 xgifb_reg_set(P3d4, 0x98, 0x01);
 295                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 296
 297                 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
 298         } else {
 299                 XGINew_SetMemoryClock(pVBInfo);
 300
 301                 switch (HwDeviceExtension->jChipType) {
 302                 case XG42:
 303                         /* CR82 */
 304                         xgifb_reg_set(P3d4,
 305                                       0x82,
 306                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 307                         /* CR85 */
 308                         xgifb_reg_set(P3d4,
 309                                       0x85,
 310                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 311                         /* CR86 */
 312                         xgifb_reg_set(P3d4,
 313                                       0x86,
 314                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 315                         break;
 316                 default:
 317                         xgifb_reg_set(P3d4, 0x82, 0x88);
 318                         xgifb_reg_set(P3d4, 0x86, 0x00);
 319                         /* Insert read command for delay */
 320                         xgifb_reg_get(P3d4, 0x86);
 321                         xgifb_reg_set(P3d4, 0x86, 0x88);
 322                         xgifb_reg_get(P3d4, 0x86);
 323                         xgifb_reg_set(P3d4,
 324                                       0x86,
 325                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 326                         xgifb_reg_set(P3d4, 0x82, 0x77);
 327                         xgifb_reg_set(P3d4, 0x85, 0x00);
 328
 329                         /* Insert read command for delay */
 330                         xgifb_reg_get(P3d4, 0x85);
 331                         xgifb_reg_set(P3d4, 0x85, 0x88);
 332
 333                         /* Insert read command for delay */
 334                         xgifb_reg_get(P3d4, 0x85);
 335                         /* CR85 */
 336                         xgifb_reg_set(P3d4,
 337                                       0x85,
 338                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 339                         /* CR82 */
 340                         xgifb_reg_set(P3d4,
 341                                       0x82,
 342                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 343                         break;
 344                 }
 345
 346                 xgifb_reg_set(P3d4, 0x97, 0x00);
 347                 xgifb_reg_set(P3d4, 0x98, 0x01);
 348                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 349                 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
 350         }
 351 }
 352
 353 static void XGINew_DDR2_DefaultRegister(
 354                 struct xgi_hw_device_info *HwDeviceExtension,
 355                 unsigned long Port, struct vb_device_info *pVBInfo)
 356 {
 357         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 358         /*
 359          * keep following setting sequence, each setting in
 360          * the same reg insert idle
 361          */
 362         xgifb_reg_set(P3d4, 0x82, 0x77);
 363         xgifb_reg_set(P3d4, 0x86, 0x00);
 364         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 365         xgifb_reg_set(P3d4, 0x86, 0x88);
 366         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 367         /* CR86 */
 368         xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
 369         xgifb_reg_set(P3d4, 0x82, 0x77);
 370         xgifb_reg_set(P3d4, 0x85, 0x00);
 371         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 372         xgifb_reg_set(P3d4, 0x85, 0x88);
 373         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 374         xgifb_reg_set(P3d4,
 375                       0x85,
 376                       pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 377         if (HwDeviceExtension->jChipType == XG27)
 378                 /* CR82 */
 379                 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
 380         else
 381                 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
 382
 383         xgifb_reg_set(P3d4, 0x98, 0x01);
 384         xgifb_reg_set(P3d4, 0x9A, 0x02);
 385         if (HwDeviceExtension->jChipType == XG27)
 386                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
 387         else
 388                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
 389 }
 390
 391 static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
 392                                u8 shift_factor, u8 mask1, u8 mask2)
 393 {
 394         u8 j;
 395
 396         for (j = 0; j < 4; j++) {
 397                 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
 398                 xgifb_reg_set(P3d4, reg, temp2);
 399                 xgifb_reg_get(P3d4, reg);
 400                 temp2 &= mask1;
 401                 temp2 += mask2;
 402         }
 403 }
 404
 405 static void XGINew_SetDRAMDefaultRegister340(
 406                 struct xgi_hw_device_info *HwDeviceExtension,
 407                 unsigned long Port, struct vb_device_info *pVBInfo)
 408 {
 409         unsigned char temp, temp1, temp2, temp3, j, k;
 410
 411         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 412
 413         xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
 414         xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
 415         xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
 416         xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
 417
 418         /* CR6B DQS fine tune delay */
 419         temp = 0xaa;
 420         XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
 421
 422         /* CR6E DQM fine tune delay */
 423         XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
 424
 425         temp3 = 0;
 426         for (k = 0; k < 4; k++) {
 427                 /* CR6E_D[1:0] select channel */
 428                 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
 429                 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
 430                 temp3 += 0x01;
 431         }
 432
 433         xgifb_reg_set(P3d4,
 434                       0x80,
 435                       pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
 436         xgifb_reg_set(P3d4,
 437                       0x81,
 438                       pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
 439
 440         temp2 = 0x80;
 441         /* CR89 terminator type select */
 442         XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
 443
 444         temp = 0;
 445         temp1 = temp & 0x03;
 446         temp2 |= temp1;
 447         xgifb_reg_set(P3d4, 0x89, temp2);
 448
 449         temp = pVBInfo->CR40[3][pVBInfo->ram_type];
 450         temp1 = temp & 0x0F;
 451         temp2 = (temp >> 4) & 0x07;
 452         temp3 = temp & 0x80;
 453         xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
 454         xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
 455         xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
 456         xgifb_reg_set(P3d4,
 457                       0x41,
 458                       pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
 459
 460         if (HwDeviceExtension->jChipType == XG27)
 461                 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
 462
 463         for (j = 0; j <= 6; j++) /* CR90 - CR96 */
 464                 xgifb_reg_set(P3d4, (0x90 + j),
 465                               pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
 466
 467         for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
 468                 xgifb_reg_set(P3d4, (0xC3 + j),
 469                               pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
 470
 471         for (j = 0; j < 2; j++) /* CR8A - CR8B */
 472                 xgifb_reg_set(P3d4, (0x8A + j),
 473                               pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
 474
 475         if (HwDeviceExtension->jChipType == XG42)
 476                 xgifb_reg_set(P3d4, 0x8C, 0x87);
 477
 478         xgifb_reg_set(P3d4,
 479                       0x59,
 480                       pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
 481
 482         xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
 483         xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
 484         xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
 485         if (pVBInfo->ram_type) {
 486                 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
 487                 if (HwDeviceExtension->jChipType == XG27)
 488                         xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
 489
 490         } else {
 491                 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
 492         }
 493         xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
 494
 495         temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 496         if (temp == 0) {
 497                 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 498         } else {
 499                 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
 500                 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 501         }
 502         xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */
 503 }
 504
 505 static unsigned short XGINew_SetDRAMSize20Reg(
 506                 unsigned short dram_size,
 507                 struct vb_device_info *pVBInfo)
 508 {
 509         unsigned short data = 0, memsize = 0;
 510         int RankSize;
 511         unsigned char ChannelNo;
 512
 513         RankSize = dram_size * pVBInfo->ram_bus / 8;
 514         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 515         data &= 0x80;
 516
 517         if (data == 0x80)
 518                 RankSize *= 2;
 519
 520         data = 0;
 521
 522         if (pVBInfo->ram_channel == 3)
 523                 ChannelNo = 4;
 524         else
 525                 ChannelNo = pVBInfo->ram_channel;
 526
 527         if (ChannelNo * RankSize <= 256) {
 528                 while ((RankSize >>= 1) > 0)
 529                         data += 0x10;
 530
 531                 memsize = data >> 4;
 532
 533                 /* Fix DRAM Sizing Error */
 534                 xgifb_reg_set(pVBInfo->P3c4,
 535                               0x14,
 536                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 537                                 (data & 0xF0));
 538                 usleep_range(15, 1015);
 539         }
 540         return memsize;
 541 }
 542
 543 static int XGINew_ReadWriteRest(unsigned short StopAddr,
 544                                 unsigned short StartAddr,
 545                                 struct vb_device_info *pVBInfo)
 546 {
 547         int i;
 548         unsigned long Position = 0;
 549         void __iomem *fbaddr = pVBInfo->FBAddr;
 550
 551         writel(Position, fbaddr + Position);
 552
 553         for (i = StartAddr; i <= StopAddr; i++) {
 554                 Position = 1 << i;
 555                 writel(Position, fbaddr + Position);
 556         }
 557
 558         /* Fix #1759 Memory Size error in Multi-Adapter. */
 559         usleep_range(500, 1500);
 560
 561         Position = 0;
 562
 563         if (readl(fbaddr + Position) != Position)
 564                 return 0;
 565
 566         for (i = StartAddr; i <= StopAddr; i++) {
 567                 Position = 1 << i;
 568                 if (readl(fbaddr + Position) != Position)
 569                         return 0;
 570         }
 571         return 1;
 572 }
 573
 574 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
 575 {
 576         unsigned char data;
 577
 578         data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 579
 580         if ((data & 0x10) == 0) {
 581                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
 582                 return (data & 0x02) >> 1;
 583         }
 584         return data & 0x01;
 585 }
 586
 587 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
 588                                 struct vb_device_info *pVBInfo)
 589 {
 590         unsigned char data;
 591
 592         switch (HwDeviceExtension->jChipType) {
 593         case XG20:
 594         case XG21:
 595                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 596                 data = data & 0x01;
 597                 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
 598
 599                 if (data == 0) { /* Single_32_16 */
 600
 601                         if ((HwDeviceExtension->ulVideoMemorySize - 1)
 602                                         > 0x1000000) {
 603                                 pVBInfo->ram_bus = 32; /* 32 bits */
 604                                 /* 22bit + 2 rank + 32bit */
 605                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 606                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 607                                 usleep_range(15, 1015);
 608
 609                                 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 610                                         return;
 611
 612                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 613                                     0x800000) {
 614                                         /* 22bit + 1 rank + 32bit */
 615                                         xgifb_reg_set(pVBInfo->P3c4,
 616                                                       0x13,
 617                                                       0x31);
 618                                         xgifb_reg_set(pVBInfo->P3c4,
 619                                                       0x14,
 620                                                       0x42);
 621                                         usleep_range(15, 1015);
 622
 623                                         if (XGINew_ReadWriteRest(23,
 624                                                                  23,
 625                                                                  pVBInfo) == 1)
 626                                                 return;
 627                                 }
 628                         }
 629
 630                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 631                             0x800000) {
 632                                 pVBInfo->ram_bus = 16; /* 16 bits */
 633                                 /* 22bit + 2 rank + 16bit */
 634                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 635                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 636                                 usleep_range(15, 1015);
 637
 638                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 639                                         return;
 640                                 xgifb_reg_set(pVBInfo->P3c4,
 641                                               0x13,
 642                                               0x31);
 643                                 usleep_range(15, 1015);
 644                         }
 645
 646                 } else { /* Dual_16_8 */
 647                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 648                             0x800000) {
 649                                 pVBInfo->ram_bus = 16; /* 16 bits */
 650                                 /* (0x31:12x8x2) 22bit + 2 rank */
 651                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 652                                 /* 0x41:16Mx16 bit */
 653                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 654                                 usleep_range(15, 1015);
 655
 656                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 657                                         return;
 658
 659                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 660                                     0x400000) {
 661                                         /* (0x31:12x8x2) 22bit + 1 rank */
 662                                         xgifb_reg_set(pVBInfo->P3c4,
 663                                                       0x13,
 664                                                       0x31);
 665                                         /* 0x31:8Mx16 bit */
 666                                         xgifb_reg_set(pVBInfo->P3c4,
 667                                                       0x14,
 668                                                       0x31);
 669                                         usleep_range(15, 1015);
 670
 671                                         if (XGINew_ReadWriteRest(22,
 672                                                                  22,
 673                                                                  pVBInfo) == 1)
 674                                                 return;
 675                                 }
 676                         }
 677
 678                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 679                             0x400000) {
 680                                 pVBInfo->ram_bus = 8; /* 8 bits */
 681                                 /* (0x31:12x8x2) 22bit + 2 rank */
 682                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 683                                 /* 0x30:8Mx8 bit */
 684                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 685                                 usleep_range(15, 1015);
 686
 687                                 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
 688                                         return;
 689
 690                                 /* (0x31:12x8x2) 22bit + 1 rank */
 691                                 xgifb_reg_set(pVBInfo->P3c4,
 692                                               0x13,
 693                                               0x31);
 694                                 usleep_range(15, 1015);
 695                         }
 696                 }
 697                 break;
 698
 699         case XG27:
 700                 pVBInfo->ram_bus = 16; /* 16 bits */
 701                 pVBInfo->ram_channel = 1; /* Single channel */
 702                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit */
 703                 break;
 704         case XG42:
 705                 /*
 706                  * XG42 SR14 D[3] Reserve
 707                  * D[2] = 1, Dual Channel
 708                  * = 0, Single Channel
 709                  *
 710                  * It's Different from Other XG40 Series.
 711                  */
 712                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
 713                         pVBInfo->ram_bus = 32; /* 32 bits */
 714                         pVBInfo->ram_channel = 2; /* 2 Channel */
 715                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 716                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
 717
 718                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 719                                 return;
 720
 721                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 722                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
 723                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 724                                 return;
 725
 726                         pVBInfo->ram_channel = 1; /* Single Channel */
 727                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 728                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
 729
 730                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 731                                 return;
 732                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 733                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 734                 } else { /* DDR */
 735                         pVBInfo->ram_bus = 64; /* 64 bits */
 736                         pVBInfo->ram_channel = 1; /* 1 channels */
 737                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 738                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 739
 740                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 741                                 return;
 742                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 743                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 744                 }
 745
 746                 break;
 747
 748         default: /* XG40 */
 749
 750                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
 751                         pVBInfo->ram_bus = 32; /* 32 bits */
 752                         pVBInfo->ram_channel = 3;
 753                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 754                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 755
 756                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 757                                 return;
 758
 759                         pVBInfo->ram_channel = 2; /* 2 channels */
 760                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 761
 762                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 763                                 return;
 764
 765                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 766                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 767
 768                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
 769                                 pVBInfo->ram_channel = 3; /* 4 channels */
 770                         } else {
 771                                 pVBInfo->ram_channel = 2; /* 2 channels */
 772                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 773                         }
 774                 } else { /* DDR */
 775                         pVBInfo->ram_bus = 64; /* 64 bits */
 776                         pVBInfo->ram_channel = 2; /* 2 channels */
 777                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 778                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
 779
 780                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
 781                                 return;
 782                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 783                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
 784                 }
 785                 break;
 786         }
 787 }
 788
 789 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
 790                                struct vb_device_info *pVBInfo)
 791 {
 792         u8 i, size;
 793         unsigned short memsize, start_addr;
 794         const unsigned short (*dram_table)[2];
 795
 796         xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
 797         xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
 798         XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
 799
 800         if (HwDeviceExtension->jChipType >= XG20) {
 801                 dram_table = XGINew_DDRDRAM_TYPE20;
 802                 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
 803                 start_addr = 5;
 804         } else {
 805                 dram_table = XGINew_DDRDRAM_TYPE340;
 806                 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
 807                 start_addr = 9;
 808         }
 809
 810         for (i = 0; i < size; i++) {
 811                 /* SetDRAMSizingType */
 812                 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
 813                 usleep_range(50, 1050); /* should delay 50 ns */
 814
 815                 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
 816
 817                 if (memsize == 0)
 818                         continue;
 819
 820                 memsize += (pVBInfo->ram_channel - 2) + 20;
 821                 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
 822                         (unsigned long)(1 << memsize))
 823                         continue;
 824
 825                 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
 826                         return 1;
 827         }
 828         return 0;
 829 }
 830
 831 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
 832                                    struct xgi_hw_device_info *HwDeviceExtension,
 833                                    struct vb_device_info *pVBInfo)
 834 {
 835         unsigned short data;
 836
 837         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
 838
 839         XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
 840
 841         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
 842         /* disable read cache */
 843         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF));
 844         XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
 845
 846         XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
 847         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
 848         /* enable read cache */
 849         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20));
 850 }
 851
 852 static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
 853 {
 854         void __iomem *rom_address;
 855         u8 *rom_copy;
 856
 857         rom_address = pci_map_rom(dev, rom_size);
 858         if (!rom_address)
 859                 return NULL;
 860
 861         rom_copy = vzalloc(XGIFB_ROM_SIZE);
 862         if (!rom_copy)
 863                 goto done;
 864
 865         *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
 866         memcpy_fromio(rom_copy, rom_address, *rom_size);
 867
 868 done:
 869         pci_unmap_rom(dev, rom_address);
 870         return rom_copy;
 871 }
 872
 873 static bool xgifb_read_vbios(struct pci_dev *pdev)
 874 {
 875         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
 876         u8 *vbios;
 877         unsigned long i;
 878         unsigned char j;
 879         struct XGI21_LVDSCapStruct *lvds;
 880         size_t vbios_size;
 881         int entry;
 882
 883         vbios = xgifb_copy_rom(pdev, &vbios_size);
 884         if (!vbios) {
 885                 dev_err(&pdev->dev, "Video BIOS not available\n");
 886                 return false;
 887         }
 888         if (vbios_size <= 0x65)
 889                 goto error;
 890         /*
 891          * The user can ignore the LVDS bit in the BIOS and force the display
 892          * type.
 893          */
 894         if (!(vbios[0x65] & 0x1) &&
 895             (!xgifb_info->display2_force ||
 896              xgifb_info->display2 != XGIFB_DISP_LCD)) {
 897                 vfree(vbios);
 898                 return false;
 899         }
 900         if (vbios_size <= 0x317)
 901                 goto error;
 902         i = vbios[0x316] | (vbios[0x317] << 8);
 903         if (vbios_size <= i - 1)
 904                 goto error;
 905         j = vbios[i - 1];
 906         if (j == 0)
 907                 goto error;
 908         if (j == 0xff)
 909                 j = 1;
 910
 911         /* Read the LVDS table index scratch register set by the BIOS. */
 912
 913         entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
 914         if (entry >= j)
 915                 entry = 0;
 916         i += entry * 25;
 917         lvds = &xgifb_info->lvds_data;
 918         if (vbios_size <= i + 24)
 919                 goto error;
 920         lvds->LVDS_Capability   = vbios[i]      | (vbios[i + 1] << 8);
 921         lvds->LVDSHT            = vbios[i + 2]  | (vbios[i + 3] << 8);
 922         lvds->LVDSVT            = vbios[i + 4]  | (vbios[i + 5] << 8);
 923         lvds->LVDSHDE           = vbios[i + 6]  | (vbios[i + 7] << 8);
 924         lvds->LVDSVDE           = vbios[i + 8]  | (vbios[i + 9] << 8);
 925         lvds->LVDSHFP           = vbios[i + 10] | (vbios[i + 11] << 8);
 926         lvds->LVDSVFP           = vbios[i + 12] | (vbios[i + 13] << 8);
 927         lvds->LVDSHSYNC         = vbios[i + 14] | (vbios[i + 15] << 8);
 928         lvds->LVDSVSYNC         = vbios[i + 16] | (vbios[i + 17] << 8);
 929         lvds->VCLKData1         = vbios[i + 18];
 930         lvds->VCLKData2         = vbios[i + 19];
 931         lvds->PSC_S1            = vbios[i + 20];
 932         lvds->PSC_S2            = vbios[i + 21];
 933         lvds->PSC_S3            = vbios[i + 22];
 934         lvds->PSC_S4            = vbios[i + 23];
 935         lvds->PSC_S5            = vbios[i + 24];
 936         vfree(vbios);
 937         return true;
 938 error:
 939         dev_err(&pdev->dev, "Video BIOS corrupted\n");
 940         vfree(vbios);
 941         return false;
 942 }
 943
 944 static void XGINew_ChkSenseStatus(struct vb_device_info *pVBInfo)
 945 {
 946         unsigned short tempbx = 0, temp, tempcx, CR3CData;
 947
 948         temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
 949
 950         if (temp & Monitor1Sense)
 951                 tempbx |= ActiveCRT1;
 952         if (temp & LCDSense)
 953                 tempbx |= ActiveLCD;
 954         if (temp & Monitor2Sense)
 955                 tempbx |= ActiveCRT2;
 956         if (temp & TVSense) {
 957                 tempbx |= ActiveTV;
 958                 if (temp & AVIDEOSense)
 959                         tempbx |= (ActiveAVideo << 8);
 960                 if (temp & SVIDEOSense)
 961                         tempbx |= (ActiveSVideo << 8);
 962                 if (temp & SCARTSense)
 963                         tempbx |= (ActiveSCART << 8);
 964                 if (temp & HiTVSense)
 965                         tempbx |= (ActiveHiTV << 8);
 966                 if (temp & YPbPrSense)
 967                         tempbx |= (ActiveYPbPr << 8);
 968         }
 969
 970         tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
 971         tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
 972
 973         if (tempbx & tempcx) {
 974                 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
 975                 if (!(CR3CData & DisplayDeviceFromCMOS))
 976                         tempcx = 0x1FF0;
 977         } else {
 978                 tempcx = 0x1FF0;
 979         }
 980
 981         tempbx &= tempcx;
 982         xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
 983         xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
 984 }
 985
 986 static void XGINew_SetModeScratch(struct vb_device_info *pVBInfo)
 987 {
 988         unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
 989
 990         temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
 991         temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
 992         temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
 993
 994         if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
 995                 if (temp & ActiveCRT2)
 996                         tempcl = SetCRT2ToRAMDAC;
 997         }
 998
 999         if (temp & ActiveLCD) {
1000                 tempcl |= SetCRT2ToLCD;
1001                 if (temp & DriverMode) {
1002                         if (temp & ActiveTV) {
1003                                 tempch = SetToLCDA | EnableDualEdge;
1004                                 temp ^= SetCRT2ToLCD;
1005
1006                                 if ((temp >> 8) & ActiveAVideo)
1007                                         tempcl |= SetCRT2ToAVIDEO;
1008                                 if ((temp >> 8) & ActiveSVideo)
1009                                         tempcl |= SetCRT2ToSVIDEO;
1010                                 if ((temp >> 8) & ActiveSCART)
1011                                         tempcl |= SetCRT2ToSCART;
1012
1013                                 if (pVBInfo->IF_DEF_HiVision == 1) {
1014                                         if ((temp >> 8) & ActiveHiTV)
1015                                                 tempcl |= SetCRT2ToHiVision;
1016                                 }
1017
1018                                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1019                                         if ((temp >> 8) & ActiveYPbPr)
1020                                                 tempch |= SetYPbPr;
1021                                 }
1022                         }
1023                 }
1024         } else {
1025                 if ((temp >> 8) & ActiveAVideo)
1026                         tempcl |= SetCRT2ToAVIDEO;
1027                 if ((temp >> 8) & ActiveSVideo)
1028                         tempcl |= SetCRT2ToSVIDEO;
1029                 if ((temp >> 8) & ActiveSCART)
1030                         tempcl |= SetCRT2ToSCART;
1031
1032                 if (pVBInfo->IF_DEF_HiVision == 1) {
1033                         if ((temp >> 8) & ActiveHiTV)
1034                                 tempcl |= SetCRT2ToHiVision;
1035                 }
1036
1037                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1038                         if ((temp >> 8) & ActiveYPbPr)
1039                                 tempch |= SetYPbPr;
1040                 }
1041         }
1042
1043         tempcl |= SetSimuScanMode;
1044         if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) ||
1045                                        (temp & ActiveTV) ||
1046                                        (temp & ActiveCRT2)))
1047                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1048         if ((temp & ActiveLCD) && (temp & ActiveTV))
1049                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1050         xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1051
1052         CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1053         CR31Data &= ~(SetNotSimuMode >> 8);
1054         if (!(temp & ActiveCRT1))
1055                 CR31Data |= (SetNotSimuMode >> 8);
1056         CR31Data &= ~(DisableCRT2Display >> 8);
1057         if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1058                 CR31Data |= (DisableCRT2Display >> 8);
1059         xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1060
1061         CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1062         CR38Data &= ~SetYPbPr;
1063         CR38Data |= tempch;
1064         xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1065 }
1066
1067 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1068                                                         *HwDeviceExtension,
1069                                       struct vb_device_info *pVBInfo)
1070 {
1071         unsigned short temp = HwDeviceExtension->ulCRT2LCDType;
1072
1073         switch (HwDeviceExtension->ulCRT2LCDType) {
1074         case LCD_640x480:
1075         case LCD_1024x600:
1076         case LCD_1152x864:
1077         case LCD_1280x960:
1078         case LCD_1152x768:
1079         case LCD_1920x1440:
1080         case LCD_2048x1536:
1081                 temp = 0; /* overwrite used ulCRT2LCDType */
1082                 break;
1083         case LCD_UNKNOWN: /* unknown lcd, do nothing */
1084                 return 0;
1085         }
1086         xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1087         return 1;
1088 }
1089
1090 static void XGINew_GetXG21Sense(struct pci_dev *pdev,
1091                                 struct vb_device_info *pVBInfo)
1092 {
1093         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1094         unsigned char Temp;
1095
1096         if (xgifb_read_vbios(pdev)) { /* For XG21 LVDS */
1097                 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1098                 /* LVDS on chip */
1099                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1100         } else {
1101                 /* Enable GPIOA/B read */
1102                 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1103                 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1104                 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1105                         XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
1106                         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1107                         /* Enable read GPIOF */
1108                         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1109                         if (xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04)
1110                                 Temp = 0xA0; /* Only DVO on chip */
1111                         else
1112                                 Temp = 0x80; /* TMDS on chip */
1113                         xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, Temp);
1114                         /* Disable read GPIOF */
1115                         xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1116                 }
1117         }
1118 }
1119
1120 static void XGINew_GetXG27Sense(struct vb_device_info *pVBInfo)
1121 {
1122         unsigned char Temp, bCR4A;
1123
1124         bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1125         /* Enable GPIOA/B/C read */
1126         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1127         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1128         xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1129
1130         if (Temp <= 0x02) {
1131                 /* LVDS setting */
1132                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1133                 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1134         } else {
1135                 /* TMDS/DVO setting */
1136                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1137         }
1138         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1139 }
1140
1141 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1142 {
1143         unsigned char CR38, CR4A, temp;
1144
1145         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1146         /* enable GPIOE read */
1147         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1148         CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1149         temp = 0;
1150         if ((CR38 & 0xE0) > 0x80) {
1151                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1152                 temp &= 0x08;
1153                 temp >>= 3;
1154         }
1155
1156         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1157
1158         return temp;
1159 }
1160
1161 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1162 {
1163         unsigned char CR4A, temp;
1164
1165         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1166         /* enable GPIOA/B/C read */
1167         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1168         temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1169         if (temp > 2)
1170                 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
1171
1172         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1173
1174         return temp;
1175 }
1176
1177 static bool xgifb_bridge_is_on(struct vb_device_info *vb_info)
1178 {
1179         u8 flag;
1180
1181         flag = xgifb_reg_get(vb_info->Part4Port, 0x00);
1182         return flag == 1 || flag == 2;
1183 }
1184
1185 unsigned char XGIInitNew(struct pci_dev *pdev)
1186 {
1187         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1188         struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1189         struct vb_device_info VBINF;
1190         struct vb_device_info *pVBInfo = &VBINF;
1191         unsigned char i, temp = 0, temp1;
1192
1193         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1194
1195         if (!pVBInfo->FBAddr) {
1196                 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
1197                 return 0;
1198         }
1199
1200         XGIRegInit(pVBInfo, xgifb_info->vga_base);
1201
1202         outb(0x67, pVBInfo->P3c2);
1203
1204         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1205
1206         /* Openkey */
1207         xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1208
1209         /* GetXG21Sense (GPIO) */
1210         if (HwDeviceExtension->jChipType == XG21)
1211                 XGINew_GetXG21Sense(pdev, pVBInfo);
1212
1213         if (HwDeviceExtension->jChipType == XG27)
1214                 XGINew_GetXG27Sense(pVBInfo);
1215
1216         /* Reset Extended register */
1217
1218         for (i = 0x06; i < 0x20; i++)
1219                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1220
1221         for (i = 0x21; i <= 0x27; i++)
1222                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1223
1224         for (i = 0x31; i <= 0x3B; i++)
1225                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1226
1227         /* Auto over driver for XG42 */
1228         if (HwDeviceExtension->jChipType == XG42)
1229                 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1230
1231         for (i = 0x79; i <= 0x7C; i++)
1232                 xgifb_reg_set(pVBInfo->P3d4, i, 0);
1233
1234         if (HwDeviceExtension->jChipType >= XG20)
1235                 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
1236
1237         /* SetDefExt1Regs begin */
1238         xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
1239         if (HwDeviceExtension->jChipType == XG27) {
1240                 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1241                 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
1242         }
1243         xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1244         xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
1245         /* Frame buffer can read/write SR20 */
1246         xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1247         /* H/W request for slow corner chip */
1248         xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1249         if (HwDeviceExtension->jChipType == XG27)
1250                 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
1251
1252         if (HwDeviceExtension->jChipType < XG20) {
1253                 u32 Temp;
1254
1255                 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1256                 for (i = 0x47; i <= 0x4C; i++)
1257                         xgifb_reg_set(pVBInfo->P3d4,
1258                                       i,
1259                                       XGI340_AGPReg[i - 0x47]);
1260
1261                 for (i = 0x70; i <= 0x71; i++)
1262                         xgifb_reg_set(pVBInfo->P3d4,
1263                                       i,
1264                                       XGI340_AGPReg[6 + i - 0x70]);
1265
1266                 for (i = 0x74; i <= 0x77; i++)
1267                         xgifb_reg_set(pVBInfo->P3d4,
1268                                       i,
1269                                       XGI340_AGPReg[8 + i - 0x74]);
1270
1271                 pci_read_config_dword(pdev, 0x50, &Temp);
1272                 Temp >>= 20;
1273                 Temp &= 0xF;
1274
1275                 if (Temp == 1)
1276                         xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1277         } /* != XG20 */
1278
1279         /* Set PCI */
1280         xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1281         xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
1282         xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
1283
1284         if (HwDeviceExtension->jChipType < XG20) {
1285                 /* Set VB */
1286                 XGI_UnLockCRT2(pVBInfo);
1287                 /* disable VideoCapture */
1288                 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1289                 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1290                 /* chk if BCLK>=100MHz */
1291                 temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1292
1293                 xgifb_reg_set(pVBInfo->Part1Port,
1294                               0x02, XGI330_CRT2Data_1_2);
1295
1296                 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1297         } /* != XG20 */
1298
1299         xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1300
1301         if ((HwDeviceExtension->jChipType == XG42) &&
1302             XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1303                 /* Not DDR */
1304                 xgifb_reg_set(pVBInfo->P3c4,
1305                               0x31,
1306                               (XGI330_SR31 & 0x3F) | 0x40);
1307                 xgifb_reg_set(pVBInfo->P3c4,
1308                               0x32,
1309                               (XGI330_SR32 & 0xFC) | 0x01);
1310         } else {
1311                 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1312                 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
1313         }
1314         xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
1315
1316         if (HwDeviceExtension->jChipType < XG20) {
1317                 if (xgifb_bridge_is_on(pVBInfo)) {
1318                         xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1319                         xgifb_reg_set(pVBInfo->Part4Port,
1320                                       0x0D, XGI330_CRT2Data_4_D);
1321                         xgifb_reg_set(pVBInfo->Part4Port,
1322                                       0x0E, XGI330_CRT2Data_4_E);
1323                         xgifb_reg_set(pVBInfo->Part4Port,
1324                                       0x10, XGI330_CRT2Data_4_10);
1325                         xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1326                         XGI_LockCRT2(pVBInfo);
1327                 }
1328         } /* != XG20 */
1329
1330         XGI_SenseCRT1(pVBInfo);
1331
1332         if (HwDeviceExtension->jChipType == XG21) {
1333                 xgifb_reg_and_or(pVBInfo->P3d4,
1334                                  0x32,
1335                                  ~Monitor1Sense,
1336                                  Monitor1Sense); /* Z9 default has CRT */
1337                 temp = GetXG21FPBits(pVBInfo);
1338                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1339         }
1340         if (HwDeviceExtension->jChipType == XG27) {
1341                 xgifb_reg_and_or(pVBInfo->P3d4,
1342                                  0x32,
1343                                  ~Monitor1Sense,
1344                                  Monitor1Sense); /* Z9 default has CRT */
1345                 temp = GetXG27FPBits(pVBInfo);
1346                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1347         }
1348
1349         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1350
1351         XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1352                                          pVBInfo->P3d4,
1353                                          pVBInfo);
1354
1355         XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1356
1357         xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1358         xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
1359
1360         XGINew_ChkSenseStatus(pVBInfo);
1361         XGINew_SetModeScratch(pVBInfo);
1362
1363         xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1364
1365         return 1;
1366 } /* end of init */