]>
git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blob - drivers/staging/xgifb/vb_init.c
1 #include <linux/delay.h>
2 #include <linux/vmalloc.h>
7 #include "vb_setmode.h"
9 static const unsigned short XGINew_DDRDRAM_TYPE340
[4][2] = {
15 static const unsigned short XGINew_DDRDRAM_TYPE20
[12][2] = {
29 #define XGIFB_ROM_SIZE 65536
32 XGINew_GetXG20DRAMType(struct xgi_hw_device_info
*HwDeviceExtension
,
33 struct vb_device_info
*pVBInfo
)
35 unsigned char data
, temp
;
37 if (HwDeviceExtension
->jChipType
< XG20
) {
38 data
= xgifb_reg_get(pVBInfo
->P3c4
, 0x39) & 0x02;
40 data
= (xgifb_reg_get(pVBInfo
->P3c4
, 0x3A) &
43 } else if (HwDeviceExtension
->jChipType
== XG27
) {
44 temp
= xgifb_reg_get(pVBInfo
->P3c4
, 0x3B);
45 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
46 if (((temp
& 0x88) == 0x80) || ((temp
& 0x88) == 0x08))
51 } else if (HwDeviceExtension
->jChipType
== XG21
) {
52 /* Independent GPIO control */
53 xgifb_reg_and(pVBInfo
->P3d4
, 0xB4, ~0x02);
54 usleep_range(800, 1800);
55 xgifb_reg_or(pVBInfo
->P3d4
, 0x4A, 0x80); /* Enable GPIOH read */
56 /* GPIOF 0:DVI 1:DVO */
57 data
= xgifb_reg_get(pVBInfo
->P3d4
, 0x48);
60 * for current XG20 & XG21, GPIOH is floating, driver will
64 data
&= 0x01; /* 1=DDRII, 0=DDR */
65 /* ~HOTPLUG_SUPPORT */
66 xgifb_reg_or(pVBInfo
->P3d4
, 0xB4, 0x02);
69 data
= xgifb_reg_get(pVBInfo
->P3d4
, 0x97) & 0x01;
77 static void XGINew_DDR1x_MRS_340(unsigned long P3c4
,
78 struct vb_device_info
*pVBInfo
)
80 xgifb_reg_set(P3c4
, 0x18, 0x01);
81 xgifb_reg_set(P3c4
, 0x19, 0x20);
82 xgifb_reg_set(P3c4
, 0x16, 0x00);
83 xgifb_reg_set(P3c4
, 0x16, 0x80);
85 usleep_range(3, 1003);
86 xgifb_reg_set(P3c4
, 0x18, 0x00);
87 xgifb_reg_set(P3c4
, 0x19, 0x20);
88 xgifb_reg_set(P3c4
, 0x16, 0x00);
89 xgifb_reg_set(P3c4
, 0x16, 0x80);
91 usleep_range(60, 1060);
92 xgifb_reg_set(P3c4
, 0x18, pVBInfo
->SR18
[pVBInfo
->ram_type
]); /* SR18 */
93 xgifb_reg_set(P3c4
, 0x19, 0x01);
94 xgifb_reg_set(P3c4
, 0x16, 0x03);
95 xgifb_reg_set(P3c4
, 0x16, 0x83);
96 usleep_range(1, 1001);
97 xgifb_reg_set(P3c4
, 0x1B, 0x03);
98 usleep_range(500, 1500);
99 xgifb_reg_set(P3c4
, 0x18, pVBInfo
->SR18
[pVBInfo
->ram_type
]); /* SR18 */
100 xgifb_reg_set(P3c4
, 0x19, 0x00);
101 xgifb_reg_set(P3c4
, 0x16, 0x03);
102 xgifb_reg_set(P3c4
, 0x16, 0x83);
103 xgifb_reg_set(P3c4
, 0x1B, 0x00);
106 static void XGINew_SetMemoryClock(struct vb_device_info
*pVBInfo
)
108 xgifb_reg_set(pVBInfo
->P3c4
,
110 pVBInfo
->MCLKData
[pVBInfo
->ram_type
].SR28
);
111 xgifb_reg_set(pVBInfo
->P3c4
,
113 pVBInfo
->MCLKData
[pVBInfo
->ram_type
].SR29
);
114 xgifb_reg_set(pVBInfo
->P3c4
,
116 pVBInfo
->MCLKData
[pVBInfo
->ram_type
].SR2A
);
118 xgifb_reg_set(pVBInfo
->P3c4
,
120 XGI340_ECLKData
[pVBInfo
->ram_type
].SR2E
);
121 xgifb_reg_set(pVBInfo
->P3c4
,
123 XGI340_ECLKData
[pVBInfo
->ram_type
].SR2F
);
124 xgifb_reg_set(pVBInfo
->P3c4
,
126 XGI340_ECLKData
[pVBInfo
->ram_type
].SR30
);
129 static void XGINew_DDRII_Bootup_XG27(
130 struct xgi_hw_device_info
*HwDeviceExtension
,
131 unsigned long P3c4
, struct vb_device_info
*pVBInfo
)
133 unsigned long P3d4
= P3c4
+ 0x10;
135 pVBInfo
->ram_type
= XGINew_GetXG20DRAMType(HwDeviceExtension
, pVBInfo
);
136 XGINew_SetMemoryClock(pVBInfo
);
138 /* Set Double Frequency */
139 xgifb_reg_set(P3d4
, 0x97, pVBInfo
->XGINew_CR97
); /* CR97 */
141 usleep_range(200, 1200);
143 xgifb_reg_set(P3c4
, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
144 xgifb_reg_set(P3c4
, 0x19, 0x80); /* Set SR19 */
145 xgifb_reg_set(P3c4
, 0x16, 0x20); /* Set SR16 */
146 usleep_range(15, 1015);
147 xgifb_reg_set(P3c4
, 0x16, 0xA0); /* Set SR16 */
148 usleep_range(15, 1015);
150 xgifb_reg_set(P3c4
, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
151 xgifb_reg_set(P3c4
, 0x19, 0xC0); /* Set SR19 */
152 xgifb_reg_set(P3c4
, 0x16, 0x20); /* Set SR16 */
153 usleep_range(15, 1015);
154 xgifb_reg_set(P3c4
, 0x16, 0xA0); /* Set SR16 */
155 usleep_range(15, 1015);
157 xgifb_reg_set(P3c4
, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
158 xgifb_reg_set(P3c4
, 0x19, 0x40); /* Set SR19 */
159 xgifb_reg_set(P3c4
, 0x16, 0x20); /* Set SR16 */
160 usleep_range(30, 1030);
161 xgifb_reg_set(P3c4
, 0x16, 0xA0); /* Set SR16 */
162 usleep_range(15, 1015);
164 xgifb_reg_set(P3c4
, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
165 xgifb_reg_set(P3c4
, 0x19, 0x0A); /* Set SR19 */
166 xgifb_reg_set(P3c4
, 0x16, 0x00); /* Set SR16 */
167 usleep_range(30, 1030);
168 xgifb_reg_set(P3c4
, 0x16, 0x00); /* Set SR16 */
169 xgifb_reg_set(P3c4
, 0x16, 0x80); /* Set SR16 */
171 xgifb_reg_set(P3c4
, 0x1B, 0x04); /* Set SR1B */
172 usleep_range(60, 1060);
173 xgifb_reg_set(P3c4
, 0x1B, 0x00); /* Set SR1B */
175 xgifb_reg_set(P3c4
, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
176 xgifb_reg_set(P3c4
, 0x19, 0x08); /* Set SR19 */
177 xgifb_reg_set(P3c4
, 0x16, 0x00); /* Set SR16 */
179 usleep_range(30, 1030);
180 xgifb_reg_set(P3c4
, 0x16, 0x83); /* Set SR16 */
181 usleep_range(15, 1015);
183 xgifb_reg_set(P3c4
, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
184 xgifb_reg_set(P3c4
, 0x19, 0x46); /* Set SR19 */
185 xgifb_reg_set(P3c4
, 0x16, 0x20); /* Set SR16 */
186 usleep_range(30, 1030);
187 xgifb_reg_set(P3c4
, 0x16, 0xA0); /* Set SR16 */
188 usleep_range(15, 1015);
190 xgifb_reg_set(P3c4
, 0x18, 0x00); /* Set SR18 */ /* EMRS */
191 xgifb_reg_set(P3c4
, 0x19, 0x40); /* Set SR19 */
192 xgifb_reg_set(P3c4
, 0x16, 0x20); /* Set SR16 */
193 usleep_range(30, 1030);
194 xgifb_reg_set(P3c4
, 0x16, 0xA0); /* Set SR16 */
195 usleep_range(15, 1015);
197 /* Set SR1B refresh control 000:close; 010:open */
198 xgifb_reg_set(P3c4
, 0x1B, 0x04);
199 usleep_range(200, 1200);
202 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info
*HwDeviceExtension
,
204 struct vb_device_info
*pVBInfo
)
206 unsigned long P3d4
= P3c4
+ 0x10;
208 pVBInfo
->ram_type
= XGINew_GetXG20DRAMType(HwDeviceExtension
, pVBInfo
);
209 XGINew_SetMemoryClock(pVBInfo
);
211 xgifb_reg_set(P3d4
, 0x97, 0x11); /* CR97 */
213 usleep_range(200, 1200);
214 xgifb_reg_set(P3c4
, 0x18, 0x00); /* EMRS2 */
215 xgifb_reg_set(P3c4
, 0x19, 0x80);
216 xgifb_reg_set(P3c4
, 0x16, 0x05);
217 xgifb_reg_set(P3c4
, 0x16, 0x85);
219 xgifb_reg_set(P3c4
, 0x18, 0x00); /* EMRS3 */
220 xgifb_reg_set(P3c4
, 0x19, 0xC0);
221 xgifb_reg_set(P3c4
, 0x16, 0x05);
222 xgifb_reg_set(P3c4
, 0x16, 0x85);
224 xgifb_reg_set(P3c4
, 0x18, 0x00); /* EMRS1 */
225 xgifb_reg_set(P3c4
, 0x19, 0x40);
226 xgifb_reg_set(P3c4
, 0x16, 0x05);
227 xgifb_reg_set(P3c4
, 0x16, 0x85);
229 xgifb_reg_set(P3c4
, 0x18, 0x42); /* MRS1 */
230 xgifb_reg_set(P3c4
, 0x19, 0x02);
231 xgifb_reg_set(P3c4
, 0x16, 0x05);
232 xgifb_reg_set(P3c4
, 0x16, 0x85);
234 usleep_range(15, 1015);
235 xgifb_reg_set(P3c4
, 0x1B, 0x04); /* SR1B */
236 usleep_range(30, 1030);
237 xgifb_reg_set(P3c4
, 0x1B, 0x00); /* SR1B */
238 usleep_range(100, 1100);
240 xgifb_reg_set(P3c4
, 0x18, 0x42); /* MRS1 */
241 xgifb_reg_set(P3c4
, 0x19, 0x00);
242 xgifb_reg_set(P3c4
, 0x16, 0x05);
243 xgifb_reg_set(P3c4
, 0x16, 0x85);
245 usleep_range(200, 1200);
248 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4
,
249 struct vb_device_info
*pVBInfo
)
251 xgifb_reg_set(P3c4
, 0x18, 0x01);
252 xgifb_reg_set(P3c4
, 0x19, 0x40);
253 xgifb_reg_set(P3c4
, 0x16, 0x00);
254 xgifb_reg_set(P3c4
, 0x16, 0x80);
255 usleep_range(60, 1060);
257 xgifb_reg_set(P3c4
, 0x18, 0x00);
258 xgifb_reg_set(P3c4
, 0x19, 0x40);
259 xgifb_reg_set(P3c4
, 0x16, 0x00);
260 xgifb_reg_set(P3c4
, 0x16, 0x80);
261 usleep_range(60, 1060);
262 xgifb_reg_set(P3c4
, 0x18, pVBInfo
->SR18
[pVBInfo
->ram_type
]); /* SR18 */
263 xgifb_reg_set(P3c4
, 0x19, 0x01);
264 xgifb_reg_set(P3c4
, 0x16, 0x03);
265 xgifb_reg_set(P3c4
, 0x16, 0x83);
266 usleep_range(1, 1001);
267 xgifb_reg_set(P3c4
, 0x1B, 0x03);
268 usleep_range(500, 1500);
269 xgifb_reg_set(P3c4
, 0x18, pVBInfo
->SR18
[pVBInfo
->ram_type
]); /* SR18 */
270 xgifb_reg_set(P3c4
, 0x19, 0x00);
271 xgifb_reg_set(P3c4
, 0x16, 0x03);
272 xgifb_reg_set(P3c4
, 0x16, 0x83);
273 xgifb_reg_set(P3c4
, 0x1B, 0x00);
276 static void XGINew_DDR1x_DefaultRegister(
277 struct xgi_hw_device_info
*HwDeviceExtension
,
278 unsigned long Port
, struct vb_device_info
*pVBInfo
)
280 unsigned long P3d4
= Port
, P3c4
= Port
- 0x10;
282 if (HwDeviceExtension
->jChipType
>= XG20
) {
283 XGINew_SetMemoryClock(pVBInfo
);
286 pVBInfo
->CR40
[11][pVBInfo
->ram_type
]); /* CR82 */
289 pVBInfo
->CR40
[12][pVBInfo
->ram_type
]); /* CR85 */
292 pVBInfo
->CR40
[13][pVBInfo
->ram_type
]); /* CR86 */
294 xgifb_reg_set(P3d4
, 0x98, 0x01);
295 xgifb_reg_set(P3d4
, 0x9A, 0x02);
297 XGINew_DDR1x_MRS_XG20(P3c4
, pVBInfo
);
299 XGINew_SetMemoryClock(pVBInfo
);
301 switch (HwDeviceExtension
->jChipType
) {
306 pVBInfo
->CR40
[11][pVBInfo
->ram_type
]);
310 pVBInfo
->CR40
[12][pVBInfo
->ram_type
]);
314 pVBInfo
->CR40
[13][pVBInfo
->ram_type
]);
317 xgifb_reg_set(P3d4
, 0x82, 0x88);
318 xgifb_reg_set(P3d4
, 0x86, 0x00);
319 /* Insert read command for delay */
320 xgifb_reg_get(P3d4
, 0x86);
321 xgifb_reg_set(P3d4
, 0x86, 0x88);
322 xgifb_reg_get(P3d4
, 0x86);
325 pVBInfo
->CR40
[13][pVBInfo
->ram_type
]);
326 xgifb_reg_set(P3d4
, 0x82, 0x77);
327 xgifb_reg_set(P3d4
, 0x85, 0x00);
329 /* Insert read command for delay */
330 xgifb_reg_get(P3d4
, 0x85);
331 xgifb_reg_set(P3d4
, 0x85, 0x88);
333 /* Insert read command for delay */
334 xgifb_reg_get(P3d4
, 0x85);
338 pVBInfo
->CR40
[12][pVBInfo
->ram_type
]);
342 pVBInfo
->CR40
[11][pVBInfo
->ram_type
]);
346 xgifb_reg_set(P3d4
, 0x97, 0x00);
347 xgifb_reg_set(P3d4
, 0x98, 0x01);
348 xgifb_reg_set(P3d4
, 0x9A, 0x02);
349 XGINew_DDR1x_MRS_340(P3c4
, pVBInfo
);
353 static void XGINew_DDR2_DefaultRegister(
354 struct xgi_hw_device_info
*HwDeviceExtension
,
355 unsigned long Port
, struct vb_device_info
*pVBInfo
)
357 unsigned long P3d4
= Port
, P3c4
= Port
- 0x10;
359 * keep following setting sequence, each setting in
360 * the same reg insert idle
362 xgifb_reg_set(P3d4
, 0x82, 0x77);
363 xgifb_reg_set(P3d4
, 0x86, 0x00);
364 xgifb_reg_get(P3d4
, 0x86); /* Insert read command for delay */
365 xgifb_reg_set(P3d4
, 0x86, 0x88);
366 xgifb_reg_get(P3d4
, 0x86); /* Insert read command for delay */
368 xgifb_reg_set(P3d4
, 0x86, pVBInfo
->CR40
[13][pVBInfo
->ram_type
]);
369 xgifb_reg_set(P3d4
, 0x82, 0x77);
370 xgifb_reg_set(P3d4
, 0x85, 0x00);
371 xgifb_reg_get(P3d4
, 0x85); /* Insert read command for delay */
372 xgifb_reg_set(P3d4
, 0x85, 0x88);
373 xgifb_reg_get(P3d4
, 0x85); /* Insert read command for delay */
376 pVBInfo
->CR40
[12][pVBInfo
->ram_type
]); /* CR85 */
377 if (HwDeviceExtension
->jChipType
== XG27
)
379 xgifb_reg_set(P3d4
, 0x82, pVBInfo
->CR40
[11][pVBInfo
->ram_type
]);
381 xgifb_reg_set(P3d4
, 0x82, 0xA8); /* CR82 */
383 xgifb_reg_set(P3d4
, 0x98, 0x01);
384 xgifb_reg_set(P3d4
, 0x9A, 0x02);
385 if (HwDeviceExtension
->jChipType
== XG27
)
386 XGINew_DDRII_Bootup_XG27(HwDeviceExtension
, P3c4
, pVBInfo
);
388 XGINew_DDR2_MRS_XG20(HwDeviceExtension
, P3c4
, pVBInfo
);
391 static void XGI_SetDRAM_Helper(unsigned long P3d4
, u8 seed
, u8 temp2
, u8 reg
,
392 u8 shift_factor
, u8 mask1
, u8 mask2
)
396 for (j
= 0; j
< 4; j
++) {
397 temp2
|= (((seed
>> (2 * j
)) & 0x03) << shift_factor
);
398 xgifb_reg_set(P3d4
, reg
, temp2
);
399 xgifb_reg_get(P3d4
, reg
);
405 static void XGINew_SetDRAMDefaultRegister340(
406 struct xgi_hw_device_info
*HwDeviceExtension
,
407 unsigned long Port
, struct vb_device_info
*pVBInfo
)
409 unsigned char temp
, temp1
, temp2
, temp3
, j
, k
;
411 unsigned long P3d4
= Port
, P3c4
= Port
- 0x10;
413 xgifb_reg_set(P3d4
, 0x6D, pVBInfo
->CR40
[8][pVBInfo
->ram_type
]);
414 xgifb_reg_set(P3d4
, 0x68, pVBInfo
->CR40
[5][pVBInfo
->ram_type
]);
415 xgifb_reg_set(P3d4
, 0x69, pVBInfo
->CR40
[6][pVBInfo
->ram_type
]);
416 xgifb_reg_set(P3d4
, 0x6A, pVBInfo
->CR40
[7][pVBInfo
->ram_type
]);
418 /* CR6B DQS fine tune delay */
420 XGI_SetDRAM_Helper(P3d4
, temp
, 0, 0x6B, 2, 0xF0, 0x10);
422 /* CR6E DQM fine tune delay */
423 XGI_SetDRAM_Helper(P3d4
, 0, 0, 0x6E, 2, 0xF0, 0x10);
426 for (k
= 0; k
< 4; k
++) {
427 /* CR6E_D[1:0] select channel */
428 xgifb_reg_and_or(P3d4
, 0x6E, 0xFC, temp3
);
429 XGI_SetDRAM_Helper(P3d4
, 0, 0, 0x6F, 0, 0xF8, 0x08);
435 pVBInfo
->CR40
[9][pVBInfo
->ram_type
]); /* CR80 */
438 pVBInfo
->CR40
[10][pVBInfo
->ram_type
]); /* CR81 */
441 /* CR89 terminator type select */
442 XGI_SetDRAM_Helper(P3d4
, 0, temp2
, 0x89, 0, 0xF0, 0x10);
447 xgifb_reg_set(P3d4
, 0x89, temp2
);
449 temp
= pVBInfo
->CR40
[3][pVBInfo
->ram_type
];
451 temp2
= (temp
>> 4) & 0x07;
453 xgifb_reg_set(P3d4
, 0x45, temp1
); /* CR45 */
454 xgifb_reg_set(P3d4
, 0x99, temp2
); /* CR99 */
455 xgifb_reg_or(P3d4
, 0x40, temp3
); /* CR40_D[7] */
458 pVBInfo
->CR40
[0][pVBInfo
->ram_type
]); /* CR41 */
460 if (HwDeviceExtension
->jChipType
== XG27
)
461 xgifb_reg_set(P3d4
, 0x8F, XG27_CR8F
); /* CR8F */
463 for (j
= 0; j
<= 6; j
++) /* CR90 - CR96 */
464 xgifb_reg_set(P3d4
, (0x90 + j
),
465 pVBInfo
->CR40
[14 + j
][pVBInfo
->ram_type
]);
467 for (j
= 0; j
<= 2; j
++) /* CRC3 - CRC5 */
468 xgifb_reg_set(P3d4
, (0xC3 + j
),
469 pVBInfo
->CR40
[21 + j
][pVBInfo
->ram_type
]);
471 for (j
= 0; j
< 2; j
++) /* CR8A - CR8B */
472 xgifb_reg_set(P3d4
, (0x8A + j
),
473 pVBInfo
->CR40
[1 + j
][pVBInfo
->ram_type
]);
475 if (HwDeviceExtension
->jChipType
== XG42
)
476 xgifb_reg_set(P3d4
, 0x8C, 0x87);
480 pVBInfo
->CR40
[4][pVBInfo
->ram_type
]); /* CR59 */
482 xgifb_reg_set(P3d4
, 0x83, 0x09); /* CR83 */
483 xgifb_reg_set(P3d4
, 0x87, 0x00); /* CR87 */
484 xgifb_reg_set(P3d4
, 0xCF, XG40_CRCF
); /* CRCF */
485 if (pVBInfo
->ram_type
) {
486 xgifb_reg_set(P3c4
, 0x17, 0x80); /* SR17 DDRII */
487 if (HwDeviceExtension
->jChipType
== XG27
)
488 xgifb_reg_set(P3c4
, 0x17, 0x02); /* SR17 DDRII */
491 xgifb_reg_set(P3c4
, 0x17, 0x00); /* SR17 DDR */
493 xgifb_reg_set(P3c4
, 0x1A, 0x87); /* SR1A */
495 temp
= XGINew_GetXG20DRAMType(HwDeviceExtension
, pVBInfo
);
497 XGINew_DDR1x_DefaultRegister(HwDeviceExtension
, P3d4
, pVBInfo
);
499 xgifb_reg_set(P3d4
, 0xB0, 0x80); /* DDRII Dual frequency mode */
500 XGINew_DDR2_DefaultRegister(HwDeviceExtension
, P3d4
, pVBInfo
);
502 xgifb_reg_set(P3c4
, 0x1B, 0x03); /* SR1B */
505 static unsigned short XGINew_SetDRAMSize20Reg(
506 unsigned short dram_size
,
507 struct vb_device_info
*pVBInfo
)
509 unsigned short data
= 0, memsize
= 0;
511 unsigned char ChannelNo
;
513 RankSize
= dram_size
* pVBInfo
->ram_bus
/ 8;
514 data
= xgifb_reg_get(pVBInfo
->P3c4
, 0x13);
522 if (pVBInfo
->ram_channel
== 3)
525 ChannelNo
= pVBInfo
->ram_channel
;
527 if (ChannelNo
* RankSize
<= 256) {
528 while ((RankSize
>>= 1) > 0)
533 /* Fix DRAM Sizing Error */
534 xgifb_reg_set(pVBInfo
->P3c4
,
536 (xgifb_reg_get(pVBInfo
->P3c4
, 0x14) & 0x0F) |
538 usleep_range(15, 1015);
543 static int XGINew_ReadWriteRest(unsigned short StopAddr
,
544 unsigned short StartAddr
,
545 struct vb_device_info
*pVBInfo
)
548 unsigned long Position
= 0;
549 void __iomem
*fbaddr
= pVBInfo
->FBAddr
;
551 writel(Position
, fbaddr
+ Position
);
553 for (i
= StartAddr
; i
<= StopAddr
; i
++) {
555 writel(Position
, fbaddr
+ Position
);
558 /* Fix #1759 Memory Size error in Multi-Adapter. */
559 usleep_range(500, 1500);
563 if (readl(fbaddr
+ Position
) != Position
)
566 for (i
= StartAddr
; i
<= StopAddr
; i
++) {
568 if (readl(fbaddr
+ Position
) != Position
)
574 static unsigned char XGINew_CheckFrequence(struct vb_device_info
*pVBInfo
)
578 data
= xgifb_reg_get(pVBInfo
->P3d4
, 0x97);
580 if ((data
& 0x10) == 0) {
581 data
= xgifb_reg_get(pVBInfo
->P3c4
, 0x39);
582 return (data
& 0x02) >> 1;
587 static void XGINew_CheckChannel(struct xgi_hw_device_info
*HwDeviceExtension
,
588 struct vb_device_info
*pVBInfo
)
592 switch (HwDeviceExtension
->jChipType
) {
595 data
= xgifb_reg_get(pVBInfo
->P3d4
, 0x97);
597 pVBInfo
->ram_channel
= 1; /* XG20 "JUST" one channel */
599 if (data
== 0) { /* Single_32_16 */
601 if ((HwDeviceExtension
->ulVideoMemorySize
- 1)
603 pVBInfo
->ram_bus
= 32; /* 32 bits */
604 /* 22bit + 2 rank + 32bit */
605 xgifb_reg_set(pVBInfo
->P3c4
, 0x13, 0xB1);
606 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x52);
607 usleep_range(15, 1015);
609 if (XGINew_ReadWriteRest(24, 23, pVBInfo
) == 1)
612 if ((HwDeviceExtension
->ulVideoMemorySize
- 1) >
614 /* 22bit + 1 rank + 32bit */
615 xgifb_reg_set(pVBInfo
->P3c4
,
618 xgifb_reg_set(pVBInfo
->P3c4
,
621 usleep_range(15, 1015);
623 if (XGINew_ReadWriteRest(23,
630 if ((HwDeviceExtension
->ulVideoMemorySize
- 1) >
632 pVBInfo
->ram_bus
= 16; /* 16 bits */
633 /* 22bit + 2 rank + 16bit */
634 xgifb_reg_set(pVBInfo
->P3c4
, 0x13, 0xB1);
635 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x41);
636 usleep_range(15, 1015);
638 if (XGINew_ReadWriteRest(23, 22, pVBInfo
) == 1)
640 xgifb_reg_set(pVBInfo
->P3c4
,
643 usleep_range(15, 1015);
646 } else { /* Dual_16_8 */
647 if ((HwDeviceExtension
->ulVideoMemorySize
- 1) >
649 pVBInfo
->ram_bus
= 16; /* 16 bits */
650 /* (0x31:12x8x2) 22bit + 2 rank */
651 xgifb_reg_set(pVBInfo
->P3c4
, 0x13, 0xB1);
652 /* 0x41:16Mx16 bit */
653 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x41);
654 usleep_range(15, 1015);
656 if (XGINew_ReadWriteRest(23, 22, pVBInfo
) == 1)
659 if ((HwDeviceExtension
->ulVideoMemorySize
- 1) >
661 /* (0x31:12x8x2) 22bit + 1 rank */
662 xgifb_reg_set(pVBInfo
->P3c4
,
666 xgifb_reg_set(pVBInfo
->P3c4
,
669 usleep_range(15, 1015);
671 if (XGINew_ReadWriteRest(22,
678 if ((HwDeviceExtension
->ulVideoMemorySize
- 1) >
680 pVBInfo
->ram_bus
= 8; /* 8 bits */
681 /* (0x31:12x8x2) 22bit + 2 rank */
682 xgifb_reg_set(pVBInfo
->P3c4
, 0x13, 0xB1);
684 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x30);
685 usleep_range(15, 1015);
687 if (XGINew_ReadWriteRest(22, 21, pVBInfo
) == 1)
690 /* (0x31:12x8x2) 22bit + 1 rank */
691 xgifb_reg_set(pVBInfo
->P3c4
,
694 usleep_range(15, 1015);
700 pVBInfo
->ram_bus
= 16; /* 16 bits */
701 pVBInfo
->ram_channel
= 1; /* Single channel */
702 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x51); /* 32Mx16 bit */
706 * XG42 SR14 D[3] Reserve
707 * D[2] = 1, Dual Channel
708 * = 0, Single Channel
710 * It's Different from Other XG40 Series.
712 if (XGINew_CheckFrequence(pVBInfo
) == 1) { /* DDRII, DDR2x */
713 pVBInfo
->ram_bus
= 32; /* 32 bits */
714 pVBInfo
->ram_channel
= 2; /* 2 Channel */
715 xgifb_reg_set(pVBInfo
->P3c4
, 0x13, 0xA1);
716 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x44);
718 if (XGINew_ReadWriteRest(24, 23, pVBInfo
) == 1)
721 xgifb_reg_set(pVBInfo
->P3c4
, 0x13, 0x21);
722 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x34);
723 if (XGINew_ReadWriteRest(23, 22, pVBInfo
) == 1)
726 pVBInfo
->ram_channel
= 1; /* Single Channel */
727 xgifb_reg_set(pVBInfo
->P3c4
, 0x13, 0xA1);
728 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x40);
730 if (XGINew_ReadWriteRest(23, 22, pVBInfo
) == 1)
732 xgifb_reg_set(pVBInfo
->P3c4
, 0x13, 0x21);
733 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x30);
735 pVBInfo
->ram_bus
= 64; /* 64 bits */
736 pVBInfo
->ram_channel
= 1; /* 1 channels */
737 xgifb_reg_set(pVBInfo
->P3c4
, 0x13, 0xA1);
738 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x52);
740 if (XGINew_ReadWriteRest(24, 23, pVBInfo
) == 1)
742 xgifb_reg_set(pVBInfo
->P3c4
, 0x13, 0x21);
743 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x42);
750 if (XGINew_CheckFrequence(pVBInfo
) == 1) { /* DDRII */
751 pVBInfo
->ram_bus
= 32; /* 32 bits */
752 pVBInfo
->ram_channel
= 3;
753 xgifb_reg_set(pVBInfo
->P3c4
, 0x13, 0xA1);
754 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x4C);
756 if (XGINew_ReadWriteRest(25, 23, pVBInfo
) == 1)
759 pVBInfo
->ram_channel
= 2; /* 2 channels */
760 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x48);
762 if (XGINew_ReadWriteRest(24, 23, pVBInfo
) == 1)
765 xgifb_reg_set(pVBInfo
->P3c4
, 0x13, 0x21);
766 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x3C);
768 if (XGINew_ReadWriteRest(24, 23, pVBInfo
) == 1) {
769 pVBInfo
->ram_channel
= 3; /* 4 channels */
771 pVBInfo
->ram_channel
= 2; /* 2 channels */
772 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x38);
775 pVBInfo
->ram_bus
= 64; /* 64 bits */
776 pVBInfo
->ram_channel
= 2; /* 2 channels */
777 xgifb_reg_set(pVBInfo
->P3c4
, 0x13, 0xA1);
778 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x5A);
780 if (XGINew_ReadWriteRest(25, 24, pVBInfo
) == 1)
782 xgifb_reg_set(pVBInfo
->P3c4
, 0x13, 0x21);
783 xgifb_reg_set(pVBInfo
->P3c4
, 0x14, 0x4A);
789 static int XGINew_DDRSizing340(struct xgi_hw_device_info
*HwDeviceExtension
,
790 struct vb_device_info
*pVBInfo
)
793 unsigned short memsize
, start_addr
;
794 const unsigned short (*dram_table
)[2];
796 xgifb_reg_set(pVBInfo
->P3c4
, 0x15, 0x00); /* noninterleaving */
797 xgifb_reg_set(pVBInfo
->P3c4
, 0x1C, 0x00); /* nontiling */
798 XGINew_CheckChannel(HwDeviceExtension
, pVBInfo
);
800 if (HwDeviceExtension
->jChipType
>= XG20
) {
801 dram_table
= XGINew_DDRDRAM_TYPE20
;
802 size
= ARRAY_SIZE(XGINew_DDRDRAM_TYPE20
);
805 dram_table
= XGINew_DDRDRAM_TYPE340
;
806 size
= ARRAY_SIZE(XGINew_DDRDRAM_TYPE340
);
810 for (i
= 0; i
< size
; i
++) {
811 /* SetDRAMSizingType */
812 xgifb_reg_and_or(pVBInfo
->P3c4
, 0x13, 0x80, dram_table
[i
][1]);
813 usleep_range(50, 1050); /* should delay 50 ns */
815 memsize
= XGINew_SetDRAMSize20Reg(dram_table
[i
][0], pVBInfo
);
820 memsize
+= (pVBInfo
->ram_channel
- 2) + 20;
821 if ((HwDeviceExtension
->ulVideoMemorySize
- 1) <
822 (unsigned long)(1 << memsize
))
825 if (XGINew_ReadWriteRest(memsize
, start_addr
, pVBInfo
) == 1)
831 static void XGINew_SetDRAMSize_340(struct xgifb_video_info
*xgifb_info
,
832 struct xgi_hw_device_info
*HwDeviceExtension
,
833 struct vb_device_info
*pVBInfo
)
837 pVBInfo
->FBAddr
= HwDeviceExtension
->pjVideoMemoryAddress
;
839 XGISetModeNew(xgifb_info
, HwDeviceExtension
, 0x2e);
841 data
= xgifb_reg_get(pVBInfo
->P3c4
, 0x21);
842 /* disable read cache */
843 xgifb_reg_set(pVBInfo
->P3c4
, 0x21, (unsigned short)(data
& 0xDF));
844 XGI_DisplayOff(xgifb_info
, HwDeviceExtension
, pVBInfo
);
846 XGINew_DDRSizing340(HwDeviceExtension
, pVBInfo
);
847 data
= xgifb_reg_get(pVBInfo
->P3c4
, 0x21);
848 /* enable read cache */
849 xgifb_reg_set(pVBInfo
->P3c4
, 0x21, (unsigned short)(data
| 0x20));
852 static u8
*xgifb_copy_rom(struct pci_dev
*dev
, size_t *rom_size
)
854 void __iomem
*rom_address
;
857 rom_address
= pci_map_rom(dev
, rom_size
);
861 rom_copy
= vzalloc(XGIFB_ROM_SIZE
);
865 *rom_size
= min_t(size_t, *rom_size
, XGIFB_ROM_SIZE
);
866 memcpy_fromio(rom_copy
, rom_address
, *rom_size
);
869 pci_unmap_rom(dev
, rom_address
);
873 static bool xgifb_read_vbios(struct pci_dev
*pdev
)
875 struct xgifb_video_info
*xgifb_info
= pci_get_drvdata(pdev
);
879 struct XGI21_LVDSCapStruct
*lvds
;
883 vbios
= xgifb_copy_rom(pdev
, &vbios_size
);
885 dev_err(&pdev
->dev
, "Video BIOS not available\n");
888 if (vbios_size
<= 0x65)
891 * The user can ignore the LVDS bit in the BIOS and force the display
894 if (!(vbios
[0x65] & 0x1) &&
895 (!xgifb_info
->display2_force
||
896 xgifb_info
->display2
!= XGIFB_DISP_LCD
)) {
900 if (vbios_size
<= 0x317)
902 i
= vbios
[0x316] | (vbios
[0x317] << 8);
903 if (vbios_size
<= i
- 1)
911 /* Read the LVDS table index scratch register set by the BIOS. */
913 entry
= xgifb_reg_get(xgifb_info
->dev_info
.P3d4
, 0x36);
917 lvds
= &xgifb_info
->lvds_data
;
918 if (vbios_size
<= i
+ 24)
920 lvds
->LVDS_Capability
= vbios
[i
] | (vbios
[i
+ 1] << 8);
921 lvds
->LVDSHT
= vbios
[i
+ 2] | (vbios
[i
+ 3] << 8);
922 lvds
->LVDSVT
= vbios
[i
+ 4] | (vbios
[i
+ 5] << 8);
923 lvds
->LVDSHDE
= vbios
[i
+ 6] | (vbios
[i
+ 7] << 8);
924 lvds
->LVDSVDE
= vbios
[i
+ 8] | (vbios
[i
+ 9] << 8);
925 lvds
->LVDSHFP
= vbios
[i
+ 10] | (vbios
[i
+ 11] << 8);
926 lvds
->LVDSVFP
= vbios
[i
+ 12] | (vbios
[i
+ 13] << 8);
927 lvds
->LVDSHSYNC
= vbios
[i
+ 14] | (vbios
[i
+ 15] << 8);
928 lvds
->LVDSVSYNC
= vbios
[i
+ 16] | (vbios
[i
+ 17] << 8);
929 lvds
->VCLKData1
= vbios
[i
+ 18];
930 lvds
->VCLKData2
= vbios
[i
+ 19];
931 lvds
->PSC_S1
= vbios
[i
+ 20];
932 lvds
->PSC_S2
= vbios
[i
+ 21];
933 lvds
->PSC_S3
= vbios
[i
+ 22];
934 lvds
->PSC_S4
= vbios
[i
+ 23];
935 lvds
->PSC_S5
= vbios
[i
+ 24];
939 dev_err(&pdev
->dev
, "Video BIOS corrupted\n");
944 static void XGINew_ChkSenseStatus(struct vb_device_info
*pVBInfo
)
946 unsigned short tempbx
= 0, temp
, tempcx
, CR3CData
;
948 temp
= xgifb_reg_get(pVBInfo
->P3d4
, 0x32);
950 if (temp
& Monitor1Sense
)
951 tempbx
|= ActiveCRT1
;
954 if (temp
& Monitor2Sense
)
955 tempbx
|= ActiveCRT2
;
956 if (temp
& TVSense
) {
958 if (temp
& AVIDEOSense
)
959 tempbx
|= (ActiveAVideo
<< 8);
960 if (temp
& SVIDEOSense
)
961 tempbx
|= (ActiveSVideo
<< 8);
962 if (temp
& SCARTSense
)
963 tempbx
|= (ActiveSCART
<< 8);
964 if (temp
& HiTVSense
)
965 tempbx
|= (ActiveHiTV
<< 8);
966 if (temp
& YPbPrSense
)
967 tempbx
|= (ActiveYPbPr
<< 8);
970 tempcx
= xgifb_reg_get(pVBInfo
->P3d4
, 0x3d);
971 tempcx
|= (xgifb_reg_get(pVBInfo
->P3d4
, 0x3e) << 8);
973 if (tempbx
& tempcx
) {
974 CR3CData
= xgifb_reg_get(pVBInfo
->P3d4
, 0x3c);
975 if (!(CR3CData
& DisplayDeviceFromCMOS
))
982 xgifb_reg_set(pVBInfo
->P3d4
, 0x3d, (tempbx
& 0x00FF));
983 xgifb_reg_set(pVBInfo
->P3d4
, 0x3e, ((tempbx
& 0xFF00) >> 8));
986 static void XGINew_SetModeScratch(struct vb_device_info
*pVBInfo
)
988 unsigned short temp
, tempcl
= 0, tempch
= 0, CR31Data
, CR38Data
;
990 temp
= xgifb_reg_get(pVBInfo
->P3d4
, 0x3d);
991 temp
|= xgifb_reg_get(pVBInfo
->P3d4
, 0x3e) << 8;
992 temp
|= (xgifb_reg_get(pVBInfo
->P3d4
, 0x31) & (DriverMode
>> 8)) << 8;
994 if (pVBInfo
->IF_DEF_CRT2Monitor
== 1) {
995 if (temp
& ActiveCRT2
)
996 tempcl
= SetCRT2ToRAMDAC
;
999 if (temp
& ActiveLCD
) {
1000 tempcl
|= SetCRT2ToLCD
;
1001 if (temp
& DriverMode
) {
1002 if (temp
& ActiveTV
) {
1003 tempch
= SetToLCDA
| EnableDualEdge
;
1004 temp
^= SetCRT2ToLCD
;
1006 if ((temp
>> 8) & ActiveAVideo
)
1007 tempcl
|= SetCRT2ToAVIDEO
;
1008 if ((temp
>> 8) & ActiveSVideo
)
1009 tempcl
|= SetCRT2ToSVIDEO
;
1010 if ((temp
>> 8) & ActiveSCART
)
1011 tempcl
|= SetCRT2ToSCART
;
1013 if (pVBInfo
->IF_DEF_HiVision
== 1) {
1014 if ((temp
>> 8) & ActiveHiTV
)
1015 tempcl
|= SetCRT2ToHiVision
;
1018 if (pVBInfo
->IF_DEF_YPbPr
== 1) {
1019 if ((temp
>> 8) & ActiveYPbPr
)
1025 if ((temp
>> 8) & ActiveAVideo
)
1026 tempcl
|= SetCRT2ToAVIDEO
;
1027 if ((temp
>> 8) & ActiveSVideo
)
1028 tempcl
|= SetCRT2ToSVIDEO
;
1029 if ((temp
>> 8) & ActiveSCART
)
1030 tempcl
|= SetCRT2ToSCART
;
1032 if (pVBInfo
->IF_DEF_HiVision
== 1) {
1033 if ((temp
>> 8) & ActiveHiTV
)
1034 tempcl
|= SetCRT2ToHiVision
;
1037 if (pVBInfo
->IF_DEF_YPbPr
== 1) {
1038 if ((temp
>> 8) & ActiveYPbPr
)
1043 tempcl
|= SetSimuScanMode
;
1044 if ((!(temp
& ActiveCRT1
)) && ((temp
& ActiveLCD
) ||
1045 (temp
& ActiveTV
) ||
1046 (temp
& ActiveCRT2
)))
1047 tempcl
^= (SetSimuScanMode
| SwitchCRT2
);
1048 if ((temp
& ActiveLCD
) && (temp
& ActiveTV
))
1049 tempcl
^= (SetSimuScanMode
| SwitchCRT2
);
1050 xgifb_reg_set(pVBInfo
->P3d4
, 0x30, tempcl
);
1052 CR31Data
= xgifb_reg_get(pVBInfo
->P3d4
, 0x31);
1053 CR31Data
&= ~(SetNotSimuMode
>> 8);
1054 if (!(temp
& ActiveCRT1
))
1055 CR31Data
|= (SetNotSimuMode
>> 8);
1056 CR31Data
&= ~(DisableCRT2Display
>> 8);
1057 if (!((temp
& ActiveLCD
) || (temp
& ActiveTV
) || (temp
& ActiveCRT2
)))
1058 CR31Data
|= (DisableCRT2Display
>> 8);
1059 xgifb_reg_set(pVBInfo
->P3d4
, 0x31, CR31Data
);
1061 CR38Data
= xgifb_reg_get(pVBInfo
->P3d4
, 0x38);
1062 CR38Data
&= ~SetYPbPr
;
1064 xgifb_reg_set(pVBInfo
->P3d4
, 0x38, CR38Data
);
1067 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1069 struct vb_device_info
*pVBInfo
)
1071 unsigned short temp
= HwDeviceExtension
->ulCRT2LCDType
;
1073 switch (HwDeviceExtension
->ulCRT2LCDType
) {
1081 temp
= 0; /* overwrite used ulCRT2LCDType */
1083 case LCD_UNKNOWN
: /* unknown lcd, do nothing */
1086 xgifb_reg_and_or(pVBInfo
->P3d4
, 0x36, 0xF0, temp
);
1090 static void XGINew_GetXG21Sense(struct pci_dev
*pdev
,
1091 struct vb_device_info
*pVBInfo
)
1093 struct xgifb_video_info
*xgifb_info
= pci_get_drvdata(pdev
);
1096 if (xgifb_read_vbios(pdev
)) { /* For XG21 LVDS */
1097 xgifb_reg_or(pVBInfo
->P3d4
, 0x32, LCDSense
);
1099 xgifb_reg_and_or(pVBInfo
->P3d4
, 0x38, ~0xE0, 0xC0);
1101 /* Enable GPIOA/B read */
1102 xgifb_reg_and_or(pVBInfo
->P3d4
, 0x4A, ~0x03, 0x03);
1103 Temp
= xgifb_reg_get(pVBInfo
->P3d4
, 0x48) & 0xC0;
1104 if (Temp
== 0xC0) { /* DVI & DVO GPIOA/B pull high */
1105 XGINew_SenseLCD(&xgifb_info
->hw_info
, pVBInfo
);
1106 xgifb_reg_or(pVBInfo
->P3d4
, 0x32, LCDSense
);
1107 /* Enable read GPIOF */
1108 xgifb_reg_and_or(pVBInfo
->P3d4
, 0x4A, ~0x20, 0x20);
1109 if (xgifb_reg_get(pVBInfo
->P3d4
, 0x48) & 0x04)
1110 Temp
= 0xA0; /* Only DVO on chip */
1112 Temp
= 0x80; /* TMDS on chip */
1113 xgifb_reg_and_or(pVBInfo
->P3d4
, 0x38, ~0xE0, Temp
);
1114 /* Disable read GPIOF */
1115 xgifb_reg_and(pVBInfo
->P3d4
, 0x4A, ~0x20);
1120 static void XGINew_GetXG27Sense(struct vb_device_info
*pVBInfo
)
1122 unsigned char Temp
, bCR4A
;
1124 bCR4A
= xgifb_reg_get(pVBInfo
->P3d4
, 0x4A);
1125 /* Enable GPIOA/B/C read */
1126 xgifb_reg_and_or(pVBInfo
->P3d4
, 0x4A, ~0x07, 0x07);
1127 Temp
= xgifb_reg_get(pVBInfo
->P3d4
, 0x48) & 0x07;
1128 xgifb_reg_set(pVBInfo
->P3d4
, 0x4A, bCR4A
);
1132 xgifb_reg_and_or(pVBInfo
->P3d4
, 0x38, ~0xE0, 0xC0);
1133 xgifb_reg_set(pVBInfo
->P3d4
, 0x30, 0x21);
1135 /* TMDS/DVO setting */
1136 xgifb_reg_and_or(pVBInfo
->P3d4
, 0x38, ~0xE0, 0xA0);
1138 xgifb_reg_or(pVBInfo
->P3d4
, 0x32, LCDSense
);
1141 static unsigned char GetXG21FPBits(struct vb_device_info
*pVBInfo
)
1143 unsigned char CR38
, CR4A
, temp
;
1145 CR4A
= xgifb_reg_get(pVBInfo
->P3d4
, 0x4A);
1146 /* enable GPIOE read */
1147 xgifb_reg_and_or(pVBInfo
->P3d4
, 0x4A, ~0x10, 0x10);
1148 CR38
= xgifb_reg_get(pVBInfo
->P3d4
, 0x38);
1150 if ((CR38
& 0xE0) > 0x80) {
1151 temp
= xgifb_reg_get(pVBInfo
->P3d4
, 0x48);
1156 xgifb_reg_set(pVBInfo
->P3d4
, 0x4A, CR4A
);
1161 static unsigned char GetXG27FPBits(struct vb_device_info
*pVBInfo
)
1163 unsigned char CR4A
, temp
;
1165 CR4A
= xgifb_reg_get(pVBInfo
->P3d4
, 0x4A);
1166 /* enable GPIOA/B/C read */
1167 xgifb_reg_and_or(pVBInfo
->P3d4
, 0x4A, ~0x03, 0x03);
1168 temp
= xgifb_reg_get(pVBInfo
->P3d4
, 0x48);
1170 temp
= ((temp
& 0x04) >> 1) | ((~temp
) & 0x01);
1172 xgifb_reg_set(pVBInfo
->P3d4
, 0x4A, CR4A
);
1177 static bool xgifb_bridge_is_on(struct vb_device_info
*vb_info
)
1181 flag
= xgifb_reg_get(vb_info
->Part4Port
, 0x00);
1182 return flag
== 1 || flag
== 2;
1185 unsigned char XGIInitNew(struct pci_dev
*pdev
)
1187 struct xgifb_video_info
*xgifb_info
= pci_get_drvdata(pdev
);
1188 struct xgi_hw_device_info
*HwDeviceExtension
= &xgifb_info
->hw_info
;
1189 struct vb_device_info VBINF
;
1190 struct vb_device_info
*pVBInfo
= &VBINF
;
1191 unsigned char i
, temp
= 0, temp1
;
1193 pVBInfo
->FBAddr
= HwDeviceExtension
->pjVideoMemoryAddress
;
1195 if (!pVBInfo
->FBAddr
) {
1196 dev_dbg(&pdev
->dev
, "pVBInfo->FBAddr == 0\n");
1200 XGIRegInit(pVBInfo
, xgifb_info
->vga_base
);
1202 outb(0x67, pVBInfo
->P3c2
);
1204 InitTo330Pointer(HwDeviceExtension
->jChipType
, pVBInfo
);
1207 xgifb_reg_set(pVBInfo
->P3c4
, 0x05, 0x86);
1209 /* GetXG21Sense (GPIO) */
1210 if (HwDeviceExtension
->jChipType
== XG21
)
1211 XGINew_GetXG21Sense(pdev
, pVBInfo
);
1213 if (HwDeviceExtension
->jChipType
== XG27
)
1214 XGINew_GetXG27Sense(pVBInfo
);
1216 /* Reset Extended register */
1218 for (i
= 0x06; i
< 0x20; i
++)
1219 xgifb_reg_set(pVBInfo
->P3c4
, i
, 0);
1221 for (i
= 0x21; i
<= 0x27; i
++)
1222 xgifb_reg_set(pVBInfo
->P3c4
, i
, 0);
1224 for (i
= 0x31; i
<= 0x3B; i
++)
1225 xgifb_reg_set(pVBInfo
->P3c4
, i
, 0);
1227 /* Auto over driver for XG42 */
1228 if (HwDeviceExtension
->jChipType
== XG42
)
1229 xgifb_reg_set(pVBInfo
->P3c4
, 0x3B, 0xC0);
1231 for (i
= 0x79; i
<= 0x7C; i
++)
1232 xgifb_reg_set(pVBInfo
->P3d4
, i
, 0);
1234 if (HwDeviceExtension
->jChipType
>= XG20
)
1235 xgifb_reg_set(pVBInfo
->P3d4
, 0x97, pVBInfo
->XGINew_CR97
);
1237 /* SetDefExt1Regs begin */
1238 xgifb_reg_set(pVBInfo
->P3c4
, 0x07, XGI330_SR07
);
1239 if (HwDeviceExtension
->jChipType
== XG27
) {
1240 xgifb_reg_set(pVBInfo
->P3c4
, 0x40, XG27_SR40
);
1241 xgifb_reg_set(pVBInfo
->P3c4
, 0x41, XG27_SR41
);
1243 xgifb_reg_set(pVBInfo
->P3c4
, 0x11, 0x0F);
1244 xgifb_reg_set(pVBInfo
->P3c4
, 0x1F, XGI330_SR1F
);
1245 /* Frame buffer can read/write SR20 */
1246 xgifb_reg_set(pVBInfo
->P3c4
, 0x20, 0xA0);
1247 /* H/W request for slow corner chip */
1248 xgifb_reg_set(pVBInfo
->P3c4
, 0x36, 0x70);
1249 if (HwDeviceExtension
->jChipType
== XG27
)
1250 xgifb_reg_set(pVBInfo
->P3c4
, 0x36, XG27_SR36
);
1252 if (HwDeviceExtension
->jChipType
< XG20
) {
1255 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1256 for (i
= 0x47; i
<= 0x4C; i
++)
1257 xgifb_reg_set(pVBInfo
->P3d4
,
1259 XGI340_AGPReg
[i
- 0x47]);
1261 for (i
= 0x70; i
<= 0x71; i
++)
1262 xgifb_reg_set(pVBInfo
->P3d4
,
1264 XGI340_AGPReg
[6 + i
- 0x70]);
1266 for (i
= 0x74; i
<= 0x77; i
++)
1267 xgifb_reg_set(pVBInfo
->P3d4
,
1269 XGI340_AGPReg
[8 + i
- 0x74]);
1271 pci_read_config_dword(pdev
, 0x50, &Temp
);
1276 xgifb_reg_set(pVBInfo
->P3d4
, 0x48, 0x20); /* CR48 */
1280 xgifb_reg_set(pVBInfo
->P3c4
, 0x23, XGI330_SR23
);
1281 xgifb_reg_set(pVBInfo
->P3c4
, 0x24, XGI330_SR24
);
1282 xgifb_reg_set(pVBInfo
->P3c4
, 0x25, 0);
1284 if (HwDeviceExtension
->jChipType
< XG20
) {
1286 XGI_UnLockCRT2(pVBInfo
);
1287 /* disable VideoCapture */
1288 xgifb_reg_and_or(pVBInfo
->Part0Port
, 0x3F, 0xEF, 0x00);
1289 xgifb_reg_set(pVBInfo
->Part1Port
, 0x00, 0x00);
1290 /* chk if BCLK>=100MHz */
1291 temp1
= xgifb_reg_get(pVBInfo
->P3d4
, 0x7B);
1293 xgifb_reg_set(pVBInfo
->Part1Port
,
1294 0x02, XGI330_CRT2Data_1_2
);
1296 xgifb_reg_set(pVBInfo
->Part1Port
, 0x2E, 0x08); /* use VB */
1299 xgifb_reg_set(pVBInfo
->P3c4
, 0x27, 0x1F);
1301 if ((HwDeviceExtension
->jChipType
== XG42
) &&
1302 XGINew_GetXG20DRAMType(HwDeviceExtension
, pVBInfo
) != 0) {
1304 xgifb_reg_set(pVBInfo
->P3c4
,
1306 (XGI330_SR31
& 0x3F) | 0x40);
1307 xgifb_reg_set(pVBInfo
->P3c4
,
1309 (XGI330_SR32
& 0xFC) | 0x01);
1311 xgifb_reg_set(pVBInfo
->P3c4
, 0x31, XGI330_SR31
);
1312 xgifb_reg_set(pVBInfo
->P3c4
, 0x32, XGI330_SR32
);
1314 xgifb_reg_set(pVBInfo
->P3c4
, 0x33, XGI330_SR33
);
1316 if (HwDeviceExtension
->jChipType
< XG20
) {
1317 if (xgifb_bridge_is_on(pVBInfo
)) {
1318 xgifb_reg_set(pVBInfo
->Part2Port
, 0x00, 0x1C);
1319 xgifb_reg_set(pVBInfo
->Part4Port
,
1320 0x0D, XGI330_CRT2Data_4_D
);
1321 xgifb_reg_set(pVBInfo
->Part4Port
,
1322 0x0E, XGI330_CRT2Data_4_E
);
1323 xgifb_reg_set(pVBInfo
->Part4Port
,
1324 0x10, XGI330_CRT2Data_4_10
);
1325 xgifb_reg_set(pVBInfo
->Part4Port
, 0x0F, 0x3F);
1326 XGI_LockCRT2(pVBInfo
);
1330 XGI_SenseCRT1(pVBInfo
);
1332 if (HwDeviceExtension
->jChipType
== XG21
) {
1333 xgifb_reg_and_or(pVBInfo
->P3d4
,
1336 Monitor1Sense
); /* Z9 default has CRT */
1337 temp
= GetXG21FPBits(pVBInfo
);
1338 xgifb_reg_and_or(pVBInfo
->P3d4
, 0x37, ~0x01, temp
);
1340 if (HwDeviceExtension
->jChipType
== XG27
) {
1341 xgifb_reg_and_or(pVBInfo
->P3d4
,
1344 Monitor1Sense
); /* Z9 default has CRT */
1345 temp
= GetXG27FPBits(pVBInfo
);
1346 xgifb_reg_and_or(pVBInfo
->P3d4
, 0x37, ~0x03, temp
);
1349 pVBInfo
->ram_type
= XGINew_GetXG20DRAMType(HwDeviceExtension
, pVBInfo
);
1351 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension
,
1355 XGINew_SetDRAMSize_340(xgifb_info
, HwDeviceExtension
, pVBInfo
);
1357 xgifb_reg_set(pVBInfo
->P3c4
, 0x22, 0xfa);
1358 xgifb_reg_set(pVBInfo
->P3c4
, 0x21, 0xa3);
1360 XGINew_ChkSenseStatus(pVBInfo
);
1361 XGINew_SetModeScratch(pVBInfo
);
1363 xgifb_reg_set(pVBInfo
->P3d4
, 0x8c, 0x87);