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staging: xillybus: fix some coding style errors
[mirror_ubuntu-bionic-kernel.git] / drivers / staging / xillybus / xillybus_core.c
1 /*
2 * linux/drivers/misc/xillybus_core.c
3 *
4 * Copyright 2011 Xillybus Ltd, http://xillybus.com
5 *
6 * Driver for the Xillybus FPGA/host framework.
7 *
8 * This driver interfaces with a special IP core in an FPGA, setting up
9 * a pipe between a hardware FIFO in the programmable logic and a device
10 * file in the host. The number of such pipes and their attributes are
11 * set up on the logic. This driver detects these automatically and
12 * creates the device files accordingly.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the smems of the GNU General Public License as published by
16 * the Free Software Foundation; version 2 of the License.
17 */
18
19 #include <linux/list.h>
20 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/io.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/fs.h>
27 #include <linux/cdev.h>
28 #include <linux/spinlock.h>
29 #include <linux/mutex.h>
30 #include <linux/crc32.h>
31 #include <linux/poll.h>
32 #include <linux/delay.h>
33 #include <linux/slab.h>
34 #include <linux/workqueue.h>
35 #include "xillybus.h"
36
37 MODULE_DESCRIPTION("Xillybus core functions");
38 MODULE_AUTHOR("Eli Billauer, Xillybus Ltd.");
39 MODULE_VERSION("1.07");
40 MODULE_ALIAS("xillybus_core");
41 MODULE_LICENSE("GPL v2");
42
43 /* General timeout is 100 ms, rx timeout is 10 ms */
44 #define XILLY_RX_TIMEOUT (10*HZ/1000)
45 #define XILLY_TIMEOUT (100*HZ/1000)
46
47 #define fpga_msg_ctrl_reg 0x0008
48 #define fpga_dma_control_reg 0x0020
49 #define fpga_dma_bufno_reg 0x0024
50 #define fpga_dma_bufaddr_lowaddr_reg 0x0028
51 #define fpga_dma_bufaddr_highaddr_reg 0x002c
52 #define fpga_buf_ctrl_reg 0x0030
53 #define fpga_buf_offset_reg 0x0034
54 #define fpga_endian_reg 0x0040
55
56 #define XILLYMSG_OPCODE_RELEASEBUF 1
57 #define XILLYMSG_OPCODE_QUIESCEACK 2
58 #define XILLYMSG_OPCODE_FIFOEOF 3
59 #define XILLYMSG_OPCODE_FATAL_ERROR 4
60 #define XILLYMSG_OPCODE_NONEMPTY 5
61
62 static const char xillyname[] = "xillybus";
63
64 static struct class *xillybus_class;
65
66 /*
67 * ep_list_lock is the last lock to be taken; No other lock requests are
68 * allowed while holding it. It merely protects list_of_endpoints, and not
69 * the endpoints listed in it.
70 */
71
72 static LIST_HEAD(list_of_endpoints);
73 static struct mutex ep_list_lock;
74 static struct workqueue_struct *xillybus_wq;
75
76 /*
77 * Locking scheme: Mutexes protect invocations of character device methods.
78 * If both locks are taken, wr_mutex is taken first, rd_mutex second.
79 *
80 * wr_spinlock protects wr_*_buf_idx, wr_empty, wr_sleepy, wr_ready and the
81 * buffers' end_offset fields against changes made by IRQ handler (and in
82 * theory, other file request handlers, but the mutex handles that). Nothing
83 * else.
84 * They are held for short direct memory manipulations. Needless to say,
85 * no mutex locking is allowed when a spinlock is held.
86 *
87 * rd_spinlock does the same with rd_*_buf_idx, rd_empty and end_offset.
88 *
89 * register_mutex is endpoint-specific, and is held when non-atomic
90 * register operations are performed. wr_mutex and rd_mutex may be
91 * held when register_mutex is taken, but none of the spinlocks. Note that
92 * register_mutex doesn't protect against sporadic buf_ctrl_reg writes
93 * which are unrelated to buf_offset_reg, since they are harmless.
94 *
95 * Blocking on the wait queues is allowed with mutexes held, but not with
96 * spinlocks.
97 *
98 * Only interruptible blocking is allowed on mutexes and wait queues.
99 *
100 * All in all, the locking order goes (with skips allowed, of course):
101 * wr_mutex -> rd_mutex -> register_mutex -> wr_spinlock -> rd_spinlock
102 */
103
104 static void malformed_message(struct xilly_endpoint *endpoint, u32 *buf)
105 {
106 int opcode;
107 int msg_channel, msg_bufno, msg_data, msg_dir;
108
109 opcode = (buf[0] >> 24) & 0xff;
110 msg_dir = buf[0] & 1;
111 msg_channel = (buf[0] >> 1) & 0x7ff;
112 msg_bufno = (buf[0] >> 12) & 0x3ff;
113 msg_data = buf[1] & 0xfffffff;
114
115 dev_warn(endpoint->dev,
116 "Malformed message (skipping): opcode=%d, channel=%03x, dir=%d, bufno=%03x, data=%07x\n",
117 opcode, msg_channel, msg_dir, msg_bufno, msg_data);
118 }
119
120 /*
121 * xillybus_isr assumes the interrupt is allocated exclusively to it,
122 * which is the natural case MSI and several other hardware-oriented
123 * interrupts. Sharing is not allowed.
124 */
125
126 irqreturn_t xillybus_isr(int irq, void *data)
127 {
128 struct xilly_endpoint *ep = data;
129 u32 *buf;
130 unsigned int buf_size;
131 int i;
132 int opcode;
133 unsigned int msg_channel, msg_bufno, msg_data, msg_dir;
134 struct xilly_channel *channel;
135
136 /*
137 * The endpoint structure is altered during periods when it's
138 * guaranteed no interrupt will occur, but in theory, the cache
139 * lines may not be updated. So a memory barrier is issued.
140 */
141 smp_rmb();
142
143 buf = ep->msgbuf_addr;
144 buf_size = ep->msg_buf_size/sizeof(u32);
145
146
147 ep->ephw->hw_sync_sgl_for_cpu(ep,
148 ep->msgbuf_dma_addr,
149 ep->msg_buf_size,
150 DMA_FROM_DEVICE);
151
152 for (i = 0; i < buf_size; i += 2)
153 if (((buf[i+1] >> 28) & 0xf) != ep->msg_counter) {
154 malformed_message(ep, &buf[i]);
155 dev_warn(ep->dev,
156 "Sending a NACK on counter %x (instead of %x) on entry %d\n",
157 ((buf[i+1] >> 28) & 0xf),
158 ep->msg_counter,
159 i/2);
160
161 if (++ep->failed_messages > 10)
162 dev_err(ep->dev,
163 "Lost sync with interrupt messages. Stopping.\n");
164 else {
165 ep->ephw->hw_sync_sgl_for_device(
166 ep,
167 ep->msgbuf_dma_addr,
168 ep->msg_buf_size,
169 DMA_FROM_DEVICE);
170
171 iowrite32(0x01, /* Message NACK */
172 ep->registers + fpga_msg_ctrl_reg);
173 }
174 return IRQ_HANDLED;
175 } else if (buf[i] & (1 << 22)) /* Last message */
176 break;
177
178 if (i >= buf_size) {
179 dev_err(ep->dev, "Bad interrupt message. Stopping.\n");
180 return IRQ_HANDLED;
181 }
182
183 buf_size = i;
184
185 for (i = 0; i <= buf_size; i += 2) { /* Scan through messages */
186 opcode = (buf[i] >> 24) & 0xff;
187
188 msg_dir = buf[i] & 1;
189 msg_channel = (buf[i] >> 1) & 0x7ff;
190 msg_bufno = (buf[i] >> 12) & 0x3ff;
191 msg_data = buf[i+1] & 0xfffffff;
192
193 switch (opcode) {
194 case XILLYMSG_OPCODE_RELEASEBUF:
195
196 if ((msg_channel > ep->num_channels) ||
197 (msg_channel == 0)) {
198 malformed_message(ep, &buf[i]);
199 break;
200 }
201
202 channel = ep->channels[msg_channel];
203
204 if (msg_dir) { /* Write channel */
205 if (msg_bufno >= channel->num_wr_buffers) {
206 malformed_message(ep, &buf[i]);
207 break;
208 }
209 spin_lock(&channel->wr_spinlock);
210 channel->wr_buffers[msg_bufno]->end_offset =
211 msg_data;
212 channel->wr_fpga_buf_idx = msg_bufno;
213 channel->wr_empty = 0;
214 channel->wr_sleepy = 0;
215 spin_unlock(&channel->wr_spinlock);
216
217 wake_up_interruptible(&channel->wr_wait);
218
219 } else {
220 /* Read channel */
221
222 if (msg_bufno >= channel->num_rd_buffers) {
223 malformed_message(ep, &buf[i]);
224 break;
225 }
226
227 spin_lock(&channel->rd_spinlock);
228 channel->rd_fpga_buf_idx = msg_bufno;
229 channel->rd_full = 0;
230 spin_unlock(&channel->rd_spinlock);
231
232 wake_up_interruptible(&channel->rd_wait);
233 if (!channel->rd_synchronous)
234 queue_delayed_work(
235 xillybus_wq,
236 &channel->rd_workitem,
237 XILLY_RX_TIMEOUT);
238 }
239
240 break;
241 case XILLYMSG_OPCODE_NONEMPTY:
242 if ((msg_channel > ep->num_channels) ||
243 (msg_channel == 0) || (!msg_dir) ||
244 !ep->channels[msg_channel]->wr_supports_nonempty) {
245 malformed_message(ep, &buf[i]);
246 break;
247 }
248
249 channel = ep->channels[msg_channel];
250
251 if (msg_bufno >= channel->num_wr_buffers) {
252 malformed_message(ep, &buf[i]);
253 break;
254 }
255 spin_lock(&channel->wr_spinlock);
256 if (msg_bufno == channel->wr_host_buf_idx)
257 channel->wr_ready = 1;
258 spin_unlock(&channel->wr_spinlock);
259
260 wake_up_interruptible(&channel->wr_ready_wait);
261
262 break;
263 case XILLYMSG_OPCODE_QUIESCEACK:
264 ep->idtlen = msg_data;
265 wake_up_interruptible(&ep->ep_wait);
266
267 break;
268 case XILLYMSG_OPCODE_FIFOEOF:
269 if ((msg_channel > ep->num_channels) ||
270 (msg_channel == 0) || (!msg_dir) ||
271 !ep->channels[msg_channel]->num_wr_buffers) {
272 malformed_message(ep, &buf[i]);
273 break;
274 }
275 channel = ep->channels[msg_channel];
276 spin_lock(&channel->wr_spinlock);
277 channel->wr_eof = msg_bufno;
278 channel->wr_sleepy = 0;
279
280 channel->wr_hangup = channel->wr_empty &&
281 (channel->wr_host_buf_idx == msg_bufno);
282
283 spin_unlock(&channel->wr_spinlock);
284
285 wake_up_interruptible(&channel->wr_wait);
286
287 break;
288 case XILLYMSG_OPCODE_FATAL_ERROR:
289 ep->fatal_error = 1;
290 wake_up_interruptible(&ep->ep_wait); /* For select() */
291 dev_err(ep->dev,
292 "FPGA reported a fatal error. This means that the low-level communication with the device has failed. This hardware problem is most likely unrelated to Xillybus (neither kernel module nor FPGA core), but reports are still welcome. All I/O is aborted.\n");
293 break;
294 default:
295 malformed_message(ep, &buf[i]);
296 break;
297 }
298 }
299
300 ep->ephw->hw_sync_sgl_for_device(ep,
301 ep->msgbuf_dma_addr,
302 ep->msg_buf_size,
303 DMA_FROM_DEVICE);
304
305 ep->msg_counter = (ep->msg_counter + 1) & 0xf;
306 ep->failed_messages = 0;
307 iowrite32(0x03, ep->registers + fpga_msg_ctrl_reg); /* Message ACK */
308
309 return IRQ_HANDLED;
310 }
311 EXPORT_SYMBOL(xillybus_isr);
312
313 /*
314 * A few trivial memory management functions.
315 * NOTE: These functions are used only on probe and remove, and therefore
316 * no locks are applied!
317 */
318
319 static void xillybus_autoflush(struct work_struct *work);
320
321 struct xilly_alloc_state {
322 void *salami;
323 int left_of_salami;
324 int nbuffer;
325 enum dma_data_direction direction;
326 u32 regdirection;
327 };
328
329 static int xilly_get_dma_buffers(struct xilly_endpoint *ep,
330 struct xilly_alloc_state *s,
331 struct xilly_buffer **buffers,
332 int bufnum, int bytebufsize)
333 {
334 int i, rc;
335 dma_addr_t dma_addr;
336 struct device *dev = ep->dev;
337 struct xilly_buffer *this_buffer = NULL; /* Init to silence warning */
338
339 if (buffers) { /* Not the message buffer */
340 this_buffer = devm_kzalloc(
341 dev, bufnum * sizeof(struct xilly_buffer),
342 GFP_KERNEL);
343
344 if (!this_buffer)
345 return -ENOMEM;
346 }
347
348 for (i = 0; i < bufnum; i++) {
349 /*
350 * Buffers are expected in descending size order, so there
351 * is either enough space for this buffer or none at all.
352 */
353
354 if ((s->left_of_salami < bytebufsize) &&
355 (s->left_of_salami > 0)) {
356 dev_err(ep->dev,
357 "Corrupt buffer allocation in IDT. Aborting.\n");
358 return -ENODEV;
359 }
360
361 if (s->left_of_salami == 0) {
362 int allocorder, allocsize;
363
364 allocsize = PAGE_SIZE;
365 allocorder = 0;
366 while (bytebufsize > allocsize) {
367 allocsize *= 2;
368 allocorder++;
369 }
370
371 s->salami = (void *) devm_get_free_pages(
372 dev,
373 GFP_KERNEL | __GFP_DMA32 | __GFP_ZERO,
374 allocorder);
375
376 if (!s->salami)
377 return -ENOMEM;
378 s->left_of_salami = allocsize;
379 }
380
381 rc = ep->ephw->map_single(ep, s->salami,
382 bytebufsize, s->direction,
383 &dma_addr);
384
385 if (rc)
386 return rc;
387
388 iowrite32((u32) (dma_addr & 0xffffffff),
389 ep->registers + fpga_dma_bufaddr_lowaddr_reg);
390 iowrite32(((u32) ((((u64) dma_addr) >> 32) & 0xffffffff)),
391 ep->registers + fpga_dma_bufaddr_highaddr_reg);
392 mmiowb();
393
394 if (buffers) { /* Not the message buffer */
395 this_buffer->addr = s->salami;
396 this_buffer->dma_addr = dma_addr;
397 buffers[i] = this_buffer++;
398
399 iowrite32(s->regdirection | s->nbuffer++,
400 ep->registers + fpga_dma_bufno_reg);
401 } else {
402 ep->msgbuf_addr = s->salami;
403 ep->msgbuf_dma_addr = dma_addr;
404 ep->msg_buf_size = bytebufsize;
405
406 iowrite32(s->regdirection,
407 ep->registers + fpga_dma_bufno_reg);
408 }
409
410 s->left_of_salami -= bytebufsize;
411 s->salami += bytebufsize;
412 }
413 return 0; /* Success */
414 }
415
416 static int xilly_setupchannels(struct xilly_endpoint *ep,
417 unsigned char *chandesc,
418 int entries
419 )
420 {
421 struct device *dev = ep->dev;
422 int i, entry, rc;
423 struct xilly_channel *channel;
424 int channelnum, bufnum, bufsize, format, is_writebuf;
425 int bytebufsize;
426 int synchronous, allowpartial, exclusive_open, seekable;
427 int supports_nonempty;
428 int msg_buf_done = 0;
429
430 struct xilly_alloc_state rd_alloc = {
431 .salami = NULL,
432 .left_of_salami = 0,
433 .nbuffer = 1,
434 .direction = DMA_TO_DEVICE,
435 .regdirection = 0,
436 };
437
438 struct xilly_alloc_state wr_alloc = {
439 .salami = NULL,
440 .left_of_salami = 0,
441 .nbuffer = 1,
442 .direction = DMA_FROM_DEVICE,
443 .regdirection = 0x80000000,
444 };
445
446 channel = devm_kzalloc(dev, ep->num_channels *
447 sizeof(struct xilly_channel), GFP_KERNEL);
448
449 if (!channel)
450 goto memfail;
451
452 ep->channels = devm_kzalloc(dev, (ep->num_channels + 1) *
453 sizeof(struct xilly_channel *),
454 GFP_KERNEL);
455
456 if (!ep->channels)
457 goto memfail;
458
459 ep->channels[0] = NULL; /* Channel 0 is message buf. */
460
461 /* Initialize all channels with defaults */
462
463 for (i = 1; i <= ep->num_channels; i++) {
464 channel->wr_buffers = NULL;
465 channel->rd_buffers = NULL;
466 channel->num_wr_buffers = 0;
467 channel->num_rd_buffers = 0;
468 channel->wr_fpga_buf_idx = -1;
469 channel->wr_host_buf_idx = 0;
470 channel->wr_host_buf_pos = 0;
471 channel->wr_empty = 1;
472 channel->wr_ready = 0;
473 channel->wr_sleepy = 1;
474 channel->rd_fpga_buf_idx = 0;
475 channel->rd_host_buf_idx = 0;
476 channel->rd_host_buf_pos = 0;
477 channel->rd_full = 0;
478 channel->wr_ref_count = 0;
479 channel->rd_ref_count = 0;
480
481 spin_lock_init(&channel->wr_spinlock);
482 spin_lock_init(&channel->rd_spinlock);
483 mutex_init(&channel->wr_mutex);
484 mutex_init(&channel->rd_mutex);
485 init_waitqueue_head(&channel->rd_wait);
486 init_waitqueue_head(&channel->wr_wait);
487 init_waitqueue_head(&channel->wr_ready_wait);
488
489 INIT_DELAYED_WORK(&channel->rd_workitem, xillybus_autoflush);
490
491 channel->endpoint = ep;
492 channel->chan_num = i;
493
494 channel->log2_element_size = 0;
495
496 ep->channels[i] = channel++;
497 }
498
499 for (entry = 0; entry < entries; entry++, chandesc += 4) {
500 struct xilly_buffer **buffers = NULL;
501
502 is_writebuf = chandesc[0] & 0x01;
503 channelnum = (chandesc[0] >> 1) | ((chandesc[1] & 0x0f) << 7);
504 format = (chandesc[1] >> 4) & 0x03;
505 allowpartial = (chandesc[1] >> 6) & 0x01;
506 synchronous = (chandesc[1] >> 7) & 0x01;
507 bufsize = 1 << (chandesc[2] & 0x1f);
508 bufnum = 1 << (chandesc[3] & 0x0f);
509 exclusive_open = (chandesc[2] >> 7) & 0x01;
510 seekable = (chandesc[2] >> 6) & 0x01;
511 supports_nonempty = (chandesc[2] >> 5) & 0x01;
512
513 if ((channelnum > ep->num_channels) ||
514 ((channelnum == 0) && !is_writebuf)) {
515 dev_err(ep->dev,
516 "IDT requests channel out of range. Aborting.\n");
517 return -ENODEV;
518 }
519
520 channel = ep->channels[channelnum]; /* NULL for msg channel */
521
522 if (!is_writebuf || channelnum > 0) {
523 channel->log2_element_size = ((format > 2) ?
524 2 : format);
525
526 bytebufsize = channel->rd_buf_size = bufsize *
527 (1 << channel->log2_element_size);
528
529 buffers = devm_kzalloc(dev,
530 bufnum * sizeof(struct xilly_buffer *),
531 GFP_KERNEL);
532
533 if (!buffers)
534 goto memfail;
535 } else
536 bytebufsize = bufsize << 2;
537
538 if (!is_writebuf) {
539 channel->num_rd_buffers = bufnum;
540 channel->rd_allow_partial = allowpartial;
541 channel->rd_synchronous = synchronous;
542 channel->rd_exclusive_open = exclusive_open;
543 channel->seekable = seekable;
544
545 channel->rd_buffers = buffers;
546 rc = xilly_get_dma_buffers(ep, &rd_alloc, buffers,
547 bufnum, bytebufsize);
548 } else if (channelnum > 0) {
549 channel->num_wr_buffers = bufnum;
550
551 channel->seekable = seekable;
552 channel->wr_supports_nonempty = supports_nonempty;
553
554 channel->wr_allow_partial = allowpartial;
555 channel->wr_synchronous = synchronous;
556 channel->wr_exclusive_open = exclusive_open;
557
558 channel->wr_buffers = buffers;
559 rc = xilly_get_dma_buffers(ep, &wr_alloc, buffers,
560 bufnum, bytebufsize);
561 } else {
562 rc = xilly_get_dma_buffers(ep, &wr_alloc, NULL,
563 bufnum, bytebufsize);
564 msg_buf_done++;
565 }
566
567 if (rc)
568 goto memfail;
569 }
570
571 if (!msg_buf_done) {
572 dev_err(ep->dev,
573 "Corrupt IDT: No message buffer. Aborting.\n");
574 return -ENODEV;
575 }
576 return 0;
577
578 memfail:
579 dev_err(ep->dev,
580 "Failed to assign DMA buffer memory. Aborting.\n");
581 return -ENOMEM;
582 }
583
584 static void xilly_scan_idt(struct xilly_endpoint *endpoint,
585 struct xilly_idt_handle *idt_handle)
586 {
587 int count = 0;
588 unsigned char *idt = endpoint->channels[1]->wr_buffers[0]->addr;
589 unsigned char *end_of_idt = idt + endpoint->idtlen - 4;
590 unsigned char *scan;
591 int len;
592
593 scan = idt;
594 idt_handle->idt = idt;
595
596 scan++; /* Skip version number */
597
598 while ((scan <= end_of_idt) && *scan) {
599 while ((scan <= end_of_idt) && *scan++)
600 /* Do nothing, just scan thru string */;
601 count++;
602 }
603
604 scan++;
605
606 if (scan > end_of_idt) {
607 dev_err(endpoint->dev,
608 "IDT device name list overflow. Aborting.\n");
609 idt_handle->chandesc = NULL;
610 return;
611 }
612 idt_handle->chandesc = scan;
613
614 len = endpoint->idtlen - (3 + ((int) (scan - idt)));
615
616 if (len & 0x03) {
617 idt_handle->chandesc = NULL;
618
619 dev_err(endpoint->dev,
620 "Corrupt IDT device name list. Aborting.\n");
621 }
622
623 idt_handle->entries = len >> 2;
624
625 endpoint->num_channels = count;
626 }
627
628 static int xilly_obtain_idt(struct xilly_endpoint *endpoint)
629 {
630 int rc = 0;
631 struct xilly_channel *channel;
632 unsigned char *version;
633
634 channel = endpoint->channels[1]; /* This should be generated ad-hoc */
635
636 channel->wr_sleepy = 1;
637 wmb(); /* Setting wr_sleepy must come before the command */
638
639 iowrite32(1 |
640 (3 << 24), /* Opcode 3 for channel 0 = Send IDT */
641 endpoint->registers + fpga_buf_ctrl_reg);
642 mmiowb(); /* Just to appear safe */
643
644 wait_event_interruptible_timeout(channel->wr_wait,
645 (!channel->wr_sleepy),
646 XILLY_TIMEOUT);
647
648 if (channel->wr_sleepy) {
649 dev_err(endpoint->dev, "Failed to obtain IDT. Aborting.\n");
650
651 if (endpoint->fatal_error)
652 return -EIO;
653
654 rc = -ENODEV;
655 return rc;
656 }
657
658 endpoint->ephw->hw_sync_sgl_for_cpu(
659 channel->endpoint,
660 channel->wr_buffers[0]->dma_addr,
661 channel->wr_buf_size,
662 DMA_FROM_DEVICE);
663
664 if (channel->wr_buffers[0]->end_offset != endpoint->idtlen) {
665 dev_err(endpoint->dev,
666 "IDT length mismatch (%d != %d). Aborting.\n",
667 channel->wr_buffers[0]->end_offset, endpoint->idtlen);
668 rc = -ENODEV;
669 return rc;
670 }
671
672 if (crc32_le(~0, channel->wr_buffers[0]->addr,
673 endpoint->idtlen+1) != 0) {
674 dev_err(endpoint->dev, "IDT failed CRC check. Aborting.\n");
675 rc = -ENODEV;
676 return rc;
677 }
678
679 version = channel->wr_buffers[0]->addr;
680
681 /* Check version number. Accept anything below 0x82 for now. */
682 if (*version > 0x82) {
683 dev_err(endpoint->dev,
684 "No support for IDT version 0x%02x. Maybe the xillybus driver needs an upgarde. Aborting.\n",
685 (int) *version);
686 rc = -ENODEV;
687 return rc;
688 }
689
690 return 0; /* Success */
691 }
692
693 static ssize_t xillybus_read(struct file *filp, char __user *userbuf,
694 size_t count, loff_t *f_pos)
695 {
696 ssize_t rc;
697 unsigned long flags;
698 int bytes_done = 0;
699 int no_time_left = 0;
700 long deadline, left_to_sleep;
701 struct xilly_channel *channel = filp->private_data;
702
703 int empty, reached_eof, exhausted, ready;
704 /* Initializations are there only to silence warnings */
705
706 int howmany = 0, bufpos = 0, bufidx = 0, bufferdone = 0;
707 int waiting_bufidx;
708
709 if (channel->endpoint->fatal_error)
710 return -EIO;
711
712 deadline = jiffies + 1 + XILLY_RX_TIMEOUT;
713
714 rc = mutex_lock_interruptible(&channel->wr_mutex);
715
716 if (rc)
717 return rc;
718
719 rc = 0; /* Just to be clear about it. Compiler optimizes this out */
720
721 while (1) { /* Note that we may drop mutex within this loop */
722 int bytes_to_do = count - bytes_done;
723
724 spin_lock_irqsave(&channel->wr_spinlock, flags);
725
726 empty = channel->wr_empty;
727 ready = !empty || channel->wr_ready;
728
729 if (!empty) {
730 bufidx = channel->wr_host_buf_idx;
731 bufpos = channel->wr_host_buf_pos;
732 howmany = ((channel->wr_buffers[bufidx]->end_offset
733 + 1) << channel->log2_element_size)
734 - bufpos;
735
736 /* Update wr_host_* to its post-operation state */
737 if (howmany > bytes_to_do) {
738 bufferdone = 0;
739
740 howmany = bytes_to_do;
741 channel->wr_host_buf_pos += howmany;
742 } else {
743 bufferdone = 1;
744
745 channel->wr_host_buf_pos = 0;
746
747 if (bufidx == channel->wr_fpga_buf_idx) {
748 channel->wr_empty = 1;
749 channel->wr_sleepy = 1;
750 channel->wr_ready = 0;
751 }
752
753 if (bufidx >= (channel->num_wr_buffers - 1))
754 channel->wr_host_buf_idx = 0;
755 else
756 channel->wr_host_buf_idx++;
757 }
758 }
759
760 /*
761 * Marking our situation after the possible changes above,
762 * for use after releasing the spinlock.
763 *
764 * empty = empty before change
765 * exhasted = empty after possible change
766 */
767
768 reached_eof = channel->wr_empty &&
769 (channel->wr_host_buf_idx == channel->wr_eof);
770 channel->wr_hangup = reached_eof;
771 exhausted = channel->wr_empty;
772 waiting_bufidx = channel->wr_host_buf_idx;
773
774 spin_unlock_irqrestore(&channel->wr_spinlock, flags);
775
776 if (!empty) { /* Go on, now without the spinlock */
777
778 if (bufpos == 0) /* Position zero means it's virgin */
779 channel->endpoint->ephw->hw_sync_sgl_for_cpu(
780 channel->endpoint,
781 channel->wr_buffers[bufidx]->dma_addr,
782 channel->wr_buf_size,
783 DMA_FROM_DEVICE);
784
785 if (copy_to_user(
786 userbuf,
787 channel->wr_buffers[bufidx]->addr
788 + bufpos, howmany))
789 rc = -EFAULT;
790
791 userbuf += howmany;
792 bytes_done += howmany;
793
794 if (bufferdone) {
795 channel->endpoint->ephw->
796 hw_sync_sgl_for_device
797 (
798 channel->endpoint,
799 channel->wr_buffers[bufidx]->
800 dma_addr,
801 channel->wr_buf_size,
802 DMA_FROM_DEVICE);
803
804 /*
805 * Tell FPGA the buffer is done with. It's an
806 * atomic operation to the FPGA, so what
807 * happens with other channels doesn't matter,
808 * and the certain channel is protected with
809 * the channel-specific mutex.
810 */
811
812 iowrite32(1 | (channel->chan_num << 1)
813 | (bufidx << 12),
814 channel->endpoint->registers +
815 fpga_buf_ctrl_reg);
816 mmiowb(); /* Just to appear safe */
817 }
818
819 if (rc) {
820 mutex_unlock(&channel->wr_mutex);
821 return rc;
822 }
823 }
824
825 /* This includes a zero-count return = EOF */
826 if ((bytes_done >= count) || reached_eof)
827 break;
828
829 if (!exhausted)
830 continue; /* More in RAM buffer(s)? Just go on. */
831
832 if ((bytes_done > 0) &&
833 (no_time_left ||
834 (channel->wr_synchronous && channel->wr_allow_partial)))
835 break;
836
837 /*
838 * Nonblocking read: The "ready" flag tells us that the FPGA
839 * has data to send. In non-blocking mode, if it isn't on,
840 * just return. But if there is, we jump directly to the point
841 * where we ask for the FPGA to send all it has, and wait
842 * until that data arrives. So in a sense, we *do* block in
843 * nonblocking mode, but only for a very short time.
844 */
845
846 if (!no_time_left && (filp->f_flags & O_NONBLOCK)) {
847 if (bytes_done > 0)
848 break;
849
850 if (ready)
851 goto desperate;
852
853 bytes_done = -EAGAIN;
854 break;
855 }
856
857 if (!no_time_left || (bytes_done > 0)) {
858 /*
859 * Note that in case of an element-misaligned read
860 * request, offsetlimit will include the last element,
861 * which will be partially read from.
862 */
863 int offsetlimit = ((count - bytes_done) - 1) >>
864 channel->log2_element_size;
865 int buf_elements = channel->wr_buf_size >>
866 channel->log2_element_size;
867
868 /*
869 * In synchronous mode, always send an offset limit.
870 * Just don't send a value too big.
871 */
872
873 if (channel->wr_synchronous) {
874 /* Don't request more than one buffer */
875 if (channel->wr_allow_partial &&
876 (offsetlimit >= buf_elements))
877 offsetlimit = buf_elements - 1;
878
879 /* Don't request more than all buffers */
880 if (!channel->wr_allow_partial &&
881 (offsetlimit >=
882 (buf_elements * channel->num_wr_buffers)))
883 offsetlimit = buf_elements *
884 channel->num_wr_buffers - 1;
885 }
886
887 /*
888 * In asynchronous mode, force early flush of a buffer
889 * only if that will allow returning a full count. The
890 * "offsetlimit < ( ... )" rather than "<=" excludes
891 * requesting a full buffer, which would obviously
892 * cause a buffer transmission anyhow
893 */
894
895 if (channel->wr_synchronous ||
896 (offsetlimit < (buf_elements - 1))) {
897
898 mutex_lock(&channel->endpoint->register_mutex);
899
900 iowrite32(offsetlimit,
901 channel->endpoint->registers +
902 fpga_buf_offset_reg);
903 mmiowb();
904
905 iowrite32(1 | (channel->chan_num << 1) |
906 (2 << 24) | /* 2 = offset limit */
907 (waiting_bufidx << 12),
908 channel->endpoint->registers +
909 fpga_buf_ctrl_reg);
910
911 mmiowb(); /* Just to appear safe */
912
913 mutex_unlock(&channel->endpoint->
914 register_mutex);
915 }
916
917 }
918
919 /*
920 * If partial completion is disallowed, there is no point in
921 * timeout sleeping. Neither if no_time_left is set and
922 * there's no data.
923 */
924
925 if (!channel->wr_allow_partial ||
926 (no_time_left && (bytes_done == 0))) {
927
928 /*
929 * This do-loop will run more than once if another
930 * thread reasserted wr_sleepy before we got the mutex
931 * back, so we try again.
932 */
933
934 do {
935 mutex_unlock(&channel->wr_mutex);
936
937 if (wait_event_interruptible(
938 channel->wr_wait,
939 (!channel->wr_sleepy)))
940 goto interrupted;
941
942 if (mutex_lock_interruptible(
943 &channel->wr_mutex))
944 goto interrupted;
945 } while (channel->wr_sleepy);
946
947 continue;
948
949 interrupted: /* Mutex is not held if got here */
950 if (channel->endpoint->fatal_error)
951 return -EIO;
952 if (bytes_done)
953 return bytes_done;
954 if (filp->f_flags & O_NONBLOCK)
955 return -EAGAIN; /* Don't admit snoozing */
956 return -EINTR;
957 }
958
959 left_to_sleep = deadline - ((long) jiffies);
960
961 /*
962 * If our time is out, skip the waiting. We may miss wr_sleepy
963 * being deasserted but hey, almost missing the train is like
964 * missing it.
965 */
966
967 if (left_to_sleep > 0) {
968 left_to_sleep =
969 wait_event_interruptible_timeout(
970 channel->wr_wait,
971 (!channel->wr_sleepy),
972 left_to_sleep);
973
974 if (!channel->wr_sleepy)
975 continue;
976
977 if (left_to_sleep < 0) { /* Interrupt */
978 mutex_unlock(&channel->wr_mutex);
979 if (channel->endpoint->fatal_error)
980 return -EIO;
981 if (bytes_done)
982 return bytes_done;
983 return -EINTR;
984 }
985 }
986
987 desperate:
988 no_time_left = 1; /* We're out of sleeping time. Desperate! */
989
990 if (bytes_done == 0) {
991 /*
992 * Reaching here means that we allow partial return,
993 * that we've run out of time, and that we have
994 * nothing to return.
995 * So tell the FPGA to send anything it has or gets.
996 */
997
998 iowrite32(1 | (channel->chan_num << 1) |
999 (3 << 24) | /* Opcode 3, flush it all! */
1000 (waiting_bufidx << 12),
1001 channel->endpoint->registers +
1002 fpga_buf_ctrl_reg);
1003 mmiowb(); /* Just to appear safe */
1004 }
1005
1006 /*
1007 * Formally speaking, we should block for data at this point.
1008 * But to keep the code cleaner, we'll just finish the loop,
1009 * make the unlikely check for data, and then block at the
1010 * usual place.
1011 */
1012 }
1013
1014 mutex_unlock(&channel->wr_mutex);
1015
1016 if (channel->endpoint->fatal_error)
1017 return -EIO;
1018
1019 return bytes_done;
1020 }
1021
1022 /*
1023 * The timeout argument takes values as follows:
1024 * >0 : Flush with timeout
1025 * ==0 : Flush, and wait idefinitely for the flush to complete
1026 * <0 : Autoflush: Flush only if there's a single buffer occupied
1027 */
1028
1029 static int xillybus_myflush(struct xilly_channel *channel, long timeout)
1030 {
1031 int rc = 0;
1032 unsigned long flags;
1033
1034 int end_offset_plus1;
1035 int bufidx, bufidx_minus1;
1036 int i;
1037 int empty;
1038 int new_rd_host_buf_pos;
1039
1040 if (channel->endpoint->fatal_error)
1041 return -EIO;
1042 rc = mutex_lock_interruptible(&channel->rd_mutex);
1043
1044 if (rc)
1045 return rc;
1046
1047 /*
1048 * Don't flush a closed channel. This can happen when the work queued
1049 * autoflush thread fires off after the file has closed. This is not
1050 * an error, just something to dismiss.
1051 */
1052
1053 if (!channel->rd_ref_count)
1054 goto done;
1055
1056 bufidx = channel->rd_host_buf_idx;
1057
1058 bufidx_minus1 = (bufidx == 0) ? channel->num_rd_buffers - 1 : bufidx-1;
1059
1060 end_offset_plus1 = channel->rd_host_buf_pos >>
1061 channel->log2_element_size;
1062
1063 new_rd_host_buf_pos = channel->rd_host_buf_pos -
1064 (end_offset_plus1 << channel->log2_element_size);
1065
1066 /* Submit the current buffer if it's nonempty */
1067 if (end_offset_plus1) {
1068 unsigned char *tail = channel->rd_buffers[bufidx]->addr +
1069 (end_offset_plus1 << channel->log2_element_size);
1070
1071 /* Copy unflushed data, so we can put it in next buffer */
1072 for (i = 0; i < new_rd_host_buf_pos; i++)
1073 channel->rd_leftovers[i] = *tail++;
1074
1075 spin_lock_irqsave(&channel->rd_spinlock, flags);
1076
1077 /* Autoflush only if a single buffer is occupied */
1078
1079 if ((timeout < 0) &&
1080 (channel->rd_full ||
1081 (bufidx_minus1 != channel->rd_fpga_buf_idx))) {
1082 spin_unlock_irqrestore(&channel->rd_spinlock, flags);
1083 /*
1084 * A new work item may be queued by the ISR exactly
1085 * now, since the execution of a work item allows the
1086 * queuing of a new one while it's running.
1087 */
1088 goto done;
1089 }
1090
1091 /* The 4th element is never needed for data, so it's a flag */
1092 channel->rd_leftovers[3] = (new_rd_host_buf_pos != 0);
1093
1094 /* Set up rd_full to reflect a certain moment's state */
1095
1096 if (bufidx == channel->rd_fpga_buf_idx)
1097 channel->rd_full = 1;
1098 spin_unlock_irqrestore(&channel->rd_spinlock, flags);
1099
1100 if (bufidx >= (channel->num_rd_buffers - 1))
1101 channel->rd_host_buf_idx = 0;
1102 else
1103 channel->rd_host_buf_idx++;
1104
1105 channel->endpoint->ephw->hw_sync_sgl_for_device(
1106 channel->endpoint,
1107 channel->rd_buffers[bufidx]->dma_addr,
1108 channel->rd_buf_size,
1109 DMA_TO_DEVICE);
1110
1111 mutex_lock(&channel->endpoint->register_mutex);
1112
1113 iowrite32(end_offset_plus1 - 1,
1114 channel->endpoint->registers + fpga_buf_offset_reg);
1115 mmiowb();
1116
1117 iowrite32((channel->chan_num << 1) | /* Channel ID */
1118 (2 << 24) | /* Opcode 2, submit buffer */
1119 (bufidx << 12),
1120 channel->endpoint->registers + fpga_buf_ctrl_reg);
1121 mmiowb(); /* Just to appear safe */
1122
1123 mutex_unlock(&channel->endpoint->register_mutex);
1124 } else if (bufidx == 0)
1125 bufidx = channel->num_rd_buffers - 1;
1126 else
1127 bufidx--;
1128
1129 channel->rd_host_buf_pos = new_rd_host_buf_pos;
1130
1131 if (timeout < 0)
1132 goto done; /* Autoflush */
1133
1134
1135 /*
1136 * bufidx is now the last buffer written to (or equal to
1137 * rd_fpga_buf_idx if buffer was never written to), and
1138 * channel->rd_host_buf_idx the one after it.
1139 *
1140 * If bufidx == channel->rd_fpga_buf_idx we're either empty or full.
1141 */
1142
1143 rc = 0;
1144
1145 while (1) { /* Loop waiting for draining of buffers */
1146 spin_lock_irqsave(&channel->rd_spinlock, flags);
1147
1148 if (bufidx != channel->rd_fpga_buf_idx)
1149 channel->rd_full = 1; /*
1150 * Not really full,
1151 * but needs waiting.
1152 */
1153
1154 empty = !channel->rd_full;
1155
1156 spin_unlock_irqrestore(&channel->rd_spinlock, flags);
1157
1158 if (empty)
1159 break;
1160
1161 /*
1162 * Indefinite sleep with mutex taken. With data waiting for
1163 * flushing user should not be surprised if open() for write
1164 * sleeps.
1165 */
1166 if (timeout == 0)
1167 wait_event_interruptible(channel->rd_wait,
1168 (!channel->rd_full));
1169
1170 else if (wait_event_interruptible_timeout(
1171 channel->rd_wait,
1172 (!channel->rd_full),
1173 timeout) == 0) {
1174 dev_warn(channel->endpoint->dev,
1175 "Timed out while flushing. Output data may be lost.\n");
1176
1177 rc = -ETIMEDOUT;
1178 break;
1179 }
1180
1181 if (channel->rd_full) {
1182 rc = -EINTR;
1183 break;
1184 }
1185 }
1186
1187 done:
1188 mutex_unlock(&channel->rd_mutex);
1189
1190 if (channel->endpoint->fatal_error)
1191 return -EIO;
1192
1193 return rc;
1194 }
1195
1196 static int xillybus_flush(struct file *filp, fl_owner_t id)
1197 {
1198 if (!(filp->f_mode & FMODE_WRITE))
1199 return 0;
1200
1201 return xillybus_myflush(filp->private_data, HZ); /* 1 second timeout */
1202 }
1203
1204 static void xillybus_autoflush(struct work_struct *work)
1205 {
1206 struct delayed_work *workitem = container_of(
1207 work, struct delayed_work, work);
1208 struct xilly_channel *channel = container_of(
1209 workitem, struct xilly_channel, rd_workitem);
1210 int rc;
1211
1212 rc = xillybus_myflush(channel, -1);
1213
1214 if (rc == -EINTR)
1215 dev_warn(channel->endpoint->dev,
1216 "Autoflush failed because work queue thread got a signal.\n");
1217 else if (rc)
1218 dev_err(channel->endpoint->dev,
1219 "Autoflush failed under weird circumstances.\n");
1220 }
1221
1222 static ssize_t xillybus_write(struct file *filp, const char __user *userbuf,
1223 size_t count, loff_t *f_pos)
1224 {
1225 ssize_t rc;
1226 unsigned long flags;
1227 int bytes_done = 0;
1228 struct xilly_channel *channel = filp->private_data;
1229
1230 int full, exhausted;
1231 /* Initializations are there only to silence warnings */
1232
1233 int howmany = 0, bufpos = 0, bufidx = 0, bufferdone = 0;
1234 int end_offset_plus1 = 0;
1235
1236 if (channel->endpoint->fatal_error)
1237 return -EIO;
1238
1239 rc = mutex_lock_interruptible(&channel->rd_mutex);
1240
1241 if (rc)
1242 return rc;
1243
1244 rc = 0; /* Just to be clear about it. Compiler optimizes this out */
1245
1246 while (1) {
1247 int bytes_to_do = count - bytes_done;
1248
1249 spin_lock_irqsave(&channel->rd_spinlock, flags);
1250
1251 full = channel->rd_full;
1252
1253 if (!full) {
1254 bufidx = channel->rd_host_buf_idx;
1255 bufpos = channel->rd_host_buf_pos;
1256 howmany = channel->rd_buf_size - bufpos;
1257
1258 /*
1259 * Update rd_host_* to its state after this operation.
1260 * count=0 means committing the buffer immediately,
1261 * which is like flushing, but not necessarily block.
1262 */
1263
1264 if ((howmany > bytes_to_do) &&
1265 (count ||
1266 ((bufpos >> channel->log2_element_size) == 0))) {
1267 bufferdone = 0;
1268
1269 howmany = bytes_to_do;
1270 channel->rd_host_buf_pos += howmany;
1271 } else {
1272 bufferdone = 1;
1273
1274 if (count) {
1275 end_offset_plus1 =
1276 channel->rd_buf_size >>
1277 channel->log2_element_size;
1278 channel->rd_host_buf_pos = 0;
1279 } else {
1280 unsigned char *tail;
1281 int i;
1282
1283 end_offset_plus1 = bufpos >>
1284 channel->log2_element_size;
1285
1286 channel->rd_host_buf_pos -=
1287 end_offset_plus1 <<
1288 channel->log2_element_size;
1289
1290 tail = channel->
1291 rd_buffers[bufidx]->addr +
1292 (end_offset_plus1 <<
1293 channel->log2_element_size);
1294
1295 for (i = 0;
1296 i < channel->rd_host_buf_pos;
1297 i++)
1298 channel->rd_leftovers[i] =
1299 *tail++;
1300 }
1301
1302 if (bufidx == channel->rd_fpga_buf_idx)
1303 channel->rd_full = 1;
1304
1305 if (bufidx >= (channel->num_rd_buffers - 1))
1306 channel->rd_host_buf_idx = 0;
1307 else
1308 channel->rd_host_buf_idx++;
1309 }
1310 }
1311
1312 /*
1313 * Marking our situation after the possible changes above,
1314 * for use after releasing the spinlock.
1315 *
1316 * full = full before change
1317 * exhasted = full after possible change
1318 */
1319
1320 exhausted = channel->rd_full;
1321
1322 spin_unlock_irqrestore(&channel->rd_spinlock, flags);
1323
1324 if (!full) { /* Go on, now without the spinlock */
1325 unsigned char *head =
1326 channel->rd_buffers[bufidx]->addr;
1327 int i;
1328
1329 if ((bufpos == 0) || /* Zero means it's virgin */
1330 (channel->rd_leftovers[3] != 0)) {
1331 channel->endpoint->ephw->hw_sync_sgl_for_cpu(
1332 channel->endpoint,
1333 channel->rd_buffers[bufidx]->dma_addr,
1334 channel->rd_buf_size,
1335 DMA_TO_DEVICE);
1336
1337 /* Virgin, but leftovers are due */
1338 for (i = 0; i < bufpos; i++)
1339 *head++ = channel->rd_leftovers[i];
1340
1341 channel->rd_leftovers[3] = 0; /* Clear flag */
1342 }
1343
1344 if (copy_from_user(
1345 channel->rd_buffers[bufidx]->addr + bufpos,
1346 userbuf, howmany))
1347 rc = -EFAULT;
1348
1349 userbuf += howmany;
1350 bytes_done += howmany;
1351
1352 if (bufferdone) {
1353 channel->endpoint->ephw->
1354 hw_sync_sgl_for_device(
1355 channel->endpoint,
1356 channel->rd_buffers[bufidx]->
1357 dma_addr,
1358 channel->rd_buf_size,
1359 DMA_TO_DEVICE);
1360
1361 mutex_lock(&channel->endpoint->register_mutex);
1362
1363 iowrite32(end_offset_plus1 - 1,
1364 channel->endpoint->registers +
1365 fpga_buf_offset_reg);
1366 mmiowb();
1367 iowrite32((channel->chan_num << 1) |
1368 (2 << 24) | /* 2 = submit buffer */
1369 (bufidx << 12),
1370 channel->endpoint->registers +
1371 fpga_buf_ctrl_reg);
1372 mmiowb(); /* Just to appear safe */
1373
1374 mutex_unlock(&channel->endpoint->
1375 register_mutex);
1376
1377 channel->rd_leftovers[3] =
1378 (channel->rd_host_buf_pos != 0);
1379 }
1380
1381 if (rc) {
1382 mutex_unlock(&channel->rd_mutex);
1383
1384 if (channel->endpoint->fatal_error)
1385 return -EIO;
1386
1387 if (!channel->rd_synchronous)
1388 queue_delayed_work(
1389 xillybus_wq,
1390 &channel->rd_workitem,
1391 XILLY_RX_TIMEOUT);
1392
1393 return rc;
1394 }
1395 }
1396
1397 if (bytes_done >= count)
1398 break;
1399
1400 if (!exhausted)
1401 continue; /* If there's more space, just go on */
1402
1403 if ((bytes_done > 0) && channel->rd_allow_partial)
1404 break;
1405
1406 /*
1407 * Indefinite sleep with mutex taken. With data waiting for
1408 * flushing, user should not be surprised if open() for write
1409 * sleeps.
1410 */
1411
1412 if (filp->f_flags & O_NONBLOCK) {
1413 bytes_done = -EAGAIN;
1414 break;
1415 }
1416
1417 wait_event_interruptible(channel->rd_wait,
1418 (!channel->rd_full));
1419
1420 if (channel->rd_full) {
1421 mutex_unlock(&channel->rd_mutex);
1422
1423 if (channel->endpoint->fatal_error)
1424 return -EIO;
1425
1426 if (bytes_done)
1427 return bytes_done;
1428 return -EINTR;
1429 }
1430 }
1431
1432 mutex_unlock(&channel->rd_mutex);
1433
1434 if (!channel->rd_synchronous)
1435 queue_delayed_work(xillybus_wq,
1436 &channel->rd_workitem,
1437 XILLY_RX_TIMEOUT);
1438
1439 if ((channel->rd_synchronous) && (bytes_done > 0)) {
1440 rc = xillybus_myflush(filp->private_data, 0); /* No timeout */
1441
1442 if (rc && (rc != -EINTR))
1443 return rc;
1444 }
1445
1446 if (channel->endpoint->fatal_error)
1447 return -EIO;
1448
1449 return bytes_done;
1450 }
1451
1452 static int xillybus_open(struct inode *inode, struct file *filp)
1453 {
1454 int rc = 0;
1455 unsigned long flags;
1456 int minor = iminor(inode);
1457 int major = imajor(inode);
1458 struct xilly_endpoint *ep_iter, *endpoint = NULL;
1459 struct xilly_channel *channel;
1460
1461 mutex_lock(&ep_list_lock);
1462
1463 list_for_each_entry(ep_iter, &list_of_endpoints, ep_list) {
1464 if ((ep_iter->major == major) &&
1465 (minor >= ep_iter->lowest_minor) &&
1466 (minor < (ep_iter->lowest_minor +
1467 ep_iter->num_channels))) {
1468 endpoint = ep_iter;
1469 break;
1470 }
1471 }
1472 mutex_unlock(&ep_list_lock);
1473
1474 if (!endpoint) {
1475 pr_err("xillybus: open() failed to find a device for major=%d and minor=%d\n",
1476 major, minor);
1477 return -ENODEV;
1478 }
1479
1480 if (endpoint->fatal_error)
1481 return -EIO;
1482
1483 channel = endpoint->channels[1 + minor - endpoint->lowest_minor];
1484 filp->private_data = channel;
1485
1486
1487 /*
1488 * It gets complicated because:
1489 * 1. We don't want to take a mutex we don't have to
1490 * 2. We don't want to open one direction if the other will fail.
1491 */
1492
1493 if ((filp->f_mode & FMODE_READ) && (!channel->num_wr_buffers))
1494 return -ENODEV;
1495
1496 if ((filp->f_mode & FMODE_WRITE) && (!channel->num_rd_buffers))
1497 return -ENODEV;
1498
1499 if ((filp->f_mode & FMODE_READ) && (filp->f_flags & O_NONBLOCK) &&
1500 (channel->wr_synchronous || !channel->wr_allow_partial ||
1501 !channel->wr_supports_nonempty)) {
1502 dev_err(endpoint->dev,
1503 "open() failed: O_NONBLOCK not allowed for read on this device\n");
1504 return -ENODEV;
1505 }
1506
1507 if ((filp->f_mode & FMODE_WRITE) && (filp->f_flags & O_NONBLOCK) &&
1508 (channel->rd_synchronous || !channel->rd_allow_partial)) {
1509 dev_err(endpoint->dev,
1510 "open() failed: O_NONBLOCK not allowed for write on this device\n");
1511 return -ENODEV;
1512 }
1513
1514 /*
1515 * Note: open() may block on getting mutexes despite O_NONBLOCK.
1516 * This shouldn't occur normally, since multiple open of the same
1517 * file descriptor is almost always prohibited anyhow
1518 * (*_exclusive_open is normally set in real-life systems).
1519 */
1520
1521 if (filp->f_mode & FMODE_READ) {
1522 rc = mutex_lock_interruptible(&channel->wr_mutex);
1523 if (rc)
1524 return rc;
1525 }
1526
1527 if (filp->f_mode & FMODE_WRITE) {
1528 rc = mutex_lock_interruptible(&channel->rd_mutex);
1529 if (rc)
1530 goto unlock_wr;
1531 }
1532
1533 if ((filp->f_mode & FMODE_READ) &&
1534 (channel->wr_ref_count != 0) &&
1535 (channel->wr_exclusive_open)) {
1536 rc = -EBUSY;
1537 goto unlock;
1538 }
1539
1540 if ((filp->f_mode & FMODE_WRITE) &&
1541 (channel->rd_ref_count != 0) &&
1542 (channel->rd_exclusive_open)) {
1543 rc = -EBUSY;
1544 goto unlock;
1545 }
1546
1547
1548 if (filp->f_mode & FMODE_READ) {
1549 if (channel->wr_ref_count == 0) { /* First open of file */
1550 /* Move the host to first buffer */
1551 spin_lock_irqsave(&channel->wr_spinlock, flags);
1552 channel->wr_host_buf_idx = 0;
1553 channel->wr_host_buf_pos = 0;
1554 channel->wr_fpga_buf_idx = -1;
1555 channel->wr_empty = 1;
1556 channel->wr_ready = 0;
1557 channel->wr_sleepy = 1;
1558 channel->wr_eof = -1;
1559 channel->wr_hangup = 0;
1560
1561 spin_unlock_irqrestore(&channel->wr_spinlock, flags);
1562
1563 iowrite32(1 | (channel->chan_num << 1) |
1564 (4 << 24) | /* Opcode 4, open channel */
1565 ((channel->wr_synchronous & 1) << 23),
1566 channel->endpoint->registers +
1567 fpga_buf_ctrl_reg);
1568 mmiowb(); /* Just to appear safe */
1569 }
1570
1571 channel->wr_ref_count++;
1572 }
1573
1574 if (filp->f_mode & FMODE_WRITE) {
1575 if (channel->rd_ref_count == 0) { /* First open of file */
1576 /* Move the host to first buffer */
1577 spin_lock_irqsave(&channel->rd_spinlock, flags);
1578 channel->rd_host_buf_idx = 0;
1579 channel->rd_host_buf_pos = 0;
1580 channel->rd_leftovers[3] = 0; /* No leftovers. */
1581 channel->rd_fpga_buf_idx = channel->num_rd_buffers - 1;
1582 channel->rd_full = 0;
1583
1584 spin_unlock_irqrestore(&channel->rd_spinlock, flags);
1585
1586 iowrite32((channel->chan_num << 1) |
1587 (4 << 24), /* Opcode 4, open channel */
1588 channel->endpoint->registers +
1589 fpga_buf_ctrl_reg);
1590 mmiowb(); /* Just to appear safe */
1591 }
1592
1593 channel->rd_ref_count++;
1594 }
1595
1596 unlock:
1597 if (filp->f_mode & FMODE_WRITE)
1598 mutex_unlock(&channel->rd_mutex);
1599 unlock_wr:
1600 if (filp->f_mode & FMODE_READ)
1601 mutex_unlock(&channel->wr_mutex);
1602
1603 if (!rc && (!channel->seekable))
1604 return nonseekable_open(inode, filp);
1605
1606 return rc;
1607 }
1608
1609 static int xillybus_release(struct inode *inode, struct file *filp)
1610 {
1611 int rc;
1612 unsigned long flags;
1613 struct xilly_channel *channel = filp->private_data;
1614
1615 int buf_idx;
1616 int eof;
1617
1618 if (channel->endpoint->fatal_error)
1619 return -EIO;
1620
1621 if (filp->f_mode & FMODE_WRITE) {
1622 rc = mutex_lock_interruptible(&channel->rd_mutex);
1623
1624 if (rc) {
1625 dev_warn(channel->endpoint->dev,
1626 "Failed to close file. Hardware left in messy state.\n");
1627 return rc;
1628 }
1629
1630 channel->rd_ref_count--;
1631
1632 if (channel->rd_ref_count == 0) {
1633
1634 /*
1635 * We rely on the kernel calling flush()
1636 * before we get here.
1637 */
1638
1639 iowrite32((channel->chan_num << 1) | /* Channel ID */
1640 (5 << 24), /* Opcode 5, close channel */
1641 channel->endpoint->registers +
1642 fpga_buf_ctrl_reg);
1643 mmiowb(); /* Just to appear safe */
1644 }
1645 mutex_unlock(&channel->rd_mutex);
1646 }
1647
1648 if (filp->f_mode & FMODE_READ) {
1649 rc = mutex_lock_interruptible(&channel->wr_mutex);
1650 if (rc) {
1651 dev_warn(channel->endpoint->dev,
1652 "Failed to close file. Hardware left in messy state.\n");
1653 return rc;
1654 }
1655
1656 channel->wr_ref_count--;
1657
1658 if (channel->wr_ref_count == 0) {
1659
1660 iowrite32(1 | (channel->chan_num << 1) |
1661 (5 << 24), /* Opcode 5, close channel */
1662 channel->endpoint->registers +
1663 fpga_buf_ctrl_reg);
1664 mmiowb(); /* Just to appear safe */
1665
1666 /*
1667 * This is crazily cautious: We make sure that not
1668 * only that we got an EOF (be it because we closed
1669 * the channel or because of a user's EOF), but verify
1670 * that it's one beyond the last buffer arrived, so
1671 * we have no leftover buffers pending before wrapping
1672 * up (which can only happen in asynchronous channels,
1673 * BTW)
1674 */
1675
1676 while (1) {
1677 spin_lock_irqsave(&channel->wr_spinlock,
1678 flags);
1679 buf_idx = channel->wr_fpga_buf_idx;
1680 eof = channel->wr_eof;
1681 channel->wr_sleepy = 1;
1682 spin_unlock_irqrestore(&channel->wr_spinlock,
1683 flags);
1684
1685 /*
1686 * Check if eof points at the buffer after
1687 * the last one the FPGA submitted. Note that
1688 * no EOF is marked by negative eof.
1689 */
1690
1691 buf_idx++;
1692 if (buf_idx == channel->num_wr_buffers)
1693 buf_idx = 0;
1694
1695 if (buf_idx == eof)
1696 break;
1697
1698 /*
1699 * Steal extra 100 ms if awaken by interrupt.
1700 * This is a simple workaround for an
1701 * interrupt pending when entering, which would
1702 * otherwise result in declaring the hardware
1703 * non-responsive.
1704 */
1705
1706 if (wait_event_interruptible(
1707 channel->wr_wait,
1708 (!channel->wr_sleepy)))
1709 msleep(100);
1710
1711 if (channel->wr_sleepy) {
1712 mutex_unlock(&channel->wr_mutex);
1713 dev_warn(channel->endpoint->dev,
1714 "Hardware failed to respond to close command, therefore left in messy state.\n");
1715 return -EINTR;
1716 }
1717 }
1718 }
1719
1720 mutex_unlock(&channel->wr_mutex);
1721 }
1722
1723 return 0;
1724 }
1725 static loff_t xillybus_llseek(struct file *filp, loff_t offset, int whence)
1726 {
1727 struct xilly_channel *channel = filp->private_data;
1728 loff_t pos = filp->f_pos;
1729 int rc = 0;
1730
1731 /*
1732 * Take both mutexes not allowing interrupts, since it seems like
1733 * common applications don't expect an -EINTR here. Besides, multiple
1734 * access to a single file descriptor on seekable devices is a mess
1735 * anyhow.
1736 */
1737
1738 if (channel->endpoint->fatal_error)
1739 return -EIO;
1740
1741 mutex_lock(&channel->wr_mutex);
1742 mutex_lock(&channel->rd_mutex);
1743
1744 switch (whence) {
1745 case 0:
1746 pos = offset;
1747 break;
1748 case 1:
1749 pos += offset;
1750 break;
1751 case 2:
1752 pos = offset; /* Going to the end => to the beginning */
1753 break;
1754 default:
1755 rc = -EINVAL;
1756 goto end;
1757 }
1758
1759 /* In any case, we must finish on an element boundary */
1760 if (pos & ((1 << channel->log2_element_size) - 1)) {
1761 rc = -EINVAL;
1762 goto end;
1763 }
1764
1765 mutex_lock(&channel->endpoint->register_mutex);
1766
1767 iowrite32(pos >> channel->log2_element_size,
1768 channel->endpoint->registers + fpga_buf_offset_reg);
1769 mmiowb();
1770 iowrite32((channel->chan_num << 1) |
1771 (6 << 24), /* Opcode 6, set address */
1772 channel->endpoint->registers + fpga_buf_ctrl_reg);
1773 mmiowb(); /* Just to appear safe */
1774
1775 mutex_unlock(&channel->endpoint->register_mutex);
1776
1777 end:
1778 mutex_unlock(&channel->rd_mutex);
1779 mutex_unlock(&channel->wr_mutex);
1780
1781 if (rc) /* Return error after releasing mutexes */
1782 return rc;
1783
1784 filp->f_pos = pos;
1785
1786 /*
1787 * Since seekable devices are allowed only when the channel is
1788 * synchronous, we assume that there is no data pending in either
1789 * direction (which holds true as long as no concurrent access on the
1790 * file descriptor takes place).
1791 * The only thing we may need to throw away is leftovers from partial
1792 * write() flush.
1793 */
1794
1795 channel->rd_leftovers[3] = 0;
1796
1797 return pos;
1798 }
1799
1800 static unsigned int xillybus_poll(struct file *filp, poll_table *wait)
1801 {
1802 struct xilly_channel *channel = filp->private_data;
1803 unsigned int mask = 0;
1804 unsigned long flags;
1805
1806 poll_wait(filp, &channel->endpoint->ep_wait, wait);
1807
1808 /*
1809 * poll() won't play ball regarding read() channels which
1810 * aren't asynchronous and support the nonempty message. Allowing
1811 * that will create situations where data has been delivered at
1812 * the FPGA, and users expecting select() to wake up, which it may
1813 * not.
1814 */
1815
1816 if (!channel->wr_synchronous && channel->wr_supports_nonempty) {
1817 poll_wait(filp, &channel->wr_wait, wait);
1818 poll_wait(filp, &channel->wr_ready_wait, wait);
1819
1820 spin_lock_irqsave(&channel->wr_spinlock, flags);
1821 if (!channel->wr_empty || channel->wr_ready)
1822 mask |= POLLIN | POLLRDNORM;
1823
1824 if (channel->wr_hangup)
1825 /*
1826 * Not POLLHUP, because its behavior is in the
1827 * mist, and POLLIN does what we want: Wake up
1828 * the read file descriptor so it sees EOF.
1829 */
1830 mask |= POLLIN | POLLRDNORM;
1831 spin_unlock_irqrestore(&channel->wr_spinlock, flags);
1832 }
1833
1834 /*
1835 * If partial data write is disallowed on a write() channel,
1836 * it's pointless to ever signal OK to write, because is could
1837 * block despite some space being available.
1838 */
1839
1840 if (channel->rd_allow_partial) {
1841 poll_wait(filp, &channel->rd_wait, wait);
1842
1843 spin_lock_irqsave(&channel->rd_spinlock, flags);
1844 if (!channel->rd_full)
1845 mask |= POLLOUT | POLLWRNORM;
1846 spin_unlock_irqrestore(&channel->rd_spinlock, flags);
1847 }
1848
1849 if (channel->endpoint->fatal_error)
1850 mask |= POLLERR;
1851
1852 return mask;
1853 }
1854
1855 static const struct file_operations xillybus_fops = {
1856 .owner = THIS_MODULE,
1857 .read = xillybus_read,
1858 .write = xillybus_write,
1859 .open = xillybus_open,
1860 .flush = xillybus_flush,
1861 .release = xillybus_release,
1862 .llseek = xillybus_llseek,
1863 .poll = xillybus_poll,
1864 };
1865
1866 static int xillybus_init_chrdev(struct xilly_endpoint *endpoint,
1867 const unsigned char *idt)
1868 {
1869 int rc;
1870 dev_t dev;
1871 int devnum, i, minor, major;
1872 char devname[48];
1873 struct device *device;
1874
1875 rc = alloc_chrdev_region(&dev, 0, /* minor start */
1876 endpoint->num_channels,
1877 xillyname);
1878
1879 if (rc) {
1880 dev_warn(endpoint->dev, "Failed to obtain major/minors");
1881 goto error1;
1882 }
1883
1884 endpoint->major = major = MAJOR(dev);
1885 endpoint->lowest_minor = minor = MINOR(dev);
1886
1887 cdev_init(&endpoint->cdev, &xillybus_fops);
1888 endpoint->cdev.owner = endpoint->ephw->owner;
1889 rc = cdev_add(&endpoint->cdev, MKDEV(major, minor),
1890 endpoint->num_channels);
1891 if (rc) {
1892 dev_warn(endpoint->dev, "Failed to add cdev. Aborting.\n");
1893 goto error2;
1894 }
1895
1896 idt++;
1897
1898 for (i = minor, devnum = 0;
1899 devnum < endpoint->num_channels;
1900 devnum++, i++) {
1901 snprintf(devname, sizeof(devname)-1, "xillybus_%s", idt);
1902
1903 devname[sizeof(devname)-1] = 0; /* Should never matter */
1904
1905 while (*idt++)
1906 /* Skip to next */;
1907
1908 device = device_create(xillybus_class,
1909 NULL,
1910 MKDEV(major, i),
1911 NULL,
1912 "%s", devname);
1913
1914 if (IS_ERR(device)) {
1915 dev_warn(endpoint->dev,
1916 "Failed to create %s device. Aborting.\n",
1917 devname);
1918 goto error3;
1919 }
1920 }
1921
1922 dev_info(endpoint->dev, "Created %d device files.\n",
1923 endpoint->num_channels);
1924 return 0; /* succeed */
1925
1926 error3:
1927 devnum--; i--;
1928 for (; devnum >= 0; devnum--, i--)
1929 device_destroy(xillybus_class, MKDEV(major, i));
1930
1931 cdev_del(&endpoint->cdev);
1932 error2:
1933 unregister_chrdev_region(MKDEV(major, minor), endpoint->num_channels);
1934 error1:
1935
1936 return rc;
1937 }
1938
1939 static void xillybus_cleanup_chrdev(struct xilly_endpoint *endpoint)
1940 {
1941 int minor;
1942
1943 for (minor = endpoint->lowest_minor;
1944 minor < (endpoint->lowest_minor + endpoint->num_channels);
1945 minor++)
1946 device_destroy(xillybus_class, MKDEV(endpoint->major, minor));
1947 cdev_del(&endpoint->cdev);
1948 unregister_chrdev_region(MKDEV(endpoint->major,
1949 endpoint->lowest_minor),
1950 endpoint->num_channels);
1951
1952 dev_info(endpoint->dev, "Removed %d device files.\n",
1953 endpoint->num_channels);
1954 }
1955
1956
1957 struct xilly_endpoint *xillybus_init_endpoint(struct pci_dev *pdev,
1958 struct device *dev,
1959 struct xilly_endpoint_hardware
1960 *ephw)
1961 {
1962 struct xilly_endpoint *endpoint;
1963
1964 endpoint = devm_kzalloc(dev, sizeof(*endpoint), GFP_KERNEL);
1965 if (!endpoint)
1966 return NULL;
1967
1968 endpoint->pdev = pdev;
1969 endpoint->dev = dev;
1970 endpoint->ephw = ephw;
1971 endpoint->msg_counter = 0x0b;
1972 endpoint->failed_messages = 0;
1973 endpoint->fatal_error = 0;
1974
1975 init_waitqueue_head(&endpoint->ep_wait);
1976 mutex_init(&endpoint->register_mutex);
1977
1978 return endpoint;
1979 }
1980 EXPORT_SYMBOL(xillybus_init_endpoint);
1981
1982 static int xilly_quiesce(struct xilly_endpoint *endpoint)
1983 {
1984 endpoint->idtlen = -1;
1985 wmb(); /* Make sure idtlen is set before sending command */
1986 iowrite32((u32) (endpoint->dma_using_dac & 0x0001),
1987 endpoint->registers + fpga_dma_control_reg);
1988 mmiowb();
1989
1990 wait_event_interruptible_timeout(endpoint->ep_wait,
1991 (endpoint->idtlen >= 0),
1992 XILLY_TIMEOUT);
1993
1994 if (endpoint->idtlen < 0) {
1995 dev_err(endpoint->dev,
1996 "Failed to quiesce the device on exit.\n");
1997 return -ENODEV;
1998 }
1999 return 0; /* Success */
2000 }
2001
2002 int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint)
2003 {
2004 int rc = 0;
2005
2006 void *bootstrap_resources;
2007 int idtbuffersize = (1 << PAGE_SHIFT);
2008 struct device *dev = endpoint->dev;
2009
2010 /*
2011 * The bogus IDT is used during bootstrap for allocating the initial
2012 * message buffer, and then the message buffer and space for the IDT
2013 * itself. The initial message buffer is of a single page's size, but
2014 * it's soon replaced with a more modest one (and memory is freed).
2015 */
2016
2017 unsigned char bogus_idt[8] = { 1, 224, (PAGE_SHIFT)-2, 0,
2018 3, 192, PAGE_SHIFT, 0 };
2019 struct xilly_idt_handle idt_handle;
2020
2021 /*
2022 * Writing the value 0x00000001 to Endianness register signals which
2023 * endianness this processor is using, so the FPGA can swap words as
2024 * necessary.
2025 */
2026
2027 iowrite32(1, endpoint->registers + fpga_endian_reg);
2028 mmiowb(); /* Writes below are affected by the one above. */
2029
2030 /* Bootstrap phase I: Allocate temporary message buffer */
2031
2032 bootstrap_resources = devres_open_group(dev, NULL, GFP_KERNEL);
2033 if (!bootstrap_resources)
2034 return -ENOMEM;
2035
2036 endpoint->num_channels = 0;
2037
2038 rc = xilly_setupchannels(endpoint, bogus_idt, 1);
2039
2040 if (rc)
2041 return rc;
2042
2043 /* Clear the message subsystem (and counter in particular) */
2044 iowrite32(0x04, endpoint->registers + fpga_msg_ctrl_reg);
2045 mmiowb();
2046
2047 endpoint->idtlen = -1;
2048
2049 smp_wmb();
2050
2051 /*
2052 * Set DMA 32/64 bit mode, quiesce the device (?!) and get IDT
2053 * buffer size.
2054 */
2055 iowrite32((u32) (endpoint->dma_using_dac & 0x0001),
2056 endpoint->registers + fpga_dma_control_reg);
2057 mmiowb();
2058
2059 wait_event_interruptible_timeout(endpoint->ep_wait,
2060 (endpoint->idtlen >= 0),
2061 XILLY_TIMEOUT);
2062
2063 if (endpoint->idtlen < 0) {
2064 dev_err(endpoint->dev, "No response from FPGA. Aborting.\n");
2065 return -ENODEV;
2066 }
2067
2068 /* Enable DMA */
2069 iowrite32((u32) (0x0002 | (endpoint->dma_using_dac & 0x0001)),
2070 endpoint->registers + fpga_dma_control_reg);
2071 mmiowb();
2072
2073 /* Bootstrap phase II: Allocate buffer for IDT and obtain it */
2074 while (endpoint->idtlen >= idtbuffersize) {
2075 idtbuffersize *= 2;
2076 bogus_idt[6]++;
2077 }
2078
2079 endpoint->num_channels = 1;
2080
2081 rc = xilly_setupchannels(endpoint, bogus_idt, 2);
2082
2083 if (rc)
2084 goto failed_idt;
2085
2086 smp_wmb();
2087
2088 rc = xilly_obtain_idt(endpoint);
2089
2090 if (rc)
2091 goto failed_idt;
2092
2093 xilly_scan_idt(endpoint, &idt_handle);
2094
2095 if (!idt_handle.chandesc) {
2096 rc = -ENODEV;
2097 goto failed_idt;
2098 }
2099
2100 devres_close_group(dev, bootstrap_resources);
2101
2102 /* Bootstrap phase III: Allocate buffers according to IDT */
2103
2104 rc = xilly_setupchannels(endpoint,
2105 idt_handle.chandesc,
2106 idt_handle.entries);
2107
2108 if (rc)
2109 goto failed_idt;
2110
2111 smp_wmb(); /* mutex_lock below should suffice, but won't hurt.*/
2112
2113 /*
2114 * endpoint is now completely configured. We put it on the list
2115 * available to open() before registering the char device(s)
2116 */
2117
2118 mutex_lock(&ep_list_lock);
2119 list_add_tail(&endpoint->ep_list, &list_of_endpoints);
2120 mutex_unlock(&ep_list_lock);
2121
2122 rc = xillybus_init_chrdev(endpoint, idt_handle.idt);
2123
2124 if (rc)
2125 goto failed_chrdevs;
2126
2127 devres_release_group(dev, bootstrap_resources);
2128
2129 return 0;
2130
2131 failed_chrdevs:
2132 mutex_lock(&ep_list_lock);
2133 list_del(&endpoint->ep_list);
2134 mutex_unlock(&ep_list_lock);
2135
2136 failed_idt:
2137 xilly_quiesce(endpoint);
2138 flush_workqueue(xillybus_wq);
2139
2140 return rc;
2141 }
2142 EXPORT_SYMBOL(xillybus_endpoint_discovery);
2143
2144 void xillybus_endpoint_remove(struct xilly_endpoint *endpoint)
2145 {
2146 xillybus_cleanup_chrdev(endpoint);
2147
2148 mutex_lock(&ep_list_lock);
2149 list_del(&endpoint->ep_list);
2150 mutex_unlock(&ep_list_lock);
2151
2152 xilly_quiesce(endpoint);
2153
2154 /*
2155 * Flushing is done upon endpoint release to prevent access to memory
2156 * just about to be released. This makes the quiesce complete.
2157 */
2158 flush_workqueue(xillybus_wq);
2159 }
2160 EXPORT_SYMBOL(xillybus_endpoint_remove);
2161
2162 static int __init xillybus_init(void)
2163 {
2164 int rc = 0;
2165
2166 mutex_init(&ep_list_lock);
2167
2168 xillybus_class = class_create(THIS_MODULE, xillyname);
2169 if (IS_ERR(xillybus_class)) {
2170 rc = PTR_ERR(xillybus_class);
2171 pr_warn("Failed to register class xillybus\n");
2172
2173 return rc;
2174 }
2175
2176 xillybus_wq = alloc_workqueue(xillyname, 0, 0);
2177 if (!xillybus_wq) {
2178 class_destroy(xillybus_class);
2179 rc = -ENOMEM;
2180 }
2181
2182 return rc;
2183 }
2184
2185 static void __exit xillybus_exit(void)
2186 {
2187 /* flush_workqueue() was called for each endpoint released */
2188 destroy_workqueue(xillybus_wq);
2189
2190 class_destroy(xillybus_class);
2191 }
2192
2193 module_init(xillybus_init);
2194 module_exit(xillybus_exit);
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